KR20190041165A - Substrate for display and display including the same - Google Patents

Abstract

The present invention relates to a substrate for a display device capable of realizing a narrow bezel with minimized variation in characteristics of a thin film transistor and a display device including the same. According to the present invention, the display device comprises: a first thin film transistor having a first oxide semiconductor layer disposed in a display area of the display device; a second thin film transistor having a second oxide semiconductor layer disposed in a non-display area of the display device, wherein the channel length of the second thin film transistor disposed in the non-display area is shorter than the channel length of the first thin film transistor disposed in the display area and the channel resistance of the second oxide semiconductor layer is higher than the channel resistance of the first oxide semiconductor layer disposed in the display area.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a substrate for a display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for a display device and a display device including the same, and more particularly, to a substrate for a display device capable of realizing a narrow bezel with minimal variation in characteristics of the thin film transistor and a display device including the same.

As a display device for realizing various information on a screen, a liquid crystal display device (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED) And an electrophoretic display device (ED).

Such a display device includes a display panel in which each sub-pixel displays an image through a pixel array independently driven by a thin film transistor (TFT), and a gate driver and a data driver for driving the display panel.

Recently, a gate-in-panel (GIP) method built in a non-display area (bezel area) of a display panel is mainly used as a gate driver.

The non-display area in which the gate driver of the GIP scheme is disposed has been continuously tried to implement the narrow bezel in order to meet various demands of the user and to improve the beauty. As the area of the bezel area decreases, the area occupied by the gate driver in the bezel area must also be reduced. To this end, when the channel length of the TFT applied to the gate driver is reduced, the line width of the gate electrode of the TFT is reduced.

The semiconductor layer 12 facing the gate electrode 16 of the TFT with the gate insulating film 14 therebetween has a channel region CH overlapping with the gate electrode 16 as shown in FIG. And source and drain regions SA and DA that are non-overlapping with the source region 16 and are made conductive. The source and drain regions SA and DA are diffused into the channel region CH when the source and drain regions SA and DA of the semiconductor layer 14 of the TFT are formed, And has a fixed value irrespective of whether or not it is. Accordingly, the smaller the channel length, the smaller the specific gravity occupied by the effective channel length Leff in the entire channel length corresponding to the line width of the gate electrode 16.

Accordingly, as shown in FIG. 2, as the effective channel length of the TFT applied to the gate driver decreases, the threshold voltage fluctuates in the negative direction due to the short channel effect, and the TFT deteriorates .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a substrate for a display device capable of realizing a narrow bezel with minimal variations in characteristics of the thin film transistor and a display device including the same.

In order to achieve the above object, a display device according to the present invention includes a first thin film transistor having a first oxide semiconductor layer disposed therein, a second thin film transistor having a second oxide semiconductor layer in a non- The channel length of the second thin film transistor disposed in the non-display region is shorter than the channel length of the first thin film transistor disposed in the display region, and the channel resistance of the second oxide semiconductor layer disposed in the non- Region is higher than the channel resistance of the first oxide semiconductor layer.

In the present invention, the channel resistance of the second thin film transistor disposed in the non-display region is relatively high and the channel resistance of the first thin film transistor disposed in the display region is relatively low. Accordingly, the present invention can improve the deterioration of the threshold voltage dispersion due to the channel length difference of the first and second thin film transistors. In addition, in the present invention, the channel length of the second thin film transistor can be reduced to be smaller than the channel length of the first thin film transistor while minimizing the characteristic change of the second thin film transistor. Accordingly, the present invention can reduce the bezel area by reducing the area of the gate driver made up of the second thin film transistor, thereby realizing a narrow bezel.

1 is a view showing a gate electrode and an oxide semiconductor layer of a conventional thin film transistor.
FIG. 2 is a graph showing a threshold voltage according to a channel length of the conventional thin film transistor shown in FIG.
3 is a plan view showing a display device according to the present invention.
FIG. 4 is a cross-sectional view showing a first thin film transistor arranged in the display region shown in FIG. 3 and a second thin film transistor arranged in the non-display region.
5 is a graph showing threshold voltage characteristics of channel lengths according to carrier concentration of the second thin film transistor shown in FIG.
6A and 6B are cross-sectional views showing various embodiments of the first thin film transistor shown in FIG.
Are circuit diagrams showing respective sub-pixels arranged in the display area shown in Fig. 3 shown in Figs. 7A and 7B.
8A and 8B are cross-sectional views illustrating embodiments of an organic light emitting diode display according to the present invention.
FIG. 9A is a graph showing the threshold voltage characteristics of the comparative example and the embodiment according to the channel length according to the thickness of the oxide semiconductor layer, FIG. 9B is a graph showing the threshold voltage characteristics of the comparative example and the embodiment according to the oxygen partial pressure of the oxide semiconductor layer, FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a display device according to the present invention.

3 includes a display panel 180, a gate driver 182 for driving the gate line GL of the display panel 180, and a data driver 170 for driving the data line DL of the display panel 180 And a data driver 184.

The display panel 180 includes a display area AA and a non-display area NA (bezel area) surrounding the display area AA.

A plurality of sub-pixels located at the intersections of the gate lines GL and the data lines DL which are arranged so as to cross each other are arranged in a matrix form in the display area AA of the display panel 180. [ Each of these sub-pixels is independently driven by a first thin film transistor (TFT) 100 shown in FIG.

A gate driver 182 and a multiplexer 186 are disposed in the non-display area NA. In addition to the gate driver 182 and the multiplexer 186, the data driver 184 may also be disposed in the non-display area NA.

The multiplexer 186 is disposed between the data driver 184 and the data line DL. The multiplexer 186 can reduce the number of output channels of the data driver 184 by dividing the data voltage from the data driver 184 into a plurality of data lines DL by time division, The number of integrated circuits can be reduced.

The driving circuit portion of at least one of the multiplexer 184 and the gate driver 182 is configured using the second thin film transistor 150 shown in FIG. At this time, the second thin film transistor 150 in the non-display area NA where the multiplexer 184 and the gate driver 182 are disposed and the first thin film transistor 100 in the display area AA are connected to the same mask And can be formed directly on the display device substrate 101 as a process.

The second thin film transistor 150 disposed in the non-display area NA and the first thin film transistor 100 disposed in the display area AA are formed to have different channels. Particularly, in order to realize a narrow bezel in the present invention, the channel length L2 of the second thin film transistor 150 disposed in the non-display area NA is set equal to the channel length L2 of the first thin film transistor 100 (L1).

For this, each of the first and second thin film transistors 100 and 150 includes gate electrodes 106 and 156, oxide semiconductor layers 104 and 154, source electrodes 108 and 158, and drain electrodes 110 and 160, Respectively.

The gate electrodes 106 and 156 are formed on the gate insulating film 112 and overlap the oxide semiconductor layers 104 and 154 with the gate insulating film 112 interposed therebetween. The first gate electrode 106 of the first thin film transistor 100 having a long channel length L1 is formed to have a longer width than the second gate electrode 156 of the second thin film transistor 150 having a short channel length L2 do. The first gate electrode 106 is formed of the same material as the second gate electrode 156 on the gate insulating film 112 which is flush with the second gate electrode 156. Accordingly, since the first and second gate electrodes 106 and 156 can be formed by the same mask process, the mask process can be reduced. Although the gate insulating film 112 shown in FIG. 4 is described as being disposed on the substrate 101 in the same shape as the interlayer insulating film 116, the gate insulating film 112 may be formed on the first oxide semiconductor layer 104 and the first gate electrode 106 and between the second oxide semiconductor layer 154 and the second gate electrode 156 with a line width similar to that of each of the first and second gate electrodes 106, .

The source and drain electrodes 108, 158, 110 and 160 are formed of a metal such as molybdenum, aluminum, chrome, gold, titanium, ) And copper (Cu), or an alloy thereof. However, the present invention is not limited thereto. The source and drain electrodes 108, 158, 110 and 160 are formed to face each other with the channel regions CH1 and CH2 of the oxide semiconductor layers 104 and 154 therebetween. The source electrodes 108 and 158 are in contact with the source region SA disposed on one side of the channel region CH through the source contact holes 114S and 164S and the drain electrodes 110 and 160 are connected to the drain contact holes 114D and 164D And is in contact with the drain region DA disposed on the other side of the channel region CH.

Each of the oxide semiconductor layers 104 and 154 is formed of an oxide containing at least one metal selected from Zn, Cd, Ga, In, Sn, Hf and Zr on the buffer layer 102. The oxide semiconductor layers 104 and 154 have a channel region CH overlapping with the gate electrode 106 and a conductiveized source region SA and a conductive drain region DA.

A light shielding layer (not shown) may be disposed on the substrate 101 and the buffer layer 102 to block external light from entering the channel region CH of the first and second oxide semiconductor layers 104 and 154 . On the other hand, since the channel region CH of the second thin film transistor 150 disposed in the non-display region NA can be shielded from external light by the bezel, the light shielding layer is disposed in the non-display region NA .

In the present invention, the channel resistance of the second thin film transistor 150 is increased to prevent the threshold voltage of the second thin film transistor 150 having a short channel length L2 from shifting in the negative direction.

To this end, the second thin film transistor 150 has an oxygen content p of the second oxide semiconductor layer 154 proportional to the channel resistance Rch and a second oxide semiconductor layer 154 of the second thin film transistor 150, which is inversely proportional to the channel resistance Rch, The thickness t of the oxide semiconductor layer 154 is adjusted. In Equation (1), L denotes a channel length and W denotes a channel width.

[Equation 1]

That is, the oxygen average content of the second oxide semiconductor layer 154 is higher than the oxygen average content of the first oxide semiconductor layer 104, and the thickness of the channel region CH of the second oxide semiconductor layer 154 is larger Is formed to be thinner than the thickness of the channel region (CH) of the semiconductor layer (104).

Here, in order to increase the oxygen average content of the second oxide semiconductor layer 154, the oxygen partial pressure in the deposition chamber in the deposition process of the second oxide semiconductor layer 154 is increased as compared with the conventional one. Here, the oxygen partial pressure means a pressure ratio of oxygen to the total gas in the deposition chamber.

As the oxygen partial pressure of the second oxide semiconductor layer 154 increases, the empty vacancy of oxygen in the second oxide semiconductor layer 154 is small, so that the carrier concentration of the second oxide semiconductor layer 154 decreases .

In addition, since the thickness of the second oxide semiconductor layer 154 becomes thinner than the conventional one, the channel resistance increases, and the carrier concentration of the second oxide semiconductor layer 154, which is inversely proportional to the channel resistance, decreases.

Even if the channel length L2 of the second thin film transistor 150 is shortened, due to the decrease in the thickness of the second oxide semiconductor layer 154 and the increase in the oxygen partial pressure, the carrier concentration of the second oxide semiconductor layer 154 Is reduced. Due to the decrease in the carrier concentration K of the second oxide semiconductor layer 154, it is possible to prevent the threshold voltage of the second thin film transistor 150 from fluctuating in the negative direction as shown in FIG.

In the case of forming the first thin film transistor 100 in the same structure as that of the second thin film transistor 150, the channel of the first oxide semiconductor layer 104 of the first thin film transistor 100, The resistance is increased more than the second thin film transistor whose channel length L2 is short. As a result, the carrier concentration of the first oxide semiconductor layer 104 is lowered and the mobility of the first thin film transistor 100 is lowered, thereby deteriorating the characteristics of the first thin film transistor 100.

Therefore, in the present invention, the first thin film transistor 100 is formed in a structure different from that of the second thin film transistor 150. That is, the second oxide semiconductor layer 154 of the second thin film transistor 150 is formed as a single layer structure, while the first oxide semiconductor layer 104 of the first thin film transistor 100 is formed of a multi- .

For example, the first oxide semiconductor layer 104 may include a lower semiconductor layer 104a, an upper semiconductor layer 104b disposed on the lower semiconductor layer 104a as shown in FIG. 4, 6A, or 6B, Lt; / RTI >

The lower semiconductor layer 104a shown in FIG. 4 is formed on the buffer layer 102 with a line width similar to that of the gate electrode 106, and is completely overlapped with the first gate electrode 106. This lower semiconductor layer 104a has only a channel region CH without a source region and a drain region. The upper semiconductor layer 104b is formed so as to cover the lower semiconductor layer 104a. The upper semiconductor layer 104b includes a channel region CH disposed on the lower semiconductor layer 104a, a source region SA connected to the first source electrode 108, a first drain electrode 110, And a drain region DA to be connected.

At this time, the lower semiconductor layer 104a and the upper semiconductor layer 104b are formed to have different oxygen contents. The oxygen content of the channel region CH of the lower semiconductor layer 104a may be greater than the channel region CH of the upper semiconductor layer 104b as shown in Figure 4, (CH) of the channel region (104b).

The lower semiconductor layer 104a of the first oxide semiconductor layer shown in FIG. 6B includes a channel region CH disposed on the buffer layer 102, a source region SA connected to the first source electrode 108, And a drain region DA connected to the first drain electrode 110. The upper semiconductor layer 104b is formed on the lower semiconductor layer 104a with a line width similar to the gate electrode 106 to expose the source region SA and the drain region DA of the lower semiconductor layer 104a. This upper semiconductor layer 104b has only the channel region CH without the source region SA and the drain region DA. The oxygen content of the channel region CH of the lower semiconductor layer 104a of the first oxide semiconductor layer 104 is formed to be larger or smaller than the channel region CH of the upper semiconductor layer 104b.

Although the lower semiconductor layer 104a and the upper semiconductor layer 104b are formed with different line widths, the same line width may be used. In this case, each of the lower semiconductor layer 104a and the upper semiconductor layer 104b has a channel region CH and a source region SA and a drain region DA opposed to each other with the channel region CH therebetween do.

Among the lower semiconductor layer 104a and the upper semiconductor layer 104b shown in Figs. 4, 6A, and 6B, the semiconductor layer having a high oxygen content has the same oxygen content as the second oxide semiconductor layer 154. [ Therefore, the oxygen average content of the first oxide semiconductor layer 104 is formed to be lower than the oxygen average content of the second oxide semiconductor layer 154.

The partial pressure of oxygen in the deposition chamber during the deposition of the semiconductor layer having a low oxygen content and the second oxide semiconductor layer 154 in the lower semiconductor layer 104a and the upper semiconductor layer 104b is controlled by the lower semiconductor layer 104a, The oxygen partial pressure in the upper semiconductor layer 104b is higher than the oxygen partial pressure in the semiconductor layer deposition process.

The channel resistance of the first thin film transistor 100 having such a structure may be increased because the channel length is longer than that of the second thin film transistor 150. However, if the oxygen average content of the first oxide semiconductor layer 104, which is proportional to the channel resistance, is lower than the oxygen average content of the second oxide semiconductor layer 154, and the total of the first oxide semiconductor layer 104 The thickness of the second oxide semiconductor layer 154 is thicker than the entire thickness of the second oxide semiconductor layer 154. Accordingly, the channel resistance of the first thin film transistor 100 can be prevented from increasing, and the carrier concentration of the first oxide semiconductor layer 104 can be kept high. As a result, the mobility of the first oxide semiconductor layer 104 is increased and the response speed of the first thin film transistor 100 can be maintained at a high speed.

The first and second thin film transistors 100 and 150 may be applied to a display device requiring a thin film transistor such as an organic light emitting display or a liquid crystal display.

In the display area of the OLED display device, the sub-pixels shown in FIG. 7A or FIG. 7B are arranged in a matrix form. The structure of each sub-pixel is very diverse. The structure shown in FIGS. 7A and 7B is a concrete example, but is not limited thereto.

Each sub-pixel includes a light emitting element 130, a switching transistor TSW, a driving transistor TD, and a storage capacitor Cst, and selectively includes a sensing transistor TSS.

The switching transistor TSW shown in Figs. 7A and 7B switches the data voltage written to each pixel located in the display area AA. The switching transistor TSW includes a gate electrode connected to the scan line SL, a source electrode connected to the data line DL, and a drain electrode connected to the gate electrode of the drive transistor TD.

The driving transistor TD operates so that the driving current flows between the high potential line VDD and the low potential line VSS in accordance with the data voltage stored in the storage capacitor Cst. This driving transistor TD has a gate electrode connected to the drain electrode of the switching transistor TSW, a source electrode connected to the high voltage (VDD) supply line, and a drain electrode connected to the light emitting element 130. [

The sensing transistor TSS shown in FIG. 7B applies a reference voltage Vref supplied to the reference line RL to the source electrode of the driving transistor Tr_D in response to the second gate voltage supplied through the sensing control line SSL. . The threshold voltage and the mobility of the driving transistor TD are sensed through the sensing transistor TSS and the reference line RL and the data voltage is compensated in proportion to the difference between the sensed value and the reference threshold voltage. The sensing transistor TSS includes a gate electrode connected to the sensing control line SSL, a source electrode connected to the reference line RL, and a drain electrode connected to the light emitting element 130.

The switching transistor TSW, the driving transistor TD and the sensing transistor TSS of each sub-pixel arranged in the display area AA are formed by the lower semiconductor layer 104a and the upper semiconductor layer 104b The transistor of the circuit driver arranged in the non-display area NA is formed of the second oxide semiconductor layer 154 having a short channel length And a second thin film transistor 150 including the first thin film transistor 150 and the second thin film transistor 150.

In addition, any one of the switching transistor TSW, the driving transistor TD and the sensing transistor TSS of each sub-pixel arranged in the display area AA is formed of any one of the first and second thin film transistors 100 and 150 And the remaining two transistors may be formed as the other one of the first and second thin film transistors 100 and 150. [ For example, as shown in FIG. 8B, the switching transistor TSW is formed of a first thin film transistor 100 having a long channel length, and the driving transistor TD and the sensing transistor TSS are formed of a second And may be formed of the thin film transistor 150.

The light emitting device 130 includes an anode electrode 132 connected to the drain electrode 160 of the driving transistor TD as shown in Figs. 8A and 8B, and at least one light emitting element 130 formed on the anode electrode 132 A stack 134, and a cathode electrode 136 formed on the luminescent stack 134.

The anode electrode 132 is connected to the drain electrode 160 of the driving transistor TD exposed through the pixel contact hole 120 passing through the planarization layer 128. The anode electrode 132 is formed in a multi-layer structure including a transparent conductive film and an opaque conductive film having high reflection efficiency. The transparent conductive film is made of a material having a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film is made of Al, Ag, Cu, Pb, Mo, Ti or an alloy thereof. For example, the anode electrode 132 is formed in a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially laminated, or a structure in which a transparent conductive film and an opaque conductive film are sequentially laminated. The anode electrode 132 is disposed on the planarization layer 128 so as to overlap not only the light emitting region provided by the bank 138 but also the circuit region in which the first and second transistors 100 and 150 are disposed, thereby increasing the light emitting area.

At least one light-emitting stack 134 is formed on the anode electrode 132 in the order of the hole-related layer, the organic light-emitting layer, and the electron-related layer. In addition, when there are two or more light emitting stacks 134, the light emitting stacks face each other across the charge generating layer. For example, the luminescent stack may have first and second luminescent stacks facing each other with one charge generating layer therebetween. In this case, the organic light emitting layer of any one of the first and second light emitting stacks generates blue light, and the organic light emitting layer of the other of the first and second light emitting stacks generates yellow-green light, White light is generated. The white light generated in the light emitting stack 134 is incident on a color filter (not shown) positioned above the light emitting stack 134, so that a color image can be realized. In addition, a color image corresponding to each sub-pixel may be generated in each light emitting stack 134 without a separate color filter. That is, the light emitting stack 134 of red (R) sub-pixel generates red light, the light emitting stack 134 of green (G) sub-pixel generates green light, and the light emitting stack 134 of blue (B) You may.

The bank 138 is formed to expose the anode electrode 132. [ These banks 138 may be formed of an opaque material (e.g., black) to prevent optical interference between adjacent sub-pixels. In this case, the bank 138 includes a light shielding material made of at least one of color pigment, organic black, and carbon.

The cathode electrode 136 is formed on the upper surface and the side surface of the light emitting stack 134 so as to face the anode electrode 132 with the light emitting stack 134 therebetween. The cathode electrode 136 is formed of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) when applied to a top emission type OLED display.

9A is a graph showing a threshold voltage characteristic of the comparative example and the embodiment according to the channel length according to the thickness of the oxide semiconductor layer. 9A, the thin film transistor of the comparative example is formed to have the same thickness in the display region and the non-display region, and the first thin film transistor 100 of the embodiment is formed thicker than the thin film transistor of the comparative example in the display region, 150 are formed to be thinner than the comparative thin film transistors in the non-display region.

In this case, in the thin film transistor of the comparative example formed in the display region and the non-display region with the same thickness, the threshold voltage is shifted greatly in the negative direction as the channel length is shortened, as shown in FIG. As a result, the threshold voltage distribution in the non-display region and the display region is large in the thin film transistor of the comparative example, and reliability is lowered.

On the other hand, the second thin film transistor 150 formed in a thin thickness in the non-display area NA has a shorter channel length than the first thin film transistor 100 formed in the display area AA in a thick thickness, The variation amount of the threshold voltage in the negative direction is smaller than that in the example. Accordingly, even when the channel length is short in the non-display area NA, the variation of the threshold voltage is small in the embodiment, so that deterioration of the second thin film transistor 150 can be minimized. Further, in the first and second thin film transistors 100 and 150 of the embodiment, the threshold voltage dispersion in the non-display area NA and the display area AA is uniform compared to the comparative example, and reliability is improved.

9B is a graph showing a threshold voltage characteristic of the comparative example and the embodiment according to the channel length according to the oxygen partial pressure of the oxide semiconductor layer. 9B, the oxygen partial pressure of the oxide semiconductor layer of the comparative example is the same in the display region and the non-display region, and the first oxide semiconductor layer 104 of the first thin film transistor 100 of the embodiment is in the display region AA And the second oxide semiconductor layer 154 of the second thin film transistor 150 of the embodiment has a higher oxygen partial pressure in the non-display area NA than that of the comparative example.

In this case, as shown in FIG. 9B, the threshold voltage of the thin film transistor of the comparative example having the same oxygen partial pressure in the display area and the non-display area is shifted greatly in the negative direction as the channel length is shortened. As a result, the threshold voltage distribution in the non-display region and the display region is large in the thin film transistor of the comparative example, and reliability is lowered.

On the other hand, the second thin film transistor 150 of the embodiment having a high oxygen partial pressure in the non-display area NA has a smaller channel density than the first thin film transistor 100 of the embodiment having the semiconductor layer with a low oxygen partial pressure in the display area AA, The variation amount of the threshold voltage in the negative direction is smaller than that of the comparative example, although the length is short. Accordingly, even when the channel length is shortened in the non-display area NA, the variation of the threshold voltage of the second thin film transistor 150 is small in the embodiment, so that deterioration of the second thin film transistor 150 can be minimized. Further, in the thin film transistor of the embodiment, the threshold voltage distribution in the non-display area NA and the display area AA is uniform compared to the comparative example, and reliability is improved.

As described above, in the present invention, the channel resistance of the second thin film transistor disposed in the non-display region is relatively increased and the channel resistance of the first thin film transistor disposed in the display region is relatively lower. Accordingly, the present invention can improve the deterioration of the threshold voltage dispersion due to the channel length difference of the first and second thin film transistors. In addition, in the present invention, the channel length of the second thin film transistor can be reduced to be smaller than the channel length of the first thin film transistor while minimizing the characteristic change of the second thin film transistor. Accordingly, the present invention can reduce the bezel area by reducing the area of the gate driver made up of the second thin film transistor, thereby realizing a narrow bezel.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

100, 150: thin film transistors 104, 154: oxide semiconductor layer
106, 156: gate electrode 108, 158: source electrode
110, 160: drain electrode

Claims (10)

A first thin film transistor disposed on the substrate and having a first oxide semiconductor layer;
And a second thin film transistor disposed on the substrate so as to be spaced apart from the first thin film transistor and having a second oxide semiconductor layer,
The channel lengths of the first and second oxide semiconductor layers are different from each other,
Wherein the first and second oxide semiconductor layers have a channel resistance inversely proportional to a channel length. The method according to claim 1,
The first oxide semiconductor layer has a multi-layer structure having different oxygen contents,
Wherein the second oxide semiconductor layer is thinner than the first oxide semiconductor layer. 3. The method of claim 2,
Wherein an oxygen content of the second oxide semiconductor layer is higher than an oxygen average content of the first oxide semiconductor layer. The method of claim 3,
Wherein the first oxide semiconductor layer includes a lower semiconductor layer and an upper semiconductor layer disposed on the lower semiconductor layer,
And the second oxide semiconductor layer has an oxygen content equal to that of the semiconductor layer having a higher oxygen content in the lower semiconductor layer and the upper semiconductor layer. A display region in which a first thin film transistor having a first oxide semiconductor layer is disposed,
And a non-display region where a second thin film transistor having a second oxide semiconductor layer is disposed,
The channel length of the second thin film transistor is shorter than the channel length of the first thin film transistor,
Wherein a channel resistance of the second oxide semiconductor layer is higher than a channel resistance of the first oxide semiconductor layer. 6. The method of claim 5,
The first oxide semiconductor layer has a multi-layer structure having different oxygen contents,
Wherein the second oxide semiconductor layer is thinner than the first oxide semiconductor layer. The method according to claim 6,
Wherein the first oxide semiconductor layer includes a lower semiconductor layer and an upper semiconductor layer disposed on the lower semiconductor layer,
And the second oxide semiconductor layer has an oxygen content equal to that of the semiconductor layer having a higher oxygen content in the lower semiconductor layer and the upper semiconductor layer. 8. The method of claim 7,
A light emitting element arranged in the display region;
A driving transistor connected to the light emitting element;
Further comprising a switching transistor connected to the driving transistor,
Wherein at least one of the driving transistor and the switching transistor comprises the first thin film transistor. 9. The method of claim 8,
And a sensing transistor connected to the driving transistor for sensing a threshold voltage of the driving transistor,
Wherein one of the driving transistor, the switching transistor, and the sensing transistor is formed of any one of the first and second thin film transistors,
Wherein the remaining two transistors among the driving transistor, the switching transistor, and the sensing transistor comprise the other one of the first and second thin film transistors. 8. The method of claim 7,
A gate driver positioned in the non-display area and driving a gate line of the display area;
A data driver driving a data line of the display area;
And a multiplexer for distributing a data voltage from the data driver to the data line,
Wherein at least one of the multiplexer and the gate driver comprises the second thin film transistor.

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