KR20190008643A - Memory system and operating method of memory system - Google Patents

Abstract

The present invention relates to a memory system for processing data by using a memory device and an operating method thereof. The memory system includes: the memory device including multiple memory blocks storing data, multiple planes including the memory blocks, and multiple memory dies including the planes; and a controller including a first memory. The controller receives multiple commands from a host, executes command operations corresponding to the commands on the memory blocks, checks the individual patterns for the commands, command operations, and user data corresponding to the command operations, allocates pattern zones corresponding to the patterns to the first memory in a dynamic manner, and loads the commands, command operations, and map segments of map data corresponding to the user data to the pattern zones.

Description

[0001] MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system, and more particularly, to a memory system for processing data in a memory device and a method of operating the memory system.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use memory systems that use memory devices, i. E., Data storage devices. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because there is no mechanical driving part, and the access speed of information is very fast and power consumption is low. As an example of a memory system having such advantages, a data storage device includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

Embodiments of the present invention provide a memory system and a method of operating a memory system that can quickly and reliably process data into a memory device by minimizing the complexity and performance degradation of the memory system and maximizing the use efficiency of the memory device do.

A memory system according to embodiments of the present invention includes a plurality of memory blocks in which data is stored and a plurality of planes including the memory blocks and a plurality of memory dies die; < / RTI > And a controller including a first memory; The controller receiving a plurality of commands from a host; Performing command operations corresponding to the commands in the memory blocks; Identify patterns for user data corresponding to the commands, the command operations, and the command operations, respectively; Assigning pattern zones to the first memory dynamically, corresponding to the patterns; Map segments of map data corresponding to the commands, the command operations, and the user data may be loaded into the pattern zones.

Here, the controller may load map segments of first map data corresponding to a first pattern in the patterns into a first pattern zone in the pattern zones; Map segments of second map data corresponding to the second pattern in the patterns may be loaded into the second pattern zone in the pattern zones.

And, the first pattern is a discontinuous pattern in which the information on the commands, the command operations, and the user data is discontinuous; The second pattern may be a continuous pattern of information about the commands, the command operations, and the user data.

The controller may read map segments of the first map data in the first unit size and load the map segments in the first pattern zone in the first unit size in the memory blocks, .

Further, the controller may read one map segment having the first unit size in the map segments of the first map data, respectively; After storing one map segment having the first unit size in the buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; One map segment having the first unit size may be loaded in the first pattern zone, respectively.

In the memory blocks, the controller may read map segments of the second map data into a second unit size, and then load the map segments into the second pattern zone with the second unit size.

The controller is further configured to: read, in map segments of the second map data, all map segments having the second unit size; Storing the entire map segments having the second unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; The entire map segments having the second unit size may be loaded in the second pattern zone.

In addition, the controller may read the entire map segments having the second unit size in the memory blocks through an interleaving scheme for the planes or the memory dies.

Map segments of the first map data loaded in the first pattern zone are managed according to MRU (Most Recently Used) and LRU (Least Recently Used); The map segments of the second map data loaded in the second pattern zone can be managed according to the execution of the command operations.

In addition, the controller can identify the first pattern and the second pattern with respect to user data corresponding to background operations or background operations on the memory device.

A method of operating a memory system according to embodiments of the present invention includes a plurality of memory blocks in which data is stored and a plurality of planes including the memory blocks and a plurality of memories The method comprising: receiving, for a memory device including memory dies, a plurality of commands from a host; Confirming patterns for the commands, the command operations corresponding to the commands, and the user data corresponding to the command operations, respectively; Assigning pattern zones dynamically to the first memory in accordance with the patterns; And loading map segments of the map data corresponding to the commands, the command operations, and the user data into the pattern zones.

The loading step may include loading map segments of first map data corresponding to a first pattern in the patterns into a first pattern zone in the pattern zones; And loading map segments of second map data corresponding to the second pattern in the patterns into a second pattern zone in the pattern zones.

And, the first pattern is a discontinuous pattern in which the information on the commands, the command operations, and the user data is discontinuous; The second pattern may be a continuous pattern of information about the commands, the command operations, and the user data.

The step of loading into the first pattern zone may further include reading the map segments of the first map data in the memory blocks in a first unit size and then reading the map segments of the first map data in the first unit size, Each can be loaded into a zone.

The loading of the first pattern zone may further include: reading one map segment having the first unit size in map segments of the first map data, respectively; Storing one map segment having the first unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies, respectively; And loading one map segment having the first unit size stored in the buffers into the first pattern zone, respectively.

The loading of the second pattern zone may include reading the map segments of the second map data in the memory blocks in a second unit size and then reading the map segments of the second map data in the second pattern zone, Lt; / RTI >

Also, the step of loading into the second pattern zone may include: reading all map segments having the second unit size in the map segments of the second map data; Storing all map segments having the second unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; And loading all map segments having the second unit size stored in the buffers into the second pattern zone.

In addition, the reading may lead to the entire map segments having the second unit size in the memory blocks through an interleaving scheme for the planes or the memory dies.

Map segments of the first map data loaded in the first pattern zone are managed according to MRU (Most Recently Used) and LRU (Least Recently Used); The map segments of the second map data loaded in the second pattern zone can be managed according to the execution of the command operations.

The method may further include confirming the first pattern and the second pattern with respect to user data corresponding to background operations or background operations on the memory device.

The memory system and method of operation of the memory system according to embodiments of the present invention minimize the complexity and performance degradation of the memory system and maximize the efficiency of use of the memory device to quickly and reliably process the data to the memory device have.

1 schematically illustrates an example of a data processing system including a memory system in accordance with an embodiment of the present invention;
Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention;
3 schematically shows a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention.
Figure 4 schematically illustrates a memory device structure in a memory system according to an embodiment of the present invention;
FIGS. 5 to 8 are diagrams schematically illustrating an example of a data processing operation when performing a plurality of command operations corresponding to a plurality of commands in a memory system according to an embodiment of the present invention; FIG.
9 is a diagram schematically illustrating an operation process of processing data in a memory system according to an embodiment of the present invention;
10 to 18 schematically illustrate other examples of a data processing system including a memory system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation according to the present invention will be described, and the description of other parts will be omitted so as not to disturb the gist of the present invention.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 1, a data processing system 100 includes a host 102 and a memory system 110.

And the host 102 includes electronic devices such as portable electronic devices such as mobile phones, MP3 players, laptop computers, or the like, or electronic devices such as desktop computers, game machines, TVs, projectors and the like, i.e. wired and wireless electronic devices.

The host 102 also includes at least one operating system (OS), which generally manages and controls the functionality and operation of the host 102, And provides interoperability between the user using the memory system 110 and the host 102. [ Here, the operating system supports functions and operations corresponding to the purpose and use of the user, and can be classified into a general operating system and a mobile operating system according to the mobility of the host 102, for example. In addition, the general operating system in the operating system may be classified into a personal operating system and an enterprise operating system according to the user's use environment. For example, the personal operating system may include a service providing function System, including windows and chrome, and enterprise operating systems are specialized systems for securing and supporting high performance, including Windows servers, linux, and unix . ≪ / RTI > In addition, the mobile operating system in the operating system may be a system characterized by supporting mobility service providing functions and a power saving function of the system for users, and may include android, iOS, windows mobile, and the like . At this time, the host 102 may include a plurality of operating systems and also executes the operating system to perform operations with the memory system 110 corresponding to a user request. Here, the host 102 transmits a plurality of commands corresponding to a user request to the memory system 110, whereby the memory system 110 performs operations corresponding to commands, that is, operations corresponding to the user request .

The memory system 110 also operates in response to requests from the host 102, and in particular stores data accessed by the host 102. In other words, the memory system 110 may be used as the main memory or auxiliary memory of the host 102. [ Here, the memory system 110 may be implemented in any one of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may be a solid state drive (SSD), an MMC, an embedded MMC, an RS-MMC (Reduced Size MMC), a micro- (Universal Flash Storage) device, a Compact Flash (CF) card, a Compact Flash (CF) card, a Compact Flash A memory card, a smart media card, a memory stick, or the like.

In addition, the storage devices implementing the memory system 110 may include a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, a read only memory (ROM), a magnetic random access memory (MROM) Volatile memory device such as a ROM, an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a ferromagnetic ROM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM) Can be implemented.

The memory system 110 also includes a memory device 150 that stores data accessed by the host 102 and a controller 130 that controls data storage in the memory device 150. [

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. In one example, controller 130 and memory device 150 may be integrated into a single semiconductor device to configure an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be further improved. In addition, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form a memory card. For example, a PC card (PCMCIA), a compact flash card (CF) , Memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash memory can do.

In another example, memory system 110 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet ), A tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a smart television, a digital audio a recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a data center, Constitute Storage, an apparatus capable of transmitting and receiving information in a wireless environment, one of various electronic apparatuses constituting a home network, one of various electronic apparatuses constituting a computer network, one of various electronic apparatuses constituting a telematics network, (radio frequency identification) device, or one of various components that constitute a computing system.

Meanwhile, the memory device 150 in the memory system 110 can maintain the stored data even when no power is supplied, and in particular, can store data provided from the host 102 through a write operation, ) Operation to the host 102. Here, the memory device 150 includes a plurality of memory blocks 152,154 and 156, each memory block 152,154, 156 including a plurality of pages, Includes a plurality of memory cells to which a plurality of word lines (WL) are connected. The memory device 150 also includes a plurality of memory dies including a plurality of planes, each of which includes a plurality of memory blocks 152, 154, 156, respectively, Lt; / RTI > In addition, the memory device 150 may be a non-volatile memory device, e.g., a flash memory, wherein the flash memory may be a three dimensional stack structure.

Here, the structure of the memory device 150 and the three-dimensional solid stack structure of the memory device 150 will be described in more detail below with reference to FIGS. 2 to 4, and a plurality of memory blocks 150, A plurality of memory dies each including a plurality of planes, and a memory device 150 including a plurality of memory dies will now be described in more detail in FIG. 6, A detailed description thereof will be omitted.

The controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102. [ For example, the controller 130 provides data read from the memory device 150 to the host 102 and stores data provided from the host 102 in the memory device 150, Write, program, erase, and the like of the memory device 150 in accordance with an instruction from the control unit 150. [

More specifically, the controller 130 includes a host interface (Host I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, A power management unit (PMU) 140, a memory interface (I / F) unit 142, and a memory 144.

In addition, the host interface unit 132 processes commands and data of the host 102, and may be a USB (Universal Serial Bus), a Multi-Media Card (MMC), a Peripheral Component Interconnect- , Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE) A Mobile Industry Processor Interface), and the like. Here, the host interface unit 132 is an area for exchanging data with the host 102, and is driven through firmware called a host interface layer (HIL) .

In addition, the ECC unit 138 corrects the error bits of the data to be processed in the memory device 150, and may include an ECC encoder and an ECC decoder. Here, the ECC encoder performs error correction encoding of data to be programmed in the memory device 150, generates data to which a parity bit is added, and data to which a parity bit is added, May be stored in memory device 150. The ECC decoder detects and corrects errors contained in the data read from the memory device 150 when reading the data stored in the memory device 150. [ In other words, the ECC unit 138 performs error correction decoding on the data read from the memory device 150, determines whether or not the error correction decoding is successful, and outputs an instruction signal, for example, an error A correction success / fail signal is output, and the parity bit generated in the ECC encoding process is used to correct the error bit of the read data. At this time, when the number of error bits exceeds the correctable error bit threshold value, the ECC unit 138 can output an error correction failure signal that can not correct the error bit and can not correct the error bit.

Here, the ECC unit 138 includes a low density parity check (LDPC) code, a Bose, a Chaudhri, and a Hocquenghem code, a turbo code, a Reed-Solomon code, Error correction can be performed using coded modulation such as convolutional code, recursive systematic code (RSC), trellis-coded modulation (TCM), and block coded modulation (BCM) It is not. In addition, the ECC unit 138 may include all of the circuits, modules, systems, or devices for error correction.

The PMU 140 provides and manages the power of the controller 130, that is, the power of the components included in the controller 130. [

The memory interface unit 142 also performs the interfacing between the controller 130 and the memory device 150 to control the memory device 150 in response to a request from the host 102 Memory / storage interface. Here, the memory interface unit 142 may be implemented as a NAND flash controller (NFC: NAND flash controller) when the memory device 150 is a flash memory, and in particular, when the memory device 150 is a NAND flash memory, Generates control signals for the memory device 150 and processes the data. The memory interface unit 142 is an interface for processing commands and data between the controller 130 and the memory device 150, for example, the operation of the NAND flash interface, in particular, the data between the controller 130 and the memory device 150 And can be driven through a firmware called a flash interface layer (FIL) as an area for exchanging data with the memory device 150.

The memory 144 is an operation memory of the memory system 110 and the controller 130 and stores data for driving the memory system 110 and the controller 130. [ The memory 144 controls the memory device 150 in response to a request from the host 102 such that the controller 130 is able to control the operation of the memory device 150, The controller 130 provides data to the host 102 and stores the data provided from the host 102 in the memory device 150 for which the controller 130 is responsible for reading, erase, etc., this operation is stored in the memory system 110, that is, data necessary for the controller 130 and the memory device 150 to perform operations.

The memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), or a dynamic random access memory (DRAM). In addition, the memory 144 may be internal to the controller 130 or external to the controller 130, as shown in FIG. 1, wherein data from the controller 130 via the memory interface And may be implemented as an external volatile memory that is input and output.

The memory 144 also stores data necessary for performing operations such as data writing and reading between the host 102 and the memory device 150 and data for performing operations such as data writing and reading as described above And includes a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a map buffer / cache, and the like for storing data.

The processor 134 controls the overall operation of the memory system 110 and controls the program operation or read operation for the memory device 150 in response to a write request or a read request from the host 102 do. Here, the processor 134 drives firmware called a Flash Translation Layer (FTL) to control all operations of the memory system 110. The processor 134 may also be implemented as a microprocessor or a central processing unit (CPU).

The controller 130 performs the requested operation from the host 102 through the processor 134 implemented in a microprocessor or central processing unit (CPU) or the like in the memory device 150, 102 to the memory device 150. The memory device 150 is a memory device. Here, the controller 130 performs a foreground operation by a command operation corresponding to a command received from the host 102, for example, performs a program operation corresponding to a write command, a read operation corresponding to a read command, An erase operation corresponding to an erase command and a parameter set operation corresponding to a set parameter command or a set feature command with a set command.

The controller 130 may then perform a background operation on the memory device 150 via a processor 134 implemented as a microprocessor or a central processing unit (CPU). Here, the background operation for the memory device 150 is an operation for copying and storing the data stored in an arbitrary memory block in the memory blocks 152, 154 and 156 of the memory device 150 to another arbitrary memory block, For example, a garbage collection (GC) operation, an operation of swapping data between memory blocks 152, 154, 156 of memory device 150 or between data stored in memory blocks 152, 154, 156, WL, Wear Leveling) operation, storing the map data stored in the controller 130 in the memory blocks 152, 154, 156 of the memory device 150, such as a map flush operation, A bad block management operation for checking bad blocks in a plurality of memory blocks 152, 154 and 156 included in the memory device 150 and for processing the bad blocks, And the like.

In addition, in the memory system according to the embodiment of the present invention, for example, the controller 130 performs a plurality of command operations corresponding to a plurality of commands received from the host 102, for example, A plurality of read operations corresponding to a plurality of read commands and a plurality of erase operations corresponding to a plurality of erase commands are performed in the memory device 150, And updates the meta data, particularly the map data, correspondingly to the performance. For example, in the memory system according to the embodiment of the present invention, when the controller 130 receives a plurality of commands from the host 102, and particularly receives the read commands or the write commands, A pattern of read operations or write operations corresponding to read commands or write commands or a pattern of data corresponding to read operations or write operations, Loads the metadata, in particular map data, corresponding to the operations or write operations into the memory 144 of the controller 130 and places the pattern 144 in the memory 144 of the controller 130 according to the identified pattern After assigning pattern zones, each map data is loaded into corresponding pattern zones. In addition, in the memory system according to the embodiment of the present invention, when the controller 130 performs background operations on the memory device 150, a pattern of back-ground operations or a pattern of data corresponding to background operations And loads the metadata corresponding to the background operations, in particular the map data, into the memory 144 of the controller 130 according to the identified pattern, and the memory 144 of the controller 130 ), And then loads the respective map data into the corresponding pattern zones. Here, in the memory system according to the embodiment of the present invention, the command operations corresponding to the plurality of cursors received from the host 102, and the operation for managing after loading the map data corresponding to the command operations Will be described in more detail later with reference to Figs. 5 to 9, and a detailed description thereof will be omitted here.

In addition, the processor 134 of the controller 130 may include a management unit (not shown) for performing bad management of the memory device 150, and the management unit may include a plurality The bad blocks are checked in the memory blocks 152, 154, and 156 of the bad blocks, and bad block management is performed to bad check the bad blocks. Bad management can be used to prevent a data light, for example, a program failure in a data program, due to a characteristic of the NAND when the memory device 150 is a flash memory, for example, a NAND flash memory, This means that the failed memory block is bad-processed and the program failed data is written to the new memory block, that is, programmed. In addition, when the memory device 150 has a three-dimensional solid stack structure as described above, if the block is processed as a bad block in response to a program failure, the utilization efficiency of the memory device 150 and the memory system 100 ), The reliability of the bad block management needs to be more reliably managed. Hereinafter, the memory device in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIG. 2 to FIG.

Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention, Figure 3 schematically illustrates a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention. FIG. 4 is a view schematically showing a memory device structure in a memory system according to an embodiment of the present invention, and schematically shows a structure when the memory device is implemented as a three-dimensional nonvolatile memory device .

2, the memory device 150 includes a plurality of memory blocks, such as BLK 0 (Block 0) 210, BLK 1 220, BLK 2 s 230), and block N-1 (BLKN-1) (240) each block comprising a (210 220 230 240) is a plurality of pages (pages), for example, 2 ^M of pages (2 including ^M pages) do. Here, for convenience of explanation, it is assumed that a plurality of memory blocks each include 2 ^M pages, but a plurality of memories may include M pages each. Each of the pages includes a plurality of memory cells to which a plurality of word lines (WL) are connected.

In addition, the memory device 150 may include a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, Multi Level Cell) memory block or the like. Here, the SLC memory block includes a plurality of pages implemented by memory cells storing one bit of data in one memory cell, and has high data operation performance and high durability. And, the MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (e.g., two bits or more) in one memory cell, Space, in other words, can be highly integrated. In particular, the memory device 150 may be an MLC memory block, as well as an MLC memory block including a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell, A triple level cell (TLC) memory block including a plurality of pages implemented by memory cells capable of storing bit data, a plurality of memory cells that are implemented by memory cells capable of storing 4-bit data in one memory cell, A Quadruple Level Cell (QLC) memory block containing pages of memory cells, or a plurality of pages implemented by memory cells capable of storing 5 bits or more of bit data in one memory cell A multiple level cell memory block, and the like.

In the embodiment of the present invention, for convenience of explanation, the memory device 150 is implemented as a non-volatile memory such as a flash memory, for example, a NAND flash memory, (RRAM), a ferroelectrics random access memory (FRAM), and a spin injection magnetic memory (STT-RAM): Spin Transfer Torque Magnetic Random Access Memory), or the like.

Each of the blocks 210, 220, 230 and 240 stores data provided from the host 102 through a program operation and provides the stored data to the host 102 through a read operation.

3, each memory block 330 in the plurality of memory blocks 152, 154, 156 included in the memory device 150 of the memory system 110 is implemented as a memory cell array, and bit lines BL0 to BLm-1, respectively. The cell string 340 of each column may include at least one drain select transistor DST and at least one source select transistor SST. Between the selection transistors DST and SST, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series. Each of the memory cells MC0 to MCn-1 may be configured as an MLC that stores data information of a plurality of bits per cell. Cell strings 340 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

3 illustrates each memory block 330 configured as a NAND flash memory cell. However, a plurality of memory blocks 152, 154, and 156 included in the memory device 150 according to the embodiment of the present invention may include NAND flash memory NOR-type flash memory, a hybrid flash memory in which two or more kinds of memory cells are mixed, and a one-NAND flash memory in which a controller is embedded in a memory chip, can be realized. In addition, the memory device 150 according to the embodiment of the present invention may include a flash memory device in which the charge storage layer is composed of a conductive floating gate, a Charge Trap Flash (CTF) memory Device, or the like.

The voltage supply unit 310 of the memory device 150 may supply the word line voltages (e.g., program voltage, read voltage, pass voltage, etc.) to be supplied to the respective word lines in accordance with the operation mode, (For example, a well region) in which the voltage supply circuit 310 is formed, and the voltage generation operation of the voltage supply circuit 310 may be performed under the control of a control circuit (not shown). In addition, the voltage supplier 310 may generate a plurality of variable lead voltages to generate a plurality of lead data, and may supply one of the memory blocks (or sectors) of the memory cell array in response to the control of the control circuit Select one of the word lines of the selected memory block, and provide the word line voltage to the selected word line and unselected word lines, respectively.

In addition, the read / write circuit 320 of the memory device 150 is controlled by a control circuit and operates as a sense amplifier or as a write driver depending on the mode of operation . For example, in the case of a verify / normal read operation, the read / write circuit 320 may operate as a sense amplifier for reading data from the memory cell array. In addition, in the case of a program operation, the read / write circuit 320 can operate as a write driver that drives bit lines according to data to be stored in the memory cell array. The read / write circuit 320 may receive data to be written into the cell array from a buffer (not shown) during a program operation, and may drive the bit lines according to the input data. To this end, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324 and 326, respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs) And each page buffer 322, 324, 326 may include a plurality of latches (not shown).

In addition, the memory device 150 may be implemented as a two-dimensional or three-dimensional memory device, and may be implemented as a non-volatile memory device of a three-dimensional solid stack structure, Structure, it may include a plurality of memory blocks BLK0 to BLKN-1. 4 is a block diagram showing memory blocks 152, 154 and 156 of the memory device 150 shown in FIG. 1, wherein each of the memory blocks 152, 154 and 156 is implemented as a three-dimensional structure (or vertical structure) . For example, each of the memory blocks 152,154, 156 may include structures extending along first to third directions, e.g., x-axis, y-axis, and z- . ≪ / RTI >

Each memory block 330 included in the memory device 150 may include a plurality of NAND strings NS extending along a second direction and may include a plurality of NAND strings arranged along the first and third directions. NAND strings NS may be provided. Here, each NAND string NS includes a bit line BL, at least one string select line SSL, at least one ground select line GSL, a plurality of word lines WL, at least one dummy word Line DWL, and a common source line CSL, and may include a plurality of transistor structures TS.

That is, in the plurality of memory blocks 152, 154, 156 of the memory device 150, each memory block 330 includes a plurality of bit lines BL, a plurality of string select lines SSL, May be coupled to a plurality of NAND strings GSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL, . In addition, in each memory block 330, a plurality of NAND strings NS may be connected to one bit line BL, and a plurality of transistors may be implemented in one NAND string NS. The string selection transistor SST of each NAND string NS may be connected to the corresponding bit line BL and the ground selection transistor GST of each NAND string NS may be connected to the common source line CSL, Lt; / RTI > Here, memory cells MC are provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS, that is, a plurality of memory blocks 152, 154 and 156 of the memory device 150 are provided, In block 330, a plurality of memory cells may be implemented. 5 to 9, the data processing to the memory device in the memory system according to the embodiment of the present invention, in particular, a plurality of commands corresponding to the commands by receiving the plurality of commands from the host 102 The data processing operation in the case of performing the operations will be described in more detail.

5 to 8 are views for schematically explaining an example of a data processing operation when performing a plurality of command operations corresponding to a plurality of commands in the memory system according to the embodiment of the present invention. Here, in the embodiment of the present invention, for convenience of explanation, the memory system 110 shown in FIG. 1 receives a plurality of commands from the host 102 and performs command operations corresponding to the commands, for example, 102 to perform a program operation corresponding to the write commands or to receive a plurality of read commands from the host 102 and to perform a read operation corresponding to the read commands And performs erase operations corresponding to the erase commands by receiving a plurality of erase commands received from the host 102 or performing a plurality of write commands and a plurality of read commands from the host 102, When the program operations and the read operations corresponding to the write commands and the read commands are performed together with the commands One example will be described in detail.

In the embodiment of the present invention, write data corresponding to a plurality of write commands received from the host 102 is stored in a buffer / cache included in the memory 144 of the controller 130 And then programs the data stored in the buffer / cache into a plurality of memory blocks included in the memory device 150 to store and thus perform program operations, and in response to program operations to the memory device 150 After updating the map data, if updated map data is stored in a plurality of memory blocks included in the memory device 150, that is, program operations corresponding to a plurality of write commands received from the host 102 Will be described as an example. In the embodiment of the present invention, when a plurality of read commands are received from the host 102 with respect to the data stored in the memory device 150, map data of the data corresponding to the read commands is checked, Reads the data corresponding to the read commands from the host 150 and stores the read data in the buffer / cache included in the memory 144 of the controller 130, That is, a case in which the read operations corresponding to the plurality of read commands received from the host 102 are performed will be described as an example. In the embodiment of the present invention, when a plurality of erase commands are received from the host 102 for the memory blocks included in the memory device 150, memory blocks corresponding to erase commands are checked , Erases the data stored in the identified memory blocks, updates the map data according to the erased data, and then stores the updated map data in the plurality of memory blocks included in the memory device 150, that is, A case in which erase operations corresponding to a plurality of erase commands received from the host 102 are performed will be described as an example.

In the embodiment of the present invention, for convenience of explanation, the command operations in the memory system 110 are performed by the controller 130 as an example. However, as described above, in the controller 130, The embedded processor 134 may perform, for example, via FTL. In the embodiment of the present invention, the controller 130 includes user data and meta data corresponding to the write commands received from the host 102 in the memory device 150 Or the user data and the metadata corresponding to the read commands received from the host 102 into the memory blocks of the plurality of memory blocks included in the memory device 150 Read from the arbitrary memory blocks and provide the host 102 with user data and metadata corresponding to erase commands received from the host 102 to a plurality of memory blocks 150 included in the memory device 150 Lt; / RTI > in any of the memory blocks.

Here, the meta data includes a logical address (logical address) including information on logical / physical (L2P) information (hereinafter referred to as logical information) for data stored in the memory blocks, 1 map data, and second map data including physical / logical (P2L) information (hereinafter referred to as "physical information"), Information on command data corresponding to the command, information on the command operation corresponding to the command, information on the memory blocks of the memory device 150 on which the command operation is performed, and map data corresponding to the command operation . In other words, the metadata may include all the information and data except for the user data corresponding to the command received from the host 102. [

That is, in the embodiment of the present invention, when the controller 130 performs command operations corresponding to a plurality of commands received from the host 102, for example, when receiving a plurality of write commands from the host 102, And the user data corresponding to the write commands may be transferred to memory blocks of the memory device 150, for example, empty memory blocks subjected to erase operations in the memory blocks, The data is written into open memory blocks or free memory blocks and stored between logical addresses and physical addresses of user data stored in memory blocks. The first map data including the mapping information, that is, the L2P map table or the L2P map list in which the logical information is recorded, The second map data including the mapping information between the physical address and the logical address for the blocks, that is, the P2L map table or the P2L map list in which the physical information is recorded, is stored in the empty memory blocks in the memory blocks of the memory device 150, Open memory blocks, or free memory blocks.

Here, when receiving the write commands from the host 102, the controller 130 writes the user data corresponding to the write commands to the memory blocks and stores the user data in the memory blocks, and the first map for the user data stored in the memory blocks And stores the metadata including the data and the second map data in the memory blocks. In particular, the controller 130 determines whether the data segments of the user data are stored in the memory blocks of the memory device 150, in accordance with the meta segments of the meta data, Generates and updates the L2P segments of the first map data and the P2L segments of the second map data with segment segments and then stores the segments in the memory blocks of the memory device 150, The map segments stored in the memory blocks of the controller 130 are loaded into the memory 144 included in the controller 130, and then the map segments are updated.

When receiving a plurality of read commands from the host 102, the controller 130 reads the read data corresponding to the read commands from the memory device 150 and outputs the read data corresponding to the read commands to the memory 144 of the controller 130, And then provides data stored in the buffer / cache from the host 102 to perform read operations corresponding to a plurality of read commands.

When receiving a plurality of erase commands from the host 102, the controller 130 identifies memory blocks of the memory device 150 corresponding to erase commands, and then performs erase operations on the memory blocks 150 Lt; / RTI > Hereinafter, the data processing operation in the memory system of the present invention will be described in more detail with reference to FIG. 5 to FIG.

5, the controller 130 executes command operations corresponding to a plurality of commands received from the host 102, for example, a program corresponding to a plurality of write commands received from the host 102 Programs the user data corresponding to the write commands to the memory blocks 552, 554, 562, 564, 572, 574, 582, 584 of the memory device 150 and also stores user data corresponding to the program operation to the memory blocks 552, 554, And then stores the generated metadata in the memory blocks 552, 554, 562, 564, 572, 574, 582, 584 of the memory device 150. [

Here, the controller 130 generates and updates information indicating that user data is stored in pages included in (552, 554, 562, 564, 572, 574, 582, 584) of the memory device 150, for example, first map data and second map data, After generating and updating the logical segments of one map data, i.e., L2P segments, and the physical segments of the second map data, i.e., P2L segments, a page contained in memory blocks 552, 554, 562, 564, 572, 574, 582, 584 of memory device 150 Lt; / RTI >

For example, the controller 130 caches and buffers the user data corresponding to the write commands received from the host 102 into the first buffer 510 included in the memory 144 of the controller 130 the data segments 512 of the user data are stored in the first buffer 510 which is the data buffer / cache and the data segments 512 stored in the first buffer 510 are stored in the memory device 150, 552, 554, 562, 564, 572, 574, 582, 584 in the pages included in the memory blocks 552, 554, The controller 130 then causes the data segments 512 of the user data corresponding to the write commands received from the host 102 to be written to pages included in the memory blocks 552, 554, 562, 564, 572, 574, 582, 584 of the memory device 150 The first map data and the second map data are generated and updated as they are stored in the second buffer 520 included in the memory 144 of the controller 130. That is, The L2P segments 522 of the data and the P2L segments 524 of the second map data are stored in the second buffer 520 which is the map buffer / cache. Here, the L2P segments 522 of the first map data and the P2L segments 524 of the second map data are stored in the second buffer 520 in the memory 144 of the controller 130 Or a map list for the L2P segments 522 of the first map data and a map list for the P2L segments 524 of the second map data may be stored. In addition, the controller 130 stores the L2P segments 522 of the first map data and the P2L segments 524 of the second map data stored in the second buffer 520 in the memory blocks 150 of the memory device 150 (Pages 552, 554, 562, 564, 572, 574, 582, 584).

The controller 130 also performs command operations corresponding to a plurality of commands received from the host 102, for example, performs read operations corresponding to a plurality of read commands received from the host 102, The map segments of the map data for the user data corresponding to the read commands such as the L2P segments 522 of the first map data and the P2L segments 524 of the second map data are stored in the second buffer 520 Reads the user data stored in the pages of the corresponding memory blocks in the memory blocks 552, 554, 562, 564, 572, 574, 582, 584 of the memory device 150 and reads the data segments 512 of the read user data from the first buffer 510 And then provides it to the host 102. [

In addition, the controller 130 performs command operations corresponding to the plurality of commands received from the host 102, for example, performs erase operations corresponding to a plurality of erase commands received from the host 102 At this time, the memory blocks corresponding to the erase commands are confirmed by the memory blocks 552, 554, 562, 564, 572, 572, 574, 582, 584 of the memory device 150, and erase operations are performed on the confirmed memory blocks.

When the controller 130 performs a background operation, for example, copying or swapping data in the memory blocks included in the memory device 150, for example, a garbage collection operation or a wear leveling operation, The data segments 512 of the corresponding user data are stored in the first buffer 510 and the map segments 522 and 524 of the map data corresponding to the user data are loaded into the second buffer 520, Operation or wear leveling operation.

6, memory device 150 includes a plurality of memory dies, such as memory die 0 610, memory die 1 630, memory die 2 650, memory die 3 610, Each memory die 610,630,650,670 includes a plurality of planes, such as memory die 0 610, including planes 0 612, planes 1 616, And memory die 1 630 includes planes 0 632, planes 1 636, planes 2 640, planes 3 612, 644 and memory die 2 650 includes plane 0 652, plane 1 656, plane 2 660, plane 3 664, and memory die 3 670 Includes plane 0 672, plane 1 676, plane 2 680, and plane 3 684. Each of the planes 612, 616, 620, 624, 632, 636, 640, 644, 652, 666, 640, 644, 652, 656, 660, 664, 652, 666, 684 of the memory dies 610, 630, 650, 670 included in the memory device 150 may include a plurality of memory blocks 614, 618, 622, 626, 634, 638, 642, 646, 654, s, for example 2 includes ^M number of pages (pages 2 ^M) of N blocks (Block0, Block1, ..., block N-1) comprising a. Memory device 150 also includes a plurality of buffers corresponding to respective memory dies 610, 630, 650 and 670, such as buffer 0 628 corresponding to memory die 0 610, Buffer 1 648, buffer 2 668 corresponding to memory die 2 650, and buffer 3 688 corresponding to memory die 3 670.

When the command operations corresponding to the plurality of commands received from the host 102 are performed, the buffers 628, 648, 66, and 688 included in the memory device 150 store data corresponding to the command operations . For example, when performing program operations, data corresponding to program operations is stored in buffers 628, 648, 66, and 888 and then stored in pages included in memory blocks of memory dies 610, 630, 650, and 670, The data corresponding to the read operations is read from the pages included in the memory blocks of the memory dies 610, 630, 650 and 670 and stored in the buffers 628, 648, 66 and 888, (Not shown).

Here, in the embodiment of the present invention, for convenience of explanation, it is assumed that the buffers 628, 648, 668, and 688 included in the memory device 150 exist outside the corresponding memory dies 610, 630, 650 and 670 respectively, 630, 650, and 670, respectively, and buffers 628, 648, 668, and 680 may also correspond to the respective planes 612, 616, 620, 620, 644, 652, 666, 640, 644, 652, 666, 684, 666, 664, 686, 680, 684 or the respective memory blocks 614, 618, 662, 646, 654, 658, 662, 646, 654, have. In the embodiment of the present invention, for convenience of explanation, the buffers 628, 648, 668, and 688 included in the memory device 150 are connected to a plurality of page buffers (not shown) included in the memory device 150, 322, 324, and 326, but may be a plurality of caches or a plurality of registers included in the memory device 150. [

In addition, the plurality of memory blocks included in the memory device 150 may be grouped into a plurality of super memory blocks, and then command operations may be performed in the plurality of super memory blocks. Here, each super memory block includes a plurality of memory blocks, for example, memory blocks included in a first memory block group and a second memory block group, wherein the first memory block group includes any one of the first memory die The second memory block group is included in the first plane of the first memory die or is included in the second plane of the first memory die and the second memory block group is included in the first plane of the second memory die, . ≪ / RTI > 7 and 8, in a memory system according to an embodiment of the present invention, a plurality of commands are received from the host 102 to perform command operations, or to a memory device (not shown) 150, the operation of loading and managing metadata, particularly map data, into the memory 144 of the controller 130 will be described in more detail with reference to an example.

7, when receiving a plurality of commands, for example, a plurality of read commands from the host 102, the controller 130 reads out the read operations corresponding to the plurality of read commands received from the host 102 In a plurality of memory blocks included in the memory device 150. In other words, as described above, the controller 130 stores map segments of map data for user data corresponding to a plurality of read commands received from the host 102 in the memory 144 of the controller 130 The user data is read from the plurality of memory blocks included in the memory device 150 and the read user data is stored in the memory 144 of the controller 130 And then provides the user data to the host 102. The host computer 102 receives the user data from the first buffer 510,

Here, in the embodiment of the present invention, for convenience of explanation, when a plurality of commands, particularly a plurality of read commands, are received from the host 102 and then the read operations corresponding to the plurality of read commands are performed However, even when program operations or erase operations corresponding to a plurality of write commands or erase commands are performed after receiving a plurality of write commands or erase commands, the same applies . In the embodiment of the present invention, for convenience of description, the case of performing command operations corresponding to a plurality of commands received from the host 102 will be described as an example, The same applies to the case of performing background operations.

In other words, in the memory system according to the embodiment of the present invention, when receiving a plurality of commands from the host 102, the controller 130 determines whether or not a plurality of commands corresponding to the patterns and commands of the plurality of commands received from the host 102 A pattern of command operations, or a pattern of data corresponding to command operations. Here, the patterns for the commands, command operations, or data include a normal pattern in the first pattern and a sequential pattern in the second pattern, and the patterns for the commands received from the host 102 The command pattern, the execution pattern of the command operations performed in the memory device 130 corresponding to the cursors, or the data corresponding to the command operations, particularly the data pattern of the user data.

The normal pattern of the first pattern means a pattern in which information on commands, command operations, or user data is discontinuous. For example, identification information of commands, order information of command operations, The logical information of the user data, such as LBA (Logical Block Address) or LPN (Logical Page Number), is a discontinuous pattern. In addition, the sequential pattern of the second pattern means a continuous pattern of information on commands, command operations, or user data, such as identification information of commands, order information of command operations, 150), logical information of user data, such as LBA or LPN, means a continuous pattern. For example, the user data of the first pattern, that is, the normal user data, is user data having one or a number of LBAs or LPNs equal to or less than the threshold number, and user data having a data size of a critical size or less, And the connection pattern or access frequency to the user data may be hot data that is equal to or higher than a threshold value. In addition, the user data of the second pattern, that is, the sequential user data, is user data having a plurality of consecutive LBAs or LPNs equal to or more than the threshold number, and user data having a data size of a critical size or more, And the connection pattern or access frequency to the user data may be cold data below the threshold value.

In addition, when receiving a plurality of commands from the host 102, the controller 130 determines whether a plurality of commands received from the host 102, for example, a plurality of read commands, are normal read commands or sequential read commands For example, whether or not the read operations corresponding to the plurality of commands, that is, the read operations corresponding to the read commands, are the normal read operations or the sequential read operations, or the user data corresponding to the command operations, For example, it is confirmed whether the user data corresponding to the read operations is the normal user data or the sequential user data. In addition, the controller 130 identifies a pattern of background operations when performing background operations on the memory device 150. Here, the controller 130 determines whether the background operations for the memory device 150 are normal background operations or sequential background operations, or whether the user data corresponding to the background operations is normal user data or a sequential user Check the data integrity.

The controller 130 controls the first and second patterns identified in correspondence with the plurality of commands received from the host 102 when receiving a plurality of commands from the host 102, Included in the memory 144 of the controller 130, in accordance with the first pattern and the second pattern identified corresponding to the background operations when performing background operations on the memory device 150, The map buffer or the map cache in which the map data for the user data is loaded in the memory 144 of the controller 130 is allocated as pattern zones, Allocate to the pattern zone. Here, the controller 130 allocates the map buffer or the map cache included in the memory 144 of the controller 130 as a first pattern zone dynamically according to the first pattern and the second pattern , Or a first pattern and a second pattern zone.

The controller 130 also stores map segments of map data corresponding to the command operations or background operations to the second The controller 130 loads the map segments of the map data corresponding to the first pattern into the first pattern zone allocated to the memory 144 of the controller 130, The map segments of the map data corresponding to the pattern are loaded in the second pattern zone allocated to the memory 144 of the controller 130 and then the first pattern zone or the second pattern Manages map segments loaded into the zone. Hereinafter, a case in which the controller 130 receives a plurality of read commands from the host 102 will be described in more detail as an example.

For example, when receiving the first group read commands from the host 102, the controller 130 generates a pattern for the first group read commands, a first group read command operations corresponding to the first group read commands Or pattern for the first group user data corresponding to the first group read command operations. Here, the controller 130 confirms that the first group read commands, the first group read command operations, or the first group user data are the first pattern, that is, the first group read commands are the normal read commands, It is confirmed that the first group read operations corresponding to the one group read commands are the normal read operations or the first group user data corresponding to the first group read operations is the normal user data.

The controller 130 then assigns the second buffer 700 included in the memory 144 of the controller 130 to the first pattern zone 700. In addition, the controller 130 may be configured to perform first group read operations, that is, map segments of the first group map data for the first group user data to read the first group user data in the memory device 150 The first group read command operations, or the first group user data are the first pattern, the first group read commands, the first group read command operations, or the first group user data are loaded into the memory 144 of the controller 130, The map segments 712, 714, 716, 718, 720, 722, 724, 726 of the first group map data corresponding to the 1 pattern are loaded into the first pattern zone 700 in the memory 144 of the controller 130. Here, the map segments 712, 714, 716, 718, 720, 722, 724, 726 of the first group map data corresponding to the first pattern may have a first unit size, for example, 2K size, The map segments 712, 714, 716, 718, 720, 722, 724, and 726 of the map data are loaded into the first pattern zone 700 in the first unit size.

In other words, the controller 130 determines that the map segments 712, 714, 716, 718, 720, 722, 724, 726 of the first group map data are not present in the second buffer 700, In the memory blocks, the map segments 712, 714, 716, 718, 720, 722, 724, 726 of the first group map data are read and loaded into the first pattern zone 700. At this time, the controller 130 is connected to the memory device 150 through a plurality of buffers 628, 648, 668, 688 corresponding to a plurality of memory dies, a plurality of flags, or a plurality of memory blocks, respectively, , Map segments 712, 714, 716, 718, 720, 722, 724, 726 are read from memory blocks of memory device 150 and then loaded into memory 144 of controller 130. Here, the map segments 712, 714, 716, 728, 720, 722, 724, and 726 are read from the memory blocks of the memory device 150 in the first unit size and then read from the memory 144 of the controller 130, And the loading operation of the map segments 712, 714, 716, 718, 720, 722, 724, and 726 will be described in detail with reference to FIG. 8, and a detailed description thereof will be omitted here.

The controller 130 also manages the map segments 712, 714, 716, 718, 720, 722, 724, 726 loaded in the first pattern zone 700 according to MRU (Most Recently Used) 702 / LRU (Least Recently Used) 704 . In particular, controller 130 maintains map segments 712, 714, 716, 718, 720, 722, 724, 726 in second buffer 700 or first pattern zone 700 according to MRU 702 / LRU 704, 150, and then discards the map. Here, the controller 130 may manage a list of map segments 712, 714, 716, 718, 720, 722, 724, and 726 stored in the first pattern zone 700, for example, an MRU / LRU list.

In addition, the controller 130 reads the first group user data from the memory blocks of the memory device 150 through the map segments 712, 714, 716, 718, 720, 722, 724, 726 of the first group map data loaded in the first pattern zone 700 The first group user data read from the memory device 150 is stored in the first buffer 510 included in the memory 144 of the controller 130, 1 < / RTI > buffer 510 to the host 102. The first group user data stored in the first buffer < RTI ID = 0.0 > Here, when the first group user data is read from the memory blocks of the memory device 150, the controller 130 controls the plurality of memory dies in the memory device 150, The first group user data is read from the memory blocks of the memory device 150 through the plurality of buffers 628, 648, 668 and 688 corresponding to the plurality of memory blocks, And the read operation of the first group user data has been described in detail with reference to FIGS. 5 and 6, and a detailed description thereof will be omitted here.

When the second group read commands are received from the host 102, the controller 130 generates a pattern for the second group read commands, second group read command operations corresponding to the second group read commands Or a pattern for the second group data, in particular the second group user data, corresponding to the second group read command operations. Here, the controller 130 determines that the second group read commands, the second group read command operations, or the second group user data are the second pattern, that is, the second group read commands are the sequential read commands, It is confirmed that the second group read operations corresponding to the second group read commands are sequential read operations or the second group user data corresponding to the second group read operations is sequential user data.

The controller 130 allocates the second buffer 750 included in the memory 144 of the controller 130 to the first pattern zone 760 and the second pattern zone 780. In particular, the controller 130 determines whether the second group read commands, the second group read command operations, or the second group user data are the second pattern, as described above, In the memory 144 of the controller 130 in which the second buffer 700 is allocated to the first pattern zone 700 in accordance with the first group read commands, (760) and a second pattern zone 780 corresponding to the second group read commands. Here, the controller 130 allocates the second pattern zone 780 to the LRUs 704 and 754 of the first pattern zones 700 and 760 in the second buffers 700 and 750 included in the memory 144 of the controller 130 In particular, in the second buffer 700 allocated only to the first pattern zone 700, a partial memory zone at the location of the LRU 704 is allocated to the second pattern zone 780.

In addition, the controller 130 performs the first group read operations, that is, to read the first group user data in the memory device 150, the map segments of the first group map data for the first group user data (762, 764, 766, 768, 770, 772) to the memory (144) of the controller (130), wherein the first group read commands, the first group read command operations, or the first group user data Map segments 762, 764, 766, 768, 770, and 772 of the first group map data corresponding to the first pattern are written in the first pattern zone 731 in the second buffer 750 included in the memory 144 of the controller 130, (760). The controller 130 also performs a second group read operation, that is, a map segment of the second group map data for the second group user data to read the second group user data in the memory device 150 782 to the memory 144 of the controller 130 where the second group read commands, the second group read command operations, or the second group user data are the second pattern, The map segment 782 of the second group map data corresponding to the pattern is loaded into the second pattern zone 780 in the second buffer 750 included in the memory 144 of the controller 130.

In this case, the map segments 762, 764, 766, 768, 770, 772 of the first group map data corresponding to the first pattern may have a first unit size, for example, 2K size, The map segments 762, 764, 766, 768, 770, and 772 of the map data are loaded into the first pattern zone 760 in the first unit size. In addition, the map segment 782 of the second group map data corresponding to the second pattern may have a second unit size, for example, 32K, and the controller 130 may generate second group map data In the second pattern zone 780 with the second unit size. In particular, the second pattern zone 780 may include a map of the second group map data loaded in the second pattern zone 780. In this case, the second pattern zone 780 may have a large size as many as an integer multiple of the first unit size, Is dynamically allocated in the second buffer 750, depending on the size of the segment 782. [

In other words, when the map segments 762, 764, 766, 768, 770, 772 of the first group map data do not exist in the first pattern zone 760 of the second buffer 750, In the blocks, the map segments 762, 764, 766, 768, 770, 772 of the first group map data are read and loaded into the first pattern zone 760. At this time, the controller 130 is connected to the memory device 150 through a plurality of buffers 628, 648, 668, 688 corresponding to a plurality of memory dies, a plurality of flags, or a plurality of memory blocks, respectively, , Map segments 762, 764, 766, 768, 770, 772 are read from the memory blocks of memory device 150 and then loaded into memory 144 of controller 130. Here, the map segments 762, 764, 766, 768, 770, and 772 of the first group map data are read from the memory blocks of the memory device 150 in the first unit size, The loading operation of the map segments 762, 764, 766, 768, 770, and 772 will be described in detail with reference to FIG. 8, and a detailed description thereof will be omitted here.

When the map segment 782 of the second group map data does not exist in the second pattern zone 780 of the second buffer 750, The map segment 782 of the second group map data is read and loaded into the second pattern zone 780. [ At this time, the controller 130 is connected to the memory device 150 through a plurality of buffers 628, 648, 668, 688 corresponding to a plurality of memory dies, a plurality of flags, or a plurality of memory blocks, respectively, The map segment 782 is read from the memory blocks of the memory device 150 and then loaded into the memory 144 of the controller 130. [ Here, the map segment 782 of the second group map data may be stored in memory blocks 150 of the memory device 150 in a second unit size through an interleaving scheme for a plurality of planes or a plurality of memory dies And loaded into the memory 144 of the controller 130 in a second unit size through a plurality of page buffers and the loading operation of the map segment 782 will be described in more detail with reference to FIG. A detailed description thereof will be omitted here

The controller 130 also manages the map segments 762, 764, 766, 768, 770, 772 loaded in the first pattern zone 760 according to the MRU 752 / LRU 754. In particular, controller 130 maintains map segments 762, 764, 766, 768, 770, 772 in first pattern zone 760, or performs map flush operations to memory device 150, according to MRU 752 / LRU 754 And then discard. Here, the controller 130 may manage a list, e.g., an MRU / LRU list, of the map segments 762, 764, 766, 768, 770, 772 stored in the first pattern zone 760.

The controller 130 also determines whether or not the map segment 782 loaded in the second pattern zone 780 is in the second pattern zone 780 according to the execution of command operations or background operations on the map segment 782 loaded in the second pattern zone 780. [ ). In other words, the controller 130 performs command operations or background operations through the map segment 782 loaded in the second pattern zone 780, performs a map flush operation to the memory device 150, Card. Here, in the embodiment of the present invention, for convenience of description, one map segment 782 having a second unit size is loaded in the second pattern zone 780. However, A plurality of map segments for the data may be loaded in the second pattern zone 780. [ At this time, a plurality of map segments for the second group map data loaded in the second pattern zone 780 may be managed according to the MRU 752 / LRU 754. When a plurality of map segments for the second group map data are loaded in the second pattern zone 780, the size of the second pattern zone 780 in the memory 144 of the controller 130 is changed to the first pattern zone 780. [ The number or size of the map segments for the second group map data is increased relative to the size of the map memory 760, in other words, the map segments for the first group map data, Since only the map segments for the second group map data are present in the first group read command operations 144, the operation performance for the first group read command operations may be degraded. Therefore, in the embodiment of the present invention, One map segment 782 having a second unit size is loaded into zone 780. Here, one map segment 782 loaded in the second pattern zone 780 indicates that after the command operations or background operations on the map segment 782 are performed, the map segment for the other second group map data And discarded in the second pattern zone 780 so as to be loaded in the second pattern zone 780.

In addition, the controller 130 reads the first group user data from the memory blocks of the memory device 150 through the map segments 762, 764, 766, 768, 770, 772 of the first group map data loaded in the first pattern zone 760 The first group user data read from the memory device 150 is stored in the first buffer 510 included in the memory 144 of the controller 130, 1 < / RTI > buffer 510 to the host 102. The first group user data stored in the first buffer < RTI ID = 0.0 > Here, when the first group user data is read from the memory blocks of the memory device 150, the controller 130 controls the plurality of memory dies in the memory device 150, The first group user data is read from the memory blocks of the memory device 150 through the plurality of buffers 628, 648, 668 and 688 corresponding to the plurality of memory blocks, And the read operation of the first group user data has been described in detail with reference to FIGS. 5 and 6, and a detailed description thereof will be omitted here.

The controller 130 also reads the second group user data from the memory blocks of the memory device 150 through the map segment 782 of the second group map data loaded in the second pattern zone 780 The second group user data read from the memory device 150 is stored in the first buffer 510 included in the memory 144 of the controller 130 and the first group user data stored in the first buffer 510 included in the memory 144 of the controller 130 is stored in the first buffer 510 in response to the second group read commands, And provides the second group user data stored in the buffer 510 to the host 102. [ Here, when the second group user data is read from the memory blocks of the memory device 150, the controller 130 performs a predetermined operation on the plurality of planes or the plurality of memory dies through the interleaving method A plurality of memory dies in the memory device 150, a plurality of planes, or a plurality of memory blocks, and then to a plurality of memory dies, a plurality of planes, or a plurality of memory blocks, respectively The second group user data is stored in the memory 144 of the controller 130 through the corresponding plurality of buffers 628, 648, 668, and 688 and the read operation of the second group user data is performed in the same manner as described above with reference to FIGS. 5 and 6 The detailed description thereof will be omitted here.

Next, referring to FIG. 8, the controller 130 transmits map segments 762, 764, 766, 768, 770, 772 of the first group map data or map segments 782 of the second group map data to the memory device 150 Such as page buffers 802, 804, 806, and 808, that correspond to a plurality of memory memory dies, a plurality of memory planes, or a plurality of memory dies, respectively, in memory device 150, In the memory blocks of the memory device 150 and then loaded into the memory 144 of the controller 130. [ Here, in the embodiment of the present invention, when the page buffers 802, 804, 806, and 808 correspond to a plurality of flags, that is, when the page buffer 0 802 is a flag of the memory device 150 0, page buffer 1 804 corresponds to plane 1 of memory device 150 and page buffer 2 806 corresponds to plane 2 of memory device 150 and page buffer 3 808 The description will be made in more detail with reference to the example corresponding to the plane 3 of the memory device 150 as an example.

That is, in the memory blocks included in the plane 0 of the memory device 150, the controller 130 reads map segments 0 (850) and stores them in the page buffer 0 (802) The map segments 0 850 stored in the map memory 802 are loaded into the memory 144 of the controller 130. The controller 130 then reads the map segments 1 860 in the memory blocks included in the plane 1 of the memory device 150 and stores the read map segments 1 860 in the page buffer 1 804, 804 in the memory 144 of the controller 130. The map segment 1 860 is stored in the memory 144 of the controller 130, Controller 130 also reads map segments 2 870 in memory blocks included in plane 2 of memory device 150 and then stores them in page buffer 2 806 and reads page buffer 2 The map segment 2 870 stored in the map memory 806 is loaded into the memory 144 of the controller 130. In addition, the controller 130 reads map segments 3 (880) in the memory blocks included in the plane 3 of the memory device 150 and then stores them in the page buffer 3 (808) 808 in the memory 144 of the controller 130. The map segments 3 880 are stored in the memory 144 of the controller 130, Here, in the memory system according to the embodiment of the present invention, the controller 130 stores the map segments 762, 764, 766, 768, 770, 772 of the first group map data and the map segment 782 of the second group map data, The operation of loading data into the memory 144 will be described in more detail with reference to an example.

For example, when the first map segment 768 is loaded into the memory 144 of the controller 130 in the map segments 762, 764, 766, 768, 770, 772 of the first group map data, The first map segment 768, which leads the first map segment 768 in memory blocks, e.g., memory blocks of plane 0, leads the first map segment 852 of the map segments 0 (850) ) In the page buffer 0 (802). Here, the first map segment 768 is read in the memory blocks of plane 0 with the first unit size, so that the first map segment 852 of the map segments 0 (850) And is stored in page buffer 0 (802). The controller 130 loads the first map segment 852 stored in the page buffer 0 802 into the first pattern zone 760 with the first unit size, that is, the first map segment 852 of the first unit size, (768) into the first pattern zone (760).

The controller 130 also determines whether the second map segment 766 is to be loaded into the memory 144 of the controller 130 in the map segments 762,764,766,768,770,772 of the first group map data. The second map segment 766 leads in memory blocks, e.g., memory blocks of plane 0, and the second map segment 766 that is read leads the second map segment 854 of map segments 0 (850) ) In the page buffer 0 (802). Here, the second map segment 766 is read in the memory blocks of plane 0 with a first unit size, so that the second map segment 854 of the map segments 0 850 has a first unit size And is stored in page buffer 0 (802). The controller 130 loads the second map segment 854 stored in the page buffer 0 802 into the first pattern zone 760 as a first unit size, (766) into the first pattern zone (760).

In addition, when the third map segment 764 is loaded into the memory 144 of the controller 130 in the map segments 762, 764, 766, 768, 770, 772 of the first group map data, The third map segment 764 leads in the memory blocks, e.g., memory blocks of plane 1, and the third map segment 764 that is read leads the first map segment 862 of the map segments 1 860 ) Is stored in the page buffer 1 (804). Here, the third map segment 764 is read in the memory blocks of plane 1 with the first unit size, so that the first map segment 862 of the map segments 1 860 has the first unit size And is stored in page buffer 1 (804). The controller 130 loads the first map segment 862 stored in the page buffer 1 804 into the first pattern zone 760 in the first unit size, (764) into the first pattern zone (760).

In addition, the controller 130 may determine that the map segment 762, 764, 766, 768, 770, 772 of the first group map data is the same as the map segment 762 of the memory device 150 when loading the fourth map segment 762 into the memory 144 of the controller 130. [ Leads the fourth map segment 762 in memory blocks, e.g., memory blocks of plane 2, and the read fourth map segment 762 leads the first map segment 872 of the map segments 2 870 ) In the page buffer 2 (806). Here, the fourth map segment 762 is read in the memory blocks of the plane 2 with the first unit size, so that the first map segment 872 of the map segments 2 870 has the first unit size And is stored in page buffer 2 (806). The controller 130 loads the first map segment 872 stored in the page buffer 2 806 into the first pattern zone 760 with the first unit size, (762) into the first pattern zone (760).

Here, the controller 130 reads the map segments 762, 764, 766, 768, 770, 772 of the first group map data in the memory blocks of the memory device 150 in the first unit size as described above, 804, 806, and 808, and also loads the map segments stored in the respective page buffers 802, 804, 806, and 808 into the first pattern zone 760 with the first unit size. In other words, the controller 130 determines that the map segments 762, 764, 766, 768, 770, 772 of the first group map data are read and written once in the memory blocks of the memory device 150, And performs a single loading in the first pattern zone 760. Also, map segments 762, 764, 766, 768, 770, 772 of the first group map data loaded into the first pattern zone 760 are managed according to the MRU 752 / LRU 754, as described above.

In addition, when the map segment 782 of the second group map data is loaded into the memory 144 of the controller 130, the controller 130 determines whether the memory block 150 is loaded with a lead, The memory blocks of plane 1, the memory blocks of plane 1, the memory blocks of plane 2, and the memory block of plane 3, for example, through the interleaving scheme for memory dies or planes of memory 150, Leads. Here, the map segment 782 of the second group map data is read from the memory blocks of the memory device 150 in the second unit size, that is, the memory blocks of the plane 0, the memory blocks of the plane 1, The memory block of plane 2, and the memory block of plane 3, with a second unit size.

The map segment 782 of the second group map data of the read leads to the page buffer 0 802 as the map segments 0 850 and the page buffer 804 as the map segments 1 860, The page buffer 2 806 and the map segments 3 880 into the second page buffer 870 and the page buffer 3 808 respectively with a third unit size such as 8K. That is, in the map segment 782 of the second group map data, the map segments 0 (850) are read in the memory blocks of the plane 0 and then stored in the page buffer 0 (802) in the third unit size . In the map segment 782 of the second group map data, the map segments 1 860 are read from the memory blocks of the plane 1 and then stored in the page buffer 1 804 in the third unit size . Also, in the map segment 782 of the second group map data, the map segments 2 870 are read in the memory blocks of the plane 2 and then stored in the page buffer 2 (806) in the third unit size . In addition, in the map segment 782 of the second group map data, the map segments 3 880 are read in the memory blocks of the plane 3 and then stored in the page buffer 3 808 in the third unit size . The controller 130 loads the map segments 850, 860, 870 and 880 stored in the page buffers 802, 804, 806 and 808 into the second pattern zone 780 with the second unit size, ) Into the second pattern zone 780 with the second unit size.

Here, the controller 130 transmits the map segment 782 of the second group map data to the memory unit 150 via the interleaving scheme for the memory dies or flags of the memory device 150, as described above, 804, 806, and 808 and also stores the map segment 782 of the second group map data stored in the page buffers 802, 804, 806, and 808 in the memory blocks of the memory device 150, And loads it into the second pattern zone 780 as a unit size. That is, the controller 130 generates map segment 0 (850), map segments 1 (860), map segments 2 (870), and map segments 3 (860) of the map segment 782 of the second group map data 880, a single read from the memory blocks of the memory device 150 and a second pattern zone 760 with a second unit size.

In this manner, in the memory system according to the embodiment of the present invention, the controller 130 confirms data corresponding to commands received from the host 102, command operations corresponding to the commands, or command operations, More efficiently use the memory 144 of the controller 130 by dynamically allocating a map buffer or map cache to the memory 144 of the controller 130 after confirming data corresponding to background operations or background operations And more efficiently loads and manages the map segments of the map data into the memory 144 of the controller 130, thereby further improving the performance in the memory system. Hereinafter, the operation of processing data in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIG.

9 is a diagram schematically illustrating an operation process of processing data in a memory system according to an embodiment of the present invention.

9, the memory system 110 receives a plurality of commands from the host 102 in step 910, and then, in step 920, receives a plurality of commands received from the host 102, a plurality of commands And pattern corresponding to the data corresponding to the command operations. Here, it is confirmed whether the plurality of commands, command operations, and data, particularly, the pattern of the user data is the first pattern or the second pattern. In addition, when performing the background operation on the memory device 150, it is confirmed whether the data corresponding to the background operations or the background operations, particularly the pattern of the user data, is the first pattern or the second pattern.

In step 930, in order to load map segments of map data corresponding to a plurality of commands, command operations, background operations, or data into the memory 144 of the controller 130, Assigns a map buffer or map cache to the memory 144 and assigns pattern zones to the map buffer or map cache, for example, in accordance with an identified pattern, for example, in the memory 144 of the controller 130, Pattern zones are dynamically allocated.

Map segments of map data corresponding to each of the patterns are then read in the memory blocks of memory device 150 and then transferred to controller 130 via buffers included in memory device 150 In the memory 144 of the first pattern zone, that is, in the first pattern zone and the second pattern zone, respectively.

Then, in step 950, through the map segments loaded in the first pattern zone and the second pattern zone, respectively, the command operations are performed, and the map segments are updated corresponding to the execution of the command operations.

Here, a plurality of commands received from the host 102, command operations corresponding to a plurality of commands, data corresponding to command operations, particularly user data, and data corresponding to background operations or background operations, In particular, according to a pattern for user data, a map buffer or a map cache is allocated to the memory 144 of the controller 130, for example, dynamically allocating pattern zones and loading map segments of map data into pattern zones 5 to 8, a detailed description thereof will be omitted here. 10 to 18, a memory system 150 including the memory device 150 and the controller 130 described with reference to FIGS. 1 to 9 according to an embodiment of the present invention, And electronic devices will now be described in more detail.

10 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 10 is a view schematically showing a memory card system to which a memory system according to an embodiment of the present invention is applied.

10, the memory card system 6100 includes a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 is coupled to a memory device 6130 implemented as a non-volatile memory, and is implemented to access the memory device 6130. For example, the memory controller 6120 is implemented to control the read, write, erase, and background operations of the memory device 6130, and the like. The memory controller 6120 is then implemented to provide an interface between the memory device 6130 and the host and is configured to drive firmware to control the memory device 6130. That is, the memory controller 6120 corresponds to the controller 130 in the memory system 110 described in FIG. 1, and the memory device 6130 corresponds to the memory device 150 in the memory system 110 described in FIG. ). ≪ / RTI >

Accordingly, the memory controller 6120 includes components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit .

In addition, the memory controller 6120 can communicate with an external device, such as the host 102 described in Fig. 1, via the connector 6110. [ For example, the memory controller 6120 may be connected to an external device such as a USB (Universal Serial Bus), an MMC (multimedia card), an eMMC (embeded MMC), a peripheral component interconnection (PCI) Advanced Technology Attachment), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS) , Bluetooth, and the like, thereby enabling the memory system and the data processing system according to embodiments of the present invention to be used in wired / wireless electronic devices, particularly mobile electronic devices, Can be applied.

The memory device 6130 may be implemented as a nonvolatile memory such as an EPROM (Electrically Erasable and Programmable ROM), a NAND flash memory, a NOR flash memory, a PRAM (Phase-change RAM), a ReRAM RAM), STT-MRAM (Spin-Torque Magnetic RAM), and the like.

In addition, the memory controller 6120 and the memory device 6130 may be integrated into one semiconductor device, and may be integrated into one semiconductor device to form a solid state drive (SSD) SD card (SD, miniSD, microSD, SDHC), PC card (PCMCIA), compact flash card (CF), smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro, eMMC) , A universal flash memory device (UFS), and the like.

11 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention.

11, data processing system 6200 includes a memory device 6230 implemented with at least one non-volatile memory, and a memory controller 6220 that controls memory device 6230. [ The data processing system 6200 shown in FIG. 11 may be a storage medium such as a memory card (CF, SD, microSD, etc.), a USB storage device, Corresponds to the memory device 150 in the memory system 110 described in Figure 1 and the memory controller 6220 can correspond to the controller 130 in the memory system 110 described in Figure 1 .

The memory controller 6220 controls read, write, erase operations and the like for the memory device 6230 in response to a request from the host 6210. The memory controller 6220 includes at least one CPU 6221, A buffer memory such as RAM 6222, an ECC circuit 6223, a host interface 6224, and a memory interface, such as an NVM interface 6225.

Here, the CPU 6221 can control the overall operation of the memory device 6230, e.g., read, write, file system management, bad page management, etc.). The RAM 6222 operates under the control of the CPU 6221 and can be used as a work memory, a buffer memory, a cache memory, and the like. Here, when the RAM 6222 is used as a work memory, the data processed by the CPU 6221 is temporarily stored. When the RAM 6222 is used as a buffer memory, the host 6210 transfers data from the memory 6230 ) Or used for buffering data transferred from the memory device 6230 to the host 6210 and when the RAM 6222 is used as cache memory the slow memory device 6230 can be used to operate at high speed have.

The ECC circuit 6223 corresponds to the ECC unit 138 of the controller 130 described with reference to FIG. 1 and includes a fail bit of data received from the memory device 6230, Or an error correction code (ECC: Error Correction Code) for correcting an error bit. In addition, the ECC circuit 6223 performs error correction encoding of data provided to the memory device 6230 to form data with a parity bit added thereto. Here, the parity bit may be stored in the memory device 6230. Also, the ECC circuit 6223 can perform error correction decoding on the data output from the memory device 6230, at which time the ECC circuit 6223 can correct the error using parity. For example, the ECC circuit 6223 uses various coded modulation such as LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC, TCM and BCM as described in FIG. So that the error can be corrected.

The memory controller 6220 transmits and receives data and the like with the host 6210 via the host interface 6224 and transmits and receives data and the like with the memory device 6230 via the NVM interface 6225. Here, the host interface 6224 can be connected to the host 6210 through a PATA bus, a SATA bus, a SCSI, a USB, a PCIe, a NAND interface, and the like. The memory controller 6220 is connected to an external device such as a host 6210 or an external device other than the host 6210 by implementing a wireless communication function, WiFi or Long Term Evolution (LTE) Data, and the like, and is configured to communicate with an external device through at least one of various communication standards, it is possible to use a memory system according to an embodiment of the present invention in wired / wireless electronic devices, And a data processing system can be applied.

12 schematically shows another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 12 is a schematic view of a solid state drive (SSD) to which a memory system according to an embodiment of the present invention is applied.

12, the SSD 6300 includes a memory device 6340 and a controller 6320, which includes a plurality of non-volatile memories. The controller 6320 corresponds to the controller 130 in the memory system 110 described in FIG. 1 and the memory device 6340 corresponds to the memory device 150 in the memory system 110 described in FIG. Lt; / RTI >

More specifically, the controller 6320 is connected to the memory device 6340 through a plurality of channels CH1, CH2, CH3, ..., CHi. The controller 6320 includes at least one processor 6321, a buffer memory 6325, an ECC circuit 6322, a host interface 6324, and a memory interface, for example, a nonvolatile memory interface 6326.

Here, the buffer memory 6325 temporarily stores data received from the host 6310 or data received from a plurality of flash memories NVMs included in the memory device 6340, or a plurality of flash memories (NVMs) ), For example, map data including a mapping table. The buffer memory 6325 may be implemented in nonvolatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, or nonvolatile memories such as FRAM, ReRAM, STT-MRAM and PRAM. But may also be external to the controller 6320. The controller 6320 of FIG.

The ECC circuit 6322 calculates the error correction code value of the data to be programmed in the memory device 6340 in the program operation and outputs the data read from the memory device 6340 in the read operation to the memory device 6340 based on the error correction code value And performs an error correction operation of the recovered data from the memory device 6340 in the recovery operation of the failed data.

The host interface 6324 also provides an interface function with an external device such as a host 6310 and a non-volatile memory interface 6326 provides an interface function with a memory device 6340 connected via a plurality of channels do.

A plurality of SSDs 6300 to which the memory system 110 described with reference to FIG. 1 is applied may implement a data processing system such as a Redundant Array of Independent Disks (RAID) system. In this case, A plurality of SSDs 6300, and a RAID controller for controlling the plurality of SSDs 6300. When the RAID controller receives the write command from the host 6310 and performs the program operation, the RAID controller reads data corresponding to the write command from the plurality of RAID levels, that is, from the plurality of SSDs 6300 to the host 6310 (I.e., SSD 6300) in accordance with the RAID level information of the write command received from the SSD 6300, and then output the selected SSD 6300 to the selected SSD 6300. When the RAID controller receives the read command from the host 6310 and performs the read operation, the RAID controller reads the RAID level of the read command received from the host 6310 in the plurality of RAID levels, that is, the plurality of SSDs 6300 In response to the information, at least one memory system, i.e., SSD 6300, may be selected and then provided to the host 6310 from the selected SSD 6300.

13 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 13 is a view schematically showing an embedded multimedia card (eMMC) to which a memory system according to an embodiment of the present invention is applied.

Referring to Fig. 13, the eMMC 6400 includes a memory device 6440 implemented with at least one NAND flash memory, and a controller 6430. [ The controller 6430 corresponds to the controller 130 in the memory system 110 described in Fig. 1 and the memory device 6440 corresponds to the memory device 150 in the memory system 110 described in Fig. Lt; / RTI >

More specifically, the controller 6430 is connected to the memory device 2100 through a plurality of channels. The controller 6430 includes at least one core 6432, a host interface 6431, and a memory interface, e.g., a NAND interface 6433.

Here, the core 6432 controls the overall operation of the eMMC 6400, the host interface 6431 provides the interface function between the controller 6430 and the host 6410, and the NAND interface 6433 is a memory And provides an interface function between the device 6440 and the controller 6430. For example, the host interface 6431 may be a parallel interface, e.g., an MMC interface, as described in FIG. 1, and may also include a serial interface, such as a UHS (Ultra High Speed) .

14-17 are diagrams schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIGS. 14 to 17 are views schematically showing a UFS (Universal Flash Storage) to which a memory system according to an embodiment of the present invention is applied.

14-17, each of the UFS systems 6500, 6600, 6700, and 6800 includes hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, And UFS cards 6530, 6630, 6730, and 6830, respectively. Here, each of the hosts 6510, 6610, 6710, and 6810 may be an application processor such as a wired / wireless electronic device, particularly a mobile electronic device, and each UFS device 6520,6620,6720,6820 ) Are embedded UFS (Embedded UFS) devices. In addition, each of the UFS cards 6530, 6630, 6730, 6830 includes an external embedded UFS device or a removable UFS card .

Also, in each of the UFS systems 6500, 6600, 6700, and 6800, each of the hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530 , 6630, 6730, 6830) can communicate with external devices, such as wired / wireless electronic devices, especially mobile electronic devices, etc., via the UFS protocol, and UFS devices 6520, And UFS cards 6530, 6630, 6730, and 6830 may be implemented in the memory system 110 described with reference to FIG. For example, in each of the UFS systems 6500, 6600, 6700, and 6800, the UFS devices 6520, 6620, 6720, and 6820 are connected to the data processing system 6200, the SSD 6300, Or eMMC 6400, and the UFS cards 6530, 6630, 6730, and 6830 may be implemented in the form of the memory card system 6100 described in FIG.

In addition, in each of the UFS systems 6500, 6600, 6700, and 6800, each of the hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530 , 6630, 6730, and 6830 can perform communication through a Universal Flash Storage (UFS) interface, for example, a MIPI M-PHY and a MIPI UniPro (Unified Protocol) in a Mobile Industry Processor Interface (MIPI) The devices 6520, 6620, 6720, 6820 and the UFS cards 6530, 6630, 6730, 6830 can communicate via protocols other than the UFS protocol, for example, various card protocols such as UFDs, MMC , Secure digital (SD), mini SD, and micro SD.

UniPro is present in each of the host 6510, the UFS 6520 and the UFS card 6530 in the UFS system 6500 shown in Fig. 14, and the host 6510 is connected to the UFS 6520, The host 6510 performs a swtiching operation in order to perform communication with the UFS card 6530 and the UFS card 6530, 6520 or performs communication with the UFS card 6530. [ At this time, communication between the UFS unit 6520 and the UFS card 6530 can be performed through link layer switching in the UniPro of the host 6510. In the embodiment of the present invention, for convenience of description, one UFS device 6520 and a UFS card 6530 are connected to the host 6510, respectively. However, a plurality of UFS devices The UFS cards may be connected to the host 6410 in a parallel form or a star form, and a plurality of UFS cards may be connected to the UFS unit 6520 in a parallel form or a star form, or in a serial form or a chain form .

In addition, in the UFS system 6600 shown in FIG. 15, UniPro exists in the host 6610, the UFS device 6620, and the UFS card 6630, respectively, and includes a switching module 6640, In particular, the host 6610 communicates with the UFS device 6620 or communicates with the UFS card 6630 via a switching module 6640 that performs link layer switching, e.g., L3 switching operation, in UniPro . At this time, the communication between the UFS unit 6520 and the UFS card 6530 may be performed through link layer switching in the UniPro of the switching module 6640. In the embodiment of the present invention, for convenience of description, one UFS device 6620 and a UFS card 6630 are connected to the switching module 6640, respectively. However, a plurality of UFS devices And UFS cards may be connected to the switching module 6640 in a parallel form or in a star form and a plurality of UFS cards may be connected to the UFS unit 6620 in a parallel form or in a star form or in a serial form or a chain form It is possible.

In addition, in the UFS system 6700 shown in Fig. 16, UniPro is present in the host 6710, the UFS device 6720, and the UFS card 6730, respectively, and includes a switching module 6740, The host 6710 communicates with the UFS device 6720 or communicates with the UFS card 6730 via a switching module 6740 that performs link layer switching, e.g., L3 switching operation, in UniPro . At this time, the UFS device 6720 and the UFS card 6730 may perform communication through link layer switching in the UniPro of the switching module 6740, and the switching module 6740 may perform communication through the UFS 6720 And may be implemented as a single module with the UFS device 6720, either internally or externally. Although one UFS unit 6620 and one UFS card 6630 are connected to the switching module 6740 for convenience of explanation in the embodiment of the present invention, And the UFS device 6720 may be connected to the host 6710 in a parallel form or in a star form, or the respective modules may be connected in a serial form or chain form, and a plurality of UFS cards May be connected to the switching module 6740 in a parallel form or in a star form.

In the UFS system 6800 shown in Fig. 17, M-PHY and UniPro are respectively present in the host 6810, the UFS device 6820, and the UFS card 6830, and the UFS device 6820, The UFS device 6820 performs a switching operation to perform communication with the host 6810 and the UFS card 6830 respectively and in particular the UFS device 6820 includes an M-PHY and UniPro module for communication with the host 6810, Communicates with the host 6810 or communicates with the UFS card 6830 through switching, e.g., Target ID, switching between the M-PHY and UniPro modules for communication with the host 6810 . At this time, the host 6810 and the UFS card 6530 may perform the communication through the target ID switching between the M-PHY and UniPro modules of the UFS unit 6820. In this embodiment of the present invention, for convenience of description, one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to one UFS device 6820 However, a plurality of UFS devices may be connected to the host 6810 in a parallel form or a star form, or may be connected in a serial form or a chain form. In a UFS device 6820, a plurality of UFS cards may be connected in parallel Or may be connected in star form, or in series form or chain form.

18 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 18 is a view schematically showing a user system to which the memory system according to the present invention is applied.

18, the user system 6900 includes an application processor 6930, a memory module 6920, a network module 6940, a storage module 6950, and a user interface 6910.

More specifically, the application processor 6930 drives the components included in the user system 6900, an operating system (OS), and for example, the components included in the user system 6900 Controllers, interfaces, graphics engines, and so on. Here, the application processor 6930 may be provided as a system-on-chip (SoC).

The memory module 6920 can be operated as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 6900. The memory module 6920 may be a volatile random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDRAM, an LPDDR3 SDRAM, an LPDDR3 SDRAM, or a nonvolatile random access memory such as a PRAM, a ReRAM, Memory. For example, the application processor 6930 and the memory module 6920 may be packaged and implemented based on a POP (Package on Package).

Also, the network module 6940 can communicate with external devices. For example, the network module 6940 may support not only wired communication but also other services such as Code Division Multiple Access (CDMA), Global System for Mobile communications (GSM), Wideband CDMA (WCDMA), CDMA- The present invention can perform communication with wired / wireless electronic devices, particularly mobile electronic devices, by supporting various wireless communications such as Access, Long Term Evolution (LTE), Wimax, WLAN, UWB, Bluetooth and WI-DI. Accordingly, the memory system and the data processing system according to the embodiment of the present invention can be applied to wired / wireless electronic devices. Here, the network module 6940 may be included in the application processor 6930.

In addition, the storage module 6950 may store data, e.g., store data received from the application processor 6930, and then transfer the data stored in the storage module 6950 to the application processor 6930. [ The storage module 6950 may be implemented as a nonvolatile memory such as a PRAM (Phase Change RAM), an MRAM (Magnetic RAM), an RRAM (Resistive RAM), a NAND flash, a NOR flash, , A removable drive such as a memory card of an user system 6900, an external drive, or the like. That is, the storage module 6950 may correspond to the memory system 110 described with reference to FIG. 1, and may also be implemented with the SSD, eMMC, and UFS described with reference to FIGS.

The user interface 6910 may include interfaces for inputting data or instructions to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, , And a user output interface such as an LCD (Liquid Crystal Display), an OLED (Organic Light Emitting Diode) display device, an AMOLED (Active Matrix OLED) display device, an LED, a speaker and a motor.

1 is applied to a mobile electronic device of a user system 6900, the application processor 6930 controls the overall operation of the mobile electronic device, The network module 6940 is a communication module that controls wired / wireless communication with an external device as described above. In addition, the user interface 6910 supports displaying data processed by the application processor 6930 as a display / touch module of the mobile electronic device, or receiving data from the touch panel.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims (20)

A memory device including a plurality of memory blocks in which data is stored, and a plurality of planes including the memory blocks and a plurality of memory dies including the planes; And
A controller including a first memory;
The controller receiving a plurality of commands from a host; Performing command operations corresponding to the commands in the memory blocks; Identify patterns for user data corresponding to the commands, the command operations, and the command operations, respectively; Assigning pattern zones to the first memory dynamically, corresponding to the patterns; Loading map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones,
Memory system.
The method according to claim 1,
The controller may load map segments of first map data corresponding to a first pattern in the patterns into a first pattern zone in the pattern zones; Loading map segments of second map data corresponding to a second pattern in the patterns into a second pattern zone in the pattern zones;
Memory system.
3. The method of claim 2,
Wherein the first pattern is a discontinuous pattern in which the information on the commands, the command operations, and the user data is discontinuous;
Wherein the second pattern is a pattern in which the commands, the command operations, and the information on the user data are continuous,
Memory system.
3. The method of claim 2,
The controller reads the map segments of the first map data in the memory blocks and loads the map segments of the first map data in the first pattern zone with the first unit size,
Memory system.
5. The method of claim 4,
The controller reads each map segment having the first unit size in map segments of the first map data, respectively; After storing one map segment having the first unit size in the buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; Loading one map segment having the first unit size into the first pattern zone,
Memory system.
3. The method of claim 2,
Wherein the controller reads the map segments of the second map data in the memory blocks and reads the map segments of the second map data into the second pattern zone with the second unit size,
Memory system.
The method according to claim 6,
The controller reads, in map segments of the second map data, all map segments having the second unit size; Storing the entire map segments having the second unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; Loading all map segments having the second unit size into the second pattern zone,
Memory system.
8. The method of claim 7,
Wherein the controller is configured to read the entire map segments having the second unit size from the memory blocks through an interleaving scheme for the planes or the memory dies,
Memory system.
3. The method of claim 2,
Map segments of the first map data loaded in the first pattern zone are managed according to MRU (Most Recently Used) and LRU (Least Recently Used);
Map segments of the second map data loaded in the second pattern zone are managed according to the execution of the command operations,
Memory system.
3. The method of claim 2,
Wherein the controller confirms the first pattern and the second pattern with respect to user data corresponding to background operations or background operations on the memory device,
Memory system.
For a memory device comprising a plurality of memory blocks for storing data and a plurality of planes including the memory blocks and a plurality of memory dies including the planes, Receiving a plurality of commands from a host;
Confirming patterns for the commands, the command operations corresponding to the commands, and the user data corresponding to the command operations, respectively;
Assigning pattern zones dynamically to the first memory in accordance with the patterns; And
And loading map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.
A method of operating a memory system.
12. The method of claim 11,
Wherein the loading comprises:
Loading map segments of first map data corresponding to a first pattern in the patterns into a first pattern zone in the pattern zones; And
And loading map segments of second map data corresponding to a second pattern in the patterns into a second pattern zone in the pattern zones.
A method of operating a memory system.
13. The method of claim 12,
Wherein the first pattern is a discontinuous pattern in which the information on the commands, the command operations, and the user data is discontinuous;
Wherein the second pattern is a pattern in which the commands, the command operations, and the information on the user data are continuous,
A method of operating a memory system.
13. The method of claim 12,
Wherein the step of loading into the first pattern zone comprises the steps of reading map segments of the first map data in the memory blocks and reading the map segments of the first map data in the first pattern zone with the first unit size, Respectively,
A method of operating a memory system.
15. The method of claim 14,
Wherein the step of loading into the first pattern zone comprises:
Reading one map segment having the first unit size from map segments of the first map data, respectively;
Storing one map segment having the first unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies, respectively; And
And loading one map segment having the first unit size stored in the buffers into the first pattern zone,
A method of operating a memory system.
13. The method of claim 12,
The loading of the second pattern zone may include reading the map segments of the second map data in the memory blocks at a second unit size and then loading the map segments of the second map data at the second unit size in the second pattern zone doing,
A method of operating a memory system. 17. The method of claim 16,
Wherein the step of loading into the second pattern zone comprises:
Reading all map segments having the second unit size in map segments of the second map data;
Storing all map segments having the second unit size in buffers corresponding to at least one of the memory blocks, the planes, and the memory dies; And
And loading all map segments having the second unit size stored in the buffers into the second pattern zone.
A method of operating a memory system.
18. The method of claim 17,
Wherein the step of reading leads the entire map segments having the second unit size in the memory blocks through an interleaving scheme for the planes or the memory dies,
A method of operating a memory system.
13. The method of claim 12,
Map segments of the first map data loaded in the first pattern zone are managed according to MRU (Most Recently Used) and LRU (Least Recently Used);
Map segments of the second map data loaded in the second pattern zone are managed according to the execution of the command operations,
A method of operating a memory system.
13. The method of claim 12,
Further comprising checking for the first pattern and the second pattern for background operations for the memory device or for user data corresponding to the background operations,
A method of operating a memory system.

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