KR20190007147A - Three dimensional semiconductor memory device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor memory device may comprise: multiple bit lines which are arranged on an upper portion of a memory cell array, aligned in a first direction, and extended in a second direction; multiple bit line contact pads which are formed on a first wiring layer under the memory cell array and individually connected to each bit line through first contacts; and a page buffer circuit formed on a substrate under the first wiring layer. The page buffer circuit may comprise: multiple bit line selection transistor units connected to the bit lines through the bit line contact pads; and multiple page buffer units which correspond to each bit line selection transistor unit and are connected to each corresponding bit line selection transistor unit. The page buffer units are arranged in the first and second directions. The bit line selection transistor units are arranged to be close to each corresponding page buffer unit in the second direction and can be arranged in a zigzag pattern in an oblique direction crossing the first and second directions. Embodiments of the present invention may provide semiconductor memory devices with an improved degree of freedom for the wiring design.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device having a three-

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a three-dimensional structure.

Dimensional structure semiconductor that forms a plurality of memory cells along a vertical channel layer protruding in a direction perpendicular to the substrate as the improvement of the degree of integration of the two-dimensional semiconductor memory device forming the memory cell as a single layer on the substrate reaches the limit A memory device has been proposed.

Embodiments of the present invention can provide a semiconductor memory device capable of improving the degree of freedom in wiring design.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of bit lines arranged on a memory cell array and arranged along a first direction and extending in a second direction and a plurality of word lines arranged on a first wiring layer below the memory cell array A plurality of bit line contact pads connected to the bit lines through the first contacts and a page buffer circuit formed on the first wiring layer lower substrate. Wherein the page buffer circuit comprises a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads and a plurality of bit line select transistor units corresponding to the bit line select transistor units, And a plurality of page buffer units. Wherein the page buffer units are arranged along the first direction and the second direction, and the bit line select transistor units are disposed adjacent to the corresponding page buffer units in the second direction, And may be arranged in a zigzag shape along the oblique direction intersecting the two directions.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of bit lines arranged on a memory cell array and arranged along a first direction and extending in a second direction and a plurality of word lines arranged on a first wiring layer below the memory cell array A plurality of bit line contact pads formed on the first wiring layer and connected to the bit lines through first contacts and a plurality of bit line contact pads formed on the substrate under the first wiring layer, Lt; RTI ID = 0.0 > a < / RTI > Wherein the page buffer circuit comprises a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads and a plurality of bit line select transistor units corresponding to the bit line select transistor units, Lt; RTI ID = 0.0 > buffer unit. ≪ / RTI > The page buffer units may be arranged along the first direction and the second direction. The bit line select transistor units may be arranged in a zigzag fashion along a diagonal direction that is adjacent to the corresponding page buffer unit in the second direction and intersects the first direction and the second direction. The bit line contact pads may be disposed in contact regions arranged in zigzags corresponding to the bit line select transistor units. The routing wiring may be formed in a curved pattern so as to pass between the contact regions.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of bit lines arranged along a first direction and extending in a second direction and a plurality of word lines formed in a first wiring layer below the bit lines, A plurality of bit line contact pads connected to the bit lines and a page buffer circuit formed on the substrate under the bit lines and connected to the memory cell array through the bit lines. Wherein the page buffer circuit comprises a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads and a plurality of bit line select transistor units corresponding to the bit line select transistor units, And a plurality of page buffer units. The page buffer units may be arranged along the first direction and the second direction. The bit line select transistor units may be arranged in a zigzag fashion along a diagonal direction that is adjacent to the corresponding page buffer unit in the second direction and intersects the first direction and the second direction. The bit line contact pads may be disposed in a plurality of contact regions arranged in a zigzag pattern corresponding to the bit line select transistor units.

Embodiments of the present invention can improve the degree of freedom of wiring design by departing from the constraints due to bit line contact pads. Further, since the routing wiring extending in the bit line direction (second direction) can be provided in the same layer as the bit line contact pads, the number of wiring layers can be reduced compared with the case where the routing wiring is formed in a layer separate from the bit line contact pads The size of the semiconductor memory device can be reduced.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
2 is a perspective view exemplarily showing one of the memory blocks shown in FIG.
3 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present invention.
4 is a plan view showing a semiconductor memory device according to an embodiment of the present invention.
FIG. 5 is a circuit diagram exemplarily showing any one of the page buffer circuits of FIG. 4; FIG.
FIG. 6 is a circuit diagram illustrating bit line select transistors and page buffers associated with any of the bit lines of FIG. 5; FIG.
7 is a plan view showing a portion corresponding to any one of the page buffer circuits of FIG.
Figs. 8 and 9 are plan views showing an enlarged view of a portion B in Fig.
10 is a cross-sectional view taken along line CC 'of FIG.
11 is a cross-sectional view taken along line DD 'of FIG.
12 is a plan view showing a part of a semiconductor memory device according to an embodiment of the present invention.
13 is a plan view showing a part of a semiconductor memory device according to an embodiment of the present invention.
FIG. 14 is a view schematically showing a memory system including a semiconductor memory device according to an embodiment of the present invention.
15 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present invention.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

1, a semiconductor memory device 100 according to an embodiment of the present invention includes a memory cell array 110, a row decoder 120, a page buffer unit 130, a column decoder 140, a voltage generator 150, a control logic 160, an input / output buffer 170, and an input / output pad unit 180.

The memory cell array 110 may include a plurality of planes in which data is stored. Hereinafter, a semiconductor memory device having four planes will be described as an example. The four planes may be composed of a first plane 110_1, a second plane 110_2, a third plane 110_3, and a fourth plane 110_4.

The first to fourth planes 110_1 to 110_4 may have the same structure. Each of the first to fourth planes 110_1 to 110_4 may include a plurality of memory blocks BLK. Each memory block BLK may be coupled to the row decoder 120 via word lines WL, at least one drain select line DSL, and at least one source select line SSL. The memory block BLK may be connected to the page buffer unit 130 via the bit lines BL.

Each memory block BLK includes a plurality of cell strings (not shown) extending along the vertical direction VD on the substrate (not shown) and arranged along the first direction FD and the second direction SD. ). The vertical direction VD indicates a direction orthogonal to the main surface of the substrate, and the first direction FD and the second direction SD indicate directions intersecting with each other on the main surface of the substrate. In this embodiment, the first direction FD and the second direction SD may be directions orthogonal to each other. Each cell string may have a structure in which at least one drain select transistor, a plurality of memory cells, and at least one source select transistor are connected in series.

The row decoder 120 outputs operating voltages provided from the voltage generator 150 in response to the row address RADD of the control logic 160 to the word lines of the selected memory block of the first to fourth planes Plane1 to Plane4 (WL), a drain select line (DSL), and a source select line (SSL).

The page buffer unit 130 may detect a program state or an erase state of the memory cells under the control of the control logic 160. [ The page buffer unit 130 may include four page buffer circuits corresponding to the first to fourth planes (Plane 1 to Plane 4), respectively. The four page buffer circuits may include a first page buffer circuit 130_1, a second page buffer circuit 130_2, a third page buffer circuit 130_3, and a fourth page buffer circuit 130_4.

Each of the first to fourth page buffer circuits 130_1 to 130_4 may include a plurality of page buffers connected to corresponding planes (any one of Plane1 to Plane4) through the bit lines BL.

The page buffers latch data received through the input / output pad unit 180, the input / output buffer 170 and the column decoder 140 during a program operation, and store page buffer control signals (PB SIGNALS) from the control logic 160 In response to a voltage required to store data in selected memory cells of the first to fourth planes (Plane1 to Plane4) to the bit lines BL. The page buffers store data read from a corresponding plane (any one of Plane 1 to Plane 4) in a read operation and output the data to the outside through a column decoder 140, an input / output buffer 170, and an input / output pad unit 180. have.

The column decoder 140 may be configured to input the program data into the page buffers of the first to fourth page buffer circuits 130_1 to 130_4 in response to the column address CADD of the control logic 160. [

The voltage generator 150 may be configured to generate the various voltages required in the semiconductor memory device 100. For example, the voltage generator 150 may be configured to generate program voltages, pass voltages, select read voltages, unselected read voltages.

The control logic 160 may include an address register / counter 161, instruction interface logic 162, and an instruction register 163.

The address register / counter 161 outputs the row address RADD among the address ADD received through the input / output pad unit 180 and the input / output buffer 170 to the row decoder 120 and outputs the column address CADD And output it to the column decoder 140.

The instruction register 163 may be configured to temporarily store the command CMD received through the input / output pad unit 180 and the input / output buffer 170 and to transfer the command CMD to the instruction interface logic 162.

The instruction interface logic 162 receives the command CMD via the instruction register 163 and controls the overall operation of the semiconductor memory device 100 such as program / read / erase, etc. according to the received command CMD Lt; / RTI > The instruction interface logic 162 may be configured to output page buffer control signals (PB SIGNALS) for controlling the page buffer section 130. [

The input / output buffer 170 transfers data (DATA) received through the input / output pad unit 180 to the column decoder 140 during a program operation and data (DATA) transmitted through the column decoder 140 during a read operation And output through the input / output pad unit 180. The input / output buffer 170 may be configured to transmit to the control logic 160 the command CMD and the address ADD received via the input / output pad unit 180.

2 is a perspective view exemplarily showing one of the memory blocks BLK shown in FIG.

Referring to FIG. 2, a memory block BLK may be formed on the semiconductor layer 10.

The semiconductor layer 10 may comprise polysilicon doped with impurities. The semiconductor layer 10 may comprise Si, Ge or SiGe. The semiconductor layer 10 may include a polysilicon substrate, a silicon on insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate.

A plurality of gate electrode films 20 and a plurality of insulating films 22 may be alternately stacked on the semiconductor layer 10. [ At least one layer from the lowest layer among the gate electrode films 20 may be used as the source select line (SSL), and at least one layer from the uppermost layer may be used as the drain select line (DSL). The conductive films between the source select line (SSL) and the drain select line (DSL) may be used as the word lines (WL).

The vertical channel films 30 penetrating the gate electrode films 20 and the insulating films 22 may be formed. The vertical channel films 30 may be connected to the semiconductor layer 10 through the gate electrode film 20 and the insulating films 22 in the vertical direction VD. The vertical channel films 30 may include polysilicon doped with impurities or polysilicon doped with no impurities.

A gate insulating layer 40 may be formed between the vertical channel layers 30 and the gate electrode layers 20 so as to surround the outer wall of the vertical channel layers 30. The gate insulating film 40 may include a tunnel insulating film, a charge storage, and a blocking insulating film. The tunnel insulating film may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and the like. The charge storage layer may comprise silicon nitride, boron nitride, silicon boron nitride, or a polysilicon layer doped with impurities. The blocking insulating film may include a single film or a laminated film such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tinarium oxide, or the like.

At the intersection of the source select line SSL and the vertical channel films 30, source select transistors may be formed. At the intersection of the word lines WL and the vertical channel films 30, memory cells may be formed. Drain select transistors may be formed at intersections of the drain select lines DSL and the vertical channel films 30. [ With this structure, the source selection transistor, the plurality of memory cells, and the drain selection transistor can be connected in series by the vertical channel layer 30 to form a cell string.

Drains 50 may be disposed on the vertical channel films 30, respectively. The drains 50 may comprise an impurity doped silicon material. For example, the drains 50 may comprise N-type silicon.

Bit line contacts (not shown) may be disposed on the drains 50, respectively. The bit lines BL may be connected to the drains 50 through bit line contacts. The bit lines BL extend in the second direction SD and may be arranged in the first direction FD. The vertical channel films 30 of cell strings arranged in a line along the first direction FD may be connected in common to a single bit line.

Although the eight word lines WL are shown as being stacked in the embodiment of FIG. 2, the number of the word lines WL is not limited to this. For example, 8, 16, 32 or 64 word lines may be stacked in the height direction VD.

2, the source select line SSL and the drain select line DSL are arranged one by one in the vertical direction VD. However, in the vertical direction VD, two or more source select lines SSL) or a drain select line (DSL) may be disposed.

FIG. 3 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a plan view illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, first to fourth page buffer circuits 130_1 to 130_4 and first and second peripheral circuit portions PERI1 and PERI2 may be disposed between the substrate 60 and the memory cell array 110 . That is, the semiconductor memory device according to the embodiment of the present invention may have a PUC (Peri Under Cell) structure. Although not shown, a plurality of bit lines may be formed on the memory cell array 110. The bit lines extend in a second direction SD and may be arranged in a first direction FD.

3 and 4, the substrate 60 may have a main surface extending in a first direction FD and a second direction SD different from the first direction FD. The second direction SD may be a direction orthogonal to the first direction FD. The vertical direction VD indicates a direction orthogonal to the main surface of the substrate 60.

The first peripheral circuit portion PERI1 may be disposed on the substrate 60 in the first direction FD. The second peripheral circuit portion PERI2 may be disposed on the substrate 60 in parallel with the first peripheral circuit portion PERI1. The first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 may be spaced apart from each other by a predetermined distance in the second direction SD.

In one embodiment, the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 are connected to a column decoder (140 in FIG. 1), a voltage generator (150 in FIG. 1), control logic (170 in FIG. 1). In one embodiment, the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 comprise a column decoder (140 in Figure 1), a voltage generator (150 in Figure 1) and control logic (160 in Figure 1) . In one embodiment, the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 include a voltage generator (150 in Fig. 1), control logic (160 in Fig. 1) and an input / output buffer . In one embodiment, the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 may include a voltage generator (150 in FIG. 1) and control logic (160 in FIG. 1).

The first page buffer circuit 130_1 may be arranged in the first direction FD along one side of the first peripheral circuit portion PERI1. The second page buffer circuit 130_2 may be arranged in the first direction FD along the other side surface of the first peripheral circuit portion PERI1. The first page buffer circuit 130_1 and the second page buffer circuit 130_2 may be disposed opposite to each other with respect to the first peripheral circuit portion PERI1. That is, the first page buffer circuit 130_1 and the second page buffer circuit 130_2 may be disposed adjacent to each other in the second direction SD with the first peripheral circuit portion PERI1 interposed therebetween.

The third page buffer circuit 130_3 may be arranged in the first direction FD along one side of the second peripheral circuit portion PERI2. The fourth page buffer circuit 130_4 may be arranged in the first direction FD along the other side surface of the second peripheral circuit portion PERI2. The third page buffer circuit 130_3 and the fourth page buffer circuit 130_4 may be disposed on opposite sides of the second peripheral circuit portion PERI2. That is, the third page buffer circuit 130_3 and the fourth page buffer circuit 130_4 may be disposed adjacent to each other in the second direction SD with the second peripheral circuit portion PERI2 interposed therebetween.

A second page buffer circuit 130_2 and a third page buffer circuit 130_3 may be disposed between the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2. The first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 may be disposed adjacent to each other in the second direction SD with the second page buffer circuit 130_2 and the third page buffer circuit 130_3 interposed therebetween.

The memory cell array 110 may include first through fourth planes 110_1 through 110_4. The first to fourth planes 110_1 to 110_4 may correspond to the first to fourth page buffer circuits 130_1 to 130_4, respectively.

The first plane 110_1 may be disposed above the first page buffer circuit 130_1 and the first peripheral circuit portion PERI1. The second plane 110_2 may be disposed above the second page buffer circuit 130_2 and the first peripheral circuit portion PERI1. The third plane 110_3 may be disposed above the third page buffer circuit 130_3 and the second peripheral circuit portion PERI2. The fourth plane 110_4 may be disposed above the fourth page buffer circuit 130_4 and the second peripheral circuit portion PERI2. For example, a semiconductor layer may be stacked on the first page buffer circuit 130_1 and the first peripheral circuit section PERI1, and the first plane 110_1 may be disposed on the semiconductor layer. The second to fourth planes 10_2 to 110_4 may also be arranged in a manner similar to the first plane 110_1.

The row decoder 120 may be disposed in one side of the first to fourth page buffer circuits 130_1 to 130_4 and the first and second peripheral circuit portions PERI1 and PERI2 in the second direction SD.

The input / output pad unit 180 may be disposed on the other side of the first to fourth page buffer circuits 130_1 to 130_4 and the first and second peripheral circuit units PERI1 and PERI2 in the second direction SD. Although not shown, the input / output pad unit 180 may be connected to the first and second peripheral circuit units PERI1 and PERI2 through a plurality of wirings.

The first page buffer circuits 130_1 to 130_4 and the first and second peripheral circuit portions PERI1 and PERI2 and the upper layer in which the memory cell array 110 is located are arranged in the second direction SD A plurality of extending routing lines 71A can be disposed. The routing wirings 71A may overlap with at least one of the first to fourth page buffer circuits 130_1 to 130_4 in the vertical direction VD. The routing interconnects 71A may be connected to at least one of the first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 through contact plugs (not shown). The first peripheral circuit portion PERI1 and the second peripheral circuit portion PERI2 may be connected to each other via the routing interconnections 71A.

5 is a circuit diagram exemplarily showing any one of the page buffer circuits 130_1 to 130_4 in FIG.

Referring to FIG. 5, the page buffer circuit may include a plurality of bit line select transistors (HVN) and a plurality of page buffers (PB).

The page buffers PB may correspond to the bit lines BL, respectively. Each of the bit line select transistors HVN may be connected between the corresponding bit line BL and the page buffer PB. The bit line select transistors HVN may operate in response to the bit line select signal SELBL. For example, when the bit line select signal SELBL is activated, the bit line select transistors HVN can electrically connect the bit lines BL and the page buffers PB. When the bit line select signal SELBL is inactivated, the bit line select transistors HVN can electrically isolate the bit lines BL and the page buffers PB. In this case, the bit lines BL may be flaoting.

The page buffers PB may operate in response to page buffer control signals (PB SIGNALS in FIG. 1) provided from the control logic (160 in FIG. 1). For example, the page buffer control signals (PB SIGNALS in FIG. 1) may include a bit line sensing signal PBSENSE, a precharge signal ECHb, a transmission signal TRANM, a set signal MSET, And a reset signal MRST.

6 is a circuit diagram exemplarily showing a bit line select transistor (HNV) and a page buffer PB associated with any one of the bit lines BL of FIG.

6, the page buffer PB includes a switching element N1 for connecting the bit line select transistor HNV and the sensing node SO in response to a bit line sensing signal PBSENSE, a precharge signal PRECHb, A switching element N2 for precharging the sensing node SO to a high level voltage VDD in response to the latch signal MLAT and a latch MLAT for latching data, A switching element N3 for connecting the node QMb to the sensing node S0, a first node QMb and a second node QM of the latch MLAT and for receiving the set signal MSET and the reset signal Switching elements N4 and N5 respectively operating in response to the potential of the sensing node S0 and a switching element N6 connected between the switching elements N4 and N5 and the ground terminal VSS, ). ≪ / RTI > Control signals (PBSENSE, PRECHb, TRANM, MSET, MRST) for controlling the operation of the switching elements N1 to N6 constituting the page buffer PB can be provided from the control logic (160 in FIG. 1) .

7 is a plan view showing a portion corresponding to any one of the page buffer circuits in FIG.

7, only the page buffer circuit, the routing wirings 71A and the bit line contact pads 71B are shown, and the illustration of the other structures is omitted.

Referring to FIG. 7, the page buffer circuit may include a plurality of bit line select transistor units (UHVN) corresponding to a plurality of page buffer units (UPB) and page buffer units (UPB), respectively.

 The page buffer units UPB can be configured by grouping the page buffers (PB in FIG. 5) included in the page buffer circuit by a predetermined size (for example, 1 KB). Thus, each page buffer unit UPB may include a plurality of page buffers (PB in FIG. 5).

The bit line select transistor units UHVN group the bit line select transistors (HVN of FIG. 5) to correspond one-to-one to the page buffers (PB of FIG. 5) included in the corresponding page buffer units UPB Can be configured. Thus, each bit line select transistor units UHVN may comprise a plurality of bit line select transistors (HVN of FIG. 5).

Although not shown, the page buffers included in each page buffer unit UPB may be arranged in a line along the first direction FD, and the bit lines included in each bit line select transistor units UHVN The selection transistors may also be arranged in a line along the first direction FD.

The bit line select transistor units UHVN may be connected to bit lines (not shown) via bit line contact pads 71B.

Corresponding page buffer units UPB may be disposed on one side of the bit line select transistor units UHVN in the second direction SD. On the other side of the bit line select transistor units UHVN in the second direction SD, contact regions CR can be defined. The bit line contact pads 71B may be disposed in the contact regions CR.

The bit line select transistor units UHVN may correspond to the contact regions CR, respectively. FIG. 7 illustrates a case where two bit line select transistor units (UHVN) disposed adjacent to each other in the second direction (SD) correspond to one contact region (CR).

The bit line select transistor units UHVN may be connected to the bit lines via bit line contact pads 71B located in corresponding respective contact regions CR.

The page buffer units UPB may be arranged along the first direction FD and the second direction SD. The page buffer units UPB arranged in a line along the first direction FD can be connected to each other. The page buffer units UPB arranged along the second direction SD may be spaced apart from each other at regular intervals.

The bit line select transistor units UHVN corresponding to odd-numbered page buffer units UPB among the page buffer units UPB arranged in a line along the first direction FD and the even- The bit line select transistor units UHVN corresponding to the bit lines UPB are not arranged in a line along the first direction FD but are connected to the page buffer units UPB arranged in a line along the first direction FD. As shown in FIG. The diagonal direction indicates a direction intersecting the first direction FD and the second direction SD. Thus, the bit line select transistor units UHVN can be arranged in a zigzag fashion along the oblique direction intersecting the first direction FD and the second direction SD.

The contact regions CR may have an arrangement corresponding to the bit line select transistor units UHVN. That is, the contact regions CR may be arranged in a zigzag fashion along the oblique direction intersecting the first direction FD and the second direction SD.

Routing wirings 71A may be formed in the same layer as the bit line contact pads 71B. The routing wirings 71A may be formed in a curved pattern so as to extend in the second direction SD and to pass between the contact regions CR.

FIGS. 8 and 9 are enlarged plan views of part B of FIG. 7, FIG. 10 is a cross-sectional view taken along the line C-C 'of FIG. 9, and FIG. 11 is a cross- sectional view taken along line D-D' of FIG.

8, the page buffer units UPB, the bit line select transistor units UHVN, the routing lines 71A, the bit line contact pads 71B and the first contacts 80, Only the page buffer units UPB, the bit line select transistor units UHVN, the first contacts 80 and the bit lines BL are shown in FIG.

8 to 11, a memory cell array 110 is disposed on a substrate 60 and a plurality of page buffer units UPB and bit line selection The transistor units UHVN may be arranged.

A semiconductor layer 10 is disposed on the page buffer units UPB and the bit line select transistor units UHVN and the memory cell array 110 can be stacked on the semiconductor layer 10. [

The memory cell array 110 includes a plurality of gate electrode films 20 and insulating films (not shown) alternately stacked in a vertical direction VD, gate electrode films 20 and insulating films in a vertical direction VD, (Not shown). A gate insulating layer 40 may be formed between the vertical channel layers 30 and the gate electrode layers 20 so as to surround the outer wall of the vertical channel layers 30. The gate insulating film 40 may include a tunnel insulating film, a charge storage, and a blocking insulating film.

A plurality of bit lines BL may be disposed above the memory cell array 110. Drains 50 may be disposed on the vertical channel films 30, respectively. The bit line contacts 52 may be disposed on the drains 50, respectively. The bit lines BL may be connected to the drains 50 through the bit line contacts 52. The bit lines BL extend in the second direction SD and can be arranged along the first direction FD.

A plurality of lower wiring layers 71A, 71B, 72, 73 may be formed between the page buffer units UPB and the bit line select transistor units UHVN and the semiconductor layer 10. [ For example, the lower wiring layers 71A, 71B, 72, and 73 may include first lower wiring layers 71A and 71B disposed at the uppermost portion, a third lower wiring layer 73 disposed at the lowermost portion, And 71B and the third lower wiring layer 73. The second lower wiring layer 72 may be formed of a metal such as aluminum,

The routing wirings 71A may be disposed in at least one of the first to third lower wiring layers 71A, 71B, 72, In the embodiment described with reference to the drawings, the routing interconnects 71A are arranged in the first lower interconnect layer.

The first lower wiring layers 71A and 71B may include the routing wirings 71A and the bit line contact pads 71B.

The bit line contact pads 71B serve to connect one of the bit lines BL and one of the bit line select transistors included in the bit line select transistor units UHVN, Pads 71B may correspond to one of bit line select transistor units UHVN and one of bit lines BL.

Each bit line contact pads 71B may be disposed in a contact region CR that is adjacent to the corresponding bit line select transistor unit UHVN in a second direction SD. Each of the contact pads 71B may overlap in the vertical direction VD with the corresponding bit line BL in the contact region CR.

The bit line contact pads 71B may be connected to the corresponding bit lines BL through the first contacts 80 formed in the vertical direction VD. The first contacts 80 penetrate the semiconductor layer 10 and the memory cell array 110 in the vertical direction VD at positions where the bit line contact pads 71B and the bit lines BL overlap, And can connect between the line contact pads 71B and the bit lines BL. A spacer insulating film 82 surrounding the outer walls of the first contacts 80 is formed between the first contacts 80 and the semiconductor layer 10 and between the first contacts 80 and the memory cell array 110 . The first contacts 80 and the semiconductor layer 10 and between the first contacts 80 and the memory cell array 110 can be insulated by the spacer insulating film 82. [

Each of the bit line select transistor units UHVN includes a third lower wiring contact 76, a third lower wiring layer 73, a second lower wiring contact 75, a second lower wiring layer 72, May be connected to the corresponding bit line contact pad 71B through the bit line contact pad 71B.

The third lower wiring layer 73 may be connected to the bit line select transistor unit UHVN through the third lower wiring contact 76. The third lower wiring contact 76 may be formed in the vertical direction VD on the bit line select transistor unit UHVN to connect the bit line select transistor unit UHVN and the third lower wiring layer 73.

The second lower wiring layer 72 may be connected to the third lower wiring layer 73 through the second lower wiring contact 75. The second lower wiring contact 75 may be formed in the vertical direction VD on the third lower wiring layer 73 to connect the third lower wiring layer 73 and the second lower wiring layer 72.

The bit line contact pad 71B may be connected to the second lower wiring layer 72 through the first lower wiring contact 74. [ The first lower wiring contact 74 may be formed on the second lower wiring layer 72 in the vertical direction VD to connect the second lower wiring layer 72 and the bit line contact pad 71B.

The routing wirings 71A may be elongated in the second direction SD. The routing wirings 71A may be formed in a curved pattern so as to pass between the first direction FD and the contact regions CR disposed in a zigzag manner in a diagonal direction intersecting with the second direction SD.

It is assumed that the bit line select transistor units are arranged in the first direction FD and the second direction SD in the same manner as the page buffer units UPB without being arranged in a zigzag manner. Since the contact regions where the bit line contact pads are located have an arrangement corresponding to the bit line select transistor units, the contact regions are also arranged in a zigzag fashion and are arranged along the first direction FD and the second direction SD Lt; / RTI > In this case, due to the bit line contact pads formed in the contact regions arranged in a line along the first direction FD, no space is secured in the first direction FD, so that the second direction It would not be possible to install wiring extending in the SD.

In this embodiment, the bit line select transistor units UHVN are arranged in a zigzag manner along the oblique direction intersecting the first direction FD and the second direction SD, The contact regions CR having the corresponding arrangement structure are arranged in a zigzag manner along the oblique direction intersecting the first direction FD and the second direction SD. The arrangement of these bit line select transistor units UHVN and contact regions CR allows the placement of routing interconnects 71A extending in the second direction SD in the same layer as the bit line contact pads 71B . Therefore, the degree of freedom of wiring design can be improved by avoiding the restriction due to the bit line contact pads 71B. In addition, since the routing wiring extending in the bit line direction (second direction) can be provided in the same layer as the bit line contact pads, the number of wiring layers can be reduced compared with the case where the routing wiring is formed in a separate layer from the bit line contact pads The size of the semiconductor memory device can be reduced.

12 is a plan view showing a part of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 12, at least one page buffer control line 90 may be disposed in the first direction FD on the page buffer units UPB arranged in a line along the first direction FD. The page buffer control line 90 may serve to convey one of the page buffer control signals (PB SIGNALS in FIG. 1).

The page buffer control line 90 may be formed under the first wiring layer where the routing wirings 71A and the bit line contact pads 71B are located. For example, the page buffer control line 90 may be formed in the second wiring layer (72 in FIG. 10) or the third lower wiring layer (73 in FIG. 10).

The page buffer units UPB arranged in a line along the first direction FD can be connected in common to the page buffer control lines 90 through the second contacts 92 formed in the vertical direction VD . That is, the page buffer units UPB arranged in a line along the first direction FD may share the page buffer control line 90. [

In this embodiment, the page buffer control lines 90 can be shared since the page buffer units UPB are arranged in a line along the first direction FD without being arranged in a zigzag form. Thus, since the page buffer control lines 90 need not be formed separately for each page buffer unit UPB, the number of page buffer control lines 90 can be reduced, and the page buffer control line 90 The size of the semiconductor memory device can be reduced.

13 is a plan view showing a part of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 13, bit line select transistor units UHVN and contact regions CR are arranged in a zigzag manner around page buffer units UPB arranged in a line along a first direction FD The bit line select transistor units UHVN and the contact regions CR about the page buffer units UPB and the spare areas SR are formed opposite to the second direction SD.

At least one of the column decoder (140 in FIG. 1) and the input / output buffer (180 in FIG. 1) may be distributed and arranged in the spare areas SR. In this case, the page buffer units (UPB) and the column decoder (140 in FIG. 1) or / and the page buffer units (UPB) and the input / output buffer (180 in FIG. 1) . Accordingly, since the distance between the page buffer units UPB and the column decoder 140 (FIG. 1) and / or the distance between the page buffer units UPB and the input / output buffer 180 .

14 is a block diagram schematically showing a memory system including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 14, a memory system 600 according to an embodiment of the present invention may include a non-volatile memory device 610 and a memory controller 620.

The nonvolatile memory device 610 may be constructed of the above-described semiconductor memory device and operated in the manner described above. The memory controller 620 may be configured to control the non-volatile memory device 610. May be provided as a memory card or a solid state disk (SSD) by the combination of the nonvolatile memory device 610 and the memory controller 620. [ The SRAM 621 is used as the operating memory of the processing unit 622. The host interface 623 has a data exchange protocol of the host connected to the memory system 600.

The error correction block 624 detects and corrects errors contained in data read from the non-volatile memory device 610.

The memory interface 625 interfaces with the non-volatile memory device 610. The processing unit 622 performs all control operations for data exchange of the memory controller 620.

Although it is not shown in the drawing, the memory system 600 according to the present invention can be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 610 may be provided in a multi-chip package comprising a plurality of flash memory chips

 The memory system 600 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. Particularly, the semiconductor memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) which has been actively studied recently. In this case, the memory controller 620 is configured to communicate with external (e.g., host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, will be.

15 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present invention.

15, a computing system 700 in accordance with the present invention includes a memory system 730 electrically coupled to a system bus 760, a microprocessor 720, a RAM 730, a user interface 740, (Not shown) for supplying the operating voltage of the computing system 700 when the computing system 700 according to the present invention is a mobile device, Will be additionally provided. Although it is not shown in the drawing, it is to be appreciated that the computing system 700 according to the present invention may be further provided with application chipsets, camera image processors (CIS), mobile DRAMs, It is obvious to those who have acquired knowledge. Memory system 730 may, for example, constitute a solid state drive / disk (SSD) using non-volatile memory to store data. Alternatively, the memory system 730 may be provided as a fusion flash memory (e.g., a one-nAND flash memory).

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments may be easily implemented by those skilled in the art from the description of the embodiments described above.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood that the invention can be variously modified and changed without departing from the technical scope thereof.

110: memory cell array
110_1 to 110_4: First to fourth planes
130_1 to 130_4: First to fourth page buffer circuits
71A: routing wiring
71B: bit line contact pads
UPB: page buffer units
UHVN: Bit line select transistor units
CR: contact areas
BL: bit lines
90: page buffer control line

Claims (15)

A plurality of bit lines disposed on the memory cell array and arranged in a first direction and extending in a second direction;
A plurality of bit line contact pads formed in a first wiring layer under the memory cell array and each connected to the bit lines through first contacts;
And a page buffer circuit formed on the first wiring layer lower substrate,
The page buffer circuit comprising: a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads;
A plurality of page buffer units each corresponding to the bit line select transistor units and each connected to a corresponding bit line select transistor unit,
Wherein the page buffer units are arranged along the first direction and the second direction,
Wherein the bit line select transistor units are arranged in a staggered manner along a diagonal direction intersecting with the first direction and the second direction and arranged adjacent to the corresponding page buffer unit in the second direction. 3. The semiconductor memory device of claim 1, further comprising: bit line select transistor units corresponding to odd-numbered page buffer units and bit line select transistors corresponding to even-number page buffer units among the page buffer units arranged in a line along the first direction And the transistor units are arranged to face each other in the oblique direction on opposite sides of the page buffer units arranged in a line along the first direction. 2. The semiconductor memory device of claim 1, wherein the bit line contact pads are disposed in a plurality of contact regions arranged in a zigzag manner corresponding to the bit line select transistor units. 4. The semiconductor memory device according to claim 3, wherein the page buffer unit and the contact region corresponding to each of the bit line select transistor units are disposed opposite to each other in the second direction around the corresponding bit line select transistor unit. 4. The semiconductor memory device according to claim 3, further comprising routing wirings formed in the first wiring layer and extending in the second direction and having a curved pattern to pass between the contact regions. 6. The semiconductor memory device according to claim 5, further comprising a peripheral circuit formed on a substrate below the first wiring layer and connected to the routing wirings. 7. The semiconductor memory device of claim 6, further comprising a page buffer control line formed in a second wiring layer between the page buffer circuit and the memory cell array and extending in the first direction,
Wherein the page buffer control lines are connected in common to page buffer units arranged in a line along the first direction. 8. The semiconductor memory device according to claim 7, wherein the second wiring layer is disposed under the first wiring layer. 2. The semiconductor memory device according to claim 1, further comprising: a plurality of bit line selection transistor units formed on the substrate below the first wiring layer and arranged in a distributed manner in regions located on opposite sides of the bit line selection transistor units, Further comprising a decoder. 2. The semiconductor memory device according to claim 1, further comprising: an input / output (I / O) unit disposed on the substrate below the first wiring layer and distributed to regions located on the opposite sides of the bit line selection transistor units from the page buffer units, Further comprising a buffer. A plurality of bit lines disposed on the memory cell array and arranged in a first direction and extending in a second direction;
Routing wires formed in a first wiring layer under the memory cell array and extending in the second direction;
A plurality of bit line contact pads formed on the first wiring layer and each connected to the bit lines through first contacts;
And a page buffer circuit formed on the substrate below the first wiring layer,
The page buffer circuit comprising: a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads;
And page buffer units each corresponding to the bit line select transistor units and each connected to a corresponding bit line select transistor unit,
Wherein the page buffer units are arranged along the first direction and the second direction,
Wherein the bit line select transistor units are arranged in a zigzag fashion along a diagonal direction intersecting with the first direction and the second direction and arranged adjacent to the corresponding page buffer unit in the second direction,
The bit line contact pads are disposed in contact regions arranged in a zigzag pattern corresponding to the bit line select transistor units,
And the routing wiring is formed in a curved pattern so as to pass between the contact regions. 12. The semiconductor memory device according to claim 11, wherein the page buffer and the contact region corresponding to each of the bit line select transistor units are disposed opposite to each other in the second direction around the corresponding bit line select transistor unit. 12. The semiconductor memory device according to claim 11, further comprising a page buffer control line formed in a second wiring layer between the page buffer circuit and the first wiring layer and extending in the first direction,
Wherein the page buffer control lines are connected in common to page buffer units arranged in a line along the first direction. A plurality of bit lines arranged along a first direction and extending in a second direction;
A plurality of bit line contact pads formed in a first wiring layer below the bit lines and connected to the bit lines through first contacts;
And a page buffer circuit formed on the substrate under the bit lines and connected to the memory cell array through the bit lines,
The page buffer circuit comprising: a plurality of bit line select transistor units coupled to the bit lines via the bit line contact pads;
A plurality of page buffer units each corresponding to the bit line select transistor units and each connected to a corresponding bit line select transistor unit,
Wherein the page buffer units are arranged along the first direction and the second direction,
Wherein the bit line select transistor units are arranged in a zigzag fashion along a diagonal direction intersecting with the first direction and the second direction and arranged adjacent to the corresponding page buffer unit in the second direction,
Wherein the bit line contact pads are disposed in a plurality of contact regions arranged in a zigzag pattern corresponding to the bit line select transistor units. 15. The semiconductor memory device according to claim 14, further comprising: a plurality of routing wirings formed in the first wiring layer and extending in the second direction and having a curved pattern to pass between the contact regions.

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