KR20190006892A - Light emitting device package - Google Patents

Abstract

The present invention provides a light emitting device package which can realize various colors, and is small in size and easy to mount. The light emitting device package according to one embodiment of the present invention includes: a plurality of light emitting chips configured to emit light having different wavelengths and arranged in a flip-chip structure; a molding member integrally formed to cover upper surfaces and side surfaces of the light emitting chips, in which a bottom surface of the molding member includes a first region where the plurality of light emitting chips are arranged and a second region surrounding the first region; a plurality of individual wirings disposed on a lower surface of the molding member and directly making contact with each of the first electrodes of the plurality of light emitting chips in the first region; a common wiring which is disposed on the lower surface of the molding member and commonly connected to and directly in contact with the second electrodes of the plurality of light emitting chips in the first region; and a plurality of electrode pads arranged in a second region of the lower surface of the molding member and connected to the plurality of individual wirings and the common wiring, respectively.

Description

[0001] LIGHT EMITTING DEVICE PACKAGE [0002]

Technical aspects of the present invention relate to a light emitting device package.

Semiconductor light emitting diodes (LEDs) are used not only as light sources for lighting devices, but also as light sources for various electronic products. In particular, it is widely used as a light source for various display devices such as a TV, a mobile phone, a PC, a notebook PC, and a PDA.

The conventional display device is mainly composed of a display panel composed of a liquid crystal display (LCD) and a backlight. In recent years, however, a backlight is not separately required by using an LED element as a pixel as it is. Such a display device can not only be made compact, but also can realize a high luminance display which is superior in light efficiency compared to the conventional LCD. In addition, since the aspect ratio of the display screen can be changed freely and can be implemented in a large area, it can be provided as a large display of various forms.

SUMMARY OF THE INVENTION One of the technical problems to be solved by the technical idea of the present invention is to provide a light emitting device package that can realize various colors and can be miniaturized and is easy to mount.

A light emitting device package according to an exemplary embodiment of the present invention includes a plurality of light emitting chips arranged in a flip chip shape, emitting light having different wavelengths, a plurality of light emitting chips Molding member, wherein a lower surface of the molding member includes a first region in which the plurality of light emitting chips are arranged and a second region surrounding the first region, the first region being disposed on a lower surface of the molding member, A plurality of individual wirings disposed on the lower surface of the molding member and contacting the first electrodes of the plurality of light emitting chips directly in the region, And a plurality of electrode pads disposed in a second region of the lower surface of the molding member and connected to the plurality of individual wirings and the common wirings, respectively.

A light emitting device package according to an embodiment of the present invention includes a plurality of pixel regions m and n arranged in a matrix of mxn, wherein m and n are integers larger than 1, and the plurality of pixel regions are respectively a first region and a first region A plurality of light emitting element units disposed in the plurality of pixel regions, and a molding member integrally formed to cover the plurality of light emitting element units. Wherein the plurality of light emitting element units are respectively disposed on a lower surface of the molding member, a red light emitting chip, a green light emitting chip, and a blue light emitting chip arranged in a flip chip form in the first region, And one common wiring directly connected to the red light emitting chip, the green light emitting chip, and the blue light emitting chip, respectively, the three separate wirings being directly connected to the blue light emitting chip, respectively; And four electrode pads connected to the individual wirings and the common wirings, respectively, and disposed in the second region of the pixel region.

A light emitting device package according to an embodiment of the present invention includes a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region, each of the first to fourth pixel regions having a first region and a second region, Emitting chips arranged in a flip chip form in each of the first regions of the first to fourth pixel regions, and a second region surrounding the first to fourth pixel regions, Wherein the first pixel region includes four electrode pads disposed in the second region and connected to the light emitting chips, and the second pixel region includes a second pixel region, Includes two electrode pads disposed in the second region and connected to at least a portion of the light emitting chips, wherein the first pixel region shares two second electrode pads with the adjacent second pixel region.

According to one embodiment of the present invention, it is possible to provide a light emitting device package that can be miniaturized and can be easily mounted, which can realize various colors.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

1 is a perspective view illustrating a light emitting device package according to an embodiment of the present invention.
2A and 2B are a plan view and a rear view of a light emitting device package according to an embodiment of the present invention.
3A, 3B and 3C are cross-sectional views taken along line I-I ', line II-II' and line III-III ', respectively, of the light emitting device package shown in FIG. 2A.
4 is a graph showing the change of the thickness of the molding material versus the transmittance.
5 and 6 are views illustrating light emitting devices employed in a light emitting device package according to an embodiment of the present invention.
7A to 7H are cross-sectional views illustrating a method of manufacturing a light emitting device package according to an embodiment of the present invention.
8 is a perspective view illustrating a light emitting device package according to an embodiment of the present invention.
9 is a cross-sectional view showing the light emitting device package of Fig.
10 is a perspective view illustrating a light emitting device package according to an embodiment of the present invention.
11 is a cross-sectional view showing the light emitting device package of Fig.
12 is a perspective view illustrating a light emitting device package according to an embodiment of the present invention.
13A and 13B are a plan view and a rear view illustrating a light emitting device package according to an embodiment of the present invention.
14A, 14B, and 14C are sectional views taken along line I-I ', line II-II', and line III-III ', respectively, of the light emitting device package shown in FIG. 13A.
15 is a plan view showing a light emitting device package according to an embodiment of the present invention.
16 is a cross-sectional view showing the light emitting device package of Fig.
17 is a cross-sectional view illustrating a light emitting device package according to an embodiment of the present invention.
18 is a cross-sectional view showing the light emitting device package of Fig.
19A and 19B are a plan view and a cross-sectional view illustrating a light emitting device package according to an embodiment of the present invention.
20 is a plan view showing a light emitting device package according to an embodiment of the present invention.
21 is a circuit diagram of a pixel set of a light emitting device package according to an embodiment of the present invention.
22 is a plan view showing a light emitting device package according to an embodiment of the present invention.
23 is a circuit diagram of a pixel set of a light emitting device package according to an embodiment of the present invention.
24 is a plan view showing a light emitting device package according to an embodiment of the present invention.
25 is a circuit diagram of a pixel set of a light emitting device package according to an embodiment of the present invention.
26 is a plan view showing a light emitting device package according to an embodiment of the present invention.
27 is a circuit diagram of a pixel set of a light emitting device package according to an embodiment of the present invention.
28A to 28D are cross-sectional views illustrating major steps of a method of manufacturing a light emitting device package according to an embodiment of the present invention.
29 is a schematic view of a display panel including a light emitting device package according to an embodiment of the present invention.
30 is a block diagram showing a configuration of a display device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view showing a light emitting device package 1 according to an embodiment of the present invention. 2A and 2B are a plan view and a rear view illustrating a light emitting device package 1 according to an embodiment of the present invention. 3 (a), 3 (b) and 3 (c) are cross-sectional views taken along lines I-I ', II-II' and III-III 'of the light emitting device package 1 shown in FIG. Sectional view.

1 to 3 (c), the light emitting device package 1 includes a plurality of light emitting chips C1, C2, and C3, a molding member 41, a plurality of individual wirings 21, 22, and 23 A common wiring 24, a plurality of electrode pads 31, 32, 33, and 34, and an insulating layer 43. [

The plurality of light emitting chips C1, C2, and C3 may be disposed apart from each other to emit different light.

The plurality of light emitting chips C1, C2, and C3 may emit red light, green light, and blue light, respectively. The light emitting chip C1 may be a red light emitting chip, the light emitting chip C2 may be a green light emitting chip, and the light emitting chip C3 may be a blue light emitting chip. The light emitting chip C 1 may include a semiconductor stack that emits red light and the light emitting chip C 2 may include a semiconductor stack that emits green light. The light emitting chip C 3 may include a semiconductor stack May include sieves. In one embodiment, the light emitting chips Cl, C2, and C3 may include a semiconductor stack that emits blue light or UV light, and the light emitting chip Cl may include a wavelength converting layer that emits red light , The light emitting chip C2 may include a wavelength conversion layer that emits green light, and the light emitting chip C3 may include a wavelength conversion layer that emits blue light.

The plurality of light emitting chips C1, C2, C3 may be arranged in a line along one direction. The chip distance d1 between the plurality of light emitting chips C1, C2, and C3 may be 10 占 퐉 or more, or 50 占 퐉 or more. The plurality of light emitting chips C1, C2, C3 may be arranged in a flip chip form. The main light emitting surfaces of the plurality of light emitting chips C1, C2 and C3 face upward and the first and second electrodes of the plurality of light emitting chips C1, C2 and C3 can be arranged to face downward have. The first electrodes of the plurality of light emitting chips C1, C2 and C3 are connected to a plurality of individual wirings 21, 22 and 23 and the second electrodes of the plurality of light emitting chips C1, May be connected to the common wiring 24 in common. When arranged in the form of a flip-chip, each of the light-emitting chips C1, C2, C3 may have an orientation angle of 160 DEG or more.

The molding member 41 may cover the upper surfaces and side surfaces of the plurality of light emitting chips C1, C2, C3. The molding member 41 can function to protect and support the plurality of light emitting chips C1, C2, and C3. The molding member 41 preferably has an elastic modulus of 2.0 GPa or more. The molding member 41 preferably has a coefficient of thermal expansion of 40 ppm / 占 폚 or lower, which is equal to or lower than the glass transition temperature Tg.

When the light emitting device package 1 is used as a pixel of a display panel, in order to obtain a high contrast ratio, the molding member 41 may be made of translucent resin. The molding member 41 may have a transmittance of 30% or more and 89% or less with respect to light having a wavelength of 460 nm to 480 nm on the basis of a thickness of 50 탆. The molding member 41 may have a transmittance of 30% or more and 89% or less with respect to light having a wavelength of 530 nm on the basis of a thickness of 50 탆. In order to obtain a high contrast ratio, the molding member 41 may have a brightness of 100 or less. The molding member 41 may preferably have a lightness of 40 or less. The brightness of the black PCB on which the light emitting device package 1 is mounted is about 20 and when the brightness of the molding member 41 is 40 or less, the light emitting device package 1 is turned off (turned off) It is difficult to visually recognize the difference in brightness of the black printed circuit board.

The molding member 41 may basically include a transparent material such as an epoxy resin, a silicone resin, a polyimide resin, and a polyester. In order to adjust transmittance and brightness, the molding member 41 may comprise 0.005 wt% or more and 1 wt% or less of carbon black. The carbon black can absorb light, and the shorter the wavelength, the greater the absorption. Preferably, the molding member 41 may comprise 0.005 wt% or more and 0.3 wt% or less of carbon black. The molding member 41 may further include an inorganic filler to control the thermal expansion coefficient and the elastic modulus. The inorganic filler may include fused silica particles or silicon oxide (SiO ₂ ) particles. The inorganic filler preferably has a maximum particle size of 100 mu m or less. When the inorganic filler is contained in an amount of 50 wt% or more, the light transmittance is lowered by light scattering.

The appropriate content of the carbon black contained in the molding member 41 may vary depending on the kind of the resin and the content of the inorganic filler. When the molding member 41 is a silicone resin containing 50 wt% of the inorganic filler, the molding member 41 is 0.04 wt% or more and 0.3 wt% or less of carbon black, more preferably 0.06 wt% or more and 0.2 wt% or less Of carbon black. When the molding member 41 is an epoxy resin containing 50 wt% of the inorganic filler, the molding member 41 may contain 0.04 wt% or more and 0.2 wt% or less of carbon black, more preferably 0.06 wt% or more And 0.12 wt% or less of carbon black. Part of the evaluation data is shown in Table 1 below.

Fig. 4 shows a change in thickness versus transmittance of a material (hereinafter referred to as a molding material) constituting a molding member. Fig. 4 shows the change in the transmittance of the molding material depending on the content of carbon black. And Figure 4 is for a molding material comprising a silicone resin containing 50 wt% of fused silica. The transmittance of FIG. 4 is a value for light of 520 nm wavelength. The transmittance decreases as the content of carbon black increases. The transmittance sharply decreases as the thickness of the molding material increases. When the content of carbon black is greater, the transmittance decreases more sharply as the thickness of the molding material increases. For example, in the case of containing 0.15 wt% of carbon black, the transmittance is 59.1% when the thickness of the molding material is 50 탆, and the transmittance is 12.6% when the thickness is 200 탆.

molding
material Color / Color saturation brightness R G B Transmittance by measurement wavelength 470 nm 530 nm 620 nm One 123 189 18 4 32 34 15.8 17.4 19.8 2 40 8 75 82 82 77 29.2 33.3 38.7 3 160 0 0 0 0 0 4.0 4.6 5.3 4 110 10 87 88 96 94 24.8 26.4 28.0 5 138 31 104 96 112 125 22.9 24.3 25.9 6 139 19 126 124 134 143 35.2 37.2 39.4 7 138 27 135 131 145 156 32.8 34.5 36.3 8 138 21 154 156 165 172 43.4 45.4 47.8 9 128 26 44 42 50 52 - - -

* Black PCB has a brightness of 20.

* The data in the above table (color / chroma, saturation, brightness, R, G, B coordinate values) are obtained by analyzing the optical image obtained by reflecting white light on each molding material.

* The transmittance of the above table is the result obtained by transmitting light of wavelengths of 470 nm, 530 nm and 620 nm to each molding material.

Molding material 1 Epoxy resin + silica 50 wt% + Carbon 0.08 wt%, thickness 200 탆

Molding material 2- Epoxy resin + silica 50 wt% + Carbon 0.04 wt%, thickness 200 탆

Molding material 3- Epoxy resin or Silicon resin + silica 50wt% + Carbon 1wt% or more, Thickness 200㎛

Molding material 4-Silicone resin + silica 50wt% + Carbon 0.08wt%, thickness 200m

Molding material 5-Silicone resin + silica 50 wt% + Carbon 0.04 wt%, thickness 300 탆

Molding material 6- Silicone resin + silica 50wt% + Carbon 0.04wt%, thickness 200m

Molding material 7- Silicone resin + silica 50 wt% + Carbon 0.02 wt%, thickness 300 탆

Molding material 8- Silicone resin + silica 50wt% + Carbon 0.02wt%, thickness 200m

Molding material 9- Epoxy resin + silica 87wt% + Carbon 0.3wt%, thickness 200㎛

In some cases, the molding member 41 does not include the carbon black, and may include an inorganic filler. The molding member 41 may include at least one of carbon black and an inorganic filler.

The molding member 41 may have a polyhedral shape, for example, a hexahedral shape, surrounding the plurality of light emitting chips C1, C2, and C3. The molding member 41 is formed so as to completely cover the plurality of light emitting chips C1, C2, and C3. The molding member 41 covers upper surfaces and side surfaces of the plurality of light emitting chips C1, C2, C3, and may be integrally formed. The total thickness c of the molding member 41 may be 500 탆 or less. More preferably, the total thickness c of the molding member 41 may be 20 탆 or more and 300 탆 or less, and the upper thickness of the molding member 41 formed on the upper surface of the plurality of light emitting chips C1, (b) may be 10 占 퐉 or more and 200 占 퐉 or less. For example, when the chip thickness a of the plurality of light emitting chips C1, C2, and C3 is about 10 占 퐉, the entire thickness c of the molding member 41 may be 20 占 퐉 or more and 130 占 퐉 or less , The upper thickness b of the molding member 41 formed on the upper surface of the plurality of light emitting chips C1, C2 and C3 may be 10 占 퐉 or more and 120 占 퐉 or less. For example, when the chip thickness a of the plurality of light emitting chips C1, C2, and C3 is about 100 占 퐉, the total thickness c of the molding member 41 may be 110 占 퐉 or more and 220 占 퐉 or less , The upper thickness b of the molding member 41 formed on the upper surface of the plurality of light emitting chips C1, C2, C3 may be 20 占 퐉 or more and 120 占 퐉 or less.

A plurality of light emitting chips C1, C2, C3 may be formed by thinly adjusting the upper thickness b of the molding member 41 formed on the upper surface of the plurality of light emitting chips C1, C2, C3 to 20 占 퐉 or more and 120 占 퐉 or less, The loss of the light emitted to the upper portion of the light sources C3 and C3 can be reduced. On the other hand, the thickness of the molding member 41 formed on the side surfaces of the plurality of light emitting chips C1, C2, C3 is greater than the thickness of the molding member 41 formed on the upper surfaces of the plurality of light emitting chips C1, The transmittance of the light emitted to the side surfaces of the plurality of light emitting chips C1, C2, C3 is relatively much lower. Therefore, since the periphery of the plurality of light emitting chips C1, C2, and C3 is dark, the contrast can be increased. Also, when the light emitting device package 1 is used as a pixel of a display panel, cross talk between neighboring light emitting device packages 1, i.e., pixels, does not occur.

The upper surface of the molding member 41 may include a surface roughness (concavo-convex structure) having a maximum value roughness Rmax of 2 탆 or more. The lower surface of the molding member 41 may include a first region in which the plurality of light emitting chips C1, C2, and C3 are arranged and a second region surrounding the first region. The first region may be, for example, a rectangular region. The second region may be a region of a rectangular ring structure.

The plurality of individual wirings 21, 22 and 23 are disposed on the lower surface of the molding member 41 and connected to the first electrodes of the plurality of light emitting chips C1, C2 and C3 in the first region , And extend from the first region to the second region. The plurality of individual wirings 21, 22, 23 can directly contact the first electrodes of the plurality of light emitting chips C1, C2, C3. The common wiring 24 is disposed on the lower surface of the molding member 41 and is commonly connected to the second electrodes of the plurality of light emitting chips C1, C2, C3 and extends from the first region to the second region . The common wiring 24 can directly contact the second electrodes of the plurality of light emitting chips C1, C2, C3. The plurality of individual wirings 21, 22, and 23 and the common wirings 24 may be made of a metal material. The metal material may include, for example, gold, silver, copper, aluminum, and the like.

The plurality of electrode pads 31, 32, 33, and 34 may be disposed in the second region of the lower surface of the molding member 41. The plurality of electrode pads 31, 32, 33, and 34 may be disposed adjacent to the vertexes of the lower surface of the molding member 41. The package distance d3 between the plurality of electrode pads 31, 32, 33 and 34 and the side surfaces of the molding member 41 may be 500 mu m or less, more preferably 200 mu m or less. The distance between the side surfaces of the light emitting chips C1 and C3 and the molding member 41 may be 520 占 퐉 or less, and more preferably 220 占 퐉 or less. The plurality of electrode pads 31, 32, 33 and 34 may be connected to a plurality of individual wirings 21, 22 and 23 and a common wiring 24, respectively. Specifically, the electrode pad 31 is in direct contact with the individual wiring 21, the electrode pad 32 is in direct contact with the individual wiring 22, and the electrode pad 33 is in direct contact with the individual wiring 23 . Then, the electrode pad 34 can directly contact the common wiring 24. The electrode pad 34 may be referred to as a common pad.

The plurality of electrode pads 31, 32, 33, and 34 may have a pad interval d2 of at least 50 mu m in at least one direction. The plurality of electrode pads 31, 32, 33, and 34 may have a pad size (PDS) of, for example, 50 μm × 50 μm or more. The plurality of electrode pads 31, 32, 33, and 34 may be made of a metal material. The metal material may include, for example, gold, silver, copper, aluminum, and the like.

The plurality of electrode pads 31, 32, 33, and 34 may be formed of a magnetic metal material. The magnetic metal material may include at least one of iron, nickel, and cobalt. For example, the magnetic metal material may include an Fe alloy, Ni-Fe-Mo, Fe-Si-Al, or the like. The plurality of electrode pads 31, 32, 33, and 34 may have a laminated structure in which the magnetic metal material having no magnetism and the magnetic metal material are coated on at least a part of the surface of the metal material. Since the plurality of electrode pads 31, 32, 33, and 34 include the magnetic metal material, the light emitting device package 1 can be easily attached to and detached from the printed circuit board (PCB) module. Therefore, the process of surface mounting the light emitting device package 1 on the PCB module can be simple and easy, and the failed light emitting device package 1 can be selectively and easily replaced. The printed circuit board (PCB) module includes metal pads to which a plurality of electrode pads 31, 32, 33, and 34 are attached, and the metal pads may include a magnetic metal material.

The insulating layer 43 may cover the wirings 21, 22, 23 and 24 on the lower surface of the molding member 41 and the electrode pads 31, 32, 33 and 34 may cover the wirings 21 and 22 , 23, 24). The insulating layer 43 has a plurality of individual wirings 21, 22 and 23 and common wirings 24 each having a contact area and a plurality of individual wirings 21, 22 and 23 and common wirings 24 And can be disposed on the lower surface of the molding member 41 such that the contact area is opened.

According to an embodiment of the present invention, since a printed circuit board (PCB) and a lead-frame are not used, a light emitting device for mounting light emitting chips on a printed circuit board (PCB) and a lead- The thickness of the light emitting device package 1 of the present invention is much thinner than that of the package. The thickness of the light emitting device package 1 may range from 30 to 500 mu m or from 100 to 300 mu m.

The package size (PKS) of the light emitting device package 1 may be, for example, 700 mu m.

5 and 6 are views showing light emitting chips that can be employed in a light emitting device package according to an embodiment of the present invention.

The light emitting chip 120 shown in Fig. 5 may include a light-transmitting substrate 121 and a semiconductor stacked body 125 disposed on the light-transmitting substrate 121. Fig.

The light-transmitting substrate 121 may be an insulating substrate such as sapphire. However, the present invention is not limited thereto, and the light-transmitting substrate 121 may be a conductive or semiconductor substrate that can ensure light transmission in addition to an insulating substrate. The upper surface of the light-transmitting substrate 121 may be a main light-emitting surface. Irregularities D may be formed on the upper surface of the light-transmitting substrate 121. The unevenness D can improve the quality of the grown single crystal while improving the light extraction efficiency.

The semiconductor laminated body 125 may include a first conductive semiconductor layer 125a, an active layer 125b and a second conductive semiconductor layer 125c sequentially disposed on the light-transmitting substrate 121. [ The buffer layer 122 may be disposed between the light-transmitting substrate 121 and the first conductivity type semiconductor layer 125a.

The buffer layer 122 may be In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1). For example, the buffer layer 122 may be GaN, AlN, AlGaN, InGaN. If necessary, a plurality of layers may be combined, or the composition may be gradually changed.

The first conductivity type semiconductor layer 125a is a nitride semiconductor semiconductor that satisfies n-type In _x Al _y Ga _{1 -x- y} N (0? _X <1, 0? _Y <1, 0? _X + y < And the n-type impurity may be Si. For example, the first conductivity type semiconductor layer 125a may include n-type GaN. The second conductivity type semiconductor layer 125c may be a nitride semiconductor layer that satisfies a relationship of p-type In _x Al _y Ga _{1 -x- y} N (0? _X <1, 0? _Y <1, 0? _X + y < And the p-type impurity may be Mg. For example, the second conductive semiconductor layer 125c may have a single-layer structure, but may have a multi-layer structure having different compositions. The active layer 125b may be a multiple quantum well (MQW) structure in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layer and the quantum barrier layer may have In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) . In a particular example, the quantum well layer may be In _x Ga _{1 - x} N (0 < x &lt; _{= 1} ) and the quantum barrier layer may be GaN or AlGaN. The active layer 125b is not limited to a multiple quantum well structure, but may be a single quantum well structure.

The semiconductor stacked body 125 is made of an InAlGaN-based nitride semiconductor material, but is not limited thereto.

The first and second electrodes 127 and 128 are formed on the mesa-etched region of the first conductivity type semiconductor layer 125a and the second conductivity type semiconductor layer 125c on the same surface (first surface) . For example, the first electrode 127 may include at least one of Al, Au, Cr, Ni, Ti, and Sn. The second electrode 128 may be formed of a reflective metal. For example, the second electrode 128 may include a material such as Ag, Ni, Al, Cr, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, As shown in FIG.

In the case where the semiconductor laminate 125 emits blue light or UV light, a wavelength conversion layer including a phosphor or a quantum dot may be further provided on the light-transmitting substrate 121.

The light emitting chip 130 shown in FIG. 6 includes a semiconductor stacked body 135 disposed on one surface of the light transmitting substrate 131. The semiconductor stack 135 may include a first conductive semiconductor layer 135a, an active layer 135b, and a second conductive semiconductor layer 135c.

The light emitting chip 130 includes first and second electrodes 137 and 138 connected to the first and second conductivity type semiconductor layers 135a and 135c, respectively. The first electrode 137 includes a connection electrode 137a such as a conductive via which is connected to the first conductivity type semiconductor layer 135a through the second conductivity type semiconductor layer 135c and the active layer 135b, And a first electrode pad 137b connected to the first electrode pad 137a. The connection electrode 137a may be surrounded by the insulating portion 133 and electrically separated from the active layer 135b and the second conductivity type semiconductor layer 135c. The connection electrode 137a may be disposed in an area where the semiconductor stacked body 135 is etched. The number, shape, pitch, or contact area between the connection electrode 137a and the first conductivity type semiconductor layer 135a can be appropriately designed so that the contact resistance is lowered. Further, the connection electrode 137a is arranged in rows and columns on the semiconductor stacked body 125, thereby improving the current flow. The second electrode 138 may include an ohmic contact layer 138a and a second electrode pad 138b on the second conductive semiconductor layer 135c.

The connection electrode 137a and the ohmic contact layer 138a may include a single layer or a multi-layer structure of the conductive material having ohmic characteristics with the first and second conductivity type semiconductor layers 135a and 135b, respectively. For example, a process of vapor-depositing or sputtering at least one of Ag, Al, Ni, Cr, and a transparent conductive oxide (TCO). The first and second electrode pads 137b and 138b may be respectively connected to the connection electrode 137a and the ohmic contact layer 138a to function as an external terminal of the light emitting chip 130. [ For example, the first and second electrode pads 137b and 138b may include Au, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, . The insulating portion 133 may include, for example, silicon oxide such as SiO ₂ , SiO _x N _y , Si _x N _y , or silicon nitride. The insulating portion 133 may disperse the light reflective filler in the light-transmitting material or introduce a distributed Bragg reflector (DBR) structure to secure a high reflectance.

When the semiconductor laminate 135 emits blue light or UV light, a wavelength conversion layer including a phosphor or a quantum dot may be further provided on the light-transmitting substrate 131.

7A to 7H are cross-sectional views of major processes illustrating a method of manufacturing the light emitting device package 1 according to an embodiment of the present invention. The manufacturing method is performed at the wafer level, and in FIGS. 7A to 7H, one light emitting device package region will be described.

7A, an adhesive tape 12 is stuck on a carrier wafer 11, and a plurality of light emitting chips C1, C2, and C3 are arranged at desired intervals. The plurality of light emitting chips (C1, C2, C3) can emit light of different wavelengths. The adhesive tape 12 may be, for example, a heat peeling tape. When the carrier wafer 11 has a property of transmitting UV, it may be a UV peeling tape. The adhesive tape 12 is not limited thereto.

Referring to FIG. 7B, the molding member 41 is formed to completely cover the plurality of light emitting chips C1, C2, and C3. The molding member 41 may be formed, for example, through a coating process and a curing process.

Referring to Fig. 7C, the carrier wafer 14 is attached to the upper surface of the molding member 41 using the adhesive tape 13. Fig. For example, the carrier wafer 14 may be a glass substrate that transmits UV, and the adhesive tape 13 may be a UV peeling tape. Alternatively, the adhesive tape 13 may be a heat peeling tape.

7D, the carrier wafer 11 is removed. For example, when the adhesive tape 12 is a heat peeling tape, the carrier wafer 11 can be removed by applying heat. The first and second electrodes of the plurality of light emitting chips C1, C2, and C3 may be exposed on one surface of the molding member 41. [

Referring to FIG. 7E, the individual wirings 21, 22, 23 and the plurality of light emitting chips C1, C2, C3 connected to the first electrodes of the plurality of light emitting chips C1, C2, A common wiring 24 is formed which is commonly connected to the second electrodes of the TFT array substrate. Then, the insulating layer 43 covering the individual wirings 21, 22, 23 and the common wiring 24 is formed. The insulating layer 43 has open regions for exposing the contact regions of the individual wirings 21, 22, 23 and the common wirings 24. The electrode pads 31, 32, 33, and 34 that contact the contact regions may be formed. A plurality of light emitting device packages may be formed on the carrier wafer 14.

7F, a tape 15 is attached to cover the electrode pads 31, 32, 33, and 34 of the plurality of light emitting device packages in order to remove the carrier wafer 14.

Referring to FIG. 7G, the carrier wafer 14 is removed. For example, when the adhesive tape 13 is a UV peeling tape, the carrier wafer 14 can be removed by irradiating UV light.

7H, the plurality of light emitting device packages are transferred to the dicing tape 16 and then cut into a desired size, for example, to a size including three light emitting chips C1, C2, and C3 So that individual light emitting device packages can be manufactured.

8 is a perspective view showing a light emitting device package 1A according to an embodiment of the present invention. 9 is a sectional view showing the light emitting device package 1A of Fig. Fig. 9 corresponds to a cross-sectional view taken along the line I-I 'in Fig.

Referring to FIGS. 8 and 9, the light emitting device package 1A may further include a metal layer 51 disposed on the upper surface of the molding member 41a, as compared with the light emitting device package 1. FIG.

The metal layer 51 may comprise any one of titanium, chromium, or combinations thereof. The metal layer 51 is a thin film formed to a thickness such that at least a part of the light emitted from the plurality of light emitting chips C1, C2, C3 can transmit. The metal layer 51 may be formed by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. In this embodiment, the molding member 41a may be made of only a transparent material such as an epoxy resin, a silicone resin, a polyimide resin, or a polyester. By forming the metal layer 51 on the upper surface of the transparent molding member 41a, a high contrast ratio can be obtained when the light emitting device package 1A is used as a pixel of a display panel.

10 is a perspective view showing a light emitting device package 1B according to an embodiment of the present invention. 11 is a cross-sectional view showing the light emitting device package 1B of Fig. 11 corresponds to a cross-sectional view taken along a line I-I 'in Fig.

10 and 11, the light emitting device package 1B may further include a lower layer 53 disposed on the lower surface of the molding member 41a, as compared with the light emitting device package 1. As shown in FIG.

The lower layer 53 may be formed of, for example, a black resin such as a black matrix containing chromium or a black pigment. The present invention is not limited thereto, and the lower layer 53 may comprise a suitable material capable of absorbing visible light. The lower layer 53 may be disposed to cover the insulating layer 43, exposing a plurality of electrode pads 31, 32, 33, and 34.

In this embodiment, the molding member 41a may be made of only a transparent material such as an epoxy resin, a silicone resin, a polyimide resin, or a polyester. By forming the lower layer 53 on the lower surface of the transparent molding member 41a, a high contrast ratio can be obtained when the light emitting device package 1B is used as a pixel of a display panel.

12 is a perspective view showing a light emitting device package 1C according to an embodiment of the present invention. 13A and 13B are a plan view and a rear view illustrating a light emitting device package 1C according to an embodiment of the present invention. 14A, 14B, and 14C are sectional views taken along line I-I ', line II-II', and line III-III ', respectively, of the light emitting device package 1C shown in FIG. 13A.

12 to 14C, the light emitting device package 1C further includes a partition wall structure 55 surrounding the plurality of light emitting chips C1, C2, C3 in comparison with the light emitting device package 1 . The barrier rib structure 55 may be formed of a black resin such as a black matrix. Further, the barrier rib structure 55 may be a metal structure whose surface is coated with titanium, chromium, or a combination thereof. The metal structure may be formed of, for example, copper, aluminum, or the like. The barrier rib structure 55 may be formed of a ceramic material such as glass frit. When the light emitting device package 1C further includes the partition wall structure 55, the light emitting device package 1C has a higher elastic modulus (2 GPa or more) and a higher elastic modulus And may have a low coefficient of thermal expansion (30 ppm / DEG C or less). Since the thermal expansion coefficient of the printed circuit board is 10 to 20 ppm / 占 폚, when the light emitting device package 1C is mounted on the printed circuit board, the mismatch of the thermal expansion coefficient is reduced and the reliability of the product can be improved . Further, the light emitting device package 1C can have a higher rigidity. The resin forming the molding member 41 has a thermal expansion coefficient of about 30 to 100 ppm / ° C. When the barrier structure 55 is a metal structure, it can function as a heat sink and have a high modulus of elasticity of 2 GPa or more and a low thermal expansion coefficient of 10 to 30 ppm / 占 폚. When the barrier rib structure 55 is made of glass frit, it can have a high elastic modulus of 2 GPa or more and a thermal expansion coefficient of 10 to 30 ppm / 占 폚.

The barrier structure 55 may have a sloped side wall, as shown. The height PT of the partition wall structure 55 may be larger than the chip thickness a of the plurality of light emitting chips C1, C2, C3. The height PT of the barrier rib structure 55 may be, for example, 80 占 퐉 or more. The upper surface of the partition wall structure 55 may be lower than the upper surface of the molding member 41. That is, the molding member 41 may cover the partition structure 55.

When the height of the barrier rib structure 55 is low, the directivity angle increases. When the height of the barrier rib structure 55 is high, the directivity angle is reduced but the color over angle (COA) can be reduced.

15 is a sectional view showing a light emitting device package 2 according to an embodiment of the present invention. 16 is a cross-sectional view taken along IV-IV 'of the light emitting device package 2 shown in FIG.

The light emitting device package 2 may include a plurality of pixel regions PX arranged in a matrix of m x n. Where m and n are integers greater than one. The structures corresponding to the light emitting device package 1 described with reference to Figs. 1 to 3 may be repeatedly arranged in the plurality of pixel regions PX. For example, the light emitting device package 2 may include a plurality of pixel regions PX arranged in a 3x4 matrix.

For convenience of explanation, the remaining components (the plurality of light emitting chips C1, C2, C3), the plurality of individual wirings 21, 22, and 23, except for the molding member 41 and the insulating layer 43, 22, and 23, the common wiring 24, and the plurality of electrode pads 31, 32, 33, and 34) are referred to as a light emitting element unit (LU).

The plurality of light emitting element units LU may be disposed in the plurality of pixel regions PX and the molding member 241 may be integrally formed to cover the plurality of light emitting element units LU.

The pixel region PX may include a first region in which a plurality of light emitting chips C1, C2, C3 are arranged and a second region surrounding the first region.

The light emitting element unit LU is disposed on the lower surface of the molding member 241 and includes a plurality of light emitting chips C1, C2 and C3 arranged in the first region of the pixel region PX, Three individual wirings 21, 22 and 23 respectively connected to the light emitting chips C1, C2 and C3 and a plurality of light emitting chips C1, C2 and C3 which are arranged on the lower surface of the molding member 241, And a plurality of electrode pads 31, 32, 33, 34 disposed in the second region of the pixel region PX. The plurality of electrode pads 31, 32, 33, and 34 may be disposed adjacent to the vertices of the pixel region PX.

The plurality of light emitting chips C1, C2, and C3 may be, for example, a red light emitting chip, a green light emitting chip, and a blue light emitting chip, respectively.

7A to 7G. In the process of FIG. 7H, the plurality of light emitting device packages are transferred to the dicing tape 16, and then cut into a desired size, For example, the individual light emitting device package 2 can be manufactured by cutting to a size including the light emitting device units (LU) of the matrix of 3 × 4.

17 is a sectional view showing a light emitting device package 2A according to an embodiment of the present invention. 18 is a cross-sectional view taken along line IV-IV 'of the light emitting device package 2A shown in Fig.

Referring to FIGS. 17 and 18, the light emitting device package 2A may further include a barrier structure 255 as compared with the light emitting device package 2.

The barrier rib structure 255 may be disposed between the plurality of light emitting element units (LU). The barrier rib structure 255 may be formed of a black resin such as a black matrix. Further, the barrier rib structure 255 may be a metal structure whose surface is coated with titanium, chromium, or a combination thereof. The metal structure may be formed of, for example, copper, aluminum, or the like.

The barrier structure 255 may have a sloped side wall, as shown. The height PT of the barrier rib structure 255 may be larger than the chip thickness a of the plurality of light emitting chips C1, C2, C3. The molding member 241 may cover the partition structure 255. The height PT of the barrier rib structure 255 may be, for example, 80 占 퐉 or more. The upper surface of the barrier rib structure 255 may be lower than the upper surface of the molding member 241. The width PW of the barrier rib structure 255 is 50 μm or more and is derived by the formula 'package size (PKS) - (light emitting chip size CS 3 × chip spacing d 1 × 2 + 50 μm) Lt; / RTI &gt; The package size (PKS) may be a pitch.

When the height of the barrier rib structure 255 is low, the directivity angle increases. When the height of the barrier rib structure 255 is high, the directivity angle decreases but the color over angle (COA) can be reduced.

19A and 19B are a plan view and a sectional view showing a light emitting device package 3 according to an embodiment of the present invention.

19A and 19B, the light emitting device package 3 differs from the light emitting device package 1 in the arrangement of the plurality of light emitting chips C1, C2, and C3. The plurality of light emitting chips C1, C2, C3 may be arranged in a triangular shape so as to be advantageous for miniaturization, instead of being arranged in a line. The light emitting device package 3 may have a smaller size than the light emitting device package 1. [ For example, the light emitting device package 1 may have a size of 700 mu m x 700 mu m, and the light emitting device package 3 may have a size of 500 mu m x 500 mu m. The light emitting device package 3 may be easy to realize a fine pitch required in a display of high picture quality (for example, 4K UHD, 8K UHD).

As the arrangement of the plurality of light emitting chips C1, C2, C3 is changed, the shape of the plurality of individual wirings 21, 22, 23 can be changed and the length can be shortened. The shape and length of the common wiring 24 can also be changed. The sizes of the plurality of electrode pads 31, 32, 33, and 34 can be reduced. For example, unlike the light emitting device package 1 of Figs. 2A and 2B, the plurality of individual wirings 21, 22, 23 and the common wirings 24 are formed by a plurality of light emitting chips C1, C2, May be disposed in the first region of the lower surface of the molding member 41 arranged. The first region may be, for example, a rectangular region.

In one embodiment, the arrangement of the plurality of light emitting chips C1, C2, C3 may be arranged in a 'Y' shape.

20 is a sectional view showing a light emitting device package 4 according to an embodiment of the present invention. 21 is a circuit diagram of a pixel set PS of a light emitting device package 4 according to an embodiment of the present invention.

20 and 21, the light emitting device package 4 may include a plurality of pixel regions PX1 and PX2 arranged in an m × n matrix. Where m and n are integers greater than one. For example, the light emitting device package 4 may include a plurality of pixel regions PX1 and PX2 arranged in a 4x4 matrix. The light emitting device package 4 may be driven in a passive matrix manner.

The plurality of pixel regions PX1 and PX2 may include a first region where a plurality of light emitting chips C1, C2, and C3 are arranged, and a second region surrounding the first region. The plurality of pixel areas PX1 and PX2 may be a plurality of pixel sets PS repeatedly arranged. The plurality of pixel sets PS may include a first pixel region PX1 and a second pixel region PX2, respectively. The plurality of light emitting chips C1, C2, and C3 may be arranged in the shape of "-11" in each of the pixel regions PX1 and PX2. That is, in each of the pixel regions PX1 and PX2, the light emitting chip C1 may be arranged in a direction rotated by 90 degrees, unlike the remaining light emitting chips C2 and C3.

The first pixel region PX1 is disposed on the lower surface of the molding member 341 and the plurality of light emitting chips C1, C2, C3 arranged in the first region. And three common wirings 21a, 22a and 23a connected to the plurality of light emitting chips C1, C2 and C3, respectively, arranged on the lower surface of the molding member 341, And four electrode pads 31a, 32a, 33a, and 34a disposed in the second region and connected to the individual wirings 21a, 22a, and 23a and the common wiring 24a, respectively. The four electrode pads 31a, 32a, 33a, and 34a may be disposed adjacent to the vertices of the first pixel region PX1.

The second pixel region PX2 is disposed on the lower surface of the molding member 341 and the plurality of light emitting chips C1, C2, C3 arranged in the first region, Three common wirings 21b, 22b and 23b respectively connected to the plurality of light emitting chips C1, C2 and C3 and three common wirings 21b, And two electrode pads 32b and 34b disposed in the second region and connected to the individual wiring 22b and the common wiring 24b, respectively.

The first pixel region PX1 may share two electrode pads with the adjacent second pixel region PX2. The individual wirings 21b connected to the first light emitting chip C1 of the second pixel region PX2 may be connected to the electrode pads 31a of the first pixel region PX1. The individual wirings 23b connected to the third light emitting chip C3 of the second pixel region PX2 may be connected to the electrode pads 33a of the first pixel region PX1. The electrode pad 31a may be connected to the first light emitting chip C1 of the first pixel region PX1 and the first light emitting chip C1 of the second pixel region PX2. The electrode pad 33a may be commonly connected to the third light emitting chip C3 of the first pixel region PX1 and the third light emitting chip C3 of the second pixel region PX2.

The molding member 341 may be formed integrally with the plurality of pixel regions PX1 and PX2. The molding member 341 may cover upper surfaces and side surfaces of the plurality of light emitting chips C1, C2, C3. The molding member 341 may be the same as the molding member 41 described above.

The plurality of light emitting chips C1, C2, and C3 may be, for example, a red light emitting chip, a green light emitting chip, and a blue light emitting chip, respectively.

The light emitting device package 4 in which neighboring pixel regions commonly use some electrode pads has a structure in which the number of electrode pads is reduced compared to the light emitting device package 2, . Accordingly, the light emitting device package 4 may be advantageous for manufacturing a light emitting device package having pixel regions of a smaller size. The light emitting device package 4 may be easy to implement a fine pitch required in a display of high picture quality (for example, 4K UHD, 8K UHD).

In one embodiment, unlike FIG. 20, one pixel set PS may constitute one light emitting device package.

22 is a sectional view showing a light emitting device package 4A according to an embodiment of the present invention. 23 is a circuit diagram of a pixel set PS 'of a light emitting device package 4A according to an embodiment of the present invention.

22 and 23, the light emitting device package 4A may include a plurality of pixel regions PX1, PX2, PX3, and PX4 arranged in an m × n matrix. Where m and n are integers greater than one. For example, the light emitting device package 4A may include a plurality of pixel regions PX1, PX2, PX3, and PX4 arranged in a 4x4 matrix. The light emitting device package 4A may be driven in a passive matrix manner.

The plurality of pixel regions PX1, PX2, PX3 and PX4 may include a first region in which a plurality of light emitting chips C1, C2 and C3 are arranged and a second region surrounding the first region, respectively . The plurality of pixel regions PX1, PX2, PX3, PX4 may be a plurality of pixel sets PS 'repeatedly arranged. The plurality of pixel sets PS 'may include a first pixel region PX1, a second pixel region PX2, a third pixel region PX3, and a fourth pixel region PX4, respectively. The plurality of light emitting chips C1, C2, and C3 may be arranged in the shape of "-11" in each of the pixel regions PX1 and PX2. That is, in each of the pixel regions PX1 and PX2, the light emitting chip C1 may be arranged in a direction rotated by 90 degrees, unlike the remaining light emitting chips C2 and C3.

The first pixel region PX1 is disposed on the lower surface of the molding member 341 and the plurality of light emitting chips C1, C2, C3 arranged in the first region. And three common wirings 21a, 22a and 23a connected to the plurality of light emitting chips C1, C2 and C3, respectively, arranged on the lower surface of the molding member 341, And four electrode pads 31a, 32a, 33a, and 34a disposed in the second region and connected to the individual wirings 21a, 22a, and 23a and the common wiring 24a, respectively. The four electrode pads 31a, 32a, 33a, and 34a may be disposed adjacent to the vertices of the first pixel region PX1.

The second pixel region PX2 is disposed on the lower surface of the molding member 341 and the plurality of light emitting chips C1, C2, C3 arranged in the first region, Three common wirings 21b, 22b and 23b respectively connected to the plurality of light emitting chips C1, C2 and C3 and three common wirings 21b, And two electrode pads 32b and 34b disposed in the second region and connected to the individual wiring 22b and the common wiring 24b1, respectively.

The first pixel region PX1 may share two electrode pads with the adjacent second pixel region PX2. The individual wirings 21b connected to the first light emitting chip C1 of the second pixel region PX2 may be connected to the electrode pads 31a of the first pixel region PX1. The individual wirings 23b connected to the third light emitting chip C3 of the second pixel region PX2 may be connected to the electrode pads 33a of the first pixel region PX1. The electrode pad 31a may be connected to the first light emitting chip C1 of the first pixel region PX1 and the first light emitting chip C1 of the second pixel region PX2. The electrode pad 33a may be commonly connected to the third light emitting chip C3 of the first pixel region PX1 and the third light emitting chip C3 of the second pixel region PX2.

The third pixel region PX3 is disposed on the lower surface of the plurality of light emitting chips C1, C2, C3 and the molding member 341 disposed in the first region, and the plurality of light emitting chips C1, C2, C3 And three common wirings 21c, 22c and 23c connected to the plurality of light emitting chips C1, C2 and C3, respectively, arranged on the lower surface of the molding member 341, And four electrode pads 31c, 32c, 33c, and 34c disposed in the second region and connected to the individual wirings 21c, 22c, and 23c and the common wiring 24c, respectively. The four electrode pads 31c, 32c, 33c, and 34c may be disposed adjacent to the vertices of the third pixel region PX3.

The fourth pixel region PX4 is disposed on a lower surface of the plurality of light emitting chips C1, C2, C3 and the molding member 341 disposed in the first region, and the plurality of light emitting chips C1, C2, C3 Three common wires 21d, 22d and 23d respectively connected to the plurality of light emitting chips C1, C2 and C3 and three common wires 21d, 24d and one electrode pad 32d connected to the individual wiring 22d.

The third pixel region PX3 may share two electrode pads with the adjacent fourth pixel region PX4. The individual wiring 21d connected to the first light emitting chip C1 of the fourth pixel region PX2 may be connected to the electrode pad 31c of the third pixel region PX3. The individual wiring 23d connected to the third light emitting chip C3 of the fourth pixel region PX4 may be connected to the electrode pad 33c of the third pixel region PX3. The electrode pad 31c may be commonly connected to the first light emitting chip C1 of the third pixel region PX3 and the first light emitting chip C1 of the fourth pixel region PX4. The electrode pad 33c may be commonly connected to the third light emitting chip C3 of the third pixel region PX3 and the third light emitting chip C3 of the fourth pixel region PX4.

The second pixel region PX2 may share one electrode pad with the adjacent fourth pixel region PX4. The common wiring 24d connected to the plurality of light emitting chips C1, C2 and C3 of the fourth pixel region PX2 may be connected to the electrode pad 34b of the second pixel region PX2. The electrode pads 34b are formed on the plurality of light emitting chips C1, C2, C3 of the second pixel region PX2 and the plurality of light emitting chips C1, C2, C3 of the fourth pixel region PX4 Can be connected.

The molding member 341 may be formed integrally with the plurality of pixel regions PX1 and PX2. The molding member 341 may cover upper surfaces and side surfaces of the plurality of light emitting chips C1, C2, C3. The molding member 341 may be the same as the molding member 41 described above.

The plurality of light emitting chips C1, C2, and C3 may be, for example, a red light emitting chip, a green light emitting chip, and a blue light emitting chip, respectively.

The light emitting device package 4A in which neighboring pixel regions commonly use some electrode pads has a structure in which the number of electrode pads is reduced compared to the light emitting device package 2, . Accordingly, the light emitting device package 4A can be advantageous for manufacturing a light emitting device package having pixel regions of a smaller size. The light emitting device package 4A may be easy to implement a fine pitch required in a display of high picture quality (for example, 4K UHD, 8K UHD).

In one embodiment, unlike FIG. 22, one pixel set PS 'may constitute one light emitting device package.

24 is a sectional view showing a light emitting device package 4B according to an embodiment of the present invention. 25 is a circuit diagram of a pixel set PS '' of a light emitting device package 4B according to an embodiment of the present invention.

24 and 25, in the light emitting device package 4B, the arrangement of the electrode pads of the first pixel region PX1 'and the second pixel region PX2' is different from that of the light emitting device package 4 . The difference will be explained below.

The plurality of pixel sets PS 'may include a first pixel region PX1' and a second pixel region PX2 ', respectively.

The first pixel region PX1 'includes three individual wirings 21a, 22a and 23a respectively connected to the plurality of light emitting chips C1, C2 and C3 and a plurality of light emitting chips C1, And one common wiring 24a commonly connected to the common wiring 24a. And three electrode pads 32a, 33a, and 34a connected to the individual wirings 22a and 23a and the common wiring 24a, respectively. The electrode pad 34a may be disposed so as to overlap the boundaries of the first pixel region PX1 'and the second pixel region PX2'. That is, a portion of the electrode pad 34a may be disposed in the second pixel region PX2 '.

The second pixel region PX2 'includes three individual wirings 21b, 22b, and 23b and a plurality of light emitting chips C1, C2, and C3 connected to the plurality of light emitting chips C1, C2, And one common wiring 24b commonly connected to each other. Three electrode pads 31b, 32b, and 34b connected to the individual wirings 21b and 22b and the common wiring 24b, respectively. The electrode pad 32b may be disposed to overlap the boundaries of the first pixel region PX1 'and the second pixel region PX2'. That is, a portion of the electrode pad 32b may be disposed in the first pixel region PX1 '.

The first pixel region PX1 'and the second pixel region PX2' may share two electrode pads. The individual wirings 21a connected to the first light emitting chip C1 of the first pixel region PX1 'may be connected to the electrode pads 31b of the second pixel region PX2'. The individual wiring 23b connected to the third light emitting chip C3 of the second pixel region PX2 'may be connected to the electrode pad 33a of the first pixel region PX1'. The electrode pad 31b may be connected to the first light emitting chip C1 of the first pixel region PX1 'and the first light emitting chip C1 of the second pixel region PX2'. The electrode pad 33a may be commonly connected to the third light emitting chip C3 of the first pixel region PX1 'and the third light emitting chip C3 of the second pixel region PX2'.

The light emitting device package 4B in which a part of the electrode pads commonly use adjacent pixel regions has a structure in which the number of electrode pads is reduced compared to the light emitting device package 2, . Therefore, the light emitting device package 4B can be advantageous for manufacturing a light emitting device package having pixel regions of a smaller size. The light emitting device package 4B may be easy to implement a fine pitch required in a display of high picture quality (for example, 4K UHD, 8K UHD).

In one embodiment, unlike FIG. 24, one pixel set PS &quot; may constitute one light emitting device package.

26 is a sectional view showing a light emitting device package 4C according to an embodiment of the present invention. 27 is a circuit diagram of a pixel set PS '' 'of a light emitting device package 4C according to an embodiment of the present invention.

Referring to FIGS. 26 and 27, the light emitting device package 4C includes a first pixel region PX1 ', a second pixel region PX2', a third pixel region PX3 ' , And the arrangement of the electrode pads of the fourth pixel region PX4 'is different. The difference will be explained below.

The plurality of pixel sets PS '' 'include a first pixel region PX1', a second pixel region PX2 ', a third pixel region PX3', and a fourth pixel region PX4 ' can do.

The first pixel region PX1 'includes three individual wirings 21a, 22a, and 23a, a plurality of light emitting chips C1, C2, and C3 connected to the plurality of light emitting chips C1, C2, and C3, And three electrode pads 32a, 33a, and 34a connected to the common wiring 24a and the common wiring 24a, respectively, which are commonly connected to the common wiring 24a and the common wiring 24a. The electrode pad 34a may be disposed so as to overlap the boundaries of the first pixel region PX1 'and the second pixel region PX2'. That is, a portion of the electrode pad 34a may be disposed in the second pixel region PX2 '.

The second pixel region PX2 'includes three individual wirings 21b, 22b, and 23b and a plurality of light emitting chips C1, C2, and C3 connected to the plurality of light emitting chips C1, C2, And one common wiring 24b commonly connected to each other. Three electrode pads 31b, 32b, and 34b connected to the individual wirings 21b and 22b and the common wiring 24b, respectively. The electrode pad 32b may be disposed to overlap the boundaries of the first pixel region PX1 'and the second pixel region PX2'. That is, a portion of the electrode pad 32b may be disposed in the first pixel region PX1 '.

The first pixel region PX1 'and the second pixel region PX2' may share two electrode pads. The individual wirings 21a connected to the first light emitting chip C1 of the first pixel region PX1 'may be connected to the electrode pads 31b of the second pixel region PX2'. The individual wiring 23b connected to the third light emitting chip C3 of the second pixel region PX2 'may be connected to the electrode pad 33a of the first pixel region PX1'. The electrode pad 31b may be connected to the first light emitting chip C1 of the first pixel region PX1 'and the first light emitting chip C1 of the second pixel region PX2'. The electrode pad 33a may be commonly connected to the third light emitting chip C3 of the first pixel region PX1 'and the third light emitting chip C3 of the second pixel region PX2'.

The third pixel region PX3 'includes three individual wirings 21c, 22c, and 23c, a plurality of light emitting chips C1, C2, and C3 connected to the plurality of light emitting chips C1, C2, And three electrode pads 32c, 33c, and 34c connected to the common wiring 24c and the individual wirings 22c and 23c and common wiring 24c, respectively, which are commonly connected to the common wiring 24c. The electrode pad 34c may be disposed so as to overlap the boundary between the third pixel region PX3 'and the fourth pixel region PX4'. That is, a portion of the electrode pad 34c may be disposed in the fourth pixel region PX4 '.

The fourth pixel region PX4 'includes three individual wirings 21d, 22d, and 23d and a plurality of light emitting chips C1, C2, and C3 connected to the plurality of light emitting chips C1, C2, And one common wiring 24d commonly connected to each other. And two electrode pads 31d and 32d connected to the individual wirings 21d and 22d, respectively. The electrode pad 32d may be disposed so as to overlap the boundary between the third pixel region PX3 'and the fourth pixel region PX4'. That is, a portion of the electrode pad 32d may be disposed in the third pixel region PX3 '.

The third pixel region PX3 'and the fourth pixel region PX4' may share two electrode pads. The individual wiring 21c connected to the first light emitting chip C1 of the third pixel region PX3 'may be connected to the electrode pad 31d of the fourth pixel region PX4'. The individual wiring 23d connected to the third light emitting chip C3 of the fourth pixel region PX4 'may be connected to the electrode pad 33c of the third pixel region PX3'. The electrode pad 31d may be commonly connected to the first light emitting chip C1 of the third pixel region PX3 'and the first light emitting chip C1 of the fourth pixel region PX4'. The electrode pad 33c may be commonly connected to the third light emitting chip C3 of the third pixel region PX3 'and the third light emitting chip C3 of the fourth pixel region PX4'.

The second pixel region PX2 'may share one electrode pad with the adjacent fourth pixel region PX4'. The common wiring 24d connected to the plurality of light emitting chips C1, C2 and C3 of the fourth pixel region PX2 'may be connected to the electrode pad 34b of the second pixel region PX2'. The electrode pad 34b is connected to the plurality of light emitting chips C1, C2 and C3 of the second pixel region PX2 'and the plurality of light emitting chips C1, C2 and C3 of the fourth pixel region PX4' Can be connected in common.

The light emitting device package 4C in which a portion of the electrode pads commonly use neighboring pixel regions has a structure in which the number of electrode pads is reduced compared to the light emitting device package 2, . Therefore, the light emitting device package 4B can be advantageous for manufacturing a light emitting device package having pixel regions of a smaller size. The light emitting device package 4B may be easy to implement a fine pitch required in a display of high picture quality (for example, 4K UHD, 8K UHD).

In one embodiment, unlike FIG. 26, one pixel set PS '' 'may constitute one light emitting device package.

28A to 28D are cross-sectional views illustrating major steps of a method of manufacturing a light emitting device package according to an embodiment of the present invention. Although the manufacturing method according to the present embodiment is for manufacturing a plurality of light emitting device packages, for convenience of description, one light emitting device package region will be mainly described in FIGS. 28A to 28D.

Referring to Fig. 28A, a plurality of light emitting chips C1, C2, C3 are attached to a first adhesive tape 112 at a desired interval and in a desired arrangement. The plurality of light emitting chips (C1, C2, C3) can emit light of different wavelengths. The first adhesive tape 112 may be, for example, a heat peeling tape or a UV peeling tape. The first adhesive tape 112 is not limited thereto.

Referring to FIG. 28B, the molding member 41 is formed so as to completely cover the plurality of light emitting chips C1, C2, and C3. The molding member 41 may be formed, for example, through a coating process and a curing process. The molding member 41 may include carbon black as described above.

Referring to Fig. 28C, after attaching the second adhesive tape 113 to the upper surface of the molding member 41, the first adhesive tape 112 is removed. The second adhesive tape 113 has a higher adhesive force than the first adhesive tape 112. The second adhesive tape 13 may be a UV peeling tape. The adhesive tape 13 may be a heat peeling tape. When the first adhesive tape 112 is removed, the first and second electrodes of the plurality of light emitting chips C1, C2, and C3 may be exposed to one surface of the molding member 41. [

The individual wirings 21, 22, 23, the common wiring 24, and the electrode pads 31, 32, 33, 34 are formed by using the printing technique. The individual wirings 21, 22, 23, the common wiring 24, and the electrode pads 31, 32, 33, 34 can be formed at the same time. The periphery of the individual wirings 21, 22, 23, the common wirings 24, and the electrode pads 31, 32, 33, 34 can be optionally filled with an insulating material.

Referring to FIG. 28D, for example, three light emitting chips C1, C2, and C3 and four electrode pads 31 and 32 are formed by cutting a plurality of light emitting device packages to a desired size using a blade or a laser , 33, and 34, the individual light emitting device package can be manufactured.

29 is a view schematically showing a display panel according to an embodiment of the present invention.

Referring to FIG. 29, a display panel 1000 may include a plurality of pixels 1100 mounted on a circuit board 1200 in a matrix form with a circuit board 1200. In Figure 29, pixels 1100 are shown as being arranged in a 9 x 16 matrix, but this is only an example. The number of pixels 1100 mounted according to the resolution and size of the display panel 1000 can be variously modified. The light emitting device packages 1, 1A, 1B, 1C, 2, 2A, 3, 4, 4A, 4B and 4C according to the embodiments of the present invention may constitute the pixels 1100. When the light emitting device packages 1, 1A, 1B, 1C, 2, 2A, 3, 4, 4A, 4B, 4C are employed in the embodiments of the present invention, The number of processes can be reduced, and the time of the surface mounting process can be shortened. The light emitting chips C1, C2 and C3 of the light emitting device packages 1, 1A, 1B, 1C, 2, 2A, 3, 4, 4A, 4B and 4C according to the embodiments of the present invention, 1000). &Lt; / RTI &gt;

The circuit board 1200 may include a driving circuit (such as a TFT array) configured such that the sub pixels (e.g., R, G, B sub pixels) of the display panel 1000 are driven independently.

The display panel 1000 may further include a protective layer for protecting the pixels 1100 from the outside. In addition, the display panel 1000 may further include a polarizing layer for adjusting the direction of light emitted from the pixels 1100 to make the screen clear and sharp.

30 is a block diagram showing a configuration of a display device according to an embodiment of the present invention.

Referring to FIG. 30, the display panel 1000 shown in FIG. 29 may constitute a display device together with the panel driver 1020 and the controller 1050. Here, the display device can be implemented as a display of various electronic devices such as an electric signboard, a video wall, a TV, an electronic board, an electronic table, a large format display (LFD), a smart phone, a tablet, a desktop PC, .

The panel driving unit 1020 can drive the display panel 1000 and the control unit 1050 can control the panel driving unit 1020. The panel driver 1020 controlled through the controller 1050 may be configured such that each of a plurality of subpixels including R (Red), G (Green), and B (Blue) is independently turned on / off.

For example, the panel driver 1020 may turn on / off each of the plurality of subpixels by transmitting a clock signal having the specific driving frequency to each of the plurality of subpixels. The controller 1050 controls the panel driver 1020 to turn on the plurality of subpixels according to the input video signal so that a desired image can be displayed on the display panel 1000.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

1, 1A, 1B, 1C, 2, 2A, 3, 4, 4A, 4B,
C1, C2, C3: light emitting chip
21, 22, 23: Individual wiring
24: Common wiring
31, 32, 33, 34: electrode pads
41, 241: Molding member
43: Insulating layer
51: metal layer
53:

Claims (10)

A plurality of light emitting chips emitting light of different wavelengths and arranged in a flip chip form;
A molding member integrally formed to cover upper surfaces and sides of the plurality of light emitting chips, the lower surface of the molding member including a first region in which the plurality of light emitting chips are arranged and a second region surrounding the first region -;
A plurality of individual wirings disposed on a lower surface of the molding member and in direct contact with the first electrodes of the plurality of light emitting chips in the first region;
A common wiring disposed on a lower surface of the molding member and connected in common to the second electrodes of the plurality of light emitting chips in the first region and in direct contact therewith; And
And a plurality of electrode pads disposed in a second region of the lower surface of the molding member and connected to the plurality of individual wirings and the common wirings, respectively.
The method according to claim 1,
Wherein the molding member is made of a translucent material having a transmittance of 30% or more and 89% or less with respect to light having a wavelength of 530 nm and a lightness of 40 or less.
3. The method of claim 2,
Wherein the molding member comprises 0.06 wt% or more and 0.02 wt% or less of carbon black.
The method of claim 3,
Wherein a thickness of the molding member on the upper surface of the plurality of light emitting chips is 10 nm or more and 120 占 퐉 or less.
The method according to claim 1,
And a metal thin film disposed on an upper surface of the molding member.

The method according to claim 1,
And a lower layer disposed to cover the molding member while exposing the plurality of electrode pads, wherein the lower layer is made of a black resin.
The method according to claim 1,
Further comprising a barrier structure disposed around the plurality of light emitting chips and having a higher height than the plurality of light emitting chips,
And the molding member covers the barrier rib structure.
a plurality of pixel regions arranged in a matrix of mxn-m and n are integers greater than 1, the plurality of pixel regions each comprising a first region and a second region surrounding the first region;
A plurality of light emitting element units disposed in the plurality of pixel regions; And
And a molding member integrally formed to cover the plurality of light emitting element units,
Wherein each of the plurality of light emitting element units includes:
A red light emitting chip, a green light emitting chip, and a blue light emitting chip arranged in a flip chip form in the first region;
Three individual wirings disposed on the lower surface of the molding member and directly connected to the red light emitting chip, the green light emitting chip, and the blue light emitting chip, respectively;
One common wiring disposed on the lower surface of the molding member and directly connected to the red light emitting chip, the green light emitting chip and the blue light emitting chip in common; And
And four electrode pads respectively connected to the individual wirings and the common wirings and disposed in the second region of the pixel region.
A first pixel region, a second pixel region, a third pixel region, and a fourth pixel region, the first through fourth pixel regions each including a first region and a second region surrounding the first region;
Light emitting chips arranged in a flip chip manner in each of the first regions of the first to fourth pixel regions; And
And a molding member integrally formed to cover the light emitting chips of the first to fourth pixel regions,
The first pixel region includes four electrode pads disposed in the second region and connected to the light emitting chips,
The second pixel region includes two electrode pads disposed in the second region and connected to at least a portion of the light emitting chips,
Wherein the first pixel region shares two adjacent electrode pads with the second pixel region.
10. The method of claim 9,
The third pixel region includes four electrode pads disposed in the second region and connected to the light emitting chips,
And the fourth pixel region includes one electrode pad disposed in the second region and connected to at least one of the light emitting chips,
Wherein the third pixel region shares two adjacent electrode pads with the fourth pixel region,
Wherein the second pixel region shares one electrode pad with the fourth pixel region adjacent thereto.

Images