KR20180122565A - 로우 큐 깊이 환경에서의 n-레벨 nand 플래시 셀들의 프로그래밍 - Google Patents

로우 큐 깊이 환경에서의 n-레벨 nand 플래시 셀들의 프로그래밍 Download PDF

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KR20180122565A
KR20180122565A KR1020180051315A KR20180051315A KR20180122565A KR 20180122565 A KR20180122565 A KR 20180122565A KR 1020180051315 A KR1020180051315 A KR 1020180051315A KR 20180051315 A KR20180051315 A KR 20180051315A KR 20180122565 A KR20180122565 A KR 20180122565A
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South Korea
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pages
page
sequence
data
memory
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Korean (ko)
Inventor
티모시 엘. 카네파
알렉스 탕
스티븐 한나
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시게이트 테크놀로지 엘엘씨
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020180051315A 2017-05-03 2018-05-03 로우 큐 깊이 환경에서의 n-레벨 nand 플래시 셀들의 프로그래밍 Ceased KR20180122565A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/585,429 US9905294B1 (en) 2017-05-03 2017-05-03 Writing logically offset pages of data to N-level memory cells coupled to a common word line
US15/585,429 2017-05-03

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Publication Number Publication Date
KR20180122565A true KR20180122565A (ko) 2018-11-13

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KR1020180051315A Ceased KR20180122565A (ko) 2017-05-03 2018-05-03 로우 큐 깊이 환경에서의 n-레벨 nand 플래시 셀들의 프로그래밍

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Country Link
US (1) US9905294B1 (cg-RX-API-DMAC10.html)
JP (1) JP2018190483A (cg-RX-API-DMAC10.html)
KR (1) KR20180122565A (cg-RX-API-DMAC10.html)
CN (1) CN108806754B (cg-RX-API-DMAC10.html)
TW (1) TWI689926B (cg-RX-API-DMAC10.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11609718B1 (en) * 2017-06-12 2023-03-21 Pure Storage, Inc. Identifying valid data after a storage system recovery
US11593262B1 (en) 2018-04-25 2023-02-28 Seagate Technology Llc Garbage collection command scheduling
US10922014B1 (en) 2018-06-05 2021-02-16 Seagate Technology Llc Die access order variation
US11138069B2 (en) 2018-06-11 2021-10-05 Seagate Technology, Llc Providing additional parity for non-standard sized parity data sets
US10896002B2 (en) 2018-06-29 2021-01-19 Seagate Technology Llc Reverse directory structure in a garbage collection unit (GCU)
US20200183622A1 (en) * 2018-12-07 2020-06-11 Micron Technology, Inc. Memory circuit package with adjustable active channel count
KR102740370B1 (ko) * 2019-03-28 2024-12-06 에스케이하이닉스 주식회사 메모리 시스템, 메모리 컨트롤러 및 그 동작 방법
US10956049B2 (en) * 2019-06-12 2021-03-23 International Business Machines Corporation Wear-aware block mode conversion in non-volatile memory
US11294820B2 (en) * 2019-06-28 2022-04-05 Micron Technology, Inc. Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
US11243711B2 (en) 2020-02-05 2022-02-08 Micron Technology, Inc. Controlling firmware storage density based on temperature detection
US11403228B2 (en) * 2020-02-18 2022-08-02 Micron Technology, Inc. Memory device page program sequence
US11275687B2 (en) 2020-07-07 2022-03-15 Micron Technology, Inc. Memory cache management based on storage capacity for parallel independent threads
US11783893B2 (en) * 2020-12-23 2023-10-10 Intel Corporation Utilizing NAND buffer for DRAM-less multilevel cell programming

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7210001B2 (en) 1999-03-03 2007-04-24 Adaptec, Inc. Methods of and apparatus for efficient buffer cache utilization
KR100389867B1 (ko) 2001-06-04 2003-07-04 삼성전자주식회사 플래시 메모리 관리방법
US7085909B2 (en) * 2003-04-29 2006-08-01 International Business Machines Corporation Method, system and computer program product for implementing copy-on-write of a file
WO2005041044A1 (en) * 2003-09-24 2005-05-06 Seagate Technology Llc Multi-level caching in data storage devices
US7549021B2 (en) 2006-02-22 2009-06-16 Seagate Technology Llc Enhanced data integrity using parallel volatile and non-volatile transfer buffers
US7499320B2 (en) * 2007-03-07 2009-03-03 Sandisk Corporation Non-volatile memory with cache page copy
ITMI20071012A1 (it) 2007-05-18 2008-11-19 St Microelectronics Srl Dispositivo di memoria migliorato a veloce programmazione
WO2008150927A2 (en) * 2007-05-30 2008-12-11 Schooner Information Technology System including a fine-grained memory and a less-fine-grained memory
US9201790B2 (en) 2007-10-09 2015-12-01 Seagate Technology Llc System and method of matching data rates
US7984259B1 (en) 2007-12-17 2011-07-19 Netapp, Inc. Reducing load imbalance in a storage system
US8180954B2 (en) 2008-04-15 2012-05-15 SMART Storage Systems, Inc. Flash management using logical page size
US8239724B2 (en) 2009-04-08 2012-08-07 Google Inc. Error correction for a data storage device
US8688894B2 (en) * 2009-09-03 2014-04-01 Pioneer Chip Technology Ltd. Page based management of flash storage
KR101619249B1 (ko) 2009-11-26 2016-05-11 삼성전자주식회사 프로그램 방법
US8301836B2 (en) 2010-02-26 2012-10-30 Red Hat, Inc. Methods for determining alias offset of a cache memory
US8677055B2 (en) 2010-04-12 2014-03-18 Sandisk Enterprises IP LLC Flexible way of specifying storage attributes in a flash memory-based object store
US20120110239A1 (en) * 2010-10-27 2012-05-03 Seagate Technology Llc Causing Related Data to be Written Together to Non-Volatile, Solid State Memory
EP2702491A4 (en) * 2011-04-26 2015-02-25 Lsi Corp VARIABLE OVERSIZING FOR NON-VOLATILE STORAGE
WO2013022915A1 (en) * 2011-08-09 2013-02-14 Lsi Corporation I/o device and computing host interoperation
US9323659B2 (en) 2011-08-12 2016-04-26 Sandisk Enterprise Ip Llc Cache management including solid state device virtualization
CN102541757B (zh) * 2011-11-30 2014-11-05 华为技术有限公司 写缓存方法、缓存同步方法和装置
US8724389B2 (en) 2012-07-26 2014-05-13 Ocz Storage Solutions, Inc. Non-volatile solid state memory-based mass storage device and methods thereof
US9104413B2 (en) * 2012-11-05 2015-08-11 Qualcomm Incorporated System and method for dynamic memory power management
US8526234B1 (en) * 2012-11-16 2013-09-03 Avalanche Technology, Inc. Controller management of memory array of storage device using magnetic random access memory (MRAM)
US9910747B2 (en) 2014-09-12 2018-03-06 International Business Machines Corporation Parallel mirrored copying with write consistency
CN105512048B (zh) * 2014-10-16 2018-11-09 瑞昱半导体股份有限公司 数据配置方法与装置
JP5804584B1 (ja) * 2014-10-30 2015-11-04 ウィンボンド エレクトロニクス コーポレーション Ｎａｎｄ型フラッシュメモリのプログラム方法

Also Published As

Publication number Publication date
US9905294B1 (en) 2018-02-27
CN108806754B (zh) 2022-04-05
JP2018190483A (ja) 2018-11-29
CN108806754A (zh) 2018-11-13
TWI689926B (zh) 2020-04-01
TW201907401A (zh) 2019-02-16

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