KR20180118085A - Semiconductor Device having a power metal-oxide-silicon transistor - Google Patents

Abstract

Provided is a semiconductor device including a power MOS transistor capable of minimizing heat generation and improving reliability. The semiconductor device including a power MOS transistor according to the present invention includes a semiconductor substrate having an impurity region having a first conductivity, a drift region formed in the impurity region and having the first conductivity, a body region formed in the impurity region to be adjacent to the drift region and having a second conductivity different from the first conductivity, a drain extension insulating film formed on the drift region, a gate insulating film and a gate electrode sequentially stacked on the semiconductor substrate to extend over a part of the body region and a part of the drift region, a drain extension electrode formed on the drain extension insulating film, and a source region having a second conductivity and formed in the body region and the drain region having the first conductivity in contact with the opposite side with respect to the body region in the drift region.

Description

[0001] The present invention relates to a semiconductor device having a power MOS transistor,

The present invention relates to a semiconductor device including a power MOS transistor, and more particularly to a semiconductor device including a power MOS transistor capable of minimizing a heat generation amount and improving reliability.

Electronic devices are becoming smaller, lighter, and more versatile according to the rapid development of the electronic industry and the demands of users. Accordingly, there is an increasing need to form a power MOS transistor, which is formed of a separate element (chip), in a power control integrated circuit.

However, the structure of a conventional power MOS transistor formed by a separate element (chip) may be deteriorated in reliability when applied to an integrated circuit, and when a power MOS transistor is formed in an integrated circuit together with reliability of other individual elements due to heat generation There is a problem that can affect.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device including a power MOS transistor capable of minimizing heat generation and improving reliability.

According to an aspect of the present invention, there is provided a semiconductor device including a power MOS transistor. A semiconductor device including a power MOS transistor according to an embodiment of the present invention includes a semiconductor substrate on which an impurity region having a first conductivity is formed, a drift region formed in the impurity region and having the first conductivity, A drain region formed in the impurity region and having a second conductivity different from the first conductivity, a drain extension insulating film formed on the drift region, a portion of the body region, and a portion of the drift region, A drain extension electrode formed on the drain extension insulating film; a gate electrode formed on the substrate, the drain extension electrode being in contact with an opposite side to the body region in the drift region, the drain region having the first conductivity, Region, and the second preform It includes a source region having a castle.

At least one recess region may be formed in a part of the upper surface of the drift region, and the drain extension insulating film may be a shallow trench insulator (STI) formed to fill at least one of the recess regions.

And a wiring line formed on the semiconductor substrate, wherein the drain extension electrode is in the form of a contact plug electrically connected to the wiring line.

And a source contact plug electrically connecting the wiring line and the source region so that a common bias is provided to the drain extension electrode and the source region.

And a body contact region formed in the body region and having the second conductivity, wherein the drain extension electrode and the body contact region are provided with a common bias, And may further include a body contact plug electrically connected thereto.

The body region, the drift region and the drain region may be disposed along a first direction, the drain extension insulating film may extend along the first direction, and a horizontal cross section may be formed in a bar shape with respect to the semiconductor substrate.

The drain extension insulating film may be a plurality of spaced-apart drain extension insulation films.

The plurality of drain extension insulating films may be arranged along the second direction different from the first direction.

The gate electrode and the drain extension electrode may be integrally formed to be electrically connected to each other.

The drain extension electrode may be in the form of a finger extending from the gate electrode onto the plurality of drain extension insulating films along the first direction.

Wherein a portion of one end of the drain extension electrode on the first direction side is undoped polysilicon and the other portion is doped polysilicon or a portion of one end of the drain extension electrode and the remaining portion of the drain extension electrode are doped with different conductivity Lt; / RTI > polysilicon.

And a barrier region formed below the impurity region in the semiconductor substrate and having a higher carrier concentration than the impurity region.

The drift region may have a higher carrier concentration than the impurity region.

A semiconductor device including a power MOS transistor according to an embodiment of the present invention includes a semiconductor substrate on which an impurity region having a first conductivity is formed, a drift region having the first conductivity formed in the impurity region, A body region formed in the impurity region, the body region having a second conductivity different from the first conductivity, formed on an upper surface of the drift region, extending along a first direction from the body region toward the drain region, A plurality of recessed regions formed in the body region and arranged to be spaced apart from each other in the second direction, a source region having the second conductivity, an opposite side to the body region in the drift region, A drain region having conductivity, a plurality of drain regions filling the plurality of recess regions Drain extension insulating film, a gate insulating film and a gate electrode sequentially stacked on the semiconductor substrate so as to extend over a part of the body region and a portion of the drift region, and a plurality of drain extensions A current flow path may be formed through a portion of the drift region between each of the plurality of drain extension insulating films and a portion of the drift region below the plurality of drain extension insulating films.

The gate electrode and the drain extension insulating film may be spaced apart from each other in the first direction.

Since the semiconductor device including the power MOS transistor according to the present invention has a hybrid form of LDMOS and DEMOS, it can have both the advantages of LDMOS and DEMOS. Therefore, the power MOS transistor formed in the semiconductor device increases the current flow path and lowers the operating resistance R _DSon between the drain region and the source region, so that the calorific power can be minimized even when a high voltage is used. Further, the electric field applied between the drain region and the source region is dispersed into the drift region between and below the drift diffusion insulating films, so that it can have a high breakdown voltage. Therefore, the reliability of the semiconductor device can be improved.

Therefore, in a semiconductor device including a power control integrated circuit and a power MOS transistor together, it is possible to reduce the chip size, minimize the power loss occurring in the chip, and increase the power efficiency.

1 to 3 are a plan view and a cross-sectional view of a semiconductor device including a power MOS transistor according to an embodiment of the present invention.
4 and 5 are a top view and a cross-sectional view of a semiconductor device including a power MOS transistor according to a modification of an embodiment of the present invention.
6 to 8 are a plan view and a cross-sectional view of a semiconductor device including a power MOS transistor according to a modification of another embodiment of the present invention.
9 is a cross-sectional view illustrating a step of preparing a semiconductor substrate according to an embodiment of the present invention.
10 is a cross-sectional view illustrating a step of forming a barrier region according to an embodiment of the present invention.
11 is a cross-sectional view illustrating a step of forming an impurity region according to an embodiment of the present invention.
12 is a cross-sectional view illustrating a step of forming a body region and a drift region according to an embodiment of the present invention.
13 and 14 are a plan view and a cross-sectional view illustrating a step of forming a body contact region, a source region, a drain region, and a drain extension insulating film according to an embodiment of the present invention.
15 and 16 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode and a drain extension electrode according to an embodiment of the present invention.
17 and 18 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode and a drain extension electrode according to an embodiment of the present invention.
19 and 20 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode according to another embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art to which the present invention pertains. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

It is to be understood that when an element is referred to as being "on" or "tangent" to another element, it is to be understood that other elements may directly contact or be connected to the image, something to do. On the other hand, when an element is described as being "directly on" or "directly adjacent" another element, it can be understood that there is no other element in between. Other expressions that describe the relationship between components, for example, "between" and "directly between"

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The word "comprising" or "having ", when used in this specification, is intended to specify the presence of stated features, integers, steps, operations, elements, A step, an operation, an element, a part, or a combination thereof.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, the present invention will be described in detail with reference to the embodiments of the present invention with reference to the accompanying drawings.

1 to 3 are a plan view and a cross-sectional view of a semiconductor device including a power MOS transistor according to an embodiment of the present invention. 2 and 3 are cross-sectional views taken along II-II and III-III in Fig. 1, respectively. However, the wiring line 600 of FIG. 2 is omitted in the plan view of FIG.

1 to 3, a semiconductor device 1 including a power MOS transistor includes an impurity region 140 having a first conductivity in a semiconductor substrate 100, and an impurity region 140 having a first conductivity is formed in the impurity region 140. In the impurity region 140, A body region 220 having a first conductivity and a second conductivity different from the first conductivity and a drift region 240 having the first conductivity may be formed. The body region 220 and the drift region 240 are shown separated by the impurity region 140. The body region 220 and the drift region 240 may be in direct contact with each other.

A barrier region 120 may be further formed between the semiconductor substrate 100 and the impurity region 140 or a portion of the upper surface of the semiconductor substrate 100 in contact with the impurity region 140. The barrier region 120 may have a higher carrier concentration than the semiconductor substrate 100 and / or the impurity region 140. The barrier region 120 may have the second conductivity or the first conductivity.

A source region 340 having the second conductivity may be formed in the body region 220, that is, in a portion from the upper surface of the body region 220. In addition, the body contact region 320 having the first conductivity may be formed in the body region 220, that is, a part of the body region 220 from the upper surface thereof. The body contact region 320 and the source region 340 may be formed to be in contact with each other or may be spaced apart from each other.

The drain region 360 having the second conductivity may be formed to contact the opposite side of the drift region 240 with respect to the body region 220. The drain region 360 may be formed in the drift region 240 or may be formed to be in contact with the drift region 240 or over the drift region 240 and the impurity region 140. That is, the drain region 360 may be formed at a portion from the upper surface of the drift region 240 and / or the impurity region 140.

A drain extension insulating film 300 may be formed on the drift region 240. The drain extension insulating film 300 may be a shallow trench insulator (STI) formed to fill at least one recess region 245 formed in a portion of the upper surface of the drift region 240. Drain extension insulating film 300 may round its edges. Further, the drain extension insulating film 300 can be gradually reduced in horizontal cross-sectional area as the depth increases.

The gate electrode 410 may be formed on the semiconductor substrate 100 to extend over a portion of the body region 220 and a portion of the drift region 240. [ The gate electrode 410 may be formed to extend from the body region 220 onto the drift region 240. The drain extension electrode 412 may extend from the gate electrode 410 and may be formed on the drain extension insulating film 300. The gate electrode 410 and the drain extension electrode 412 may be an extension gate electrode 414 formed integrally. That is, the conductive material covering the semiconductor substrate 100 may be formed and patterned to form the gate electrode 410 and the drain extension electrode 412. In this case, the gate electrode 410 extends from the extension gate electrode 414 in the second direction (y direction) and the drain extension electrode 412 extends from the gate electrode 410 in the first direction (x direction) Shaped portion that extends along the length of the finger. In this case, the drain extension electrode 412 may be formed to extend over a part of the drift region 240 and a part of the drain extension insulating film 300. A gate electrode 410 may optionally be formed over the source region 340. The first direction (x direction) and the second direction (y direction) are different directions, and may be, for example, a vertical direction.

The extended gate electrode 414 may round the connection portion of the gate electrode 410 and the drain extension electrode 412 to disperse the electric field. In addition, at one end of the drain extension electrode 412 remote from the gate electrode 410, the extended width of the extension gate electrode 414 can be narrowed to disperse the electric field. Thus, the shape of the extension gate electrode 414 can be optimized by adjusting the width of the extension and rounding the edges to prevent the electric field from concentrating.

In addition, although the extended portions of the extended gate electrode 414 are shown to have the same length, if a plurality of extended gate electrodes 414 extend from the gate electrode 410 in one power MOS transistor, The lengths of the extended portions of the extended gate electrodes 414 that are narrowed may be different from each other, or may be formed differently.

A gate insulating layer 400 may be formed under the gate electrode 410. That is, the gate insulating film 400 and the gate electrode 410 may be sequentially stacked on the semiconductor substrate 100. The gate insulating layer 400 may also be formed under the drain extension electrode 412. That is, the gate insulating layer 400 and the extended gate electrode 414 may be formed by forming a preliminary gate insulating layer and a conductive material on the semiconductor substrate 100 and then patterning the preliminary gate insulating layer and the conductive material. 2, the gate insulating layer 400 is formed on the drain extension insulating layer 300, but the present invention is not limited thereto. When the gate insulating film 400 is formed by a deposition method, the gate insulating film 400 may also be formed on the drain extension insulating film 300. However, when the gate insulating film 400 is formed by a thermal oxidation method, the gate insulating film 400 may not be formed on the drain extending insulating film 300. When the gate insulating film 400 is formed on the drain extension insulating film 300, the gate insulating film 400 and the drain extension insulating film 300 may be integrally formed without being separated from each other.

Drain extension insulating film 300 may extend in a first direction (x direction), and a horizontal cross section with respect to the semiconductor substrate 100 may have a bar shape. Drain extension insulating films 300 may be spaced apart from each other. Drain extension insulating films 300 may be arranged along the second direction (y direction) when a plurality of drain extension insulating films 300 are provided.

The drain extension electrode 412 extends from the gate electrode 410 and extends over one side of the bar-shaped drain extension insulation film 300 and extends over the drain extension insulation film 300. The drain extension electrode 412 may be formed on the four sides of the bar-shaped drain extension insulating film 300 so as to extend only on one side toward the body region 220 and spaced apart from the three sides so as not to overlap on the remaining three sides. Therefore, the gate electrode 410 may be spaced apart from the drain extension insulating film 300. The gate electrode 410 is formed on the drain extension insulating film 300 in the drift region 240 so that the gate electrode 410 is not formed on the portion between the plurality of drain extension insulating films 300 in the drift region 240. [ And a plurality of spaced-apart portions.

The source region 340, the body region 220, the drain region 360, and the gate electrode 410 may constitute a power MOS transistor. The drift region 240 and the drain extension electrode 412 together with the source region 340, the body region 220, the drain region 360 and the gate electrode 410 may constitute a power MOS transistor. In this case, And the drift region 240 may serve to extend the drain region 360.

A body contact plug 520, a source contact plug 540 and a drain contact plug 560 may be formed on the body contact region 320, the source region 340, and the drain region 360, respectively. The body contact plug 520, the source contact plug 540 and the drain contact plug 560 are formed on the semiconductor substrate 100 on which the body contact region 320, the source region 340 and the drain region 360 are formed, A contact hole may be formed to form a contact hole exposing a portion of each of the body contact region 320, the source region 340, and the drain region 360, and then filling the contact holes with a conductive material. The body contact plug 520, the source contact plug 540 and the drain contact plug 560 may have the same height, or some or all of them may have different heights. When a part or all of the body contact plug 520, the source contact plug 540 and the drain contact plug 560 have different heights, the interlayer insulating layer may be a plurality of contact holes, Or may be formed so as to penetrate some or all of the layers.

A wiring line 600 may be formed on the body contact plug 520 and the source contact plug 540. The wiring line 600 is electrically connected to the body contact plug 520 and the source contact plug 540 and includes a body contact region 320 and a source contact plug 540 electrically connected to the body contact plug 520, A common bias may be applied to the source region 340 electrically connected thereto. The body contact plug 520 and the source contact plug 540 may be electrically connected to different wiring lines 600 so that a separate bias may be applied to the body contact region 320 and the source region 340.

The first conductivity may be n-type or p-type, and the second conductivity may be p-type or n-type. When the first conductivity is the n-type and the second conductivity is the p-type, the power MOS transistor formed in the semiconductor device 1 may be an n-type power MOS transistor. When the first conductivity is p-type and the second conductivity is n-type, the power MOS transistor formed in the semiconductor device 1 may be a p-type power MOS transistor.

The gate electrode 410 and the drain extension electrode 412 may be formed of undoped polysilicon or doped polysilicon. (N + or n-) or p-type (p + or p-) impurity if the gate electrode 410 and the drain extension electrode 412 are doped polysilicon.

For example, when the power MOS transistor formed in the semiconductor element 1 is an n-type power MOS transistor, the semiconductor substrate 100 is p-type and can have a carrier concentration of about 10 ¹⁵ / cm 3, 120 may be p-type or n-type and may have a carrier concentration of about 10 ¹⁹ / cm 3 or more. The impurity region 140 is n-type and may have a carrier concentration of about 10 ¹⁵ / cm 3, the drift region 240 may be n-type and may have a carrier concentration of about 10 ¹⁶ / cm 3 or less, 220) is a p-type, and may have a carrier concentration of about 10 ¹⁷ / ㎤ to 10 ¹⁸ / ㎤. The body contact region 320, the source region 340, and the drain region 360 are p-type, n-type, and n-type, respectively, and may have a carrier concentration of about 10 ¹⁹ / cm 3 or more.

When a negative bias is applied to the gate electrode 410 and the drain extension electrode 412, depletion occurs in the drift region 240 and the drain region 360 is expanded. The power MOS transistor formed in the semiconductor element 1 is connected to the drift diffusion insulating film 300 with the first current flow path I1 flowing through the lower portion of the drift region 240 under the drift diffusion insulating films 300 A second current flow path I2 may be formed which flows through the upper portion of the drift region 240 between each of the first current flow paths I1 and I2. The power MOS transistor formed in the semiconductor device 1 can operate similar to a LDMOS (Laterally diffused Metal-Oxide-Semiconductor) and the second current flow path I2 can operate similarly to the LDMOS The power MOS transistor formed in the semiconductor device 1 may operate similarly to a DEMOS (Drain-extended Metal-Oxide-Semiconductor). Therefore, the power MOS transistor formed in the semiconductor device 1 according to the embodiment of the present invention has both the advantages of the LDMOS and the DEMOS because it has the hybrid form of the LDMOS and the DEMOS. That is, in the power MOS transistor formed in the semiconductor device 1 according to the embodiment of the present invention, the current flow path increases and the operation resistance R _DSon between the drain region 360 and the source region 340 is lowered , The amount of heat generated can be minimized even when a high voltage is used. The electric field applied between the drain region 360 and the source region 340 is dispersed in the drift region 240 between the drift diffusion insulating films 300 and thus can have a high breakdown voltage. Reliability can be improved.

For example, when the power MOS transistor formed in the semiconductor element 1 is a p-type power MOS transistor, the conductivity of each constituent element can be formed by reversing the conductivity of the n-type power MOS transistor.

The gate electrode 410 is formed to be spaced from the drain extension insulating film 300 and the gate electrode 410 is formed on the portion of the drift region 240 located between each of the drain extension insulating films 300, Can be prevented from being concentrated, so that the breakdown voltage can be maintained at a high level.

Therefore, the semiconductor device 1 including the power control integrated circuit and the power MOS transistor can be formed to reduce the chip size, minimize the power loss occurring in the chip, and increase the power efficiency.

4 and 5 are a top view and a cross-sectional view of a semiconductor device including a power MOS transistor according to a modification of an embodiment of the present invention. 5 is a cross-sectional view taken along line V-V of Fig. However, the wiring line 600 of FIG. 5 is omitted in the plan view of FIG. 4 and 5, except for the drain extension electrode, are the same as in FIGS. 1 to 3, and thus may be omitted.

4 and 5, a semiconductor device 2 including a power MOS transistor includes an extension gate electrode 414a formed of a gate electrode 410 and a drain extension electrode 412a. The drain extension electrode 412a may include a first drain extension electrode 416a and a second drain extension electrode 416b. The second drain extension electrode 416b is a portion of one end of the drain extension electrode 412a on the first direction (x direction) side, that is, a portion of the drain extension electrode 412a extending from the gate electrode 410, The first drain extension electrode 416a may be a remaining portion of the drain extension electrode 412a except for the second drain extension electrode 416b.

The second drain extension electrode 416b of the extension gate electrode 414a may have a conductivity different from that of the rest of the gate electrode 410 and the first drain extension electrode 416a or may not have conductivity. For example, when the gate electrode 410 and the first drain extension electrode 416a are n-type (n + or n-) doped polysilicon, the second drain extension electrode 416b may be a p-type (p + ) Doped polysilicon or undoped polysilicon. Similarly, when the gate electrode 410 and the first drain extension electrode 416a are p-type (p + or p-) -doped polysilicon, the second drain extension electrode 416b may be an n-type (n + Polysilicon or undoped polysilicon.

For example, when the extension gate electrode 414a is all n-type doped polysilicon and a negative bias is applied to the n-type drift region 240 to cause depletion, a portion of the extension gate electrode 414a Electrons can be accumulated. However, in the case where the second drain extension electrode 416b is p-type doped polysilicon or undoped polysilicon, electrons can be prevented from accumulating and the end of the extension gate electrode 414a, that is, It is possible to prevent the electric field from concentrating on the first electrode 416b, so that the breakdown voltage can be kept high.

6 to 8 are a plan view and a cross-sectional view of a semiconductor device including a power MOS transistor according to a modification of another embodiment of the present invention. 7 and 8 are cross-sectional views taken along VII-VII and VIII-VIII in Fig. 6, respectively. However, the wiring line 600a of Fig. 7 is omitted in the plan view of Fig. 6 and 8, the contents except for the gate electrode and the drain extension electrode are almost the same as those in Figs. 1 to 3, and can be omitted.

6 to 8, a semiconductor device 3 including a power MOS transistor includes a gate electrode 410a and a drain extension electrode 580. [ Unlike the semiconductor device 1 including the power MOS transistor shown in Figs. 1 to 3, the semiconductor device 3 including the power MOS transistor shown in Figs. 6 to 8 has the gate electrode 410a and the drain extension electrode 580 may not be integrated. The drain extension electrode 580 may be formed in the form of a contact plug as well as the body contact plug 520 and / or the source contact plug 540. The drain extension electrode 580 has a slot-like contact hole exposing a portion of the drain extension insulating film 300 in the interlayer insulation layer, as in the case of forming the body contact plug 520 and / or the source contact plug 540 And then filling the contact hole with a conductive material. The drain extension insulating film 580 extends along the first direction (x direction) and may have a horizontal cross section with respect to the semiconductor substrate 100. The drain extension electrode 580 may be formed with the body contact plug 520 and / or the source contact plug 540.

The drain extension electrode 580 may be electrically connected to the wiring line 600a such that a common bias is provided to the body contact region 320 and / or the source region 340. That is, the drain extension electrode 580 is electrically connected to the body contact region 320 through the wiring line 600a and the body contact plug 520 so that the bias provided through the wiring line 600a is electrically connected to the body contact region 320 and a common bias. Or the drain extension electrode 580 is electrically connected to the source region 340 through the wiring line 600a and the source contact plug 540 to connect the source contact region 340 with the bias provided through the wiring line 600a, And a common bias. Or the drain extension electrode 580 are electrically connected to the body contact region 320 and the source region 340 through the wiring line 600a and the body contact plug 520 and the source contact plug 540, The bias provided through the body contact region 320a and the source region 340 may be provided with a common bias.

That is, in the semiconductor device 1 including the power MOS transistor according to the embodiment of the present invention shown in FIGS. 1 to 3, a common bias is provided to the gate electrode 410 and the drain extension electrode 412, The semiconductor device 3 including the power MOS transistor according to another embodiment of the present invention as shown in FIGS. 6 to 8 may have a depletion in the body contact region 320 and / A common bias may be provided to the drift region 340 and the drain extension electrode 580 so that depletion may occur in the drift region 240.

Therefore, the semiconductor device 1 including the power MOS transistor according to one embodiment of the present invention shown in FIGS. 1 to 3 and the semiconductor device 1 including the power MOS transistor according to another embodiment of the present invention shown in FIGS. The operation principle and the method of the power MOS transistor may be the same only in the method 3 only in the method of providing the bias to the drain extension electrodes 412/580.

9 to 20 are plan views and sectional views showing a method of manufacturing a semiconductor device including a power MOS transistor according to embodiments of the present invention. Hereinafter, description will be made on the basis of a semiconductor element including an n-type power MOS transistor, and in the case of a semiconductor element including a p-type power MOS transistor, the conductivity can be produced by reversing the conductivity.

9 is a cross-sectional view illustrating a step of preparing a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 9, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 may be a substrate including a semiconductor material such as a silicon substrate, a silicon on insulator (SOI) substrate, a gallium-arsenic substrate, a silicon germanium substrate, or a ceramic substrate, a quartz substrate, Lt; / RTI > In the semiconductor substrate 100, for example, an impurity implantation region such as a well may be formed. When the semiconductor substrate 100 is a p-type, the semiconductor substrate 100 may be a bare wafer containing a p-type impurity or a well into which a p-type impurity formed in a substrate containing a semiconductor material is implanted. Alternatively, the semiconductor substrate 100 may have a structure (p + / p- or n + / n-) in which a semiconductor layer having a relatively low carrier concentration is formed on a wafer having a carrier concentration of a relatively high concentration.

10 is a cross-sectional view illustrating a step of forming a barrier region according to an embodiment of the present invention.

Referring to FIG. 10, a barrier region 120 may be formed on a semiconductor substrate 100 or a portion of a top surface of a semiconductor substrate 100. The barrier region 120 may be an insulating material formed on the semiconductor substrate 100 or a region where a high concentration of impurities is implanted into a portion of the upper surface of the semiconductor substrate 100. That is, the barrier region 120 may be an oxide layer deposited or thermally grown on the semiconductor substrate 100, or a high concentration impurity region formed by implanting impurities through the upper surface of the semiconductor substrate 100. Barrier region 120 may be a n + doped semiconductor material layer or a p + doped semiconductor material layer. Barrier region 120 may have a carrier concentration of, for example, about 10 ¹⁹ / cm 3 or more.

11 is a cross-sectional view illustrating a step of forming an impurity region according to an embodiment of the present invention.

Referring to FIG. 11, an impurity region 140 is formed on a semiconductor substrate 100. When the barrier region 120 is formed, the impurity region 140 can be formed on the barrier region 120. The impurity region 140 may be formed by an epitaxial growth method, and the impurity region 140 may be a n-type doped semiconductor material layer. The impurity region 140 may have a carrier concentration of about 10 ¹⁵ / ㎤ to 10 ¹⁶ / ㎤.

However, the present invention is not limited thereto, and the barrier region 120 may be formed by implanting ions of relatively high concentration into the deep portion from the surface of the semiconductor substrate 100, The impurity region 140 may be formed by ion implanting a relatively low concentration impurity into the low portion from the surface of the impurity region 140. [

12 is a cross-sectional view illustrating a step of forming a body region and a drift region according to an embodiment of the present invention.

12, a body region 220 and a drift region 240 are formed by implanting a p-type impurity and an n-type impurity into a portion of the impurity region 140, that is, a portion from the top surface of the impurity region 140 . Body region 220 may have a carrier concentration of about 10 ¹⁷ / ㎤ to 10 ¹⁸ / ㎤. Drift region 240 may have a carrier concentration of about 10 ¹⁶ / cm 3 or less. The body region 220 and the drift region 240 may have a higher carrier concentration than the impurity region 140. The drift region 240 is formed so as to have a relatively low carrier concentration at a relatively high voltage and at a relatively high carrier concentration at a relatively low voltage in consideration of a voltage that can be used in a semiconductor device to be formed However, it can be formed to have a higher carrier concentration than the impurity region 140.

Although the body region 220 and the drift region 240 are illustrated as being spaced apart by the impurity region 140, the body region 220 and the drift region 240 may be in direct contact with each other.

13 and 14 are a plan view and a cross-sectional view illustrating a step of forming a body contact region, a source region, a drain region, and a drain extension insulating film according to an embodiment of the present invention. 14 is a cross-sectional view taken along the line XIV-XIV in Fig.

Referring to FIGS. 13 and 14, a body contact region 320 and a source region 340 are formed by implanting a p-type impurity and an n-type impurity into a portion of an upper surface of the body region 220, respectively. Further, an n-type impurity is implanted into a part of the upper surface of the drift region 240 and / or the impurity region 140 to form a drain region 360. [ The source region 340 and the drain region 360 can be formed by implanting n-type impurities at the same time. Although the body contact region 320 and the source region 340 are illustrated as being in direct contact with each other, they may be spaced apart.

A portion of the drift region 240 may be removed either before or after forming the body contact region 320 and / or the source / drain regions 340 and 360 so that at least one recess region (not shown) is formed on the top surface of the drift region 240 245 may be formed. Then, the drain extension insulating film 300 can be formed by filling the recessed region 245 with an insulating material. The upper surface of the drain extension insulating film 300 and the upper surface of the drift region 240 are located on the same plane but may be formed such that the upper surface of the drain extension insulating film 300 is higher than the upper surface of the drift region 240 .

The drain extension insulating film 300 may be formed of an oxide, a nitride, an oxynitride, or a combination thereof.

15 and 16 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode and a drain extension electrode according to an embodiment of the present invention. 16 is a cross-sectional view taken along line XVI-XVI in Fig.

15 and 16, a gate electrode 410 extending from the body region 220 to the drift region 240 and a drain extension electrode 340 extending from the gate electrode 410 to the drain extension insulating film 300 Forming an extended gate electrode 414 including a gate electrode 412. A gate insulating layer 400 may be formed under the extended gate electrode 414. That is, the gate insulating layer 400 and the extended gate electrode 414 may be formed by forming a preliminary gate insulating layer and a conductive material on the semiconductor substrate 100 and then patterning the preliminary gate insulating layer and the conductive material. The extension gate electrode 414 may be made of undoped polysilicon or doped polysilicon. If the extension gate electrode 414 is doped polysilicon, it may be doped with n-type (n + or n-) or p-type (p + or p-) impurities.

As shown in FIGS. 1 to 3, a body contact plug 520, a source contact plug 540 and a drain contact plug 560 are formed and a wiring line 600 is formed to form a semiconductor The element 1 can be formed.

The body contact plug 520, the source contact plug 540 and the drain contact plug 560 may be formed by performing at least one or more processes of forming a conductive material filling the interlayer insulating film deposition / contact hole / contact hole. At least one of the body contact plug 520, the source contact plug 540, and the drain contact plug 560 may have a structure in which two or more plug electrodes are stacked.

17 and 18 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode and a drain extension electrode according to an embodiment of the present invention. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig.

Referring to FIGS. 15 to 18, after the extension gate electrode 414 as shown in FIGS. 15 and 16 is formed of undoped polysilicon, impurities may be implanted into a part of the drain extension electrode 412, 15 and 16 are formed of doped polysilicon and impurities having a conductivity different from that of the doped polysilicon are injected into a part of the drain extension electrode 412 to form the extended gate electrode 414 shown in FIGS. Thereby forming the extension gate electrode 414a shown in FIG.

A portion of the extension gate electrode 414a extending in the second direction (y direction) is the gate electrode 410 and the finger-shaped portion extending from the gate electrode 410 along the first direction (x direction) And may be referred to as an extended electrode 412a. A portion of the drain extension electrode 412a which is in contact with the gate electrode 410 and has the same conductivity is a first drain extension electrode 416a and a portion of one end opposite to the gate electrode 410, 416a may be referred to as a second drain extension electrode 416b.

When the second drain extension electrode 416b is made of undoped polysilicon, the extension gate electrode 414 as shown in FIGS. 15 and 16 is formed of undoped polysilicon and then the second drain extension electrode 416b is formed of undoped polysilicon. The extension gate electrode 414a can be formed.

When the second drain extension electrode 416a is polysilicon having conductivity different from the rest of the extension gate electrode 414a, the extension gate electrode 414 as shown in FIGS. 15 and 16 may be formed of doped polysilicon The extended gate electrode 414a may be formed by implanting an impurity having a conductivity different from that of the doped polysilicon to the second drain extension electrode 416b.

4 and 5, a body contact plug 520, a source contact plug 540 and a drain contact plug 560 are formed and a wiring line 600 is formed to form a semiconductor The element 2 can be formed.

19 and 20 are a plan view and a cross-sectional view illustrating a step of forming a gate electrode according to another embodiment of the present invention. 20 is a cross-sectional view taken along the line XX-XX in FIG.

19 and 20, a gate insulating layer 400a and a gate electrode 410a extending from the body region 220 to the drift region 240 and extending in the second direction (y direction) are formed.

6 to 8, a body contact plug 520, a source contact plug 540, a drain contact plug 560, and a drain extension electrode 580 are formed and a wiring line 600a is formed The semiconductor device 3 including the power MOS transistor can be formed. The drain extension electrode 580 may be formed by the same fabrication process with the body contact plug 520 and / or the source contact plug 540.

A semiconductor device comprising: a semiconductor substrate; 120: barrier region; 140: impurity region; 220: body region; 240: drift region; 300: drain extension insulating film; 320: body contact region; A source contact plug, a drain contact plug, a drain contact plug, a wiring line, and a drain line.

Claims (10)

A semiconductor substrate on which an impurity region having a first conductivity is formed;
A drift region formed in the impurity region and having the first conductivity and having at least one recess region in a portion of the top surface;
A body region formed in the impurity region so as to be adjacent to the drift region, the body region having a second conductivity different from the first conductivity;
A drain extension insulating film formed on the drift region and being a shallow trench insulator (STI) filling at least one of the recessed regions;
A gate insulating film and a gate electrode sequentially stacked on the semiconductor substrate so as to extend over a part of the body region and a part of the drift region;
A drain extension electrode extending along the first direction from the gate electrode on the drain extension insulating film;
A drain region in contact with an opposite side to the body region in the drift region, the drain region having the first conductivity; And
And a power MOS (Metal Oxide Semiconductor) transistor having a source region formed in the body region and having the second conductivity,
Wherein a portion of one end of the drain extension electrode in the first direction is undoped polysilicon and the remaining portion is doped polysilicon or a portion of one end of the drain extension electrode and the remaining portion of the drain extension electrode are doped Polysilicon. The method according to claim 1,
And a wiring line formed on the semiconductor substrate,
And the drain extension electrode is in the form of a contact plug electrically connected to the wiring line. The method according to claim 1,
Wherein the body region, the drift region, and the drain region are disposed along the first direction,
Wherein the drain extension insulating film extends along the first direction and has a horizontal cross section with respect to the semiconductor substrate. The method of claim 3,
And the drain extension insulating films are spaced apart from each other. 5. The method of claim 4,
And the plurality of drain extension insulating films are arranged along a second direction different from the first direction. 6. The method of claim 5,
Wherein the gate electrode and the drain extension electrode are integrally formed to be electrically connected to each other. The method according to claim 6,
Wherein the drain extension electrode is in the form of a finger extending from the gate electrode to a plurality of the drain extension insulating films along the first direction. The method according to claim 1,
Wherein a width of one end portion of the drain extension electrode remote from the gate electrode is narrower than a width of the remaining portion. A semiconductor substrate on which an impurity region having a first conductivity is formed;
A drift region having the first conductivity formed in the impurity region;
A body region formed in the impurity region so as to be adjacent to the drift region, the body region having a second conductivity different from the first conductivity;
A plurality of recessed regions formed on the upper surface of the drift region and extending along a first direction from the body region to the drain region and spaced apart from each other along a second direction different from the first direction;
A source region formed in the body region and having the second conductivity;
A drain region in contact with an opposite side to the body region in the drift region, the drain region having the first conductivity;
A plurality of drain extension insulating films filling the plurality of recessed regions;
A gate insulating film and a gate electrode sequentially stacked on the semiconductor substrate so as to extend over a part of the body region and a part of the drift region; And
And a plurality of drain extension electrodes extending from the gate electrode on the plurality of drain extension insulating films, respectively, along the first direction,
A current flow path is formed through a portion of the drift region between each of the plurality of drain extension insulating films and a portion of the drift region below the plurality of drain extension insulating films,
Wherein a portion of one end of each of the plurality of drain extension electrodes in the first direction is undoped polysilicon and the remaining portion is doped polysilicon or a portion of the one end of each of the drain extension electrodes and the remaining portion of the drain extension electrode have different conductivity Wherein the power MOS transistor is a doped polysilicon. 10. The method of claim 9,
Wherein the gate electrode and the drain extension insulating film are spaced apart from each other in the first direction,
Wherein each of the plurality of drain extension electrodes has a width at one end remote from the gate electrode being narrower than a width of the remaining portion.

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