KR20180115560A - Pwm control apparatus of radio frequency multi-channel with low power function - Google Patents

Abstract

The present invention provides a high-frequency multi-channel PWM control apparatus which can reduce overall current consumption. According to an embodiment of the present invention, the high-frequency multi-channel PWM control apparatus comprises: a prescaler to divide a main clock signal to generate a first clock signal; and a multi-channel PWM generator including a first to an n^th (n is a natural number higher than or equal to 2) PWM generator to use the first clock signal to generate a first to an n^th PWM signal having corresponding periods and duties by first and second N/2 bit counting for the main clock signal. The first to n^th PWM generators each performs first N/2 bit counting for the main clock signal based on the first clock signal, a corresponding coarse duty value, and a corresponding coarse period value to generate a coarse clock signal, and performs second N/2 bit counting for the coarse clock signal based on a corresponding fine duty value and a corresponding fine period value to generate a corresponding PWM signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-frequency multi-channel PWM control device having a low-

The present invention relates to a high frequency multi-channel PWM control device having a low power function.

Generally, a PWM (Pulse Width Modulator) method is used to control an actuator such as a voice coil motor.

Recently, a PWM method in which the PWM period is 1 MHz or more and the resolution is 8 bits or more is used. If the PWM period is 1 MHz and the resolution is 10 bits, the PWM pulse should use a clock of 1 GHz.

If the conventional PWM control apparatus has a high-frequency multi-channel structure, a high-frequency counter may be included to count a high-frequency clock for each channel.

For example, a PWM method using a 1 GHz clock may be applied to a next generation OIS (Driver IC), and a 1 GHz clock may be used.

In this case, since the high frequency counter generates current consumption in response to a transition of a high frequency clock (for example, 1 GHz clock), there is a problem that current consumption is increased as the number of channels increases.

For example, it is easy to implement a high-speed counter using ultra-fine processes. However, when a 0.18-μm or 0.13-μm process is used, a high-resolution (eg, 10-bit) counter It may not be easy to do, and the higher the resolution, the more current consumption becomes.

Japanese Patent Application Laid-Open No. 1999-109919

An embodiment of the present invention provides a high frequency multi-channel PWM control device capable of reducing the switching current and reducing the total consumption current by reducing the number of high frequency counters having a higher resolution than the number of channels do.

According to an embodiment of the present invention, there is provided a semiconductor device including: a prescaler dividing a main clock signal to generate a first clock signal; And generating first to n-th (n is a natural number of 2 or more) PWM signals having a corresponding period and duty using first and second N / 2 bit counts for the main clock signal using the first clock signal A multi-channel PWM generator including first to n-th PWM generators; Wherein each of the first through the n-th PWM generators performs the first N / 2 bit count on the main clock signal based on the first clock signal, a corresponding course duty value and a corresponding course period value, Frequency PWM control apparatus for generating a PWM signal by generating a clock signal and performing the second N / 2 bit count on the course clock signal based on the fine duty value and the fine cycle value to generate a corresponding PWM signal .

According to another embodiment of the present invention, there is provided a method of driving a semiconductor device, the method comprising: a prescaler dividing a main clock signal to generate a first clock signal; And generating first to n-th (n is a natural number of 2 or more) PWM signals having a corresponding period and duty using first and second N / 2 bit counts for the main clock signal using the first clock signal A multi-channel PWM generator including first to n-th PWM generators; Wherein the first PWM generator performs the first N / 2 bit count on the main clock signal based on the first clock signal, the first course duty value and the first course period value, A first course controller for generating a clock signal; And a first fine controller for performing the second N / 2 bit count on the first course clock signal based on a first fine duty value and a first fine period value to generate the first PWM signal, Wherein the nth PWM generator performs the first N / 2 bit count on the main clock signal based on the first clock signal, the nth course duty value, and the nth course frequency value to generate an nth course clock signal Nth course controller; And an n-th fine-tune controller for performing the second N / 2 bit count on the n-th coarse clock signal based on the n-th fine-duty value and the n-th fine-cycle value to generate the n-th PWM signal. Frequency PWM control device.

According to an embodiment of the present invention, by reducing the number of high-frequency counters having a high resolution compared to the number of channels, the switching current can be reduced and the total consumed current can be reduced.

Further, in the PWM control device of the camera module which requires a PWM cycle of 1 MHz or more and high resolution control, as the number of channels increases, current consumption is further reduced as compared with the conventional device.

1 is a block diagram of a high-frequency multi-channel PWM controller according to an embodiment of the present invention.
2 is a timing chart of a main clock signal, a first clock signal, and a start signal according to an embodiment of the present invention.
3 is a diagram illustrating an example of a k-th PWM generator according to an embodiment of the present invention.
4 is a diagram illustrating an operation timing chart of a high-frequency multi-channel PWM control apparatus according to an embodiment of the present invention.
5 is an example of an kth course value C1_duty, a kth course period value C1_per, a kth fine duty value F1_duty, and a kth fine period value F1_per according to an embodiment of the present invention. to be.
FIG. 6 is a block diagram showing an example of a k-th coefficient value register (C1_duty), a k-th cycle period value C1_per, a k-th fine-duty value F1_duty, (Set-N).

It should be understood that the present invention is not limited to the embodiments described and that various changes may be made without departing from the spirit and scope of the present invention.

In addition, in each embodiment of the present invention, the structure, shape, and numerical values described as an example are merely examples for helping understanding of the technical matters of the present invention, so that the spirit and scope of the present invention are not limited thereto. It should be understood that various changes may be made without departing from the spirit of the invention. The embodiments of the present invention may be combined with one another to form various new embodiments.

In the drawings referred to in the present invention, components having substantially the same configuration and function as those of the present invention will be denoted by the same reference numerals.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

1 is a block diagram of a high-frequency multi-channel PWM controller according to an embodiment of the present invention.

Referring to FIG. 1, a high-frequency multi-channel PWM controller according to an embodiment of the present invention may include a prescaler 100 and a multi-channel PWM generator 200.

The prescaler 100 is a frequency divider that divides the frequency of the main clock signal clk and divides the main clock signal clk to generate a main clock signal clk having a frequency lower than that of the main clock signal clk 1 clock signal f_clk.

For example, when the frequency of the main clock signal clk is 1 GHz and the dividing ratio of the prescaler 100 is 4, the frequency of the first clock signal f_clk may be 250 MHz.

The multi-channel PWM generator 200 may include first through n-th PWM generators 200-1 through 200-n, and each of the first through n-th PWM generators 200-1 through 200- (N is a natural number of 2 or more) PWMs having a corresponding period and duty through first and second N / 2 bit counts for the main clock signal clk using the first clock signal f_clk, It is possible to generate the signals PWM1 to PWMn.

For example, each of the first to the n-th PWM generators 200-1 to 200-n is based on the first clock signal f_clk, the k-course duty value Ck_duty and the k-th cycle period value Ck_per (Kk) clock signal (gk_clk) by performing the first N / 2 bit count on the main clock signal (clk) and outputting a kth fine duty value (Fk_duty) The second N / 2 bit count is performed on the kth course clock signal gk_clk based on the kth PWM signal PWMk.

The first PWM generator 200-1 may include a first course controller 210-1 and a first fine controller 220-1.

The first course controller 210-1 generates the main clock signal clk based on the first clock signal f_clk, the first course duty value C1_duty and the first course period value C1_per And may perform the first N / 2 bit count to generate the first course clock signal g1_clk.

The first fined controller 220-1 generates the second fine clock signal g1_clk based on the first fine duty value F1_duty and the first fine period value F1_per based on the second N / Counting can be performed to generate the first PWM signal PWM1.

The second PWM generator 200-2 may include a second course controller 210-2 and a second fine controller 220-2.

The second course controller 210-2 generates the main clock signal clk based on the first clock signal f_clk, the second course duty value C2_duty and the second course period value C2_per And may perform the first N / 2 bit count to generate the second course clock signal g2_clk.

The second fine controller 220-2 may output the second N / 2 bit (g2_clk) to the second course clock signal g2_clk based on the second fine duty value F2_duty and the second fine period value F2_per Counting can be performed to generate the second PWM signal PWM2.

The nth PWM generator 200-n may include an nth course controller 210-n and an nth fine controller 220-n.

The nth course controller 210-n is a circuit for generating the nth course controller 210-n with respect to the main clock signal clk based on the first clock signal f_clk, the n-course duty value Cn_duty and the nth course period value Cn_per. And may perform the first N / 2 bit count to generate the nth course clock signal gn_clk.

The n-th fine-tuning controller 220-n outputs the second N / 2 bits (n-2) to the n-th coarse clock signal gn_clk based on the n-th fine duty value Fn_duty and the n- Counting can be performed to generate the n-th PWM signal PWMn.

When each of the first to n-th PWM generators 200-1 to 200-n corresponds to the k-th PWM generator 200-k (k is a natural number equal to or greater than 1 and equal to or less than n) K-th controller 200-k may include a kth course controller 210-k and a kth fine controller 220-k.

The kth course controller 210-k is configured to generate the main clock signal clk based on the first clock signal f_clk, the k-course duty value Ck_duty and the k-th course period value Ck_per The first N / 2 bit counting may be performed to generate the kth course clock signal gk_clk.

The k-th fine-motion controller 220-k outputs the second N / 2 bits (k-1) to the k-th coarse clock signal gk_clk based on the k-th fine-duty value Fk_duty and the k- Counting can be performed to generate the k-th PWM signal PWMk.

For each figure of the present invention, possible unnecessary redundant explanations can be omitted for the same reference numerals and components having the same function, and possible differences for each figure can be explained.

2 is a timing chart of a main clock signal, a first clock signal, and a start signal according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, when the resolution of the high-frequency multi-channel PWM controller is 4 bits, the frequency divider ratio of the prescaler 100 may be set to 4. In this case, The first clock signal f_clk of 250 MHz can be generated by dividing the main clock signal clk of the first clock signal clk by four.

2 shows an example of the main clock signal clk and the first clock signal f_clk, but is not limited thereto.

3 is a diagram illustrating an example of a k-th PWM generator according to an embodiment of the present invention.

3, the kth course controller 210-k includes a first N / 2 (N is a number of bits of resolution) bit counter 211, a first comparator 212, a second comparator 213, A first logical product circuit 214 and a first logical sum circuit 215. [

The first N / 2 bit counter 211 may provide the first count value by counting the first clock signal f_clk.

For example, when the resolution N of the high-frequency multi-channel PWM controller is 8 bits, the first N / 2 bit counter 211 may be a 4-bit counter.

The first comparator 212 may compare the first count value with the kth duty value Ck_duty to provide a first comparison signal com1. The second comparator 213 may compare the first count value and the k-th cycle period value Ck_per to provide a second comparison signal com2.

For example, the first comparator 212 may provide a first comparison signal com1 having an active level (e.g., 1 or a high level) when the first count value and the kth duty value Ck_duty are the same can do. The second comparator 213 may provide a second comparison signal com2 having an active level (e.g., 1) if the first count value and the kth course period value Ck_per are equal to each other.

For example, when the resolution N bits of the high-frequency multi-channel PWM controller are 10 bits, the kth course value Ck_duty may be 499, the kth course period value Ck_per may be 999, The first count value may be any one of 0 to 999.

In another example, when the resolution N bits of the high-frequency multi-channel PWM controller are 2 bits, the kth course value (Ck_duty) may be 2, the kth course period value (Ck_per) may be 3 , And the first count value may be any one of 0 to 3.

The first AND circuit 214 may perform a logical sum operation on the first comparison signal com1 and the second comparison signal com2 to provide a clock enable signal gclk_en.

For example, the first AND circuit 214 may include an OR gate for performing an OR operation on the first comparison signal com1 and the second comparison signal com2.

The first OR circuit 215 may provide the kth course clock signal gk_clk based on the clock enable signal gclk_en and the main clock signal clk.

For example, the first OR circuit 215 includes an AND gate (AND gate) for performing the logical sum operation on the clock enable signal gclk_en and the main clock signal clk to provide the kth course clock signal gk_clk, . ≪ / RTI >

3, the k-th-order controller 220-k includes a second N / 2 bit counter 221, a third comparator 222, a fourth comparator 223, a second logical summing circuit 224 and a holding circuit 225. [

The second N / 2 bit counter 221 may count the kth course clock signal gk_clk to provide a second count value.

For example, when the resolution N of the high-frequency multi-channel PWM controller is 8 bits, the second N / 2 bit counter 221 may be a 4-bit counter.

Here, the first N / 2 bit counter 211 may perform a first N / 2 bit count and the second N / 2 bit counter 221 may perform a second N / have.

The third comparator 222 may compare the second count value with the k-th fine duty value Fk_duty to provide a clear signal clear. The fourth comparator 223 may compare the second count value with the kth course period value Ck_per to provide a set signal set.

For example, the third comparator 222 may provide the clear signal clear having an active level (e.g., 1) if the second count value and the k-th fine duty value Fk_duty are the same. The fourth comparator 223 may provide the set signal set having an active level (e.g., 1) if the second count value and the k-th course period value Ck_per are the same.

The second OR circuit 224 can perform a logical sum operation on the set signal set and the start signal begin to provide it to the set terminal of the holding circuit 225. [

For example, the OR circuit 224 may include an OR gate for performing an OR operation on the set signal (set) and the start signal (begin).

The holding circuit 225 sets the output terminal based on the output signal from the second OR circuit 224 and resets the output terminal based on the clear signal clear to output the kth PWM signal PWMk ). ≪ / RTI >

For example, the holding circuit 225 sets an output stage based on the output signal from the second OR circuit 224, and outputs an RS latch or an RS flip-flop for resetting the output stage based on the clear signal clear. Flop.

For example, when the level of the output signal from the second OR circuit 224 is an active level (e.g., 1), the holding circuit 225 sets the output stage, and if the level of the clear signal clear is active Level (e.g., 1), the output terminal may be reset to provide the k-th PWM signal PWMk.

As described above, according to an embodiment of the present invention, the kth course controller 210-k includes one first N / 2 (N is a number of bits of resolution) bit counter 211, The k-th fine-controller 220-k includes another second N / 2 bit counter 221, i.e., instead of the existing one N-bit count, / 2-bit counter so that the number of high-frequency counters having a higher resolution than the number of channels can be reduced, thereby reducing the switching current and reducing the total consumed current.

4 is a diagram illustrating an operation timing chart of a high-frequency multi-channel PWM control apparatus according to an embodiment of the present invention.

The high-frequency multi-channel PWM control apparatus shown in Figs. 1 to 3 is configured such that when the resolution of the high-frequency multi-channel PWM control apparatus is 4 bits (N = 4) as shown in Fig. 4, (2), the kth course period value (Ck_per) is 3, the kth fine duty value (Fk_duty) is 1, and the kth fine period value (Fk_per) is 3.

Referring to FIGS. 1 to 4, when the high frequency multi-channel PWM controller according to the embodiment of the present invention has a 4-bit resolution, the first N / 2 counter 211 can operate as a 2-bit counter, The second N / 2 counter 221 can operate as a 2-bit counter.

Here, each of the first N / 2 counter 211 and the second N / 2 counter 221 may count 2 ² (2 ² = 4) clocks.

First, when the start signal Begin is input, the first N / 2 counter 211 and the second N / 2 counter 221 are initialized to zero and the count operation can be started.

The prescaler 100 divides the main clock signal clk to generate a first clock signal f_clk and outputs the first clock signal f_clk and the main clock signal clk to the multi- K < / RTI > course controller 210-k of FIG.

For example, if the dividing ratio is 4 in the prescaler 100 of FIG. 1, the first clock signal f_clk that is divided by 4 is generated and the first N / 2 counter (k) of the kth course controller 210- 211).

The first N / 2 bit counter 211 of the kth course controller 210-k generates a first count value by counting the first clock signal f_clk and outputs the first count value to the first comparator 212, The comparator 213 and the first AND circuit 214 respectively output the clock enable signal (Ck_duty) or the k-th cycle period value (Ck_per) when the first count value reaches a predetermined k- and the first OR circuit 215 can generate the kth course clock signal gk_clk based on the main clock signal clk when the clock enable signal gclk_en is one.

The kth course duty value Ck_duty is a value indicating a time point at which the clock enable signal gclk_en is changed from 1 to 0 in the kth coarse controller 210-k, Ck_per is a value indicating the time when the clock enable signal gclk_en is changed from 0 to 1 in the k-th coarse controller 210-k.

The k-th fine duty value Fk_duty is a value indicating a time point at which the k-th PWM signal PWMk is changed from 1 to 0 in the k-th fine controller 220-k, Fk_per is a value indicating the time at which the kth PWM signal PWMk is changed from 0 to 1 in the k-th fine controller 220-k.

The first N / 2 counter 211 is initialized when the start signal (begin) or the set signal (set) is 1. At this time, the state of the k-th PWM signal PWMk may be 1.

The first N / 2 counter 211 may count a first clock signal f_clk to provide a first count value. For example, when the kth course value (Ck_duty) is 2 and the kth course period value (Ck_per) is 3, when the first count value of the first N / 2 counter 211 becomes 2 or 3, The clock enable signal gclk_en is set to 1 by the first comparator 212, the second comparator 213 and the first logical product circuit 214. When the clock enable signal gclk_en is 1, the k-th course clock gk_clk having the same frequency can be generated in synchronization with the clock signal clk and supplied to the second N / 2 counter 221 of the k-th controller 220-k.

At this time, if the first count value of the first N / 2 counter 211 is equal to the k-course duty value Ck_duty, the k-th course clock gk_clk is supplied to the second N / 2 counter 221 And the second N / 2 counter 221 starts counting the kth course clock signal gk_clk.

Each of the third comparator 222 and the fourth comparator 223 may be configured such that the second count value of the second N / 2 counter 221 is a k-th duty value Fk_duty or a k- (For example, 1) when the second count value of the second N / 2 counter 221 is equal to the k-th duty value Fk_duty as compared with each of the first count value Fk_per and the second count value Fk_per, , 1), and clears the holding circuit 225 to make the level of the k-th PWM signal PWMk zero. Thereafter, even when the first count value of the first N / 2 counter 211 reaches 3, which is the k-th cycle period value (Ck_per), the kth course clock signal gk_clk is generated and the second N / The set signal set is generated when the k-th cycle period value Ck_per is 3 and the k-th cycle period value Fk_per is 3 and the state of the k-th PWM signal PWMk is 1 .

Through the above-described process, the high-frequency multi-channel PWM controller according to the embodiment of the present invention can complete the control of the PWM signal for one period.

The number of clocks required in the high-frequency multi-channel PWM controller according to an embodiment of the present invention is shown in Table 1 below.

[Table 1]

Referring to FIG. 4 and Table 1, when the resolution is 4 (N = 4) and k = 1, the number of clocks required for one period of the PWN signal requires 16 main clocks, (gk_clk) and four first clock signals (f_clk) are required.

For example, the number of clocks of the first clock signal f_clk required for the N-bit resolution and the k channel is k × 2 ( ^{N / 2} ), and the number of clocks of the main clock signal clk is ^2N + k × a ² × 2 ^{(N / 2)} requires the dog to the total number of clocks required for the PWM control is ^{2 N + k × 3 × 2} (N / 2).

For example, as shown in Table 1, when one channel (k = 1) is assumed, the number of clocks of the present invention is rather larger and the switching current consumption is more. However, the number of clocks required for multi-channel configuration of more than 2 channels is reduced. When N = 10, when 8-channel PWM is used, less than 1/4 of the clock is used.

Referring to Table 1, the power consumption of the digital circuit is proportional to the state transition, and the amount of switching current consumed by the clock takes a large proportion. Therefore, the consumption current can be expected to be reduced through the embodiment of the present invention.

On the other hand, when a high frequency multi-channel PWM control apparatus according to an embodiment of the present invention is applied to a camera module, a PWM 1 channel may be used to drive one actuator, There are cases where the control is performed independently. Therefore, when driving P-channel and N-channel, two-channel PWM control is required for each actuator.

Or, in the case of OIS, 4-channel PWM output is required for X-axis and Y-axis control, and 8-channel PWM control is required for OIS control of dual cameras. Therefore, when OIS control for dual cameras is performed, PWM control is possible with about 21.88% power consumption compared with the conventional method.

For example, in a conventional system, a 1GHz clock should be used if the resolution is 10 bits with a 1MHz PWM period. When a 10-bit counter is configured at 1 GHz, it is difficult to implement a digital circuit in some cases. Although it can be implemented relatively easily when implemented using a high-speed cell having a high power consumption, it uses a cell having a large power consumption, which causes a disadvantage that an overall current consumption is increased.

In the case of using two (N / 2) bit counters using the high frequency multi-channel PWM control device according to the embodiment of the present invention, it is very easy to implement a digital circuit and can be implemented using a general low- have.

In the high-frequency multi-channel PWM control apparatus according to the embodiment of the present invention, the structure for minimum power consumption uses two (N / 2) bit counters instead of the N-bit counters. When N is odd A counter of M bits and a counter of L bits (M + L = N, M = L + 1). For control, a setting value for generating a course clock signal (g_clk) must be specified as an input in the first N / 2 counter 211, and a detail value for generating a PWM signal in the second N / 2 counter 221 You must specify input values for duty and period adjustments.

Here, the PWM period and the duty setting can be set by using a register in a digital circuit, and when the resolution (N) is 10 bits, the cycle and the duty of the PWM signal can be designated as a count value ranging from 0 to 1023 .

For example, when the resolution N is 10 bits and the frequency of the main clock signal clk is 1 GHz, the course duty value C_duty may be 499 and the course period value C_per may be 999 (E.g., 1) for 500 clocks from 0 to 499 during the course duty value C_duty and an active level (e.g., 0 or low level) during the remaining 500 clocks, and 50% The duty ratio can be a PWM signal. In this case, since the frequency of the main clock signal clk is 1 GHz, the frequency of the PWM signal can be about 1 MHz.

In the high frequency multi-channel PWM controller according to an embodiment of the present invention, when the resolution is changed, each register may be composed of two (N / 2) bit registers. Here, if the resolution is not changed and fixed to N bits, the register can be divided into upper (N / 2) bits and lower (N / 2) bits to input a set value.

For example, in the case of a 10-bit register, the upper 5 bits and the lower 5 bits can be used as input values of the present invention. However, when the value of N is changed, it is effective to store the upper (N / 2) and lower (N / 2) in separate registers to perform a coarse and fine control. Here, in the case of N = 10, since the coarse and fine control are performed using the 5-bit counter in the configuration of the present invention, the period and the duty setting range are limited to 5 bits and have values ranging from 0 to 31 .

For example, in order to set the 1 kHz PWM period and the 50% duty ratio, 999 and 499 can be expressed in binary numbers as shown in FIGS. 5 and 6.

5 is an example of an kth course value C1_duty, a kth course period value C1_per, a kth fine duty value F1_duty, and a kth fine period value F1_per according to an embodiment of the present invention. to be.

5, the number of 10 bits is divided into upper N / 2 bits and lower N / 2 bits, upper N / 2 bits are used for coarse control and lower N / 2 bits are used for fine control You can use the following settings.

In the case of setting as shown in FIG. 5, C_per = 31, C_duty = 15, F_per = 7, and F_duty = 19. If N = 10, the entire 5 bits of the resolution and 10 bits of the lower 5 bits must be used separately. Therefore, it is possible to use a register to be set by the user in the same way as before. However, if N is changed, ) And fine (Fine) control can be set separately.

FIG. 6 is a block diagram showing an example of a k-th coefficient value register (C1_duty), a k-th cycle period value C1_per, a k-th fine-duty value F1_duty, (Set-N).

Referring to FIG. 6, in another example, an additional register (Set_N) having one cycle and duty setting registers and specifying the number of bits of N may be used.

For example, if N = 8 and the additional register (Set_N) is set to 8, 8 bits are divided into 4 upper 4 bits and used for the calculation. As an example, the additional register (Set_N) in FIG. 6 may be an 8-bit register.

6, since the effective digits of the period and duty setting registers are calculated and processed according to the value of the additional register Set_N, the period and the duty are set to separate registers according to the coarse and fine It is easier to do.

100: prescaler
200: Multi-channel PWM generator
200-1 to 200-n: First to nth PWM generators
clk: Main clock signal
f_clk: first clock signal
PWM1 to PWMn: First to nth PWM signals
C1_duty to Cn_duty: First to nth course duty values
C1_per to Cn_duty: First to nth course period values
g1_clk to gn_clk: first to nth course clock signals
F1_duty to Fn_duty: first to n-th fine duty values
F1_per to Fn_per: First to nth fine cycle values

Claims (15)

A prescaler dividing the main clock signal to generate a first clock signal; And
And generating first to n-th (n is a natural number of 2 or more) PWM signals having a corresponding period and duty using first and second N / 2 bit counts for the main clock signal using the first clock signal, A multi-channel PWM generator including first through n-th PWM generators; Lt; / RTI >
Each of the first to n < th >
And a second N / 2 bit counter for performing a first N / 2 bit count on the main clock signal based on the first clock signal, a corresponding course duty value, and a corresponding course period value to generate a coarse clock signal, And the second N / 2 bit counting is performed on the course clock signal based on the first N / 2 bit value to generate a corresponding PWM signal
High frequency multi-channel PWM control device.
2. The apparatus of claim 1, wherein each of the first through n < th >
A kth course controller for generating a course clock signal based on the main clock signal, the first clock signal, a corresponding course duty value and a corresponding course period value; And
A k-th fine-pitched controller for generating a corresponding PWM signal based on the course clock signal, the fine duty value and the fine period value;
Frequency PWM control device.
3. The method of claim 2, wherein the kth course controller
A first N / 2 bit counter for counting the first clock signal to provide a first count value;
A first comparator for comparing the first count value and the k-course duty value to provide a first comparison signal;
A second comparator for comparing the first count value with a kth course period value to provide a second comparison signal;
A first AND circuit for ORing the first comparison signal and the second comparison signal to provide a clock enable signal; And
A first logical summing circuit for providing a kth course clock signal based on the clock enable signal and the main clock signal;
Frequency PWM control device.
4. The apparatus of claim 3, wherein the k <
A second N / 2 bit counter for counting the kth course clock signal to provide a second count value;
A third comparator comparing the second count value with a k-th fine duty value to provide a clear signal;
A fourth comparator comparing the second count value with a kth course period value to provide a set signal;
A second OR circuit for performing an OR operation on the set signal and the start signal; And
A holding circuit for setting an output stage based on an output signal from the second logical sum circuit, resetting the output stage based on the clear signal and providing a k-th PWM signal;
Frequency PWM control device.
4. The apparatus of claim 3, wherein the first comparator
Providing a first comparison signal having an active level if the first count value and the k-course duty value are equal,
The second comparator
And providing a second comparison signal having an active level if the first count value and the kth course period value are equal
High frequency multi-channel PWM control device.
4. The semiconductor memory device according to claim 3, wherein the first OR circuit
An AND gate for performing the logical sum operation on the clock enable signal and the main clock signal to provide the kth course clock signal;
Frequency PWM control device.
5. The apparatus of claim 4, wherein the third comparator
Providing the clear signal having an active level if the second count value and the k-th fine duty value are the same,
The fourth comparator
Providing said set signal having an active level if said second count value and said kth course period value are equal
High frequency multi-channel PWM control device.
5. The semiconductor memory device according to claim 4, wherein the holding circuit
And sets the output stage if the level of the output signal from the second logical sum circuit is an active level and resets the output stage if the level of the clear signal is active level to provide the kth PWM signal
High frequency multi-channel PWM control device.
A prescaler dividing the main clock signal to generate a first clock signal; And
And generating first to n-th (n is a natural number of 2 or more) PWM signals having a corresponding period and duty using first and second N / 2 bit counts for the main clock signal using the first clock signal, A multi-channel PWM generator including first through n-th PWM generators; Lt; / RTI >
The first PWM generator
A first course controller for performing the first N / 2 bit count on the main clock signal based on the first clock signal, the first course duty value, and the first course period value to generate a first course clock signal; And a first fine controller for performing the second N / 2 bit count on the first course clock signal based on a first fine duty value and a first fine period value to generate a first PWM signal,
The n-th PWM generator
An nth course controller that performs the first N / 2 bit counting on the main clock signal based on the first clock signal, the nth course duty value, and the nth course period value to generate an nth course clock signal; And
An n-th fine-tune controller for performing the second N / 2 bit count on the n-th coarse clock signal based on the n-th fine-duty value and the n-th fine-cycle value to generate an n-th PWM signal;
Frequency PWM control device.
10. The apparatus of claim 9, wherein the kth course controller
A first N / 2 bit counter for counting the first clock signal to provide a first count value;
A first comparator for comparing the first count value and the k-course duty value to provide a first comparison signal;
A second comparator for comparing the first count value with a kth course period value to provide a second comparison signal;
A first AND circuit for ORing the first comparison signal and the second comparison signal to provide a clock enable signal; And
A first logical summing circuit for providing a kth course clock signal based on the clock enable signal and the main clock signal;
Frequency PWM control device.
11. The apparatus of claim 10, wherein the k <
A second N / 2 bit counter for counting the kth course clock signal to provide a second count value;
A third comparator comparing the second count value with a k-th fine duty value to provide a clear signal;
A fourth comparator comparing the second count value with a kth course period value to provide a set signal;
A second OR circuit for performing an OR operation on the set signal and the start signal; And
A holding circuit for setting an output stage based on an output signal from the second logical sum circuit, resetting the output stage based on the clear signal and providing a k-th PWM signal;
Frequency PWM control device.
11. The apparatus of claim 10, wherein the first comparator
Providing a first comparison signal having an active level if the first count value and the k-course duty value are equal,
The second comparator
And providing a second comparison signal having an active level if the first count value and the kth course period value are equal
High frequency multi-channel PWM control device.
11. The semiconductor memory device according to claim 10, wherein the first OR circuit
An AND gate for performing the logical sum operation on the clock enable signal and the main clock signal to provide the kth course clock signal;
Frequency PWM control device.
12. The apparatus of claim 11, wherein the third comparator
Providing the clear signal having an active level if the second count value and the k-th fine duty value are the same,
The fourth comparator
Providing said set signal having an active level if said second count value and said kth course period value are equal
High frequency multi-channel PWM control device.
12. The method of claim 11, wherein the holding circuit
And sets the output stage if the level of the output signal from the second logical sum circuit is an active level and resets the output stage if the level of the clear signal is active level to provide the kth PWM signal
High frequency multi-channel PWM control device.

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