KR20180113901A - Semiconductor structures and methods - Google Patents

Abstract

A method comprises the steps of: attaching a carrier to a substrate; aligning an external connector on a first surface of a first semiconductor package on a first conductive pad of a first surface of the substrate spaced apart from and opposing to the carrier; and performing a reflow process, wherein a difference in coefficient of thermal expansion (CTE) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, a difference in CTE between materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and the first shape substantially coincides with the second shape. The method further includes a step of separating the carrier from the substrate after the reflow process.

Description

[0001] SEMICONDUCTOR STRUCTURES AND METHODS [0002]

<Priority claim and cross reference>

This application claims priority to U.S. Provisional Patent Application No. 62 / 483,198, entitled " Semiconductor Structures and Methods, " filed April 7, 2017, which is incorporated herein by reference in its entirety. .

<Background>

BACKGROUND OF THE INVENTION The semiconductor industry is rapidly growing due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Most of these improvements in integration density result from repeated shrinking of the minimum feature size, so that more parts can be integrated in a given area. As the demand to shrink electronic devices grows, there is a need for smaller and more original packaging techniques for semiconductor die. One example of such a packaging system is a package-on-package (PoP) technology. In the case of PoP devices, the upper semiconductor package is stacked on top of the lower semiconductor package to provide a high degree of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and small footprint. Another example is a chip-on-wafer-on-substrate (CoWoS) in which a semiconductor chip is attached to a wafer (e.g., an interposer) to form a chip-on-wafer structure. A CoW structure is attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure.

BRIEF DESCRIPTION OF THE DRAWINGS The aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying drawings. Depending on the industry standard practice, the various features are not shown in scale. In practice, the dimensions of the various features may be scaled up or down arbitrarily for convenience of explanation.
Figures 1-4 illustrate cross-sectional views of semiconductor devices at various fabrication steps in accordance with one embodiment.
Figures 5-8 illustrate cross-sectional views of semiconductor devices at various fabrication steps in accordance with one embodiment.
Figures 9-13 illustrate cross-sectional views of semiconductor devices at various fabrication steps in accordance with one embodiment.
14-17 illustrate cross-sectional views of semiconductor devices at various fabrication steps in accordance with one embodiment.
Figures 18-21 illustrate cross-sectional views of a carrier according to various embodiments.
22 shows a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

The following disclosure provides a number of different embodiments or embodiments for implementing the different features of the present invention. Specific embodiments of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples, and are not intended to be limiting. For example, in the following description, formation of a first feature of a second feature over or on may include embodiments wherein the first and second features are formed in direct contact, Embodiments may also include that additional features may be formed between the first and second features such that the second features are not in direct contact.

Also, terms related to space such as "beneath", "below", "lower", "above", "upper" May be used herein for ease of description in describing the relationship of the feature to the other element (s) or feature (s). The term space-related is intended to encompass different orientations of the device during use or operation, as well as the directions shown in the figures. The device may be oriented differently (rotated 90 degrees or in other directions) and the spatial related descriptor used herein may be similarly interpreted accordingly.

Embodiments of the present disclosure will be described in the context of semiconductor manufacturing, and more particularly in the context of forming a three-dimensional (3D) semiconductor structure. In some embodiments, the 3D semiconductor structure includes a semiconductor package attached to a conductive pad on a first side of the substrate. A second side of the substrate opposite the first side is attached to the carrier. In some embodiments, mismatch in the thermal expansion coefficient causes warpage in the semiconductor package and the substrate during the reflow process. According to some embodiments, the carrier is designed to induce a predetermined level of deflection within the substrate to substantially match the first deflection of the first surface of the substrate with the second deflection of the bottom surface of the semiconductor package. This disclosure reduces or prevents cold joints and improves process yield.

1-4 illustrate cross-sectional views of semiconductor device 100 at various stages of fabrication. Referring to FIG. 1, a substrate 105 is attached to the carrier 101 through an adhesive layer 103. The substrate 105 may be made of BT (bismaleimide triazine) resin, FR-4 (a composite material composed of a fiberglass fabric woven with a flame retardant epoxy resin binder), ceramic, glass, plastic, tape, film, . As shown in Fig. 1, conductive pads 107, such as aluminum pads or copper pads, are formed on the top surface of the substrate 105. The conductive pad 107 may be electrically connected to a conductive feature (e.g., a conductive line or via, not shown) formed in the substrate 105. The conductive pad 107 may be electrically connected to another electrical device or component (e.g., a semiconductor die, semiconductor package, capacitor, inductor, resistor, diode, etc.) ). &Lt; / RTI &gt; In some embodiments, the substrate 105 may include electrical components such as resistors, capacitors, signal distribution circuits, combinations thereof, and the like. These electrical components may be active, passive, or a combination thereof. In another embodiment, there are no active and passive electrical components inside the substrate 105. It is entirely intended that all such combinations are included within the scope of the present embodiment.

In some embodiments, the substrate 105 is a PCB such as a single layer printed circuit board (PCB) or a multi-layer PCB. Metal interconnects (not shown), including metal lines and vias, are formed in / on the PCB and are electrically coupled to the conductive pads 107. For example, in the case of a single layer PCB, metal lines may be formed on one or both sides of the PCB, and vias may extend through the PCB to form metal lines on both sides of the PCB. Although not shown in FIG. 1, the conductive pad 107 may also be formed on the lower surface of the substrate 105 facing the carrier 101. In embodiments where the substrate 105 is a multi-layer PCB, metal lines and vias are also formed in at least one layer of the substrate 105 between both sides of the substrate 105. As shown in FIG. 1, a passivation layer 109, such as a solder resist, is formed over the substrate 105 and over the conductive pad 107. An opening is formed in the passivation layer 109 to expose the conductive pad 107. In an exemplary embodiment, the substrate 105 is a PCB having dimensions of about 30 mm x about 30 mm or larger, although other dimensions are possible.

The carrier 101 includes a rigid material and has a top surface 101U. The upper surface 101U may be flat at room temperature, for example. The lower surface of the substrate 105 is attached to the upper surface 101U of the carrier 101. The carrier 101 is a temporary carrier used to support the substrate 105 in a subsequent process, e.g., a bonding process. Thereafter, in some embodiments, the carrier 101 is separated from the substrate 105 when the bonding process is completed.

The carrier 101 may comprise any suitable material capable of providing structural support to the substrate 105. For example, the carrier 101 may comprise metal (e.g., steel), glass, ceramic, silicon (e.g., bulk silicon), combinations thereof, multilayers thereof, and the like. The coefficient of thermal expansion (CTE) of the carrier 101 is greater than the coefficient of thermal expansion (CTE) of the carrier 101 and the coefficient of thermal expansion of the substrate 105 after the substrate 105 is attached to the carrier 101 and during the reflow process. (E.g., a difference) between the CTEs of the substrate 105 is adjusted to induce a predetermined (e.g., designed) level of deflection of the substrate 105. The details thereof will be discussed below.

In some embodiments, only one substrate 105 is attached to the carrier 101, and the other substrate is not attached to the carrier 101. In other words, one carrier 101 supports only one substrate 105. In another embodiment, a plurality of substrates 105 are attached to the carrier 101, and thus one carrier 101 supports a plurality of substrates 105. The shape of the carrier 101 in a top view (not shown) may be any shape suitable for receiving one or more substrates 105. For example, the carrier 101 may have a rectangular, square, polygonal, or circular shape. The size (e.g., surface area) of the carrier 101 is, in some embodiments, equal to or greater than the size (e.g., surface area) of one or more substrates 105 attached to the carrier. In the embodiment in which one carrier 101 supports one substrate 105, the shape of the carrier 101 is the same as or similar to the shape of the substrate 105. For example, both the carrier 101 and the substrate 105 may have the same rectangular or similar rectangular shape when viewed in plan view. It should be noted that since the surface area of the carrier 101 is equal to or larger than the surface area of the substrate 105, the substrate 105 is fully supported by the carrier 101 downward. For example, in a plan view, the substrate 105 is disposed in the outer periphery of the carrier 101.

In the example of Fig. 1, the substrate 105 is attached to the carrier 101 by the adhesive layer 103. Fig. In some embodiments, the adhesive layer 103 is a polymer adhesive layer. For example, the adhesive layer 103 may be a light-to-heat conversion (LTHC) film in which adhesiveness is reduced or lost when exposed to a radiation source (e.g., ultraviolet light or laser). Therefore, in order to separate the carrier 101 from the substrate 105 in a subsequent process, irradiation of ultraviolet rays (UV) or a laser beam onto the adhesive layer 103 (e.g., LTHC film) It can be easily separated from the substrate 105. Other suitable adhesive layers, such as a die attaching film (DAF), may also be used, and the separation process of the carrier 101 may include a mechanical peel-off process, a grinding process, or an etching process, The cleaning process may be performed. In some embodiments, the adhesive layer 103 is removed by applying water to the adhesive layer 103.

Next, as shown in Fig. 2, a semiconductor package 250 is disposed on the substrate 105. Fig. The external connectors 217 of the semiconductor package 250 are aligned with the respective conductive pads 107 of the substrate 105 to prepare for a subsequent bonding process (e.g., a reflow process). Solder paste (not shown) may be dispensed over the conductive pads 107 to temporarily attach the semiconductor package 250 to the substrate 105.

The semiconductor package 250 may be a system-on-chip (SoC) package, an integrated-fan-out (InFO) package, or a chip-on-wafer-on-substrate package. In the example of FIG. 2, semiconductor package 250 is a Chip-On-Wafer (CoW) package that is bonded to substrate 105 in subsequent processing to form a CoWoS package.

As shown in FIG. 2, the semiconductor package 250 includes a semiconductor die (also referred to as die) 201 attached to the top surface of the interposer 211 through a die connector 205. The semiconductor package 250 further includes an external connector 217 that is electrically coupled to the molding material 203 on the top surface of the interposer 211 and around the die 201 and the bottom surface of the interposer 211 do.

 Hereinafter, the semiconductor package 250 will be described in detail. The semiconductor die 201 may include a substrate (not individually shown), an electrical component (not individually shown) on the substrate, a metallization layer (not individually shown) on the substrate, a passivation layer (Not individually shown), and a die connector 205 on the passivation layer. In one embodiment, the substrate may comprise an active layer of a doped or undoped bulk silicon, or a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, graded substrates, or hybrid orientation substrates.

Electrical components include a variety of active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, inductors) that can be used to create desirable structural and functional requirements of the design for semiconductor die 201. The electrical component may be formed on or within the substrate of the die 201 using any suitable method.

The metallization layer is formed over the substrate and the electrical component and is designed to connect the various electrical components to form a functional circuit. In one embodiment, the metallization layer is formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (e.g., deposition, damascene, dual damascene, etc.). In one embodiment, there may be four metallization layers separated from the substrate by at least one interlevel dielectric layer (ILD), but the exact number of metallization layers depends on the design of the semiconductor die 201.

The passivation layer may be formed over the metallization layer to some extent protect the underlying structure. The passivation layer may comprise one or more of a low k dielectric such as silicon oxide, silicon nitride, carbon doped oxide, ultra low k dielectric such as porous carbon doped silicon dioxide, combinations thereof, and the like. May be made of a suitable dielectric material. The passivation layer may be formed through a process such as chemical vapor deposition (CVD), but any suitable process may be used.

A conductive pad may be formed over the metallization layer to make electrical contact with the metallization layer. The conductive pad may comprise aluminum, but other materials, such as copper, may alternatively be used. The conductive pad may be formed using a deposition process such as sputtering or plating to form a material layer (not shown), wherein a portion of the material layer is removed through an appropriate process (e.g., photolithographic masking and etching) A pad can be formed. However, any other suitable process may be used to form the conductive pad.

The die connector 205 may be formed on the conductive pad to provide a conductive region in the contact between the metallization layer of the die 201 and the conductive pad 215 of the interposer 211, for example. In one embodiment, die connector 205 may be a contact bump, such as a micro-bump, or may comprise a material such as tin or other suitable material such as silver or copper. In embodiments where the die connector 205 is a tin solder bump, the die connector 205 may be formed by first forming a tin layer by any suitable method, such as evaporation, electroplating, printing, solder transfer, . When a tin layer is formed on the structure, reflow is performed to form the material into a desired bump shape having a diameter of, for example, about 10 mu m to 100 mu m, alternatively any suitable size may be used.

However, those skilled in the art will appreciate that although the die connector 205 has been described as a micro-bump, these are illustrative only and are not intended to limit the embodiments. Rather, a controlled collapse chip connection (C4) bump, a copper pillar, a copper layer, a nickel layer, a lead free (LF) layer, an electroless nickel electroless palladium immersion gold (ENEPIG) Layer, an Sn / Ag layer, Sn / Pb, combinations thereof, or the like, may alternatively be used. Any suitable external connector, and any suitable process for forming the external connector, may be used in the die connector 205, all of which are entirely intended to be within the scope of the embodiments.

Looking at the interposer 211, it includes a substrate 213 and a conductive path 215 (e.g., through a through substrate via (TSV)). The substrate 213 may be a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, the substrate 213 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or other substrate that may provide suitable protection and / or interconnection functionality. These and other suitable materials may alternatively be used for the substrate 213.

In some embodiments, the substrate 213 may include electrical components such as resistors, capacitors, signal distribution circuits, combinations thereof, and the like. These electrical components may be active, passive, or a combination thereof. In another embodiment, there are no active and passive electrical components inside the substrate 213. It is entirely intended that all such combinations are included within the scope of the present embodiment.

In addition, in some embodiments, the substrate 213 is a semiconductor wafer. As such, when one or more semiconductor dies, e.g., die 201, are bonded to substrate 213, the combined structure may form a chip-on-wafer (CoW) configuration.

Conductive path 215 may be a TSV or other suitable conductive path. In embodiments where the conductive path 215 is a TSV, a TSV is formed by first forming an electrically conductive path partially through the substrate 213, and then later thinning the substrate 213 to expose the electrically conductive path . In another embodiment, the conductive path 215 extends through the substrate 213 when initially formed, and thinning of the substrate 213 is not required. The conductive path 215 may be formed by forming a suitable photoresist or hard mask on the substrate 213 and then patterning the photoresist or hard mask and then etching the substrate 213 to create an opening (e.g., a TSV opening) .

If an opening for the conductive path 215 is formed, the opening may be filled with a conductive material, for example, a liner (not separately shown in FIG. 2), a barrier layer (also not separately shown in FIG. 2), and a conductive material. In one embodiment, the liner can be a silicon nitride, a silicon oxide, a dielectric polymer, a combination thereof, or the like formed by processes such as chemical vapor deposition, oxidation, physical vapor deposition, atomic layer deposition and the like.

The barrier layer may comprise a conductive material such as titanium nitride, but other materials such as, for example, carbonitride, titanium, another dielectric, etc., may alternatively be used. The barrier layer may be formed using a CVD process such as plasma enhanced CVD (PECVD). However, other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), etc. may also be used. The barrier layer may be formed to outline the bottom shape of the opening for the conductive path 215.

The conductive material may comprise copper, but other suitable materials such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, and the like may also be used as an alternative. The conductive material may be formed by depositing a seed layer, then electroplating copper on the seed layer and overfilling the openings for the conductive path 215. Once the opening for the conductive path 215 is filled, the excess barrier layer and the excess conductive material outside the opening may be removed through a grinding process such as chemical mechanical polishing (CMP), any suitable removal process may be used.

Although not shown in FIG. 2, the top surface of the substrate 213 facing the die 201 is electrically connected to the conductive path 215, the die connector 205, and the semiconductor die 201 to provide electrical interconnectivity between the conductive path 215, A rewiring structure may be formed. The rewiring structure includes a redistribution layer (RDL) (e.g., conductive lines and / or vias) disposed in one or more dielectric layers of the rewiring structure. The rewiring structure can be formed using a general method for forming an interconnect structure in an integrated circuit, and a detailed description thereof will not be repeated here.

When a rewiring structure is formed, a conductive pad (not shown) may be formed on the RDL on the upper surface of the substrate 213 and electrically connected to the RDL. The conductive pad may comprise aluminum, but other materials, such as copper, may alternatively be used. Conductive pads may be formed using a deposition process, such as sputtering, to form a material layer (not shown), where portions of the material layer are removed through suitable processes (e.g., photolithographic masking and etching) . However, any other suitable process may be used to form the conductive pad.

Next, an external connector 217 may be formed on the lower surface of the substrate 213 and electrically coupled to the RDL via, for example, a conductive path 215. The external connector 217 is physically and electrically coupled to the substrate 105, e.g., by a reflow process, in subsequent processing (see FIGS. 3A and 3B) to form a CoWoS structure. The external connector 217 may be formed of a copper pillar, a controlled collapse chip connection (C4) bump, a micro bump, a copper layer, a nickel layer, a leadless (LF) layer, electroless nickel electroless palladium immersion gold (ENEPIG) / LF layer, Sn / Ag layer, Sn / Pb, combinations thereof, and the like. Any suitable external connector, and any suitable process for forming the external connector, may be used in the external connector 217, and it is entirely contemplated that such external connectors are all included within the scope of the embodiments.

When ready, the semiconductor die 201 may be bonded to the interposer 211 using, for example, a bonding process. For example, a reflow process may be performed to bond the die connector 205 to the respective contact pads (not shown) on the upper surface of the substrate 213.

Once bonded, an underfill material (not shown) may be inserted or otherwise formed in the space between the interposer 211 and the semiconductor die 201. The underfill material may, for example, be dispensed between the semiconductor die 201 and the substrate 213 and then comprise a hardened liquid epoxy. In another embodiment, no underfill is used. Instead, the gap between the die 201 and the substrate 213 is filled with a molding material 203, described below.

Next, a molding material 203 is formed on the upper surface of the substrate 213. The molding material 203 surrounds the semiconductor die 201 in some embodiments. The molding material 203 may comprise, for example, an epoxy, an organic polymer, a silica-based or glass-filled or free glass polymer to be added, or other materials. In some embodiments, the molding material 203 comprises a liquid molding compound (LMC) that is a gel type liquid phase upon application. The molding material 203 may comprise a liquid material or a solid material at the time of application. Alternatively, the molding material 203 may comprise other insulating material and / or encapsulating material. The molding material 203 is applied using a wafer level molding process in some embodiments. The molding material 203 may be molded using, for example, compression molding, transfer molding, molded underfill (MUF), or other methods.

Next, the molding material 203 is cured using a curing process in some embodiments. The curing process may include heating the molding material 203 to a predetermined temperature for a predetermined time using, for example, an annealing process or other heating process. The curing process may include an ultraviolet (UV) exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination of these with a heating process. Alternatively, the molding material 203 may be cured using other methods. In some embodiments, it does not include a curing process. Next, a planarization process such as CMP may be performed to planarize the upper surface of the hardened molding material 203. [ Thus, the semiconductor package 250 is formed.

Next, as shown in FIG. 3A, the semiconductor package 250 is physically and electrically coupled to the substrate 105 through a bonding process (e.g., a reflow process). In the bonding process, the external connectors 217 of the semiconductor package 250 are aligned with the respective conductive pads 107 of the substrate 105. In some embodiments, the solder paste is dispensed onto the conductive pad 107 using, for example, a solder jet printing process. Next, the external connector 217 of the semiconductor package 250 is brought into contact with the respective conductive pads 107 of the substrate 105. A reflow process may then be performed to bond the external connector 217 of the semiconductor package 250 to each conductive pad 107 of the substrate 105. The reflow process can be performed at a temperature of about 220 캜 or higher.

After the reflow process, a solder region (not individually shown) may be formed between the conductive pad 107 and the conductive path 215. In embodiments where the external connector 217 includes a copper filler, a solder region may be formed between the copper filler and the conductive pad 107. In embodiments where the external connector 217 is a solder bump (e.g., a C4 bump), the solder of the external connector 217 melts during the reflow process to form a solder region &lt; RTI ID = 0.0 &gt; As shown in FIG.

Referring now to FIG. 3B, there is shown a view of zooming in on area 280 of FIG. 3A. The substrate 105 and the semiconductor package 250 can be bent at the reflow temperature, as shown in FIG. 3B and described below. For illustrative purposes, the bending level is exaggerated in Figure 3b. Mismatch of the CTEs between the different materials of the semiconductor package 250 may cause warpage of the semiconductor package 250 at reflow temperatures (e.g., above 220 캜). For example, the molding material 203 may have a higher CTE than the substrate 213. As a result, the lower surface 213L of the semiconductor package 250 is not flat but bent (e.g., curved). Specifically, the center of the lower surface 213L of the substrate 213 is higher (e.g., extends further away from the carrier 101) than both ends of the lower surface 213L. The curved lower surface 213L of the substrate 213 in Figure 3B is also described as being bent upwardly. 3B is an example only. In another embodiment, the CTE mismatch between the materials of the semiconductor package 250 may cause the lower surface 213L of the substrate 213 to bend downward, since the center of the lower surface 213L of the substrate 213 is lower (E.g., extends closer to the carrier 101) than the end of the surface 213L.

Similarly, mismatch between the CTE of the substrate 105 and the CTE of the carrier 101 may cause the substrate 105 to bend during the reflow process. The upper surface 105U of the substrate 105 may be bent upward or downward depending on the CTE of the substrate 105 and the CTE of the carrier 101. [ The external connector 217 is attached to the lower surface 213L of the substrate 213 so that the warp of the substrate 213 is prevented from being bent at the bottom of the external connector 217 (e.g., the lowermost portion of the external connector 217 in Fig. On the curved surface. If the upper surface 105U of the substrate 105 on which the conductive pad 107 is formed is flat or has a different shape and / or different curvature than the curved surface of the external connector 217, then simply in the reflow process It will be very difficult to bond the entire external connector 217 to the respective conductive pads 107 because some external connectors 217 do not contact the respective conductive pads 107. [ This may result in a cold joint between the external connector 217 and the conductive pad 107. Cold joints result in defective semiconductor devices and reduce the yield of semiconductor fabrication.

3B, the present disclosure provides, in some embodiments, a top surface 105U of a substrate 105 having a shape (e.g., bending upwards or downwards) and / or curvature (e.g., (E.g., the level of warpage) substantially coincides with the shape and / or curvature of the lower surface 213L of the semiconductor package 250 by directing a predetermined level of warpage to the substrate 105 during the reflow process prevent. The top surface 109U of the passivation layer 109 may have the same shape and / or curvature as the top surface 105U of the substrate 105, since the passivation layer 109 has a substantially uniform thickness. Likewise, the top surface of the conductive pad 107 is also in a curved surface that may have the same shape and / or curvature as the top surface 105U.

3B, the entire external connector 217 of the semiconductor package 250 is brought into contact with the semiconductor package 250 at the time of the reflow process (for example, the semiconductor package 250) by matching the warpage of the substrate 105 with the warpage of the semiconductor package 250. [ (E.g., electrical connection) between the semiconductor package 250 and the substrate 105 when the semiconductor package 250 and the substrate 105 are bent).

In some embodiments, the step of inducing a predetermined level of warpage in the substrate 105 includes analyzing the warpage of the semiconductor package 250 at reflow temperature, And adjusting the CTE of the carrier 101 such that a mismatch between the CTE of the carrier 101 and the CTE of the substrate 105 causes a deflection of the substrate 105 during the reflow process, The second shape of the curved upper surface 105U of the substrate 105 substantially coincides with the first shape of the curved lower surface 213L of the semiconductor package 250 during this reflow process.

In some embodiments, analyzing the warpage of the semiconductor package 250 includes estimating warpage of the semiconductor package 250 through computer simulation. For example, the dimensions, structure and materials of the semiconductor package 250, and the reflow temperature may be input as input parameters to a computer simulation program, and then specifics (e.g., Shape, curvature) is generated by a computer program.

In some embodiments, warpage of the semiconductor package 250 is obtained by measuring and analyzing moiré patterns using a defect inspector. Moire patterns can be generated using methods known in the art. For example, a reference pattern etched on the low-expansion quartz glass can be projected onto the curved surface of the semiconductor package 250. As seen from the quartz glass, the geometric inference between the reference pattern and the projected pattern on the curved surface of the semiconductor package 250 produces a moiré pattern. The deflection level can be measured using a defect tester such as KLA-Tencor's ICOS optical defect tester.

As a result of the analysis of the warping of the semiconductor package 250, details such as the shape and / or curvature of the lower surface 213L of the semiconductor package 250 are obtained. These details can be used as a target of induced deflection of the substrate 105 as described below.

In some embodiments, the step of inducing a predetermined level of warpage of the substrate 105 is performed such that a CTE mismatch between the substrate 105 and the carrier 101 at the reflow temperature is greater than the CTE mismatch between the curved lower surface of the semiconductor package 250 And adjusting the CTE of the carrier 101 with respect to the CTE of the substrate 105 so as to result in a curved upper surface 105U substantially coincident with the CTE of the substrate 105. [ For example, considering the case where the lower surface 213L is bent upward as shown in FIG. 3B (for example, because the CTE of the molding material 203 is larger than the CTE of the substrate 213) The CTE of the carrier 101 is aligned with the substrate 105 such that the CTE mismatch between the carriers 101 may cause the upper surface 105U of the substrate 105 to bend upwardly to coincide with the curved lower surface 213L. Lt; RTI ID = 0.0 &gt; CTE. &Lt; / RTI &gt; As another example, a case in which the lower surface 213L is bent downward may be considered. In this case, the CTE mismatch between the substrate 105 and the carrier 101 may cause the upper surface 105U of the substrate 105 to also be bent downward so that the carrier 105 can be aligned with the curved lower surface 213L, The CTE of the substrate 101 is adjusted to be larger than the CTE of the substrate 105. [

It will be appreciated by those skilled in the art that "substantial agreement" herein means agreement within the error margin. For example, the distance between the curved lower surface 213L and the curved upper surface 105U may vary from an expected value (e.g., a value equal to the sum of the height of the external connector 217 and the thickness of the passivation layer 109) And may have a value that deviates less than 20% (e.g., a larger or smaller value). For example, the thickness of the passivation layer 109 may be 20 占 퐉, the height of the external connector 217 may be 80 占 퐉, and the distance between the curved lower surface 213L and the curved upper surface 105U may be Value, for example, from about 10 percent to about 20 percent. All of the external connectors 217 of the semiconductor package 250 are electrically connected to the respective conductive pads 107 of the substrate 105 as a result of the curved upper surface 105U and the curved lower surface 213L coinciding during the reflow process. , And thus are physically and electronically coupled to each conductive pad 107. [

The CTE and structure of the carrier 101 are such that the flat upper surface 105U of the substrate 105 coincides with the flat lower surface 213L when the semiconductor package 250 has a flat lower surface 213L during the reflow process. In which case the carrier 101 ensures that there is little or no warpage with respect to the substrate 105 or that there is little or no warpage with respect to the top surface 105U of the substrate 105 To be guaranteed. Thus, in this specification, the step of inducing a predetermined level of warpage in the substrate 105 such that the warpage of the substrate 105 substantially coincides with the warpage of the substrate 213 may cause the substrate 105 and the substrate 213 to be flat In this case, the CTE of the carrier 101 is adjusted to maintain the flat surface 105U of the substrate 105 coincident with the flat lower surface 213L (e.g., Is equal to the CTE of the substrate 105). The CTE of the carrier 101 and the CTE of the substrate 105 can be set to the entirety of the carrier 101 (e.g., the CTE of the carrier 101), since the carrier 101 and the substrate 105 may each contain a plurality of materials (E.g., average) CTE and the total CTE of the substrate 105, respectively.

In some embodiments, adjusting the CTE of the carrier 101 may be accomplished by adjusting the CTE of the carrier 101 such that the upper surface 105U of the substrate 105 is substantially aligned with the lower surface 213L of the semiconductor package 250 during the reflow process Lt; RTI ID = 0.0 &gt; 101). &Lt; / RTI &gt; Factors such as the dimensions of the carrier 101, the dimensions of the substrate 105, the CTE and structure of the substrate 105, and the like can be used to determine the CTE of the carrier 101. [ Computer molding and simulation can be used to estimate the details of the warping of the substrate 105 with respect to a given CTE of the carrier 101. In addition, an experiment using different materials (and different CTEs) for the carrier 101 may be performed, and the moire pattern may be measured and analyzed by a defect checker. In some embodiments, computer moldings and simulations are used to determine the potential CTE values for the carrier 101 or the range of CTE values for the carrier 101. Experiments using different materials with different CTE values are then carried out and the CTE values of the carrier 101 are checked and / or fine tuned until the target details for the warping of the substrate 105 are achieved Moire pattern measurement and analysis is performed.

3A and 3B show a carrier 101 having a single layer structure. The carrier 101 may have a multi-segment structure and / or a multi-layer structure, as shown in Figs. The multi-segment structure and the multi-layer structure (see Figs. 18-21) can have increased flexibility in selecting the structure and materials used to construct the carrier 101, as compared to a carrier made of a single bulk material. Because there are more parameters in adjusting the design of the carrier 101, design flexibility is increased, so that the degree of freedom in designing the carrier 101 to meet the target detail of the induced warping of the substrate 105 at reflow temperatures Can be increased. For example, induced deflection in a substrate 105 having a complicated shape (e.g., an asymmetric curved upper surface 105U) may not be able to achieve a complex shape previously, but may use multiple segments and / or multi-layer structures &Lt; / RTI &gt;

Referring to Fig. 18, there is shown a sectional view of the carrier 101. Fig. The carrier 101 has a multi-segment structure including a first segment 101A, a second segment 101B, and a third segment 101C. The first segment 101A has a first width W1 and a first CTE value, the second segment 101B has a second width W2 and a second CTE value, and the third segment 101C has a first width W1 and a second CTE value. 3 &lt; / RTI &gt; width W3 and a third CTE value. In the illustrated embodiment, the first segment 101A, the second segment 101B, and the third segment 101C have the same height H.

The widths (e.g., W1, W2, and W3) and the CTE values (e.g., the first CTE value, the second CTE value, and the third CTE value) of different segments (e.g., 101A, 101B, and 101C) Allowing greater flexibility in the design of the carrier 101, since it can be selected independently. In some embodiments, the widths W1, W2, and W3 have different values. In some embodiments, the first CTE value, the second CTE value, and the third CTE value have different values. The first segment 101A and the third segment 101C have the same width and CTE value and the second segment 101B has the same width and the same CTE value as the first segment 101A (and the third segment 101C) Lt; RTI ID = 0.0 &gt; CTE &lt; / RTI &gt;

19 shows a cross-sectional view of a carrier 101 according to some embodiments. The carrier 101 has a multilayer structure including a first layer 101A, a second layer 101B, and a third layer 101C. The first layer 101A has a first height H1 and a first CTE value and the second layer 101B has a second height H2 and a second CTE value, 3 &lt; / RTI &gt; height (H3) and a third CTE value. In the illustrated embodiment, the first layer 101A, the second layer 101B, and the third layer 101C have the same width (W).

Continuing with Figure 19, the heights (e.g., H1, H2, and H3) and CTE values (e.g., the first CTE value, the second CTE value, and the second CTE value) of different layers (e.g., 101A, 101B, and 101C) Third CTE value) can be selected independently of each other, allowing greater flexibility in the design of the carrier 101. [ In some embodiments, the heights H1, H2, and H3 have different values. In some embodiments, the first CTE value, the second CTE value, and the third CTE value have different values. In another embodiment, the first CTE value of the first layer 101A is greater than the second CTE value of the second layer 101B, and the second CTE value of the second layer 101B is greater than the second CTE value of the third layer 101C. Is greater than the third CTE value.

The multi-segment structure of Fig. 18 and the multilayer structure of Fig. 19 may be combined to form the carrier 101, as shown in Figs. 20 and 21. Fig. 20, the carrier 101 is similar to the carrier 101 of Fig. 18, except that the intermediate segment 101B has a multilayer structure similar to that shown in Fig. In the example shown in Fig. 20, the layers 101B1, 101B2, and 101B3 have respective heights H1, H2, and H3 and a common width W2. The sum of the heights H1, H2, and H3 is equal to the height H of the other segments 101A and 101C in some embodiments. The dimensions (e.g., height, width) and CTE values of the different segments / layers of the carrier 101 may be adjusted independently of each other to achieve target detail for warping of the substrate 105 at the reflow temperature.

Fig. 21 shows another embodiment of the carrier 101. Fig. The carrier 101 in Fig. 21 is similar to the carrier 101 in Fig. 20, but the position (denoted by reference numeral 101C) of the multilayer segment is on the right side of the carrier 101. Fig. The other details are similar to those in Fig. 20 and thus will not be repeated.

18 to 21 are only non-limiting examples. Other variations and modifications are possible, and are entirely intended to be within the scope of this disclosure. For example, the number of segments in a multi-segment structure may be more or less than three. Likewise, the number of layers in the multilayer structure may be more or less than three. Further, in the embodiment where the multi-segment structure and the multi-layer structure are combined, the plurality of segments of the carrier 101 may have a multi-layer structure, and the position of the segment having the multi-layer structure may be any suitable segment of the carrier 101 It is possible.

Advantages of the present disclosure include reduced device failure rates and improved manufacturing yields. The external connector 217 of the semiconductor package 250 is brought into contact with the lower surface 213L of the semiconductor package 250 so that the warpage of the upper surface 105U of the substrate 105 at the reflow temperature coincides with the warpage of the lower surface 213L of the semiconductor package 250. [ Contacts each conductive pad 107 on the upper surface 105U to prevent or reduce cold joints. In a conventional method using a clamp that clamps the left and right sides of the semiconductor package 250 to reduce warpage of the semiconductor package 250 during the reflow process, the clamped portion of the semiconductor package 250 is subjected to high stress, And the middle portion of the unclamped semiconductor package 250 may remain deflected and may have a cold joint problem. The present disclosure, however, does not clamp the semiconductor package 250 and thus avoids the problems associated with clamping. Further, since the carrier 101 completely supports the lower surface of the substrate 105, it is possible to disperse the stress of the substrate 105 over a large area (for example, the lower surface of the substrate 105) To prevent or reduce damage to the device. The multi-layer structure and multi-segment structure of the carrier 101 allow a great deal of flexibility in selecting the structure and materials for the carrier 101. A complicated shape for the warping of the substrate 105 can be achieved, which could not have been possible using conventional carrier designs.

Referring now to FIG. 4, the carrier 101 is separated after the bonding process, e.g., after the semiconductor device 100 has cooled to room temperature. The carrier 101 can be removed by applying ultraviolet light (UV) or laser to the adhesive layer 103 (see Fig. 3A) through a carrier 101 that can be transparent to ultraviolet (UV) or laser, for example. In some embodiments, the adhesive layer 103 is separated by applying water to the adhesive layer. Other suitable methods such as mechanical stripping, etching, grinding, etc. may also be used. After the carrier 101 is separated, the residue of the adhesive layer 103, if any, can be separated by an additional cleaning process. Thus, the semiconductor device 100 shown in Fig. 4 forms the CoWoS package in some embodiments.

5-8 illustrate cross-sectional views of semiconductor device 100 at various fabrication stages according to yet another embodiment. Similar reference numerals used in Figs. 5-8 show similar components in Figs. 1-4. Fig. 5 to 8 are similar to the embodiment of Figs. 1 to 4 except that the substrate 105 is attached to the carrier 101 without the use of the adhesive layer 103. Fig. In an exemplary embodiment, the carrier 101 of Figs. 5-8 is an electro-static chuck. By supplying a voltage to the electrostatic chuck, the substrate 105 is attached to the electrostatic chuck by attraction of opposite electric charges. When the electric field is blocked (for example, by stopping the supply of the voltage to the electrostatic chuck), the substrate 105 can be easily separated from the carrier 101. Since there is no adhesive layer to be removed, the number of process steps and the processing time are reduced.

In Fig. 5, by supplying a voltage to the carrier 101, the substrate 105 is attached to the carrier 101 (electrostatic chuck). 6, the semiconductor package 250 is disposed on the substrate 105 with the external connector 217 aligned with the respective conductive pads 107 on the upper surface of the substrate 105. A solder paste (not shown) may be formed on the conductive pad 107. 7, the external connector 217 of the semiconductor package 250 is physically and electrically bonded to each conductive pad 107 during a bonding process (e.g., a reflow process). In some embodiments, in order to avoid or reduce the cold joint by bringing the external connector 217 into contact with the respective conductive pads 107 during the reflow process, the carrier 101 is pre- Level deflection. The details of the carrier 101 are similar to those described above with reference to Figs. 1 to 4 and 18 to 21, and thus will not be repeated. 8, the carrier 101 is separated from the substrate 105 by stopping the supply of the voltage to the carrier 101 after the bonding process.

9-13 illustrate cross-sectional views of a semiconductor device 100 at various fabrication stages according to yet another embodiment. The embodiment of Figures 9-13 is similar to the embodiment of Figures 1 to 4 except that the InFO package 350 is attached to the conductive pad 107 of the substrate 105 instead of the CoW package 250 similar. Similar reference numerals used in Figs. 9-13 show similar components in Figs. 1-4. Fig.

In Fig. 9, the substrate 105 is attached to the carrier 101. Fig. Details of the substrate 105 and the carrier 101 are similar to those described above with reference to FIG.

10 shows a cross-sectional view of the InFO package 350. FIG. As shown in Fig. 10, a rear dielectric layer 305 is formed on the carrier 301. The backside dielectric layer 305 can be a backside passivation layer and can include a polymer, polyimide, silicon oxide, silicon nitride, or other suitable material formed by PVC, CVD, or other suitable deposition methods. Carrier 301 may comprise a base material such as silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, beryllium oxide, tape, or other suitable material for structural support. An adhesive layer such as a light-to-heat conversion (LTHC) film may be formed between the rear dielectric layer 305 and the carrier 301.

The die 309 is attached to the backside dielectric layer 305, for example, via a DAF 307. Upon viewing the die 309, a contact pad 311 is formed on the upper surface of the die 309 and a passivation layer 315 is formed on the contact pad 311. The via 316 extends through the passivation layer 315 and is electrically connected to the contact pad 311. A conductive pad 318 is formed over the passivation layer 315 and is electrically connected to the via 316. Details regarding the formation of the die 309 may be similar to those for the die 201 of Fig. 2 and thus will not be repeated.

Vias 317 are formed over the back dielectric layer 305 and laterally spaced from the die 309. The via 317 may comprise a conductive material such as copper, tungsten, etc., to form a seed layer over the back dielectric layer 305, to form a patterned photoresist over the seed layer, to fill the openings of the patterned photoresist layer And removing the seed layer and the photoresist outside the boundary of the via 317. In this case, The via 317 may be formed before or after the die 309 is attached to the dielectric layer 305.

Next, a molding material 313 is formed on the rear dielectric layer 305. The molding material 313 encapsulates the die 309 and the via 317. The molding material 313 may be a molding compound, an epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. After curing, the molding material 313 may be subjected to a grinding process, such as a chemical mechanical planarization (CMP) process, to expose the conductive pads 318 of the die 309 and the upper surface of the vias 317.

 Next, a re-wiring structure 320 is formed on the molding material 313 and the die 309. The rewiring structure 320 may include one or more RDLs (e.g., a conductive line 321, a via 323) formed in one or more dielectric layers 325. Through vias 317 are electrically coupled to the RDL of the rewiring structure 320. The RDL of the rewiring structure 320 is also electrically coupled to the die 309. The RDL of the rewiring structure 320 may be formed of a metal such as aluminum, copper, tungsten, titanium, combinations thereof, or the like, and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plating, As shown in FIG. One or more dielectric layers 325 of the rewiring structure 320 may include a low k dielectric such as silicon oxide, silicon nitride, carbon doped oxide, an ultra low k dielectric such as porous carbon doped silicon dioxide, combinations thereof, and the like And may be formed through processes such as CVD, PVD or other suitable deposition methods.

Next, an under-bump metallurgy (UBM) structure 331 is formed on the upper surface of the re-wiring structure 320, as shown in FIG. The UBM structure 331 may be formed by depositing and patterning a conductive material, such as copper, gold, or aluminum, on the reordering structure 320. An electrical component 333, such as an integrated passive device (IPD), may be coupled to the UBM structure 331. [ An external connector 335 may be formed on the UBM structure 331, such as a ball grid array (BGA), a conductive filler (e.g., copper filler), or a conductive filler having a solder region thereon. Next, although not shown, the external connector 335 is attached to a tape such as a dicing tape in a state where the InFO package 350 of FIG. 10 is turned upside down. The carrier 301 is then separated from the IFO package 350 by a de-bonding process. In some embodiments, since a plurality of InFO packages (not shown) are formed on the carrier 101 together before the carrier 101 is separated, dicing is performed after the carrier 101 is removed, and a plurality of individual InFOs Package 350 may be generated.

 In Fig. 11, an InFO package 350 is disposed on the substrate 105. Fig. The external connectors 335 of the InFO package 350 are aligned with the respective conductive pads 107 of the substrate 105. For example, a solder paste (not shown) may be formed on the conductive pad 107 of the substrate 105 using a solder jet printing process.

12, a bonding process such as a reflow process is performed to physically and electrically connect the external connector 335 of the InFO package 350 to the conductive pad 107 of the substrate 105. [ In some embodiments, in order to avoid or reduce cold joints by contacting external connector 335 with respective conductive pads 107 during the reflow process, carrier 101 may be pre-determined on substrate 105 at reflow temperature Level deflection. In some embodiments, a first bend (e.g., a curved upper surface) of the substrate 105 due to a CTE mismatch between the carrier 101 and the substrate 105 causes a second bend in the InFO package 350, And the CTE of the carrier 101 is adjusted so as to be substantially coincident with the curved lower surface. The details of the carrier 101 are similar to those described above with reference to Figs. 1 to 4 and 18 to 21, and thus will not be repeated.

In Fig. 13, the carrier 101 is separated using processing steps similar to those described above with reference to Fig. Detailed description is not repeated.

14-17 illustrate cross-sectional views of semiconductor device 100 at various fabrication steps in accordance with yet another embodiment. Similar reference numerals used in Figs. 14-17 show similar components in Figs. 9-13. 14 to 17 are similar to the embodiments of Figs. 9 to 13 except that the substrate 105 is attached to the carrier 101 without the use of the adhesive layer 103. Fig. In the exemplary embodiment, the carrier 101 is an electrostatic chuck. By supplying a voltage to the electrostatic chuck, the substrate 105 is attached to the electrostatic chuck. When the electric field is blocked, the substrate 105 can be easily separated from the carrier 101. Since there is no adhesive layer to be removed, the number of processing steps and the processing time are reduced.

In Fig. 14, by supplying a voltage to the carrier 101, the substrate 105 is attached to the carrier 101 (electric chuck). 15, a semiconductor package 350 (e.g., an InFO package) is disposed on the substrate 105 with the external connector 335 aligned with the respective conductive pads 107 on the upper surface of the substrate 105 . A solder paste (not shown) may be formed on the conductive pad 107. 16, the external connector 335 of the semiconductor package 350 is physically and electrically bonded to each conductive pad 107 during a bonding process (e.g., a reflow process). In some embodiments, in order to avoid or reduce cold joints by contacting external connector 335 with respective conductive pads 107 during the reflow process, carrier 101 may be pre-determined on substrate 105 at reflow temperature Level deflection. The details of the carrier 101 are similar to those described above with reference to Figs. 1 to 4 and 18 to 21, and thus will not be repeated. In Fig. 17, the carrier 101 is separated from the substrate 105 by stopping the supply of the voltage to the carrier 101 after the reflow process.

 The embodiments of the present disclosure can achieve a number of effects. For example, with a suitable design of the carrier 101, a predetermined warp to match the deflection of the semiconductor device (e.g., reference numeral 250 in FIG. 3A and reference numeral 350 in FIG. 12) during the reflow process is applied to the substrate 105 . Cold joints are avoided and production efficiency increases. The present disclosure avoids damage to the semiconductor package due to non-uniformly distributed stresses, since it does not require a clamp to clamp the semiconductor device. Further, the flexibility of the design of the carrier 101 is increased by the multilayer structure of the carrier 101 and the multi-segment structure. A complex shape for the warpage of the substrate 105, which was not possible before, can be achieved.

22 shows a flowchart of a method of manufacturing a semiconductor device according to some embodiments. It should be understood that the method embodiment shown in FIG. 22 is only one of many possible method embodiments. Numerous variations, alternatives, and modifications will occur to those skilled in the art. For example, the various steps shown in FIG. 22 may be added, removed, replaced, rearranged, and repeated.

Referring to Fig. 22, in step 1010, a substrate is attached to a carrier. In step 1020, the external connector of the first semiconductor package is aligned with the first conductive pad on the first surface of the substrate facing away from the carrier. In step 1030, a reflow process is performed, a first mismatch in the coefficient of thermal expansion (CTE) between the substrate and the carrier causes a first warp of the substrate during the reflow process, and a second mismatch of CTEs between the materials of the first semiconductor package Causing a second deflection of the first semiconductor package during the reflow process, wherein the first deflection substantially coincides with the second deflection. In step 1040, the carrier is separated from the substrate after the reflow process.

In one embodiment, a method includes attaching a substrate to a carrier, aligning an external connector on a first surface of the first semiconductor package with a first conductive pad on a first surface of the substrate facing away from the carrier And performing a reflow process, wherein a difference in the coefficient of thermal expansion (CTE) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, Wherein the first shape is substantially coincident with the second shape, wherein a difference in thermal expansion coefficient between the first semiconductor package and the second semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, And separating the carrier from the substrate after the reflow process. The method further includes separating the carrier from the substrate after the reflow process. In one embodiment, attaching the substrate to the carrier includes attaching the substrate to the carrier using an adhesive layer. In one embodiment, the carrier is an electrostatic chuck, and the step of attaching the substrate to the carrier comprises applying a voltage to the electrostatic chuck. In one embodiment, the substrate is a printed circuit board (PCB). In one embodiment, the first shape and the second shape are curved shapes. In one embodiment, the reflow process physically and electrically couples the first semiconductor package to the substrate. In one embodiment, the method further comprises aligning an external connector of a second semiconductor package to a second conductive pad on a first surface of the substrate prior to performing the reflow process, The row process physically and electrically couples the first semiconductor package and the second semiconductor package to the substrate. In one embodiment, the substrate has a rectangular, square, polygonal or circular shape.

In one embodiment, a method includes adjusting a coefficient of thermal expansion (CTE) of a carrier, attaching a first side of the substrate to the carrier, the substrate having a second side of the substrate opposite the first side The method comprising the steps of: attaching a semiconductor package on a second side of the substrate, wherein the external connector on the first side of the semiconductor package, facing the substrate, Wherein each of the conductive pads is aligned with a respective conductive pad; and heating the substrate, the carrier, and the semiconductor package, wherein the first surface of the semiconductor package is in contact with a first curve Wherein the CTE of the carrier is adjusted relative to the CTE of the substrate such that the second side of the substrate has a second curved shape during the heating step, Song shape corresponds substantially to the second curved shape. In an embodiment, the method further comprises separating the carrier from the substrate after heating the substrate, the carrier, and the semiconductor package. In one embodiment, the external connector of the semiconductor package contacts each conductive pad of the substrate during the heating step. In one embodiment, the method further comprises analyzing the warpage of the semiconductor package at a heating temperature and determining a first curvature shape of the first surface of the semiconductor package at the heating temperature . In one embodiment, the substrate is a printed circuit board. In one embodiment, the semiconductor package includes a semiconductor die, a molding material around the semiconductor die, a conductive feature electrically coupled to the semiconductor die, the conductive feature extending beyond a boundary of the semiconductor die, Wherein the conductive feature is between the semiconductor die and the external connector. In one embodiment, the conductive feature is a redistribution layer (RDL) of a rewiring structure between the semiconductor die and the external connector. In one embodiment, the conductive feature is a via of the interposer between the semiconductor die and the external connector.

In one embodiment, a method includes attaching a first side of a substrate to a carrier, bonding a semiconductor package to a second side of the substrate opposite the first side, Wherein a first side of the package has a first curved shape at a bonding temperature and a difference in thermal expansion coefficient (CTE) between the carrier and the substrate causes a second curved shape for the second side of the substrate at the bonding temperature, The first curved shape coincides with the second curved shape. In one embodiment, bonding the semiconductor package comprises bonding an external connector of the semiconductor package to a contact pad disposed on a second side of the substrate, Contacting each conductive pad of the substrate during the step. In an embodiment, the method further comprises analyzing the warping of the semiconductor package at the bonding temperature. In one embodiment, the analyzing step comprises measuring and analyzing a moiré pattern of the semiconductor package.

The foregoing is a summary of features of the various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same effects of the embodiments presented herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the disclosure.

<Bookkeeping>

One. In the method,

Attaching the substrate to a carrier,

Aligning an external connector on a first surface of a first semiconductor package with a first conductive pad on a first surface of the substrate facing away from the carrier;

Performing a reflow process, wherein a difference in the coefficient of thermal expansion (CTE) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, Wherein a difference in CTE between the first surface and the second surface causes a second shape for the first surface of the first semiconductor package during the reflow process and wherein the first shape substantially coincides with the second shape, Performing,

And separating the carrier from the substrate after the reflow process.

2. 2. The method of claim 1, wherein attaching the substrate to the carrier comprises attaching the substrate to the carrier using an adhesive layer.

3. 2. The method of claim 1, wherein the carrier is an electro-static chuck, and wherein attaching the substrate to a carrier comprises applying a voltage to the electrostatic chuck.

4. The method of claim 1, wherein the substrate is a printed circuit board (PCB).

5. 5. The method of claim 4, wherein the first shape and the second shape are curved.

6. 2. The method of claim 1, wherein performing the reflow process comprises physically and electrically coupling the first semiconductor package to the substrate.

7. 2. The method of claim 1, further comprising aligning an external connector of a second semiconductor package to a second conductive pad on a first surface of the substrate prior to performing the reflow process, And physically and electrically coupling the first semiconductor package and the second semiconductor package to the substrate.

8. The method of claim 1, wherein the substrate has a rectangular, square, polygonal, or circular shape.

9. In the method,

Adjusting a coefficient of thermal expansion (CTE) of the carrier,

Attaching a first side of a substrate to the carrier, wherein the substrate has a conductive pad on a second side of the substrate opposite the first side;

Placing a semiconductor package on a second side of the substrate such that an external connector on a first side of the semiconductor package facing the substrate is aligned with a respective conductive pad of the substrate; ,

Wherein the first surface of the semiconductor package has a first curved shape during the heating step and the CTE of the carrier is greater than the second surface of the substrate Wherein the first curved shape is adjusted to the CTE of the substrate to have a second curved shape during the heating step, the first curved shape being substantially coincident with the second curved shape.

10. 10. The method of claim 9, further comprising separating the carrier from the substrate after heating the substrate, the carrier, and the semiconductor package.

11. 10. The method of claim 9, wherein the external connector of the semiconductor package contacts each conductive pad of the substrate during the heating step.

12. 10. The method of claim 9,

Analyzing the warpage of the semiconductor package at a heating temperature,

Further comprising determining a first curvature shape of the first surface of the semiconductor package at the heating temperature.

13. 10. The method of claim 9, wherein the substrate is a printed circuit board.

14. 10. The semiconductor package according to claim 9,

A semiconductor die,

A molding material around the semiconductor die,

A conductive feature that is electrically coupled to the semiconductor die and extends beyond a boundary of the semiconductor die,

And an external connector electrically coupled to the conductive feature, wherein the conductive feature is between the semiconductor die and the external connector.

15. 15. The method of claim 14, wherein the conductive feature is a redistribution layer (RDL) of a rewiring structure between the semiconductor die and the external connector.

16. 15. The method of claim 14, wherein the conductive feature is a via of an interposer between the semiconductor die and the external connector.

17. In the method,

Attaching a first side of the substrate to the carrier,

Bonding a semiconductor package to a second side of the substrate opposite the first side at a bonding temperature, the first side of the semiconductor package facing the substrate having a first curved shape at the bonding temperature Wherein a difference in the coefficient of thermal expansion (CTE) between the carrier and the substrate causes a second curved shape with respect to the second surface of the substrate at the bonding temperature, the first curved shape conforming to the second curved shape / RTI &gt;

18. 18. The method of claim 17, wherein bonding the semiconductor package comprises bonding an external connector of the semiconductor package to a contact pad disposed on a second side of the substrate, And contacting each conductive pad of the substrate during the step.

19. 18. The method of claim 17, further comprising analyzing warpage of the semiconductor package at the bonding temperature.

20. 20. The method of claim 19, wherein analyzing comprises measuring and analyzing a moiré pattern of the semiconductor package.

Claims (10)

In the method,
Attaching the substrate to a carrier,
Aligning an external connector on a first surface of a first semiconductor package with a first conductive pad on a first surface of the substrate facing away from the carrier;
Performing a reflow process, wherein a difference in the coefficient of thermal expansion (CTE) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, Wherein a difference in CTE between the first surface and the second surface of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, Wow,
Separating the carrier from the substrate after the reflow process
&Lt; / RTI &gt; 2. The method of claim 1, wherein attaching the substrate to the carrier comprises attaching the substrate to the carrier using an adhesive layer. 2. The method of claim 1, wherein the carrier is an electro-static chuck, and wherein attaching the substrate to a carrier comprises applying a voltage to the electrostatic chuck. 2. The method of claim 1, wherein performing the reflow process comprises physically and electrically coupling the first semiconductor package to the substrate. 2. The method of claim 1, further comprising aligning an external connector of a second semiconductor package to a second conductive pad on a first surface of the substrate prior to performing the reflow process, And physically and electrically coupling the first semiconductor package and the second semiconductor package to the substrate. In the method,
Adjusting a coefficient of thermal expansion (CTE) of the carrier,
Attaching a first side of a substrate to the carrier, wherein the substrate has a conductive pad on a second side of the substrate opposite the first side;
Placing a semiconductor package on a second side of the substrate such that an external connector on a first side of the semiconductor package facing the substrate is aligned with a respective conductive pad of the substrate; ,
Heating the substrate, the carrier, and the semiconductor package
Wherein the first side of the semiconductor package has a first curved shape during the heating step and the CTE of the carrier is less than the CTE of the substrate so that the second side of the substrate has a second curved shape during the heating step And the first curved shape coincides with the second curved shape. 7. The method of claim 6 further comprising separating the carrier from the substrate after heating the substrate, the carrier, and the semiconductor package. 7. The method of claim 6, wherein the external connector of the semiconductor package contacts each conductive pad of the substrate during the heating step. The method according to claim 6,
Analyzing the warpage of the semiconductor package at a heating temperature,
Determining a first curved shape of the first surface of the semiconductor package at the heating temperature
&Lt; / RTI &gt; In the method,
Attaching a first side of the substrate to the carrier,
Bonding the semiconductor package to a second side of the substrate opposite the first side at a bonding temperature
Wherein a first surface of the semiconductor package facing the substrate has a first curved shape at the bonding temperature and a difference in thermal expansion coefficient (CTE) between the carrier and the substrate is greater than a difference Wherein the first curved shape coincides with the second curved shape.

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