KR20180110503A - Memory device having voltage generating circuit - Google Patents

Abstract

The present technique relates to a memory device. The memory device includes a memory block which includes a channel film formed in a vertical direction between junction regions included in a well, a source select line, word lines, and drain select lines surrounding the channel film, separated from each other and sequentially stacked; a first voltage source for generating voltages applied to source lines connected to the junction regions; and a second voltage source for generating voltages applied to the well. In the erase operation of the memory block, a first erase voltage generated in the first voltage source is applied to the source line. A second erase voltage generated in the second voltage source is applied to the well. The reliability of the memory device can be improved.

Description

[0001] The present invention relates to a memory device having a voltage generating circuit,

The present invention relates to a memory device including a voltage generating circuit, and more particularly to a voltage generating circuit including a plurality of voltage sources and a memory device including the same.

The memory device may be formed in a two-dimensional structure in which the strings are arranged horizontally on the semiconductor substrate, or a three-dimensional structure in which the strings are stacked on the semiconductor substrate in a vertical direction. A memory device having a three-dimensional structure may include a plurality of memory cells stacked vertically on a semiconductor substrate as a memory device designed to overcome the limitations of integration of a memory device having a two-dimensional structure.

Embodiments of the present invention provide a memory device comprising a voltage generation circuit capable of improving reliability of a memory device.

A memory device according to an embodiment of the present invention includes a channel film formed in a vertical direction between junction regions included in a well and source select lines, word lines, and source lines surrounding the channel film and sequentially stacked, A memory block including drain select lines; A first voltage source for generating voltages applied to source lines connected to the junction regions; And a second voltage source for generating voltages applied to the well, wherein during a erase operation of the memory block, a first erase voltage generated at the first voltage source is applied to the source line, and a second erase voltage generated at the second voltage source And a second erase voltage applied to the well is applied to the well.

A memory device according to an embodiment of the present invention includes: a memory block formed on a well and including strings connected between a source line and bit lines; And peripheral circuits configured to apply a first erase voltage to the source line and a second erase voltage to the well, respectively, in an erase operation of memory cells included in the strings.

This technique can improve the reliability of the erase operation of the memory device.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.
2 is a diagram for explaining the memory device of FIG.
FIG. 3 is a diagram for explaining the memory block of FIG. 2. FIG.
4 is a cross-sectional view for explaining the structure of the string of FIG.
5 is a view for explaining voltage sources according to an embodiment of the present invention.
FIGS. 6 to 8 are views for explaining an erase operation according to the configuration of a well and a memory block.
9 to 11 are diagrams for explaining embodiments of the erase operation of the present invention.
12 is a diagram for explaining another embodiment of the memory system including the memory device shown in Fig.
FIG. 13 is a diagram for explaining another embodiment of the memory system including the memory device shown in FIG. 2. FIG.
14 is a diagram for explaining another embodiment of a memory system including the memory device shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.

1, a memory system 1000 includes a memory device 1100 for storing data, a memory controller 1100 for controlling the memory device 1100 under the control of a host 2000, A memory controller 1200, and the like.

The host 2000 may be connected to the memory 2000 using an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA) And can communicate with the system 1000. In addition, the interface protocols between the host 2000 and the memory system 1000 are not limited to the above-described examples. For example, USB (Universal Serial Bus), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI) Drive Electronics) and the like.

The memory controller 1200 controls the overall operation of the memory system 1000 and can control the exchange of data between the host 2000 and the memory device 1100. For example, the memory controller 1200 may control the memory device 1100 in response to a request from the host 2000 to program or read data. In addition, the memory controller 1200 stores information on main memory blocks and sub memory blocks included in the memory device 1100, and performs program operation on a main memory block or a sub memory block according to the amount of data loaded for the program operation The memory device 1100 may be selected to perform.

The memory device 1100 may perform a program, read, or erase operation under the control of the memory controller 1200. [

2 is a diagram for explaining the memory device of FIG.

Referring to FIG. 2, the memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 includes a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data, (Not shown). Memory device 1100 may include control logic 300 that controls peripheral circuits 200 under the control of a memory controller (1200 of FIG. 1).

The memory cell array 100 may include a plurality of memory blocks MB1 to MBk (k is a positive integer). Local lines LL and bit lines BL1 to BLm (where m is a positive integer) may be connected to each of the memory blocks MB1 to MBk. For example, the local lines LL may include a first select line, a second select line, a plurality of word lines arranged between the first and second select lines lines. Here, the first select line may be a source select line and the second select line may be a drain select line. In addition, the local lines LL may include dummy lines arranged between the first select line and the word lines, and between the second select line and the word lines. For example, local lines LL may include word lines, drain and source select lines, and source lines. For example, the local lines LL may further include dummy lines. In addition, the local lines LL may include at least one or more source lines.

A part of the local lines LL may be connected to the memory blocks MB1 to MBk respectively or may be connected in common to the plurality of memory blocks MB1 to MBk. The bit lines BL1 to BLm may be commonly connected to the memory blocks MB1 to MBk. The memory blocks MB1 to MBk may be implemented in a three-dimensional structure. For example, in memory blocks of a three-dimensional structure, pages may be arranged vertically from the substrate. Here, a page refers to a group of memory cells connected to the same word line.

Peripheral circuits 200 may be configured to perform program, read, and erase operations of the selected memory block under the control of control logic 300. [ For example, the peripheral circuits 200 supply the verify voltage and the pass voltages to the first select line, the second select line and the word lines under the control of the control logic 300, Select lines and word lines, and verify memory cells connected to a selected one of the word lines. For example, the peripheral circuits 200 may include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, An input / output circuit 250, and a sensing circuit 260. The input /

The voltage generation circuit 210 may include a plurality of voltage sources for generating various operating voltages Vop each used for program, read and erase operations in response to an operation code OP_CD . The voltage sources can generate voltages independently of each other. In addition, the voltage generation circuit 210 may selectively float the local lines LL or selectively apply various levels of voltages to the local lines LL in response to the opcode OP_CD . For example, the voltage generating circuit 210 may control the program voltages, verify voltages, pass voltages, select line voltages, read voltages, erase voltages, source line voltages, Ground voltage and various levels of voltages.

For example, in the erase operation, the voltage generating circuit 210 may apply a ground voltage or a positive voltage to the word lines. The voltage generating circuit 210 may selectively apply select line voltages or a ground voltage to the first and second select lines, or may flock the first and second select lines. The voltage generating circuit 210 can apply the first erase voltage to the source line and apply the second erase voltage to the well. Here, the first and second erase voltages are higher than the ground voltage (e.g., 0V) and may be set to the same level or set to different levels.

The row decoder 220 may transmit the operating voltages Vop to the local lines LL connected to the selected memory block in response to the row address RADD.

The page buffer group 230 may include a plurality of page buffers PB1 to PBm connected to the bit lines BL1 to BLm. The page buffers PB1 to PBm may operate in response to the page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBm temporarily store the data received via the bit lines BL1 to BLm, or the voltage or current of the bit lines BL1 to BLm during the read or verify operation Can be sensed.

The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 may exchange data with the page buffers PB via the data lines DL, or may exchange data with the input / output circuit 250 through the column lines CL .

The input / output circuit 250 transfers the command CMD and the address ADD received from the memory controller 1200 (FIG. 1) to the control logic 300 or the data DATA to / from the column decoder 240 have.

The sensing circuit 260 generates a reference current in response to a permission bit VRY_BIT <#> at the time of a read operation or a verify operation and outputs a sensing voltage VPB) and the reference voltage generated by the reference current to output the pass signal PASS or the fail signal FAIL.

The control logic 300 outputs an operation code OP_CD, a row address RADD, page buffer control signals PBSIGNALS and a permission bit VRY_BIT <# > in response to the command CMD and the address ADD The peripheral circuits 200 can be controlled. In addition, the control logic 300 may determine whether the verify operation has passed or failed in response to the pass or fail signal (PASS or FAIL).

FIG. 3 is a diagram for explaining the memory block of FIG. 2. FIG.

Referring to FIG. 3, the memory cell array 100 may include a plurality of memory blocks MB1 to MBk. 3, the internal structure of the first memory block MB1 is shown and the internal structure of the remaining memory blocks MB2 to MBk is omitted for the sake of understanding. The second to k-th memory blocks MB1 to MBk may be configured similarly to the first memory block MB1.

The first memory block MB1 may include a plurality of strings ST11 'to ST1m', ST21 'to ST2m'. Each of the plurality of strings ST11 'to ST1m', ST21 'to ST2m' may extend along the vertical direction (Z direction). Within the first memory block MB1, m strings in the row direction (X direction) may be arranged. In FIG. 3, two strings are shown to be arranged in the column direction (Y direction), but this is for convenience of description, and three or more strings may be arranged in the column direction (Y direction).

Each of the plurality of strings ST11 'to ST1m' and ST21 'to ST2m' includes at least one source select transistor (SST), first to nth memory cells MC1 to MCn, and at least one drain select transistor (DST).

The source select transistor SST of each string may be connected between the source line SL and the memory cells MC1 to MCn. Source select transistors of strings arranged in the same row may be connected to the same source select line. The source select transistors of the strings ST11 'to ST1m' arranged in the first row may be connected to the first source select line SSL1. The source select transistors of the strings ST21 'to ST2m' arranged in the second row may be connected to the second source select line SSL2. As another embodiment, the source select transistors of the strings ST11 'to ST1m', ST21 'to ST2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each string may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to n-th memory cells MC1 to MCn may be connected to the first to the n-th word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n &lt; th &gt; memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the string can be stably controlled. Accordingly, reliability of data stored in the memory block MB1 can be improved.

The drain select transistor DST of each string can be connected between the bit line and the memory cells MC1 to MCn. The drain select transistors DST of the strings arranged in the row direction may be connected to a drain select line extending in the row direction. The drain select transistors DST of the strings CS11 'to CS1m' of the first row may be connected to the first drain select line DSL1. The drain select transistors DST of the strings CS21 'to CS2m' of the second row may be connected to the second drain select line DSL2.

4 is a cross-sectional view for explaining the structure of the string of FIG.

Referring to FIG. 4, pillars 44 and 46 may be formed on a substrate on which a well (WE) is formed. The well WE can be formed by doping an impurity into a substrate. Junctions 42 may be formed in the well WE. The junction regions 42 may be formed by doping impurities of different types from the well WE. The pillars 44 and 46 may be formed on the well WE between the junction regions 42. [ The pillars 44 and 46 may include an inner insulating film 44 and a channel film 46. The inner insulating film 44 may be formed of a cylindrical insulating material. The channel film 46 may be formed of a cylindrical polysilicon film surrounding the inner insulating film 44. The source select lines SSL1, the word lines WL1 to WLn and the drain select lines DSL1 may be formed around the pillars 44 and 46 while being spaced apart from each other. Source select transistors may be formed between the source select lines SSL1 and the channel film 46. [ The memory cells may be formed between the word lines (WL1 to WLn) and the channel film (46). Drain select transistors may be formed between the drain select lines DSL1 and the channel film 46. [ A capping layer 48 may be formed on the upper portions of the pillars 44 and 46. The capping film 48 may be formed of a polysilicon film in a cylindrical shape. The capping film 48 may be connected to the bit line BL.

The source lines SL may be connected to the junction regions 42, and the first erase voltage Vera1 may be applied during the erase operation. In the erase operation, the second erase voltage Vera2 may be applied to the well WE. For example, the first erase voltage Vera1 and the second erase voltage Vera2 may be generated from different voltage sources. The first erase voltage Vera1 and the second erase voltage Vera2 may be generated at the same level or may be generated at different levels.

5 is a view for explaining voltage sources according to an embodiment of the present invention.

Referring to FIG. 5, the voltage generation circuit 210 may include a plurality of voltage sources for selectively generating voltages having various levels. The voltage sources can operate independently of each other. For example, the voltage generation circuit 210 may include a drain select line voltage source DSL_VG, a word line voltage source WL_VG, a source select line voltage source SSL_VG, a source line voltage source SL_VG, and a well voltage source WE_VG. have. The voltages generated by the voltage generation circuit 210 during the erase operation will be described in detail as follows.

The drain select line voltage source DSL_VG generates drain select line voltages Vdsl to be applied to the drain select lines DSL1 of FIG. 4, applies a ground voltage (0V) to the drain select lines DSL1, The drain select lines DSL1 can be floated.

The word line voltage source WL_VG can generate the word line voltages Vwl to be applied to the word lines WL1 to WLn in FIG. 4 or the ground voltage 0V to the word lines WL1 to WLn have.

The source select line voltage source SSL_VG generates source select line voltages Vssl to be applied to the source select lines (SSL1 in FIG. 4), applies a ground voltage (0 V) to the source select lines SSL1, The source select lines SSL1 can be floated.

The source line voltage source SL_VG may generate the first erase voltage Vera1 to be applied to the source line (SL in Fig. 4).

The well voltage source WE_VG may generate the second erase voltage Vera2 to be applied to the well (WE in Fig. 4).

FIGS. 6 to 8 are views for explaining an erase operation according to the configuration of a well and a memory block.

6 shows an embodiment of a memory device in which one memory block is formed in one well.

Referring to FIG. 6, the first memory block MB1 may be formed in the first well WE1, and the second memory block MB2 may be formed in the second well WE2. In this manner, the kth memory block MBk may be formed in the kth well WEk. The first to k-th wells WE1 to WEk are electrically isolated from each other.

In the erase operation of the memory device, an erase voltage may be applied to the source line and the well, respectively. The first erase voltage Vera1 is applied to the source line of the second memory block MB2 and the second erase voltage Vera2 is applied to the second well WE2 when the second memory block MB2 is a block to be erased, Respectively. Here, the first erase voltage Vera1 may be set to the same level as the second erase voltage Vera2 or may be set to another level.

4 and 6, the first erase voltage Vera1 is applied to the source line SL and the second erase voltage Vera2 is applied to the well WE during the erase operation . For example, the first erase voltage Vera1 and the second erase voltage Vera2 can be simultaneously applied to the source line SL and the well WE. For example, after the first erase voltage Vera1 is applied to the source line SL, the second erase voltage Vera2 may be applied to the well WE. However, the second erase voltage Vera2 is not applied to the well WE in a state where the ground voltage is applied to the source line SL. As described above, when the erase voltage is applied to the source line SL and the well WE, the erase operation time can be shortened because the erase voltage is quickly forcibly injected into the erase voltage channel. In addition, since the erase voltages applied to the source line SL and the well WE are generated from different voltage sources (SL_VG and WE_VG in Fig. 5), the erase voltage can be easily adjusted depending on the memory device. Further, since the time for which the erase voltages are applied can be individually adjusted, the erase operation can be easily controlled.

7 shows an embodiment of a memory device in which a plurality of wells (WE1 to WEa; a is a positive integer) are included in a memory device, and a plurality of memory blocks are formed in each well.

Referring to FIG. 7, as another embodiment, two memory blocks may be included in one well. For example, the first and second memory blocks MB1 and MB2 may be formed in the first well WE1. In this manner, the k-th and k-th memory blocks MBk-1 and MBk may be formed in the a-th well WEa. The first to the a-th wells WE1 to WEa may be formed to be electrically isolated from each other.

In the erase operation of the memory device, an erase voltage may be applied to the source line and the well, respectively. The first erase voltage Vera1 is applied to the source line of the second memory block MB2 and the second erase voltage Vera2 is applied to the first well WE2 when the second memory block MB2 is the erase target block, Respectively. Here, the first erase voltage Vera1 may be set to the same level as the second erase voltage Vera2 or may be set to another level. An erase prevention voltage is applied to the source line connected to the first memory block MB1 so that the memory cells of the first memory block MB1 sharing the first well WE1 with the second memory block MB2 are not erased . For example, a ground voltage may be applied to the source line connected to the non-selected first memory block MB1 as an erase prevention voltage. In addition, erase prevention voltages may be applied to non-selected wells including only unselected memory blocks, or wirings connected to non-selected wells may be floating.

7 is a view for explaining an embodiment of the present invention, the number of memory blocks included in one well may be different depending on the memory device.

8 shows an embodiment of a memory device in which one well WE is included in the memory device and all the memory blocks are formed in the well WE.

8, since all the memory blocks MB1 to MBk share one well WE, a first erase voltage is applied to the source line connected to the selected memory block, and the first erase voltage is connected to the remaining unselected memory blocks An erase preventing voltage may be applied to the source lines. The first erase voltage Vera1 is applied only to the source line of the second memory block MB2 and the second erase voltage Vera2 is applied to the well WE when the second memory block MB2 is a block to be erased. . At this time, the erase-preventing voltage may be applied to the source lines connected to the remaining non-selected memory blocks MB1, MB3 to MBk, or may be floating.

9 to 11 are diagrams for explaining embodiments of the erase operation of the present invention.

9 is a view for explaining an embodiment of erase voltages applied to the source line SL and the well WE in the erase operation of the memory device.

Referring to FIG. 9, a first erase voltage Vera1 may be applied to the source line SL, and a second erase voltage Vera2 may be applied to the well WE. For example, the first and second erasing voltages Vera1 and Vera2 may be applied to the source line SL and the well WE at the eleventh time point T11, respectively. The first and second erasing voltages Vera1 and Vera2 can reach the target level at the twelfth time point T12. An erase operation of the memory cells may be performed during the 12th time point T12 to the 13th time point T13. At the thirteenth time point T13, the wirings connected to the source line SL and the well WE can be discharged. Since the first and second erase voltages Vera1 and Vera2 can be generated from different voltage sources (SL_VG and WE_VG in Fig. 5), the first erase voltage Vera1 is equal to the second erase voltage Vera2 Or may be set to a high or low level.

10 is a view for explaining another embodiment of erase voltages applied to the source line SL and the well WE in the erase operation of the memory device.

Referring to FIG. 10, the first erase voltage Vera1 may be applied to the source line SL and the second erase voltage Vera2 may be applied to the well WE. For example, at the twenty-first time point T21, the first erasing voltage Vera1 may be applied to the source line SL. At this time, the well WE may be in a floating state, and the potential of the well WE may be increased 10a by the first source voltage Vera1 applied to the source line SL. Subsequently, at the 22nd time point T22, the second erase voltage Vera2 may be applied to the well WE (10b). At the 23rd time point T23, the first and second erasing voltages Vera1 and Vera2 can both be raised to the target level. The erase operation may be performed during the 22nd to 24th time points (T22 to T24). At the 24th time point T24, the wirings connected to the source line SL and the well WE can be discharged. Since the first and second erase voltages Vera1 and Vera2 can be generated from different voltage sources (SL_VG and WE_VG in Fig. 5), the first erase voltage Vera1 is equal to the second erase voltage Vera2 Or may be set to a high or low level.

11 is a view for explaining another embodiment of erase voltages applied to the source line SL and the well WE in the erase operation of the memory device.

Referring to FIG. 11, the first erase voltage Vera1 may be applied to the source line SL and the second erase voltage Vera2 may be applied to the well WE. For example, the first and second erasing voltages Vera1 and Vera2 may be applied to the source line SL and the well WE at the 31st time point T31, respectively. Or the first erase voltage Vera1 may be applied to the source line SL before the second erase voltage Vera2 is applied to the well WE, as described in Fig.

A ground voltage (for example, 0 V) or a word line voltage Vwl is applied to the word lines WL from the 31st time point T31 so that electrons trapped in the memory cells can be de-trapped . For example, the word line voltage Vwl may be set to a level higher than the ground voltage (0V) and lower than the first and second erase voltages Vera1 and Vera2. A ground voltage (0 V) may be applied to the source select line (SSL) until the 31st time point (T31).

When the level of the first or second erase voltage Vera1 or Vera2 becomes high, the source select line voltage Vssl may be applied to the source select line SSL. For example, the source select line voltage Vssl may be applied to the source select line SSL between the 31st to 32nd time points T31 to T32. The source select line voltage Vssl may be set between the ground voltage 0V and the first or second erase voltage Vera1 or Vera2 or may be set equal to the first or second erase voltage Vera1 or Vera2 .

The source select line SSL can be floating when both the first and second erase voltages Vera1 and Vera2 and the source select line voltage Vss1 reach the target level (T32).

At the 33rd time point T33, the source select line SSL, the source line SL and the well WE can be discharged. When the word line voltage Vw1 is applied to the word lines WL, the word lines WL can also be discharged at the 33rd time point T33.

12 is a diagram for explaining another embodiment of the memory system including the memory device shown in Fig.

12, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device . The memory system 30000 can include a memory device 1100 and a memory controller 1200 that can control the operation of the memory device 1100. The memory controller 1200 may control the data access operation of the memory device 1100 such as a program operation, an erase operation or a read operation under the control of the processor 3100. [

The data programmed into the memory device 1100 may be output through a display (Display) 3200 under the control of the memory controller 1200.

The radio transceiver 3300 can transmit and receive radio signals through the antenna ANT. For example, the wireless transceiver 3300 may change the wireless signal received via the antenna ANT to a signal that can be processed by the processor 3100. Thus, the processor 3100 can process the signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 1200 or display 3200. The memory controller 1200 may program the signal processed by the processor 3100 to the semiconductor memory device 1100. [ In addition, the wireless transceiver 3300 may convert the signal output from the processor 3100 into a wireless signal, and output the modified wireless signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100 and includes a touch pad, A pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 is connected to the display 3200 so that data output from the memory controller 1200, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output via the display 3200. [ Can be controlled.

According to an embodiment, a memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 3100 and may also be implemented as a separate chip from the processor 3100.

FIG. 13 is a diagram for explaining another embodiment of the memory system including the memory device shown in FIG. 2. FIG.

13, the memory system 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant ), A portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations of the memory device 1100.

A processor 4100 may output data stored in the memory device 1100 through a display 4300 according to data input through an input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. [ The memory controller 1200 capable of controlling the operation of the memory device 1100 according to an embodiment may be implemented as part of the processor 4100 or in a separate chip from the processor 4100. [

14 is a diagram for explaining another embodiment of a memory system including the memory device shown in Fig.

14, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

The memory controller 1200 can control the exchange of data between the semiconductor memory device 1100 and the card interface 7100. [ According to an embodiment, the card interface 7100 may be an SD (secure digital) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 7100 can interface data exchange between the host 60000 and the memory controller 1200 according to the protocol of the host (HOST) 60000. According to the embodiment, the card interface 7100 can support USB (Universal Serial Bus) protocol and IC (InterChip) -USB protocol. Here, the card interface may mean hardware that can support the protocol used by the host 60000, software installed on the hardware, or a signal transmission method.

When the memory system 70000 is connected to the host interface 6200 of the host 60000 such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set- The interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of a microprocessor 6100.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

1000: memory system 1100: memory device
1200: memory controller 100: memory cell array
200: peripheral circuits 300: control logic

Claims (18)

A memory block including a channel film formed in a vertical direction between junction regions included in a well, a source select line surrounding the channel film and sequentially stacked, word lines, and drain select lines;
A first voltage source for generating voltages applied to source lines connected to the junction regions; And
And a second voltage source for generating voltages applied to the well,
Wherein a first erase voltage generated in the first voltage source is applied to the source line and a second erase voltage generated in the second voltage source is applied to the well in the erase operation of the memory block.
The method according to claim 1,
Wherein the first voltage source and the second voltage source operate independently of each other.
The power supply according to claim 1,
The first erase voltage is simultaneously output when the second erase voltage is output from the second voltage source,
And outputs the first erase voltage before the second erase voltage is output from the second voltage source.
The method according to claim 1,
And voltage sources for generating voltages applied to the source select line, the word lines, and the drain select lines, respectively.
5. The method of claim 4,
Wherein the voltage sources operate independently of each other.
5. The method of claim 4,
When the first and second erase voltages are applied to the source line and the well, respectively,
And a voltage source connected to the source select line among the voltage sources generates a source select line voltage and applies the source select line voltage to the source select line.
The method according to claim 6,
The voltage source connected to the source select line,
And applies the source select line voltage to the source select line after the first or second erase voltage is applied.
8. The method of claim 7,
The voltage source connected to the source select line,
And after the source select line voltage is applied to the source select line, floating the source select line.
5. The method of claim 4,
When the first and second erase voltages are applied to the source line and the well, respectively,
Wherein voltage sources coupled to the word lines of the voltage sources apply a word line voltage or a ground voltage to the word lines.
A memory block formed on the well and including strings connected between the source line and the bit lines; And
And peripheral circuits configured to apply a first erase voltage to the source line and a second erase voltage to the well, respectively, in an erase operation of memory cells included in the strings.
11. The method of claim 10,
Wherein the source line is connected to junction regions formed by doping different types of impurities with the well in the well.
The voltage generation circuit according to claim 10,
A source line voltage source for generating the first erase voltage; And
And a well voltage source for generating the second erase voltage.
13. The method of claim 12,
Wherein the source line voltage source and the well voltage source are configured to operate independently of each other.
13. The method of claim 12, wherein the source line voltage source comprises:
The first erase voltage is simultaneously output when the second erase voltage is output from the well voltage source,
And outputs the first erase voltage before the second erase voltage is output from the well voltage source.
The voltage generation circuit according to claim 10,
A word line voltage source for supplying a voltage to the word lines connected to the strings;
A source select line voltage source for supplying a voltage to a source select line connected to the strings; And
And a drain select line voltage source for supplying a voltage to a drain select line coupled to the strings.
16. The method of claim 15, wherein the source select line voltage source comprises:
When the first and second erase voltages are applied to the source line and the well,
And applies a source select line voltage to the source select line.
17. The method of claim 16, wherein the source select line voltage source comprises:
And wherein the source select line is floating when the source select line voltage rises to a target level.
16. The method of claim 15, wherein the word line voltage source comprises:
When the first and second erase voltages are applied to the source line and the well,
And applies a word line voltage or a ground voltage to the word lines.

Images