KR20180101698A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor element including a field effect transistor having improved degree of integration and a manufacturing method thereof. More specifically, the semiconductor element comprises: a substrate including a PMOSFET region and a NMOSFET region; first active patterns in the PMOSFET region; second active patterns in the NMOSFET region; gate electrodes crossing the first and second active patterns and extending in a first direction; and first wires disposed on the gate electrodes and extending in the first direction. The gate electrodes are arranged in a second direction crossing the first direction according to a first pitch (P1). The first wires are arranged in the second direction according to a second pitch (P2). The second pitch (P2) is smaller than the first pitch (P1).

Description

Technical Field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, and a hybrid semiconductor element including a memory element and a logic element. As the electronics industry develops, there is a growing demand for properties of semiconductor devices. For example, there is an increasing demand for high reliability, high speed and / or multifunctionality for semiconductor devices. In order to meet these requirements, structures in semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more and more highly integrated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device including a field effect transistor having an improved integration degree.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device including a field effect transistor having an improved integration degree.

According to a concept of the present invention, a semiconductor device includes: a substrate including a PMOSFET region and an NMOSFET region; First active patterns on the PMOSFET region; Second active patterns on the NMOSFET region; Gate electrodes extending in a first direction across the first and second active patterns; And first wirings disposed on the gate electrodes and extending in the first direction. The gate electrodes are arranged in a second direction crossing the first direction according to a first pitch P1 and the first wirings are arranged in the second direction in accordance with a second pitch P2, The pitch P2 may be smaller than the first pitch P1.

According to another aspect of the present invention, a semiconductor device may include a first logic cell and a second logic cell on a substrate. Wherein the first logic cell and the second logic cell comprise the same logic circuit, each of the first and second logic cells comprising: a gate electrode extending in the first direction across the PMOSFET region and the NMOSFET region; ; And an internal wiring disposed on the gate electrode and extending in the first direction. Wherein the internal wiring is a wiring constituting the logic circuit and a distance offset of the internal wiring of the first logic cell from the gate electrode of the first logic cell is determined by the distance between the internal wiring of the second logic cell The distance offset from the gate electrode of the logic cell.

According to still another aspect of the present invention, a method of manufacturing a semiconductor device includes: designing a layout of a semiconductor device; And forming the patterns on the substrate using the layout. Designing the layout may include: placing standard cells; Rearranging the internal wiring patterns in at least one of the standard cells to the wiring pattern tracks; And routing the routing patterns to the wiring pattern tracks to route the standard cells.

In the semiconductor device according to the present invention, the minimum pitch between the wirings may be smaller than the minimum pitch between the gate electrodes. As a result, the pattern density of the wirings in the logic cell can be increased to improve the integration and electrical characteristics of the semiconductor device.

1 is a block diagram illustrating a computer system for performing semiconductor design according to embodiments of the present invention.
2 is a flowchart showing a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.
3 is a flow chart illustrating placement and routing of standard cells according to embodiments of the present invention to more specifically illustrate the layout design steps of FIG.
4 to 6 are layouts according to an embodiment of the present invention for explaining the placement and routing of the standard cells of FIG.
7 is a layout in the case where the rearrangement step according to the embodiments of the present invention is omitted.
8A is an exemplary circuit diagram of a standard cell according to embodiments of the present invention.
Fig. 8B is a standard cell layout corresponding to the circuit diagram of Fig. 8A.
Figs. 9-11 are layouts according to an embodiment of the present invention to illustrate the placement and routing of the standard cells of Fig.
12 and 13 are enlarged plan views of the internal wiring patterns of FIGS. 9 and 10 and the first wiring patterns connected thereto, respectively.
14 is a plan view illustrating a semiconductor device according to embodiments of the present invention.
15A to 15F are cross-sectional views taken along line A-A ', line B-B', line C-C ', line D-D', line E-E 'and line F-F', respectively.
16, 17 and 19 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
Figs. 17A, 19A and 21A are cross-sectional views corresponding to the line A-A 'in Figs. 16, 17 and 19, respectively.
Figs. 17B, 19B and 21B are cross-sectional views corresponding to lines B-B 'in Figs. 16, 17 and 19, respectively.
Figs. 19C and 21C are cross-sectional views corresponding to line C-C 'in Figs. 18 and 19, respectively.
Figs. 19D and 21D are cross-sectional views corresponding to the line D-D 'in Figs. 18 and 19, respectively.
22 is a plan view for explaining a semiconductor device according to embodiments of the present invention.
23 is a cross-sectional view taken along the line A-A 'in Fig.

1 is a block diagram illustrating a computer system for performing semiconductor design according to embodiments of the present invention. 1, a computer system may include a CPU 10, a working memory 30, an input / output device 50, and an auxiliary memory device 70. [ Here, the computer system may be provided as a dedicated apparatus for the layout design of the present invention. Further, the computer system may include various design and verification simulation programs.

The CPU 10 may execute software (application programs, operating systems, device drivers) to be executed in the computer system. The CPU 10 may execute an operating system loaded into the working memory 30. The CPU 10 can execute various application programs to be driven based on the operating system. For example, the CPU 10 may execute the layout design tool 32, placement, reordering and routing tool 34, and / or the OPC tool 36 loaded into the working memory 30.

The operating system or the application programs may be loaded into the working memory 30. The operating system image (not shown) stored in the auxiliary memory device 70 at the time of booting of the computer system can be loaded into the working memory 30 based on the boot sequence. All of the input / output operations of the computer system can be supported by the operating system. Likewise, the application programs may be loaded into the working memory 30 for user selection or for basic service provisioning.

The layout design tool 32 for layout design can be loaded into the working memory 30 from the auxiliary memory device 70. [ A rearrangement and routing tool 34 for routing the designed standard cells, rearranging the internal wiring patterns in the placed standard cells, and routing the arranged standard cells, is provided from the auxiliary memory 70 to the working memory 30 Can be loaded. An OPC tool 36 for performing optical proximity correction (OPC) on the designed layout data can be loaded from the auxiliary memory device 70 into the working memory 30.

The layout design tool 32 may have a bias function capable of changing the shape and position of specific layout patterns to those defined by the design rule. The layout design tool 32 may perform a design rule check (DRC) under the changed bias data condition. The working memory 30 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory such as a PRAM, an MRAM, a ReRAM, a FRAM, and a NOR flash memory.

The input / output device 50 controls user input and output from the user interface devices. For example, the input / output device 50 may include a keyboard or a monitor to receive information from a designer. By using the input / output device 50, the designer can receive information on the semiconductor region or the data paths requiring the adjusted operating characteristics. The processing and processing results of the OPC tool 36 can be displayed through the input / output device 50.

The auxiliary storage device 70 is provided as a storage medium of a computer system. The auxiliary storage device 70 may store an application program, an operating system image, and various data. The auxiliary storage device 70 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The auxiliary storage device 70 may include a NAND-type Flash memory having a large storage capacity. Alternatively, the auxiliary memory device 70 may include a next-generation non-volatile memory such as PRAM, MRAM, ReRAM, and FRAM, or a NOR flash memory.

The system interconnect 90 may be a system bus for providing a network within a computer system. The CPU 10, the working memory 30, the input / output device 50, and the auxiliary memory device 70 are electrically connected through the system interconnect 90 and exchange data with each other. However, the configuration of the system interconnect 90 is not limited to the above description, and may further include arbitration means for efficient management.

2 is a flowchart showing a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 2, a high level design of a semiconductor integrated circuit can be performed using the computer system described with reference to FIG. 1 (S10). Higher-level design can refer to describing the integrated circuit being designed as a higher-level language of the computer language. For example, you can use an upper language like C language. Circuits designed by higher level design can be more specifically expressed by register transfer level (RTL) coding or simulation. Further, the code generated by the register transfer level coding can be converted into a netlist and synthesized into an entire semiconductor device. The synthesized schematic circuit is verified by the simulation tool and the adjustment process can be accompanied by the verification result.

A layout design for realizing a logic completed semiconductor contact circuit on a silicon substrate can be performed (S20). For example, a layout design can be performed by referring to a schematic circuit synthesized in a high-level design or a corresponding netlist. The layout design may include a routing procedure for placing and connecting various standard cells provided in a cell library according to prescribed design rules.

The cell library for layout design can also include information on the operation, speed, and power consumption of the standard cell. A cell library for expressing a circuit of a specific gate level in layout is defined in most layout design tools. The layout may be a procedure that actually defines the shape and size of the pattern to form the transistors and metal lines to be formed on the silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, layout patterns such as PMOS, NMOS, N-WELL, gate electrodes, and metal wirings to be disposed thereon can be appropriately arranged. For this purpose, it is possible to search for and select an appropriate one of the inverters already defined in the cell library.

Routing for selected and deployed standard cells may be performed. Specifically, upper wires (routing patterns) may be disposed on standard cells arranged. By routing, standard cells placed can be connected to each other according to the design. The placement and routing of standard cells can be performed automatically by the placement, reordering and routing tool 34. [

After routing, verification of the layout can be performed to determine whether there are any contradictory parts of the design rule. The items to be verified include DRC (Design Rule Check) for verifying that the layout is correct according to the design rules, ERC (Electronical Rule Check) for verifying that the layout has been properly electrically disconnected, and whether the layout matches the gate- LVS (Layout vs Schematic) to confirm the image.

An Optical Proximity Correction (OPC) procedure may be performed (S30). By using a photolithography process, layout patterns obtained through layout design can be implemented on a silicon substrate. At this time, the optical proximity correction may be a technique for correcting a distortion phenomenon that may occur in the photolithography process. That is, through the optical proximity correction, a distortion phenomenon such as a refraction or a process effect caused by the characteristics of light at the time of exposure using the laid-out pattern can be corrected. The shape and position of the designed layout patterns can be slightly changed (biased) while performing optical proximity correction.

A photomask can be produced based on the layout changed by the optical proximity correction (S40). In general, the photomask can be manufactured in such a manner that the layout patterns are depicted using a chromium film applied on a glass substrate.

A semiconductor device can be manufactured using the generated photomask (S50). In the manufacturing process of a semiconductor device using a photomask, various types of exposure and etching processes can be repeated. Through these processes, the shapes of the patterns configured in the layout design on the silicon substrate can be sequentially formed.

3 is a flow chart illustrating placement and routing of standard cells according to embodiments of the present invention to more specifically illustrate layout design step S20 of FIG. 4 to 6 are layouts according to an embodiment of the present invention for explaining the placement and routing of the standard cells of FIG.

Referring to FIGS. 3 and 4, a first standard cell STD1 and a second standard cell STD2 may be arranged (S110). The first standard cell STD1 and the second standard cell STD2 may be arranged side by side in the second direction D2. The first standard cell STD1 and the second standard cell STD2 may be different standard cells. The logic circuit constituted by the first standard cell STD1 may be different from the logic circuit constituted by the second standard cell STD2.

The first and second standard cells STD1 and STD2 may include gate patterns GEa, first wiring patterns M1a, internal wiring patterns M2a_I and via patterns V2a. Furthermore, the first and second standard cells STD1 and STD2 may further include other layout patterns (e.g., active patterns, active contact patterns, gate contact patterns, etc.). (E.g., active patterns, active contact patterns, gate contact patterns, etc.) in the first and second standard cells STD1 and STD2 shown in Figs. 4 to 6 for the sake of simplicity, Is omitted.

The gate patterns GEa extend in a first direction D1 and may be arranged along a second direction D2 that intersects (e.g., crosses) the first direction D1. The gate patterns GEa may define gate electrodes. The gate patterns GEa may be aligned with the gate pattern tracks GPT. The gate pattern tracks GPT may be arbitrarily set lines used to place the gate patterns GEa in the standard cell. The center line of each of the gate patterns GEa may be overlapped with each of the gate pattern tracks GPT. The distance between the adjacent pair of gate pattern tracks GPT may be the first distance L1. In other words, the minimum distance between the gate pattern tracks GPT may be the first distance L1. The gate pattern tracks GPT may be arranged along the second direction D2 at a constant interval L1. The minimum pitch between the gate patterns GEa may be the first pitch P1, which may be equal to the first distance L1. The term "pitch" or "minimum pitch" used in the present invention may be the sum of the distance between adjacent pair of patterns and the width of one pattern.

The first wiring patterns M1a may be located at a higher level than the gate patterns GEa. The first wiring patterns M1a may define a first metal layer (first wirings). The first wiring patterns M1a may extend along the second direction D2.

The internal wiring patterns M2a_I may be located at a higher level than the first wiring patterns M1a. The internal wiring patterns M2a_I can define a second metal layer (second wirings). The internal wiring patterns M2a_I may extend along the first direction D1. The internal wiring patterns M2a_I may be parallel to the gate patterns GEa.

The via patterns V2a may be disposed in areas where the first wiring patterns M1a and the internal wiring patterns M2a_I overlap. The via patterns V2a are used for vertically connecting first wirings (for example, first wiring patterns M1a) and second wirings (for example, internal wiring patterns M2a_I) Vias can be defined. In one example, the via patterns V2a may be formed as a second metal layer together with the inner wiring patterns M2a_I.

The internal wiring patterns M2a_I arranged in the first and second standard cells STD1 and STD2 of FIG. 4 can define the wirings constituting the logic circuits of the first and second standard cells STD1 and STD2 have. For example, the internal wiring patterns M2a_I may define wirings that function as output nodes or input nodes of the logic circuits of the first and second standard cells STD1 and STD2.

The internal wiring patterns M2a_I may be aligned with the first wiring pattern tracks MPT1. The first wiring pattern tracks MPT1 may be arbitrarily set lines used for arranging the internal wiring patterns M2a_I in the standard cell. The center line of each of the internal wiring patterns M2a_I may overlap with each of the first wiring pattern tracks MPT1. The distance between the adjacent pair of first wiring pattern tracks MPT1 may be the second distance L2. In other words, the minimum distance between the internal wiring patterns M2a_I may be the second distance L2. The second distance L2 may be substantially the same as the first distance L1 described above. The minimum pitch between the internal wiring patterns M2a_I may be the first pitch P1 equal to the minimum pitch between the gate patterns GEa. The interval between the internal wiring patterns M2a_I may be nxP1 (n is an integer of 1 or more). For example, the interval between the first inner wiring pattern M2a_I and the second inner wiring pattern M2a_I of the first standard cell STD1 may be 1 x P1. The interval between the second internal wiring pattern M2a_I of the first standard cell STD1 and the internal wiring pattern M2a_I of the second standard cell STD2 may be 3 x P1.

The first and second standard cells STD1 and STD2 may be arranged according to a first pitch P1 which is a gate pitch. The smaller the first pitch P1 that is the gate pitch, the higher the degree of integration of the semiconductor element. The minimum value of the first pitch P1 may be determined according to the degree of miniaturization of the manufacturing process of the semiconductor device

Referring to FIGS. 3 and 5, at least one internal wiring pattern M2a_I in at least one of the first and second standard cells STD1 and STD2 may be rearranged (S120). After the first and second standard cells STD1 and STD2 are disposed, new second wiring pattern tracks MPT2 may be set instead of the first wiring pattern tracks MPT1 that have been set. The second wiring pattern tracks MPT2 may be arbitrarily set lines used for arranging the routing patterns M2a_O to be placed in the subsequent routing step S130 (see Fig. 6). The distance between a pair of adjacent second wiring pattern tracks MPT2 may be a third distance L3. The third distance L3 may be smaller than the second distance L2 (or the first distance L1).

The internal wiring patterns M2a_I in the first and second standard cells STD1 and STD2 can be rearranged in accordance with the second wiring pattern tracks MPT2. Each of the internal wiring patterns M2a_I may be rearranged in accordance with the second wiring pattern track MPT2 closest thereto. The center line of each of the inner wiring patterns M2a_I may overlap with each of the second wiring pattern tracks MPT2.

During the reordering step, the internal wiring patterns M2a_I can horizontally move in a direction parallel to the second direction D2. As the internal wiring patterns M2a_I are rearranged, the distance and the direction in which they are moved may be equal to or different from each other. For example, the first internal wiring pattern M2a_I in the first standard cell STD1 can move by the fourth distance L4 in the direction opposite to the second direction D2, The second internal wiring pattern M2a_I can move by a fifth distance L5 larger than the fourth distance L4 in the second direction D2. The interval between the rearranged internal wiring patterns M2a_I may be different from the interval (nxP1) between the internal wiring patterns M2a_I before rearrangement.

The via patterns V2a may be rearranged to the second wiring pattern track MPT2 together with the internal wiring patterns M2a_I. In other words, the via pattern V2a can be moved together with the corresponding internal wiring pattern M2a_I.

Referring to FIGS. 3 and 6, a step of routing standard cells may be performed (S130). Routing the standard cells may include placing routing patterns M2a_O. Through the arrangement of the routing patterns M2a_O, the standard cells can be connected to each other according to the designed circuit.

The routing patterns M2a_O may belong to the same level as the internal wiring patterns M2a_I. The routing patterns M2a_O may form the second wiring patterns M2a together with the internal wiring patterns M2a_I. The second wiring patterns M2a may define a second metal layer. The routing patterns M2a_O may be aligned with the second wiring pattern tracks MPT2. The center line of each of the routing patterns M2a_O may be overlapped with each of the second wiring pattern tracks MPT2. Although not shown, routing patterns located at a higher level than the second wiring patterns M2a in the routing step S130 may be arranged.

The minimum pitch between the second wiring patterns M2a may be a second pitch P2 equal to the third distance L3. The second pitch P2 may be smaller than the first pitch P1. The interval between the second wiring patterns M2a may be n x P2 (n is an integer of 1 or more).

Upon completion of placement and routing of the standard cells according to Fig. 3, optical proximity correction is performed on the designed layout, and a photomask can be fabricated. A semiconductor process is performed using the produced photomask, so that a semiconductor device can be manufactured (see FIG. 1).

The method of arranging and routing the standard cells according to the embodiments of the present invention is a step of rearranging the internal wiring patterns M2a_I according to the arrangement interval of the routing patterns M2a_O (i.e., the second pitch P2) . If the reordering step is omitted, the routing patterns M2a_O may not be disposed in the vicinity of the internal wiring patterns M2a_I.

7 is a layout in the case where the rearrangement step according to the embodiments of the present invention is omitted. 7, when the rearrangement step of the internal wiring patterns M2a_I described above with reference to FIG. 5 is omitted, the arrangement of the internal wiring patterns M2a_I of FIG. 7 corresponds to the internal wiring patterns M2a_I ). ≪ / RTI > The routing pattern M2a_O arranged in FIG. 6 may not be arranged between the pair of inner wiring patterns M2a_I in the first standard cell STD1 of FIG. When the routing pattern M2a_O is arranged between the pair of inner wiring patterns M2a_I, the distance between these patterns is too close to ensure a process margin. The routing pattern M2a_O arranged in FIG. 6 may not be arranged on one side of the internal wiring pattern M2a_I in the second standard cell STD2 of FIG. When the routing pattern M2a_O is arranged on one side of the internal wiring pattern M2a_I, the distance between these patterns is too close to ensure a process margin.

It can be confirmed that the number of routing patterns M2a_O arranged in FIG. 6 is larger than the number of routing patterns M2a_O arranged in FIG. As a result, the pattern density of the second wiring patterns M2a in the standard cell can increase because the method of arranging and routing standard cells according to the embodiments of the present invention includes the above-described reordering.

Hereinafter, embodiments of the present invention will be described in more detail based on the above description. 8A is an exemplary circuit diagram of a standard cell STD according to embodiments of the present invention. Fig. 8B is a standard cell (STD) layout corresponding to the circuit diagram of Fig. 8A. Figs. 9-11 are layouts according to an embodiment of the present invention to illustrate the placement and routing of the standard cells of Fig. 12 and 13 are enlarged plan views of the internal wiring patterns of FIGS. 9 and 10 and the first wiring patterns connected thereto, respectively. In the present embodiment, detailed description of technical features overlapping with those described above with reference to Figs. 3 to 6 will be omitted, and differences will be described in detail.

Referring to FIG. 8A, the standard cell STD of the present embodiment may be a NAND 2 standard cell. The standard cell STD of the present embodiment may include first through fourth transistors TR1 through TR4. The first and second transistors TR1 and TR2 may be PMOS transistors. The third and fourth transistors TR3 and TR4 may be NMOS transistors.

The first transistor TR1 may be connected between the node to which the power supply voltage VDD is supplied and the output node O. [ The first input (I1) may be transmitted to the gate of the first transistor (TR1). The second transistor TR2 may be connected between the node to which the power supply voltage VDD is supplied and the output node O. [ A second input (I2) may be delivered to the gate of the second transistor (TR2). The first and second transistors TR1 and TR2 may be connected in parallel between the node to which the power supply voltage VDD is supplied and the output node O. [

The third transistor TR3 may be coupled between the output node O and the fourth transistor TR4. And the second input (I2) may be transmitted to the gate of the third transistor (TR3). The fourth transistor TR4 may be connected between the node to which the ground voltage VSS is supplied and the third transistor TR3. The first input I1 may be transmitted to the gate of the fourth transistor TR4. The third and fourth transistors TR3 and TR4 may be connected in series between the node to which the ground voltage VSS is supplied and the output node O. [

8A and 8B, the standard cell STD of the present embodiment includes the gate patterns GEa, the first wiring patterns M1a, the internal wiring pattern M2a_I, and the via patterns V2a . For the sake of simplicity, other layout patterns (e.g., active patterns, active contact patterns, gate contact patterns, etc.) in the standard cell STD shown in FIG. 8B have been omitted. The gate patterns GEa may be aligned with the gate pattern tracks GPT. The minimum pitch between the gate patterns GEa may be the first pitch P1.

Some of the first wiring patterns M1a may define first wirings for supplying the power supply voltage VDD and the ground voltage VSS. The internal wiring pattern M2a_I can define wirings constituting the NAND circuit. Specifically, the internal wiring pattern M2a_I may correspond to the output node O of the NAND circuit. The via patterns V2a may provide a vertical connection between the first wiring patterns M1a and the internal wiring pattern M2a_I.

The internal wiring pattern M2a_I can be aligned with the first wiring pattern tracks MPT1. The interval between the first wiring pattern tracks MPT1 may be the first pitch P1 equal to the interval between the gate pattern tracks GPT.

Referring to FIGS. 3, 9 and 12, a plurality of NAND 2 standard cells STD described with reference to FIGS. 8A and 8B may be provided and arranged along a second direction D2 (S110). Specifically, the first to third standard cells STD1, STD2, and STD3 may be disposed along the second direction D2. The first to third standard cells STD1, STD2, and STD3 may be the same NAND 2 standard cell STD of FIG. 8B. The third standard cell STD3 may be mirror symmetrically arranged with respect to the first and second standard cells STD1 and STD2. The first to third standard cells STD1, STD2 and STD3 may be arranged according to the gate pitch. The gate pitch may be a first pitch P1 as shown in Fig. 8B.

12, in each of the first to third standard cells STD1, STD2 and STD3, the first wiring pattern M1a connected to the internal wiring pattern M2a_I has one end EN . One end EN may be adjacent to one side of the internal wiring pattern M2a_I. The distance between one end of the one end EN and the inner wiring pattern M2a_I may be the sum of the first margin D and the second margin OV. The first margin D may be half of the second pitch P2 which is the minimum pitch between the second wiring patterns M2a to be described later (D = P2 / 2). The second margin (OV) may be the minimum margin determined to prevent process failure. The minimum margin may be a value that can prevent a contact failure from occurring due to distortion of the pattern when the pattern is implemented in the process. The minimum margin may be defined by a design rule.

Referring to FIGS. 3, 10 and 13, the internal wiring patterns M2a_I in the first to third standard cells STD1, STD2, and STD3 may be rearranged (S120). After the first to third standard cells STD1, STD2, and STD3 are disposed, new second wiring pattern tracks MPT2 may be set instead of the first wiring pattern tracks MPT1 shown in FIG. 8B. The distance L3 between the adjacent pair of second wiring pattern tracks MPT2 may be smaller than the distance L2 between the adjacent pair of first wiring pattern tracks MPT1. The internal wiring patterns M2a_I in the first to third standard cells STD1, STD2 and STD3 can be rearranged in accordance with the second wiring pattern tracks MPT2. The via patterns V2a may be rearranged to the second wiring pattern track MPT2 together with the internal wiring patterns M2a_I.

During the reordering step, the internal wiring patterns M2a_I can horizontally move in a direction parallel to the second direction D2. As the internal wiring patterns M2a_I are rearranged, the distance and the direction in which they are moved may be equal to or different from each other. The maximum travel distance at which the internal wiring patterns M2a_I can move may be half of the third distance L3 (L3 / 2). In other words, the maximum movement distance at which the internal wiring patterns M2a_I can move can be half of the second pitch P2 (P2 / 2). For example, the internal wiring pattern M2a_I of the second standard cell STD2 is located at the center of the pair of second wiring pattern tracks MPT2, and the internal wiring pattern M2a_I is located at the maximum moving distance And can be rearranged according to any one of the second wiring pattern tracks MPT2.

Referring again to FIG. 13, for example, the internal wiring pattern M2a_I in the second standard cell STD2 can be moved by the sixth distance L6 in the second direction D2. The sixth distance L6 may be substantially the same as or similar to the maximum travel distance. The sixth distance L6 may be about half of the second pitch P2. Since the first wiring pattern M1a of FIG. 12 has not only the second margin OV but also the first margin D, the internal wiring patterns M2a_I are rearranged to form one end of the first wiring pattern M1a At least the second margin (OV) can be secured. Therefore, it is possible to prevent a process failure from occurring due to the rearrangement of the internal wiring patterns M2a_I.

3 and 11, a step of routing standard cells is performed, and routing patterns M2a_O may be placed in the first to third standard cells STD1, STD2, and STD3 (S130). The routing patterns M2a_O may be aligned with the second wiring pattern tracks MPT2. The arranged routing patterns M2a_O can form the second wiring patterns M2a together with the internal wiring patterns M2a_I. The minimum pitch between the second wiring patterns M2a may be a second pitch P2 equal to the third distance L3. The second pitch P2 may be smaller than the first pitch P1 which is the gate pitch. The interval between the second wiring patterns M2a may be n x P2 (n is an integer of 1 or more).

14 is a plan view illustrating a semiconductor device according to embodiments of the present invention. 15A to 15F are cross-sectional views taken along line A-A ', line B-B', line C-C ', line D-D', line E-E 'and line F-F', respectively. The semiconductor device shown in Figs. 14 and 15A to 15F is an example of a semiconductor device implemented on an actual substrate using the designed layout of Fig.

Referring to Figs. 14 and 15A to 15F, first to third logic cells LC1, LC2, LC3 may be provided. The first to third logic cells LC1, LC2, LC3 may be arranged in the second direction D2. Each of the first to third logic cells LC1, LC2, LC3 may constitute a logic circuit. In one example, logic transistors constituting a logic circuit may be arranged on each of the first to third logic cells LC1, LC2, LC3.

In this embodiment, the first to third logic cells LC1, LC2, LC3 may include the same logic circuit. For example, the first to third logic cells LC1, LC2, LC3 may be the same NAND 2 cell. The first and second logic cells LC1, LC2 may have the same transistor structure and internal wiring structure. The third logic cell LC3 can achieve a mirror symmetry with the transistor structure and the internal nonlinear structure of each of the first and second logic cells LC1, LC2. Hereinafter, the logic transistors and wirings constituting the first to third logic cells LC1, LC2, LC3 will be described in more detail.

A substrate 100 may be provided. As an example, the substrate 100 may be a silicon substrate, a germanium substrate, or a SOI (Silicon On Insulator) substrate. The substrate 100 may be provided with second element isolation films ST2 that define the PMOSFET region PR and the NMOSFET region NR. The second device isolation films ST2 may be formed on the substrate 100. [

The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1 with the second element isolation film ST2 therebetween. The PMOSFET region PR and the NMOSFET region NR may extend across the first to third logic cells LC1, LC2, LC3 while extending in the second direction D2. Although not shown, additional PMOSFET regions and additional NMOSFET regions may be defined by the second isolation layers ST2 as well as the PMOSFET region PR and the NMOSFET region NR.

A plurality of first active patterns FN1 extending in the second direction D2 may be provided on the PMOSFET region PR. A plurality of second active patterns FN2 extending in the second direction D2 may be provided on the NMOSFET region NR. The first and second active patterns FN1 and FN2 may be portions protruding from the upper surface of the substrate 100 as a part of the substrate 100. [ The first and second active patterns FN1 and FN2 may be arranged along the first direction D1.

In one example, two first active patterns FN1 may extend along the second direction D2 on the PMOSFET region PR. As an example, three second active patterns FN2 may extend along the second direction D2 on the NMOSFET region NR. However, the number and shape of the first active patterns FN1 on the PMOSFET region PR and the number and shape of the second active patterns FN2 on the NMOSFET region NR are exemplary and are not limited to the illustrated form Do not.

The first device isolation films ST1 extending in the second direction D2 may be disposed on both sides of each of the first and second active patterns FN1 and FN2. The first device isolation layers ST1 may fill the trenches between the first active patterns FN1. The first device isolation layers ST1 may fill the trenches between the second active patterns FN2.

The upper portions of the first and second active patterns FN1 and FN2 may be positioned higher than the upper surfaces of the first element isolation films ST1. The upper portions of the first and second active patterns FN1 and FN2 may vertically protrude from the first element isolation films ST1. The upper portion of each of the first and second active patterns FN1 and FN2 may have a fin shape protruding between the pair of first element isolation films ST1.

The second device isolation films ST2 and the first device isolation films ST1 may be one insulating film substantially connected to each other. The upper surfaces of the second element isolation films ST2 and the upper surfaces of the first element isolation films ST1 may be coplanar. The thickness of the second element isolation films ST2 may be thicker than the thickness of the first element isolation films ST1. In this case, the first element isolation films ST1 may be formed by a process different from the second device isolation films ST2. For example, the first and second isolation films ST1 and ST2 may include a silicon oxide film.

First channel regions CH1 and first source / drain regions SD1 may be provided at upper portions of the first active patterns FN1. The first source / drain regions SD1 may be p-type impurity regions. Each of the first channel regions CH1 may be interposed between the pair of first source / drain regions SD1. Second channel regions CH2 and second source / drain regions SD2 may be provided at upper portions of the second active patterns FN2. The second source / drain regions SD2 may be n-type impurity regions. Each of the second channel regions CH2 may be interposed between the pair of second source / drain regions SD2.

The first and second source / drain regions SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth process. The upper surfaces of the first and second source / drain regions SD1 and SD2 may be located at a higher level than the upper surfaces of the first and second channel regions CH1 and CH2. The first and second source / drain regions SD1 and SD2 may include a substrate and other semiconductor elements. In one example, the first source / drain regions SD1 may comprise a semiconductor element having a lattice constant greater than the lattice constant of the semiconductor element of the substrate 100. In this way, the first source / drain regions SD1 can provide compressive stress to the first channel regions CH1. In one example, the second source / drain regions SD2 may comprise a semiconductor element having a lattice constant that is less than the lattice constant of the semiconductor element of the substrate 100. As such, the second source / drain regions SD2 may provide tensile stress to the second channel regions CH2. As another example, the second source / drain regions SD2 may include the same semiconductor element as the semiconductor element of the substrate 100. [

In view of the first direction D1, the cross-sectional shape of the first source / drain regions SD1 may be different from the cross-sectional shape of the second source / drain regions SD2 (see FIG. 15C). For example, the first source / drain regions SD1 may comprise silicon-germanium and the second source / drain regions SD2 may comprise silicon.

Gate electrodes GE1-GE4 extending in the first direction D1 across the first and second active patterns FN1 and FN2 may be provided. The gate electrodes GE1 to GE4 may be spaced apart from each other in the second direction D2. The minimum pitch between the gate electrodes GE1-GE4 may be the first pitch P1. The gate electrodes GE1 to GE4 may be arranged at regular intervals along the first pitch P1.

The gate electrodes GE1-GE4 may vertically overlap with the first and second channel regions CH1 and CH2. Each gate electrode GE1-GE4 may surround the top and both sidewalls of each of the first and second channel regions CH1, CH2 (see FIG. 15D). In one example, the gate electrodes GE1-GE4 comprise at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal material (e.g., titanium, tantalum, tungsten, .

A pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE1-GE4. The gate spacers GS may extend in the first direction D1 along the gate electrodes GE1-GE4. The upper surfaces of the gate spacers GS may be higher than the upper surfaces of the gate electrodes GE1-GE4. The upper surfaces of the gate spacers GS may be coplanar with the upper surface of the gate cap film CP, which will be described later. In one example, the gate spacers GS may comprise at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS may comprise a multi-layer of at least two of SiCN, SiCON and SiN.

Gate dielectric films GI may be interposed between the gate electrodes GE1-GE4 and the first and second active patterns FN1 and FN2. Each gate dielectric layer GI may extend along the bottom surface of each of the gate electrodes GE1-GE4. Each gate dielectric layer (GI) may cover the top and both sidewalls of each of the first and second channel regions (CHl, CH2). The gate dielectric layers (GI) may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. In one example, the high-k material may be selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, Lead scandium tantalum oxide, lead zinc niobate, and lead zinc niobate.

A gate capping layer CP may be provided on each of the gate electrodes GE1-GE4. The gate capping films CP may extend in the first direction D1 along the gate electrodes GE1-GE4. The gate capping layer CP may include a material having etching selectivity with respect to the first interlayer insulating layer 110 described later. Specifically, the gate capping films CP may include at least one of SiON, SiCN, SiCON, and SiN.

The gate electrodes GE1 to GE4 in the first to third logic cells LC1, LC2 and LC3 may be the first to fourth gate electrodes GE1 to GE4. The first to fourth gate electrodes GE1 to GE4 may cross each of the first to third logic cells LC1, LC2, LC3. Within each of the first logic cell LC1 and the second logic cell LC2, the first through fourth gate electrodes GE1-GE4 may be arranged along the second direction D2. In the third logic cell LC3, the first to fourth gate electrodes GE1 to GE4 may be arranged along the direction opposite to the second direction D2. This is because the third logic cell LC3 makes a mirror symmetry with the first logic cell LC1 and the second logic cell LC2.

A first interlayer insulating film 110 covering the first and second active patterns FN1 and FN2, the gate spacers GS and the gate capping films CP may be provided. A second interlayer insulating film 120 and a third interlayer insulating film 130 sequentially stacked on the first interlayer insulating film 110 may be provided. Each of the first to third interlayer insulating films 110, 120, and 130 may include a silicon oxide film or a silicon oxynitride film.

At least one active contact (not shown) electrically connected to the first and second source / drain regions SD1 and SD2 through the first interlayer insulating film 110 is formed between the pair of gate electrodes GE1 to GE4 AC) may be provided. The active contacts AC may have the form of a bar extending in a first direction D1. In one example, at least one active contact (AC) may be coupled to a plurality of first source / drain regions SD1. In one example, at least one active contact (AC) may be connected to a plurality of second source / drain regions SD2. As another example, although not shown, at least one active contact (AC) may be connected to one first source / drain region SD1 or one second source / drain region SD2, and is not particularly limited.

At least one gate contact electrically connected to at least one gate electrode GE1-GE4 through the first interlayer insulating film 110 and the gate capping film CP on at least one gate electrode GE1-GE4, (GC) may be provided. The gate contacts GC may have a bar shape extending in the second direction D2. For example, gate contacts GC may be provided on the second and third gate electrodes GE2, GE3. From a plan viewpoint, the gate contacts GC can be disposed between the PMOSFET region PR and the NMOSFET region NR. The gate contacts GC can vertically overlap with the second isolation film ST2 between the PMOSFET region PR and the NMOSFET region NR.

Active contacts (AC) and gate contacts (GC) may comprise the same conductive material. The active contacts AC and the gate contacts GC may comprise at least one of a metallic material, for example aluminum, copper, tungsten, molybdenum and cobalt.

The first interconnects M1 and the first vias V1 may be provided in the second interlayer insulating film 120. [ The first wirings M1 and the first vias V1 may constitute a first metal layer. The first wirings M1 may include power supply lines VDD and VSS extending in the second direction D2 across the first to third logic cells LC1, LC2 and LC3. The first wires M1 may have a line shape or a bar shape extending in the second direction D2. In other words, the first wirings M1 may all extend in parallel to each other in the second direction D2.

The first vias V1 are interposed between the first wirings M1 and the active contacts AC and can electrically connect them to each other. The first vias V1 are interposed between the first wirings M1 and the gate contacts GC and can electrically connect them to each other. The first wiring M1 and the first via V1 under the first wiring M1 may be integrally connected to each other to form one conductive structure. In other words, the first wiring M1 and the first via V1 can be formed together. For example, the first wiring M1 and the first via V1 may be formed as a single conductive structure through a dual damascene process.

The shape and location of the active contacts AC, gate contacts GC, first vias V1 and first wirings M1 in the first logic cell LC1 are the same in the second logic cell LC2 May be substantially the same as the shapes and positions of the active contacts (AC), the gate contacts (GC), the first vias (V1) and the first interconnects (M1). This is because the first logic cell LC1 and the second logic cell LC2 comprise the same logic circuit. The shape and location of the active contacts AC, gate contacts GC, first vias V1 and first wirings M1 in the second logic cell LC2 are the same in the third logic cell LC3 Mirror symmetry with the shape and position of active contacts AC, gate contacts GC, first vias V1 and first interconnects M1.

Second interconnection (M2) and second vias (V2) may be provided in the third interlayer insulating film (130). The second wirings M2 may include internal wirings M2_I and routing wirings M2_O. The second wirings M2 and the second vias V2 may constitute a second metal layer. The second wirings M2 may have a line shape or a bar shape extending in the first direction D1. In other words, the second wirings M2 may all extend parallel to each other in the first direction D1. From a plan viewpoint, the second wirings M2 may be parallel to the gate electrodes GE1-GE4.

The minimum pitch between the second wirings M2 may be the second pitch P2. The interval between the adjacent second wirings M2 may be n x P2 (n is an integer of 1 or more). The gate electrodes GE1-GE4 and the second wires M2 may be formed using the gate patterns GEa and the second wiring patterns M2a in the layout of FIG. 11, respectively. The gate electrodes GE1 to GE4 are formed by the gate patterns GEa aligned with the gate pattern tracks GPT and the second wiring patterns The second wirings M2 may be formed by the first wirings M2a. Accordingly, the second pitch P2, which is the minimum pitch between the second wirings M2, may be smaller than the first pitch P1, which is the pitch between the gate electrodes GE1-GE4.

The second vias V2 are interposed between the second wirings M2 and the first wirings M1 to electrically connect them to each other. The second wiring M2 and the second via V2 under the second wiring M2 may be connected to each other. In other words, the second wirings M2 and the second vias V2 can be formed together. For example, the second wirings M2 and the second vias V2 may be formed through a dual damascene process.

The internal wiring M2_I in each of the first to third logic cells LC1, LC2, LC3 can extend over the NMOSFET region NR on the PMOSFET region PR. The internal wiring M2_I on the PMOSFET region PR is electrically connected to the first source / drain regions SD1 through the second via V2, the first wiring M1, the first via V1 and the active contact AC. (See Fig. 15A). The internal wiring M2_I on the NMOSFET region NR is electrically connected to the second source / drain regions SD2 through the second via V2, the first wiring M1, the first via V1 and the active contact AC. (See FIG. 15B). In other words, the internal wiring M2_I in each of the first to third logic cells LC1, LC2 and LC3 is connected to the PMOS transistor (PMOSFET) of the PMOSFET region PR and the NMOS transistor (NMOSFET) of the NMOSFET region NR They can be electrically connected to each other. The internal wiring M2_I in each of the first to third logic cells LC1, LC2, LC3 can electrically connect the source / drain of the PMOSFET and the source / drain of the NMOSFET to each other.

The internal wiring M2_I in each of the first to third logic cells LC1, LC2, LC3 may be a wiring constituting a logic circuit. For example, the internal wiring M2_I may be the output node of the NAND 2 cell. The internal wiring M2_I in the first logic cell LC1 may not extend beyond the boundary of the first logic cell LC1. In other words, both ends of the internal wiring M2_I may be located in the first logic cell LC1. For example, one end of the internal wiring M2_I may be located on the PMOSFET region PR and the other end of the internal wiring M2_I may be located on the NMOSFET region NR. The internal wirings M2_I in the second and third logic cells LC2 and LC3 may also have substantially the same shape as the internal wirings M2_I in the first logic cell LC1.

Although the first to third logic cells LC1, LC2 and LC3 include the same logic circuit, the positions of the internal wirings M2_I in the first to third logic cells LC1, LC2 and LC3 are different from each other . From the viewpoint of planarization, the distance that the internal wiring M2_I of the first logic cell LC1 is offset from the third gate electrode GE3 adjacent thereto, the internal wiring M2_I of the second logic cell LC2 is adjacent thereto The distance offset from the third gate electrode GE3 and the distance offset from the third gate electrode GE3 adjacent to the internal wiring M2_I of the third logic cell LC3 may be different from each other.

The internal wiring M2_I in the first logic cell LC1 may partially overlap the third gate electrode GE3 vertically. From a plan viewpoint, the internal wiring M2_I in the first logic cell LC1 can be horizontally spaced from the fourth gate electrode GE4 (see Figs. 14 and 15A).

The internal wiring M2_I in the second logic cell LC2 may partially overlap with the fourth gate electrode GE4 vertically. From a plan viewpoint, the internal wiring M2_I in the second logic cell LC2 can be horizontally spaced from the third gate electrode GE3 (see Figs. 14 and 15E).

From a plan viewpoint, the internal wiring M2_I in the third logic cell LC3 may be located between the third gate electrode GE3 and the fourth gate electrode GE4. The internal wiring M2_I in the third logic cell LC3 can be horizontally spaced from both the third gate electrode GE3 and the fourth gate electrode GE4 (see Figs. 14 and 15F).

Routing wirings M2_O within each of the first through third logic cells LC1, LC2, LC3 can couple their logic circuitry with the logic circuitry of the other logic cell. In other words, the routing wirings M2_O may be independent of the logic circuits (e.g., NAND 2 circuits) of the first to third logic cells LC1, LC2, LC3. The number and shape of the routing wirings M2_O in the first to third logic cells LC1, LC2, LC3 may be different from each other. The routing wirings M2_O may extend beyond the boundaries of the first through third logic cells LC1, LC2, LC3. Alternatively, at least one routing line M2_O may not extend beyond the boundaries of the first through third logic cells LC1, LC2, LC3. The length and arrangement of the routing wirings M2_O shown are arbitrary and not particularly limited.

The first wirings M1, the first vias V1, the second wirings M2, and the second vias V2 may include the same conductive material. For example, the first wirings M1, the first vias V1, the second wirings M2, and the second vias V2 may be formed of at least one selected from aluminum, copper, tungsten, molybdenum, and cobalt And may include one metal material. Although not shown, additional metal layers may be further disposed on the third interlayer insulating film 130. The additional metal layers may include routing wires.

According to the embodiments of the present invention, the second pitch P2, which is the minimum pitch between the second wirings M2, may be smaller than the first pitch P1 which is the minimum pitch between the gate electrodes GE1-GE4. The internal wirings M2_I of the second wirings M2 may be arranged in alignment with the arrangement interval of the routing wirings M2_O (i.e., the second pitch P2). Therefore, the pattern density of the second wirings M2 in the logic cell can be increased.

16, 17 and 19 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. 17A, 19A and 21A are sectional views corresponding to the line A-A 'in FIGS. 16, 17 and 19, and FIGS. 17B, 19B and 21B are sectional views corresponding to line B- 19C and 21C are cross-sectional views corresponding to line C-C 'in FIGS. 18 and 19, respectively, and FIGS. 19D and 21D are cross-sectional views corresponding to line D-D' admit. The method of manufacturing a semiconductor device according to the present embodiment includes the steps of forming patterns on an actual substrate using the designed layout of Fig.

16, 17A and 17B, a substrate 100 may be provided. As an example, the substrate 100 may be a silicon substrate, a germanium substrate, or a SOI (Silicon On Insulator) substrate. The first and second active patterns FN1 and FN2 may be formed by patterning the upper portion of the substrate 100. [ First element isolation films ST1 filling the space between the first and second active patterns FN1 and FN2 may be formed. Second device isolation films ST2 that define the PMOSFET region PR and the NMOSFET region NR may be formed on the substrate 100. [

The first and second isolation films ST1 and ST2 may be formed by a shallow trench isolation (STI) process. The first and second isolation films ST1 and ST2 may be formed using silicon oxide.

Referring to FIGS. 18 and 19A to 19D, gate electrodes GE1 to GE4 extending in the first direction D1 across the first and second active patterns FN1 and FN2 may be formed . Gate dielectric films GI may be formed under the gate electrodes GE1-GE4. Gate spacers GS may be formed on both sides of each of the gate electrodes GE1-GE4. Gate capping films CP may be formed on the gate electrodes GE1-GE4.

Specifically, forming the gate electrodes GE1-GE4 includes forming sacrificial patterns across the first and second active patterns FN1, FN2, forming gate spacers GS), and replacing the sacrificial patterns with gate electrodes (GE1-GE4).

The gate electrodes GE1-GE4 may comprise at least one of a conductive metal nitride and a metal material. The gate dielectric layers (GI) may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. The gate spacers GS may comprise at least one of SiCN, SiCON, and SiN. The gate capping layers CP may include at least one of SiON, SiCN, SiCON, and SiN.

First source / drain regions SD1 may be formed at upper portions of the first activation patterns FN1. Second source / drain regions SD2 may be formed on top of the second active patterns FN2. The first and second source / drain regions SD1 and SD2 may be formed on both sides of each of the gate electrodes GE1 to GE4. The first source / drain regions SD1 may be doped with a p-type impurity and the second source / drain regions SD2 may be doped with an n-type impurity.

Specifically, the first and second source / drain regions SD1 and SD2 may be formed as epitaxial patterns by a selective epitaxial growth process. After partially recessing the first and second active patterns FN1 and FN2 on both sides of each of the gate electrodes GE1-GE4, the first and second active patterns FN1 and FN2, The epitaxial growth process can be performed on the regions.

The first interlayer insulating film 110 may be formed on the front surface of the substrate 100. [ The first interlayer insulating film 110 may be formed of a silicon oxide film or a silicon oxynitride film. Active contacts (AC) and gate contacts (GC) may be formed in the first interlayer insulating film (110). Active contacts AC may be formed on the first and second source / drain regions SD1 and SD2. Active contacts (AC) may have a bar shape extending in a first direction (D1). Gate contacts GC may be formed on the gate electrodes GE1-GE4. And may have a bar shape extending in the second direction D2 of the gate contacts GC.

Referring to FIG. 20 and FIGS. 21A to 21D, a second interlayer insulating film 120 may be formed on the first interlayer insulating film 110. The second interlayer insulating film 120 may be formed of a silicon oxide film or a silicon oxynitride film.

The first interconnects M1 and the first vias V1 may be formed in the second interlayer insulating film 120. [ The first vias V1 may be formed between the first wirings M1 and the active contacts AC and between the first wirings M1 and the gate contacts GC. The first wires M1 may have a line shape or a bar shape extending in the second direction D2.

Specifically, the first photomask can be manufactured using the first wiring patterns M1a in the layout of FIG. 11 (see S40 in FIG. 2). The first wiring holes may be formed in the second interlayer insulating film 120 by performing a photolithography process using the first photomask. The first wiring holes M1 may be formed by filling the first wiring holes with a conductive material (see S50 in FIG. 2).

Referring again to FIGS. 14 and 15A to 15D, a third interlayer insulating film 130 may be formed on the second interlayer insulating film 120. FIG. The third interlayer insulating film 130 may be formed of a silicon oxide film or a silicon oxynitride film.

The second interconnects M2 and the second vias V2 may be formed in the third interlayer insulating film 130. [ The second vias V2 may be formed between the second wirings M2 and the first wirings M1. The second wirings M2 may have a line shape or a bar shape extending in the first direction D1.

Specifically, a second photomask can be manufactured using the second wiring patterns M2a in the layout of FIG. 11 (see S40 in FIG. 2). The second wiring holes may be formed in the third interlayer insulating film 130 by performing a photolithography process using the second photomask. A third photomask can be fabricated using the via patterns V2a in the layout of FIG. 11 (see S40 in FIG. 2). The photolithography process using the third photomask may be performed to form vertical holes that expose a part of the first interconnects M1 in the second interconnect holes. The second wiring holes and the vertical holes may be filled with a conductive material so that the second wires M2 and the second vias V2 may be integrally formed together (refer to S50 in FIG. 2).

22 is a plan view for explaining a semiconductor device according to embodiments of the present invention. 23 is a cross-sectional view taken along the line A-A 'in Fig. In the present embodiment, detailed descriptions of technical features overlapping with those described with reference to FIG. 14 and FIGS. 15A to 15F will be omitted, and differences will be described in detail.

Referring to Figures 22 and 23, first and second logic cells LC1, LC2 may be provided. The first and second logic cells LC1, LC2 may be arranged in a second direction D2. Each of the first and second logic cells LC1, LC2 may comprise any logic circuit. In this embodiment, the first and second logic cells LC1 and LC2 may comprise the same logic circuit. In other words, the first and second logic cells LC1, LC2 may have the same transistor structure and internal wiring structure.

Gate electrodes GE1-GE3 may be provided across the PMOSFET region PR and the NMOSFET region NR of the substrate 100. [ The minimum pitch between the gate electrodes GE1-GE3 may be the first pitch P1. The gate electrodes GE1 to GE3 may be arranged at regular intervals along the first pitch P1. The gate electrodes GE1 to GE3 in the first and second logic cells LC1 and LC2 may include first to third gate electrodes GE1 to GE3.

The second to third interlayer insulating films 120, 130, and 140 may be sequentially stacked on the first interlayer insulating film 110. A first metal layer may be provided in the second interlayer insulating film 120, a second metal layer may be provided in the third interlayer insulating film 130, and a third metal layer may be provided in the fourth interlayer insulating film 140 . The first metal layer in the second interlayer insulating film 120 may include first wirings M1 and first vias V1. The second metal layer in the third interlayer insulating film 130 may include second wirings M2 and second vias V2. The third metal layer in the fourth interlayer insulating film 140 may include third wirings M3_I and M3_O and third vias V3.

At least one of the first wirings M1 may include a portion extending in the first direction D1 and a portion extending in the second direction D2. The first wirings M1 of the present embodiment are different from the first wirings M1 described with reference to Figs. 14 and 15A to 15F in the first direction D1 and / or the second direction D2 ), And is not particularly limited.

And the second wirings M2 may extend in the second direction D2. Unlike the second wirings M2 described with reference to Figs. 14 and 15A to 15F, the second wirings M2 of the present embodiment are formed so as to cross the extending direction of the gate electrodes GE1-GE3 And may extend in the second direction D2.

The shape and location of the logic transistors, the first metal layer and the second metal layer in the first logic cell LC1 are determined by the shape of the logic transistors, the first metal layer and the second metal layer in the second logic cell LC2, Position. ≪ / RTI > This is because the first logic cell LC1 and the second logic cell LC2 comprise the same logic circuit.

The third wirings M3_I and M3_O may include the internal wirings M3_I and the routing wirings M3_O. The third wirings M3_I and M3_O may extend in a first direction D1 parallel to the extending direction of the gate electrodes GE1-GE3.

The minimum pitch between the third wirings M3_I and M3_O may be the second pitch P2. The interval between the adjacent third wirings M3_I and M3_O may be n x P2 (n is an integer of 1 or more). The second pitch P2 which is the minimum pitch between the third wirings M3_I and M3_O may be smaller than the first pitch P1 which is the minimum pitch between the gate electrodes GE1 and GE3.

The internal wiring M3_I in each of the first and second logic cells LC1 and LC2 may extend over the NMOSFET region NR on the PMOSFET region PR. The internal wiring M3_I can electrically connect the PMOSFET and the NMOSFET to each other. In other words, the internal wiring M3_I in each of the first and second logic cells LC1, LC2 may be a wiring constituting a logic circuit. For example, the internal wiring M3_I may be an input node or an output node of the logic circuit.

Although the first and second logic cells LC1 and LC2 include the same logic circuit, the positions of the internal wirings M3_I in the first and second logic cells LC1 and LC2 may be different from each other. The distance offset from the first gate electrode GE1 adjacent to the internal wiring M3_I of the first logic cell LC1 is smaller than the distance between the internal wiring M3_I of the second logic cell LC2 and the adjacent 1 < / RTI > gate electrode GE1.

The routing interconnects M3_O in each of the first and second logic cells LC1, LC2 can couple their logic circuitry with the logic circuitry of the other logic cell. In other words, the routing interconnections M3_O may be independent of the logic circuits of the first and second logic cells LC1, LC2. The number and type of routing interconnections M3_O in the first and second logic cells LC1, LC2 may be different.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is to be understood, therefore, that the embodiments described above are in all respects illustrative and not restrictive.

Claims (20)

A substrate including a PMOSFET region and an NMOSFET region;
First active patterns on the PMOSFET region;
Second active patterns on the NMOSFET region;
Gate electrodes extending in a first direction across the first and second active patterns; And
And first wirings disposed on the gate electrodes and extending in the first direction,
The gate electrodes are arranged in a second direction intersecting the first direction according to a first pitch (P1)
The first wirings are arranged in the second direction in accordance with the second pitch P2,
And the second pitch (P2) is smaller than the first pitch (P1).
The method according to claim 1,
Wherein the first wirings include a routing wiring and an internal wiring,
From a planar viewpoint, the internal wiring extends from the PMOSFET region to the NMOSFET region,
The internal wiring electrically connecting the first active patterns and the second active patterns to each other,
From a plan viewpoint, one end of the internal wiring is located on the PMOSFET region,
The other end of the internal wiring is located on the NMOSFET region.
3. The method of claim 2,
Wherein the PMOSFET region and the NMOSFET region constitute one logic cell,
Wherein the routing interconnect extends over another logic cell beyond a boundary of the logic cell.
3. The method of claim 2,
The interval between the routing wiring and the internal wiring is n x P2,
And n is an integer of 1 or more.
The method according to claim 1,
Wherein the gate electrodes are aligned with virtual gate tracks extending in the first direction,
Wherein the first wirings are aligned with virtual wiring tracks extending in the first direction,
The distance between the gate tracks adjacent to each other is the first pitch Pl,
And a distance between the adjacent wiring tracks is the second pitch (P2).
The method according to claim 1,
An interlayer insulating film covering the first and second active patterns and the gate electrodes on the substrate;
Further comprising active contacts and gate contacts in the interlayer dielectric,
Wherein the first and second active patterns comprise:
Channel regions under the gate electrodes; And
Source / drain regions between the channel regions,
The active contacts are connected to the source / drain regions,
Wherein the gate contacts are connected to the gate electrodes.
The method according to claim 6,
Further comprising second wirings interposed between the active contacts and the first wirings and between the gate contacts and the first wirings,
The second wirings extend in the second direction,
Wherein the second wirings electrically connect the active contacts and the gate contacts with the first wirings.
A first logic cell and a second logic cell on the substrate,
Wherein the first logic cell and the second logic cell comprise the same logic circuit,
Each of said first and second logic cells comprising:
A gate electrode extending in the first direction across the PMOSFET region and the NMOSFET region; And
And an internal wiring disposed on the gate electrode and extending in the first direction,
Wherein the internal wiring is a wiring constituting the logic circuit,
From a plan viewpoint, the distance of the internal wiring of the first logic cell offset from the gate electrode of the first logic cell is such that the internal wiring of the second logic cell is offset from the gate electrode of the second logic cell Distance and other semiconductor devices.
9. The method of claim 8,
Wherein the internal wiring electrically connects the PMOS transistor of the PMOSFET region and the NMOS transistor of the NMOSFET region to each other.
9. The method of claim 8,
From a plan viewpoint, one end of the internal wiring is located on the PMOSFET region,
The other end of the internal wiring is located on the NMOSFET region.
9. The method of claim 8,
Wherein the shape of the internal wiring of the first logic cell is substantially the same as the shape of the internal wiring of the second logic cell.
9. The method of claim 8,
Each of the first and second logic cells further includes a routing wiring disposed at the same level as the internal wiring and extending in the first direction,
Wherein the routing interconnect connects each of the first and second logic cells to another logic cell.
13. The method of claim 12,
Wherein a plurality of said gate electrodes in each of said first and second logic cells are provided,
The gate electrodes are arranged in a second direction intersecting the first direction according to a first pitch (P1)
The internal wiring and the routing wiring are arranged in the second direction in accordance with the second pitch P2,
And the second pitch (P2) is smaller than the first pitch (P1).
9. The method of claim 8,
Each of the first and second logic cells further includes a first wiring interposed between the gate electrode and the internal wiring,
Wherein the first wiring extends in a second direction crossing the first direction,
Wherein the arrangement of the first wiring in the first logic cell is substantially the same as the arrangement of the first wiring in the second logic cell.
9. The method of claim 8,
Wherein the gate electrode of the first logic cell and the gate electrode of the second logic cell form the same gate in the logic circuit.
Designing the layout of semiconductor devices; And
And forming patterns on the substrate using the layout,
Designing the layout includes:
Placing standard cells;
Rearranging the internal wiring patterns in at least one of the standard cells to the wiring pattern tracks; And
And routing routing patterns to the wiring pattern tracks to route standard cells.
17. The method of claim 16,
Each of the standard cells including gate patterns aligned with gate pattern tracks,
The distance between the adjacent wiring pattern tracks is a first distance,
The distance between the adjacent gate pattern tracks is a second distance,
Wherein the first distance is smaller than the second distance.
18. The method of claim 17,
Wherein the gate patterns, the internal wiring pattern, and the routing patterns have a line shape or a bar shape extending in a first direction.
17. The method of claim 16,
Wherein the internal wiring pattern and the routing patterns are disposed at the same level.
17. The method of claim 16,
The distance between the adjacent wiring pattern tracks is a first distance,
Wherein a maximum distance that the inner wiring patterns move while rearranging is half of the first distance.

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