KR20180072515A - Photo Mask and Display Panel using thereof and Method for Fabricating Display Panel using the thereof - Google Patents

Abstract

A display panel according to the present invention includes data lines, gate lines, links, a pad electrode, and a pad protection unit. The links are arranged in a non-display region and are connected to the data lines or gate lines. The pad electrode is connected to any one among the links. The pad protection unit is formed with a shape to surround the edges of the upper side and the lateral side of the pad electrode. The pad protection unit is made of the same materials as a pixel planarization film located on a drain electrode and a source electrode of a transistor arranged in the display region. The thickness of the pad protection unit is thinner than the thickness of the pixel planarization unit. Accordingly, the present invention can reduce a photoresist process.

Description

[0001] The present invention relates to a photo mask and a display panel using the same,

The present invention relates to a photomask, a display panel using the same, and a method of manufacturing the display panel.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

The display device includes a display panel and a drive IC for applying various drive signals to the display panel. The signal wiring of the display panel is connected to signal wirings of the drive IC through an anisotropic conductive film (ACF). The anisotropic conductive film is pressed through a tap bonding process, and the conductive ball in the anisotropic conductive film electrically connects the pad electrode of the display panel and the flexible printed circuit board.

The pad electrode of the display panel is at least partially exposed to be in electrical contact with the conductive ball of the anisotropic conductive film and is protected by a pad protection layer surrounding the side surface of the pad electrode.

Various methods for reducing the mask process in the manufacturing process of the display panel have been searched, and a method for simplifying the method and the process for forming the pad protective layer are needed.

The present invention provides a photomask capable of simplifying a manufacturing method of a display panel, a display panel using the same, and a manufacturing method of the display panel.

A display panel according to the present invention has data lines and gate lines, links, pad electrodes, and pad protectors. The links are arranged in the non-display area and are connected to the data lines or gate lines. The pad electrode is connected to any one of the links. The pad protecting portion is formed so as to surround the side edge and the upper edge of the pad electrode. The pad protecting portion is made of the same material as the pixel planarizing film located on the source electrode and the drain electrode of the transistor disposed in the display region, and the thickness of the pad protecting portion is formed thinner than the thickness of the pixel planarizing film.

A manufacturing method of a display panel according to the present invention includes forming a transistor disposed in a display region and a pad electrode disposed in a non-display region. And forming a planarizing film covering the transistor and the pad electrode. Forming a pixel planarizing film covering the transistor in the display region, a pad hole exposing a part of the pad electrode, and a pad protecting portion surrounding and covering the edge of the side surface and the upper portion, by selectively etching the planarizing film. The step of forming the pad protecting portion is performed such that the thickness of the pad protecting portion is thinner than the thickness of the pixel planarizing film.

A photomask according to the present invention includes first through third light transmission regions. The first light transmitting region is aligned with a region in which a pad hole where a part of the pad electrode is exposed is arranged. And the second light transmitting region is arranged in a region where the pad protecting portion which covers and covers the pad electrode is arranged. The third light transmitting region is aligned with the region where the pixel planarizing film covering the transistor is disposed. The light transmittance of the second light transmitting region is higher than the light transmittance of the third light transmitting region and is lower than the light transmittance of the first light transmitting region or higher than the light transmittance of the first light transmitting region, .

The present invention can reduce the photoresist process by removing the passivation layer from the display panel and by using the planarization film as a passivation layer.

In addition, conventionally, the function of protecting the pad electrode can be maintained by forming the pad protecting portion formed using the passivation layer by using the planarizing film. Particularly, the display panel according to the present invention can be provided with various functions by forming the pixel planarizing film and the pad protecting part differently in thickness.

1 is a view showing a display device of the present invention.
2 is a schematic diagram showing an example of the pixel shown in Fig.
3 is a cross-sectional view of a region where the driving transistor is arranged in the display region.
4 is a cross-sectional view taken along the line I-I 'shown in FIG.
5 is a view showing a pad portion.
6 is a cross-sectional view taken along line II-II 'in FIG.
7 is a cross-sectional view of a pad portion according to a comparative example.
8 and 9 are views showing a photomask for an exposure process of a planarizing film.
10 is an enlarged view of a slit region of the photomask.
11 is a schematic view for explaining a region corresponding to the pad portion of the photomask for the exposure process.
12 is a schematic enlarged view of the X region of FIG. 11 for explaining the photomask corresponding to the rim of the pad electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Although the present invention has been described with reference to an organic light emitting display, the technical idea of the present invention is not limited thereto. It is apparent that the present invention can also be applied to a liquid crystal display device, an electrophoretic display device, and the like.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Fig. 1 is a diagram showing a display device, and Fig. 2 is a diagram showing an example of a pixel.

1 and 2, a display device according to the present invention includes a data driver SIC, a gate driver GIC, and a display panel 100.

The data driver SIC converts the input video data into a data voltage and outputs the data voltage in response to a data timing control signal supplied from a timing controller (not shown). The data voltage is supplied to the pixels P in the display area AA through the data line. The data driver SIC can be mounted on the data communication circuit board (S-COF) in a chip-on-film (COF) manner.

The gate driver GIC outputs a gate pulse while shifting the level of the gate voltage in response to the gate timing control signal supplied from the timing controller. The gate pulse is supplied to the pixels P in the display area AA through the gate lines GL. The gate driver 40 may be mounted on the gate flexible circuit board (G-COF) by a chip on film method or may be mounted on a non-display area (NA) of the display panel 100 by a gate- As shown in FIG.

The display panel 100 includes a display area AA and a non-display area NA. A plurality of pixels P are arranged in the display area AA. Each pixel P displays a gray level corresponding to the data voltage using a gate pulse supplied through the gate line GL. Links (DLINK, GLINK) are located in the non-display area (NA). The links (DLINK, GLINK) include a data link (DLINK) and a gate link (GLINK). The data link DLINK connects the data flexible circuit board S-COF and the data line DL and the gate link GLINK connects the gate flexible circuit board G-COF and the gate line GL.

Each pixel P includes a switching transistor SW, a driving transistor DT, a compensation circuit CC and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light in accordance with the driving current formed by the driving transistor DT.

The switching transistor SW stores the data voltage supplied from the data line DL in the storage capacitor Cst in response to the gate pulse supplied through the gate line GL. The driving transistor DT generates a driving current proportional to the data voltage stored in the storage capacitor Cst. The organic light emitting diode OLED emits light with brightness proportional to the driving current through the drain electrode and the source electrode of the driving transistor DT.

The compensation circuit CC compensates for a variation in the threshold voltage and the mobility characteristic of the driving transistor DT, and may be formed of a combination of one or more thin film transistors.

The pixel structure shown in FIG. 2 is a simple model of an example of the organic light emitting diode display, and the structure of the pixel structure and the compensation circuit CC may be any known one. Therefore, the connection relationship between the driving transistor DT and the storage capacitor Cst, the switching transistor SW and the compensation circuit CC is not limited to the embodiment shown in Fig.

3 is a diagram showing a sectional structure of a display region, in particular, a sectional structure of a region to which a driving transistor belongs.

Referring to FIG. 3, a polyimide (PI) layer may be positioned on the base substrate in the display area AA. The first buffer layer BUF1 is located on the polyimide (PI) layer. The first buffer layer BUF1 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof.

A shield layer BSM is located on the first buffer layer BUF1. The shield layer BSM serves to prevent the current amount of the semiconductor layer ACT from decreasing due to the charge flow of the polyimide (PI) layer.

The second buffer layer BUF2 is located on the shield layer LS. The second buffer layer BUF2 serves to protect the thin film transistor formed in the subsequent process from impurities such as alkali ions or the like that flow out from the shield layer LS. The second buffer layer BUF2 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof.

The semiconductor layer ACT is located on the second buffer layer BUF2. The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, the polycrystalline silicon has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, and can be applied to a gate driver for a driving device and / or a multiplexer (MUX) have. On the other hand, since the oxide semiconductor has low off-current, it is suitable for a switching TFT which has a short ON time and a long OFF time. Further, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low speed driving and / or low power consumption. Further, the semiconductor layer ACT includes a source region and a drain region including a p-type or n-type impurity, and includes a channel therebetween.

A gate insulating film GI is disposed on the semiconductor layer ACT. The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. The gate electrode GA is located on the gate insulating film GI at a position corresponding to a certain region of the semiconductor layer ACT, that is, a channel when an impurity is implanted. The gate electrode GA is formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) Any one of them or an alloy thereof. The gate electrode GA may be formed of a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. For example, the gate electrode GA can be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

A first interlayer insulating film ILD for insulating the gate electrode GA is located on the gate electrode GA. The first interlayer insulating film ILD may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The capacitor metal layer TM1 is located on the first interlayer insulating film ILD1. The capacitor metal layer TM1 faces the gate electrode GE with the gate insulating film GI interposed therebetween and the capacitor metal layer TM1 and the gate electrode GE form the storage capacitor Cst.

The second interlayer insulating film ILD2 is located on the capacitor metal layer TM1. The second interlayer insulating film ILD2 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The drain electrode DE and the source electrode SE are located on the second interlayer insulating film ILD. The source electrode SE is connected to the semiconductor layer ACT through the first contact hole CN1 and the drain electrode DE is connected to the semiconductor layer ACT through the second contact hole CN2.

The source electrode SE and the drain electrode DE may be formed of a single layer or a multilayer. When the source electrode SE and the drain electrode DE are a single layer, molybdenum (Mo), aluminum (Al) (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). When the source electrode SE and the drain electrode DE are multilayered, a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum- neodymium / molybdenum ≪ / RTI >

The semiconductor layer ACT, the gate electrode GE, the drain electrode DE and the source electrode SE constitute a driving transistor DT.

A pixel planarizing film PLN1 is located on the source electrode SE and the drain electrode DE. The pixel planarizing film PLN1 protects the transistors disposed in the driving transistor DT and the display area AA and relaxes the step of the display area AA.

An anode electrode (AND) of the organic light emitting diode (OLED) is located on the pixel planarizing film (PLN1). The anode electrode AND is connected to the drain electrode DE of the driving transistor DT via a via hole Via. The anode electrode ANO may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

On the anode electrode (AND), a bank layer (BSL) for partitioning the pixels is located. The bank layer BSL is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

4 is a cross-sectional view taken along the line I-I 'shown in FIG. FIG. 5 is a plan view showing a data pad portion, and FIG. 6 is a cross-sectional view taken along the line II-II 'shown in FIG.

4 to 6, the data pad unit PAD includes a plurality of pad electrodes PE. Each of the pad electrodes PE is connected to a data flexible circuit board (S-COF) on which the data driver SIC is mounted through an anisotropic conductive film.

The pad electrodes PE are connected to a data link DLINK disposed in the non-display area NA. Each of the data links DLINK is connected to a data line DL of the display area AA.

The data links DLINKs may be made of the same metal layer as the gate electrodes GE of the transistors disposed in the display area AA. The pad electrode PE may be formed of the same source metal layer as the source electrode SE of the transistors disposed in the display area AA. The pad electrode PE and the data link DLINK are connected one-to-one through the contact hole CN3.

A pad protection portion PLN2 is disposed on the pad electrode PE of the non-display area NA. The pad protection portion PLN2 covers the side edge and the upper edge of the pad electrode PE. The pad protecting portion PLN2 prevents moisture from being wetted to the side surface of the pad electrode PE. The pad protection portion PLN2 is made of the same material as the pixel planarizing film PLN1 of the display area AA. The thickness h1 of the pad protection portion PLN2 is made thinner than the thickness h1 of the pixel planarization film PLN1.

If the pad protection portion PLN2 has the same thickness as the pixel planarizing film PLN1, the contact between the data flexible circuit substrate S-COF and the pad electrode PE becomes poor.

FIG. 7 is a cross-sectional view of a pad portion according to a comparative example, showing a pad portion in which a pad protecting portion having a thickness equal to that of the pixel planarizing film is formed.

Referring to FIG. 7, the pad electrode PE is in electrical contact with the signal line CL of the data communication circuit board (S-COF) through the anisotropic conductive film (ACF). The anisotropic conductive film ACF includes a plurality of conductive balls CB dispersed in the adhesive resin AR.

The pixel planarizing film PLN1 of the display area AA should be formed to have a certain thickness, for example, about 2 mu m in order to improve the step of the display area. 7, if the pad protection portion PLN2 is formed to have a thickness of about 2 탆, the signal line CL of the conductive ball CB flexible circuit board S-COF of the anisotropic conductive film ACF, A phenomenon occurs that the pad electrode PE of the panel is not brought into contact with the substrate.

Therefore, the pad protecting portion PLN2 according to the present invention is formed to have a thickness thinner than the thickness of the pixel planarizing film PLN1 of the display area AA as shown in FIG.

A method of forming the pixel planarizing film PLN1 and the pad protecting portion PLN2 will be described below.

8 is a cross-sectional view of a planarizing film over the entire surface of the display panel and a cross-sectional view of the photomask, and Fig. 9 is a view showing the plane of the photomask.

8 and 9, the planarizing film PLN is formed so as to cover the transistor disposed in the display area AA and the pad electrode PE in the non-display area NA.

The photomask PM includes a normal region NM and a slit region HTM. The normal area NM is aligned on the display area AA and includes a first light transmitting area A1 and a third light transmitting area A3. The slit area HTM is aligned on the non-display area NA and includes a second light transmitting area A2 and a third light transmitting area A3.

The light transmittance of the second light transmitting region A2 is higher than the light transmittance of the third light transmitting region A3 and lower than the light transmittance of the first light transmitting region A1.

The first light transmitting region A1 corresponds to the opening region and completely transmits light in the exposure process. The first light transmission region A1 corresponds to a region where the pixel planarizing film PLN1 of the display region AA is formed.

The second light transmitting region A2 is composed of a slit structure including a blocking portion and an opening portion. And the second light transmitting region A2 is aligned with the region where the pad protecting portion PLN2 is formed. The second light transmitting area A2 may be designed to correspond to the entire surface of the non-display area NA except the pad hole PH in addition to the pad protecting part PLN2.

The third light transmitting region A3 corresponds to a region for blocking light and corresponds to a region where the via hole Via of the display region AA and the pad hole PH of the non-display region NA are formed.

An exposure process is performed using the photomask (PM), and then the planarizing film (PLN) is patterned through a developing process.

The region where the first light transmitting region A1 of the photomask PM contacts the display panel 100 is left as it is in the developing process and becomes the pixel flattening film PLN1.

The region of the display panel 100 in which the second light transmitting region A2 of the photomask PM comes into contact with the planarizing film PLN is partially etched through the developing process to become the pad protecting portion PLN2.

The region where the third light transmitting region A3 of the photomask PM comes into contact with the display panel 100 is completely removed from the planarizing film PLN through the developing process to become the pad hole PH and the via hole Via .

In the developing process, the thickness of the pad protection portion PLN2 is determined by the ratio of the blocking portion to the opening portion of the second light transmitting region A2.

10 is a view showing a second light transmitting region of the photomask according to the present invention.

Referring to FIG. 10, the second light transmitting region includes a blocking portion CA and an opening portion OA. The opening portion OA is formed by a slit structure formed in one direction in the second light transmitting region.

[Table 1] below is a table showing experimental results of measuring the thickness of the pad protection portion PLN2 according to the width W2 of the opening portion and the width W1 of the blocking portion.

The width (W2) 0.5 탆 1 탆 1.5 탆 2 탆 The width (W1) 1 탆 0.67 탆 1.37 탆 1.71 탆 1.82 탆 1.5 탆 0.17 탆 0.90 탆 1.26 탆 1.44 탆 2 탆 0.00 탆 0.57 탆 0.94 탆 1.17 탆

Referring to Table 1, the thickness of the pad protection portion PLN2 formed through the developing process is proportional to the width W2 of the opening portion and inversely proportional to the width W1 of the blocking portion.

The thickness of the pad protection portion PLN2 determined by the width W1 of the blocking portion and the width W2 of the opening portion is selected in consideration of the thickness of the conductive balls CB of the anisotropic conductive film ACF . It is preferable that the thickness h2 of the pad protection portion PLN2 is set smaller than the diameter of the conductive ball CB shown in Fig. For example, if the thickness of the conductive ball CB is about 2 占 퐉, the width W1 of the shielding portion and the width W2 of the opening portion can be determined within the range where the pad protecting portion PLN2 is 2 占 퐉 or less.

Since the pad protecting portion PLN2 is provided to prevent moisture from being permeated or corroded through the side surface of the pad electrode PE, the minimum width of the thickness need not be considered. For example, the pad protecting portion PLN2 may be formed to have a thickness of about 0.01 mu m.

As described above, the present invention can simultaneously form the pixel planarizing film PLN1 of the display area AA and the pad protecting part PLN2 of the non-display area NA by selectively etching the planarizing film PLN . As a result, the number of masks in the photoresist process can be reduced in comparison with the formation of the pixel planarizing film PLN1 and the pad protecting portion PLN2 separately. When the thickness of the pad protection portion PLN2 is equal to that of the pixel flattening film PLN1, the contact failure may occur with the anisotropic conductive film. However, the present invention is not limited to this, By changing the thickness, it is possible to improve the defective contact with the anisotropic conductive film.

The embodiment of the present invention has been described with reference to a data pad unit (PAD) connected to a data flexible circuit board (S-COF) on which a data driver is mounted. However, it is obvious that the technical idea of the present invention can be equally applied to the gate pad portion.

Although the present invention has been described with reference to a planarizing film in which the exposed region in the exposure process remains after the developing process, depending on the type of the planarizing film, the first light transmitting region A1 and the third light transmitting region A3 It can be disposed at the opposite position. Even in this case, the position where the second light transmitting region A2 according to the present invention is formed is the same as the position described in this specification.

More specifically, in the exposure method using the photomask (PM) described above, the region where the light of the photomask (PM) is transmitted in the substantially negative manner is not etched in the etching process because the planarizing film (PLN) And a region having a low transmittance is partially etched so that a low level planarizing film (PLN) is disposed, and a region where light is not transmitted is completely etched.

Another way is the positive approach. Positive method is a method in which a region exposed to light is etched using a photomask (PM) in contrast to the above-described method.

As described above, in the positive type exposure method among the negative type and positive type exposure methods described above, a finer process can be performed, which is advantageous in disposing a structure having a relatively small width or a fine electrode. In addition, the photomask (PM) used in the two methods must be designed in different forms.

The method of designing the photomask (PM) according to the difference of the exposure method may be different from each other. In the above-described example, the process of disposing the planarizing film (PLN) has been described based on the Negative method.

However, in recent years, an ultra-high-resolution display device has been developed and a positively-based exposure method can be used when a finer process is required for disposing the planarizing film (PLN). The two types of exposure methods can be selectively used in various embodiments to which the present invention can be applied.

That is, in the embodiment of the present invention, when the positive exposure method is applied, the light transmittance of the second light transmitting area A2 of the photomask PM is lower than the light transmittance of the third light transmitting area A3 May be higher than the light transmittance of the first light transmitting region A1.

FIG. 11 is a schematic view for explaining a region corresponding to the pad portion of the photomask for the exposure process, and FIG. 12 is a schematic view for explaining the edge of the pad electrode and the photomask corresponding to the X region of FIG. Fig.

11, the photomask PM defines a third light transmitting region A3 and a second light transmitting region A2 and at least a part of the edge of the pad electrode PE is a second light transmitting region A2. When the negative process is used in the exposure process, the transmittance of the second light transmitting region A2 is higher than that of the third light transmitting region A3. However, in the positive exposure method, the transmittance of the second light transmitting region A2 is lower than that of the third light transmitting region A3.

The pad electrode PE may be arranged in substantially the same material as the source electrode SE or the drain electrode DE when the source electrode SE and the drain electrode DE are multilayered, A double layer, a triple layer of titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

The planarizing layer (PLN) must be opened because the pad electrode (PE) has to be electrically connected through the conductive film, and the planarizing layer (PLN) coated with the etching solution is opened. At this time, aluminum (AL) of the above-mentioned material constituting the pad electrode (PE) reacts rapidly with the etching liquid, so that the etchant is eroded at the rim of the pad electrode (PE) PE) may cause corrosion.

11, when the photomask PM corresponding to the rim portion of the pad electrode PE of the display panel 100 is made to correspond to the second light transmitting region A2, A portion of the planarizing film PLN may be left in the edge region of the pad electrode PE to cover the pad electrode PE when the flattened film PLN is opened through the etching process, Can be minimized.

Next, with reference to FIG. 12, a description will be made of a configuration in which the edge portion of the pad electrode PE described above further minimizes damage by the etching solution. The transmittance of the second light transmitting region A2 is adjusted according to the width and the width of the slit disposed in the photomask PM.

The second light transmitting region A2 having the slit may be arranged such that the planarizing layer PLN covers the edge region of the pad electrode PE in the post-exposure etching process. The planarizing layer PLN ) May be uneven. When the direction of the slit is adjusted as in the case of the second light transmitting region A2 of the photomask PM shown in Fig. 12, the blocking portion CA and the opening OA are arranged at the rim of the pad electrode PE And in a subsequent exposure and etching process, a part of the planarization layer (PLN) is arranged so as to cover the rim of the pad electrode (PE), and can be arranged to have a more uniform height. That is, the planarization layer PLN can be disposed with a uniform thickness corresponding to the direction of the boundary of the pad electrode PE.

As described above, the planarization layer (PLN) is disposed at a uniform thickness in correspondence with the direction of the boundary of the pad electrode (PE) to oxidize the pad electrode (PE) by the etchant generated at the edge of the pad electrode Can be further minimized.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SIC: Data driver GIC: Gate driver
S-COF, G-COF: Flexible circuit board PLN1: Pixel planarization film
PLN2: Pad protection part PE: Pad electrode
ACF: Anisotropic conductive film

Claims (11)

Data lines and gate lines arranged in a display area;
A plurality of data lines or gate lines disposed in the non-display region;
A pad electrode connected to any one of the links; And
And a pad protecting portion surrounding the side edges and the upper edges of the pad electrode,
Wherein the pad protecting portion is made of the same material as the pixel planarizing film located on the source electrode and the drain electrode of the transistor disposed in the display region, and the thickness of the pad protecting portion is thinner than the thickness of the pixel planarizing film. The method according to claim 1,
Wherein the pad electrode comprises the same metal layer as the source electrode of the display region. The method according to claim 1,
The source electrode is disposed in a metal layer different from a gate electrode of the transistor with an insulating film interposed therebetween,
And the links are made of the same gate metal layer as the gate electrode. Forming a transistor disposed in the display region and a pad electrode disposed in the non-display region;
Forming a planarization layer covering the transistor and the pad electrode; And
Forming a pixel planarization film covering the transistor in the display region by selectively etching the planarization film, forming a pad protection hole for exposing a part of the pad electrode, and a pad protection portion surrounding and covering the side edge and the upper edge of the pad electrode, Lt; / RTI >
Wherein the forming of the pad protecting portion is performed such that the thickness of the pad protecting portion is thinner than the thickness of the pixel flattening film. 5. The method of claim 4,
The step of selectively etching the planarization layer
Aligning the mask on the planarizing film and performing an exposure process; And
Removing the photomask and etching the photomask,
The photomask
A first light transmitting region arranged in a region where the pad holes are arranged;
A second light transmitting region arranged in a region where the pad protecting section is disposed; And
And a third light transmitting region arranged in a region where the pixel planarizing film is disposed,
Wherein the light transmittance of the second light transmitting region is higher than the light transmittance of the third light transmitting region and lower than the light transmittance of the first light transmitting region or higher than the light transmittance of the first light transmitting region, The light transmittance of the region is lower than the light transmittance of the region. 6. The method of claim 5,
The second light transmitting region of the photomask
A blocking unit for blocking light emitted in the exposure process; And
And an opening portion through which the light is transmitted,
Wherein the width of the blocking portion is 1 to 2 占 퐉 and the width of the opening is 0.5 to 1 占 퐉. The method according to claim 6,
Wherein at least a portion of the blocking portion and the transmissive portion of the photomask are parallel to a peripheral portion of the pad electrode. 5. The method of claim 4,
The step of forming the transistor
Forming an active layer;
Forming a gate electrode on the gate insulating film covering the active layer; And
Forming a source electrode and a drain electrode by using a source metal layer on an insulating film covering the gate electrode,
Wherein the pad electrode is formed using the source metal layer. A photomask for selectively exposing a planarization film covering a transistor and a pad electrode formed on a display panel,
A first light transmitting region arranged in a region where a pad hole in which a part of the pad electrode is exposed is arranged;
A second light transmitting region arranged in a region in which the pad protecting portion that covers and covers the pad electrode is disposed; And
And a third light transmitting region arranged in a region where a pixel planarizing film covering the transistor is arranged,
The light transmittance of the second light transmitting region is higher than the light transmittance of the third light transmitting region and lower than the light transmittance of the first light transmitting region or higher than the light transmittance of the first light transmitting region, Lt; RTI ID = 0.0 > light transmittance. ≪ / RTI > 10. The method of claim 9,
The second light transmitting region of the photomask
A blocking unit for blocking light emitted in the exposure process; And
And an opening portion through which the light is transmitted,
Wherein the shielding portion has a width of 1 탆 to 2 탆 and a width of the opening is 0.5 탆 to 1 탆. 11. The method of claim 10,
Wherein at least a portion of the blocking portion and the transmissive portion of the photomask are parallel to the periphery of the pad electrode.

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