KR20180065881A - Multi-core processor and cache management method thereof - Google Patents

Abstract

Provided is a cache structure or a processor structure capable of easily detecting and correcting faults in a multi-core system. According to an embodiment of the present invention, a multi-core processor connected to a main memory or a peripheral device and having a dual modular redundancy mode in which each processor performs an identical task includes: a first processor for generating first write-in data by performing the task, and writing the first write-in data to the main memory or the peripheral device after a fault detection operation on the first write-in data; a second processor for generating second write-in data by performing the task, and preventing the second write-in data from being written to the main memory or the peripheral device after the fault detection operation on the second write-in data; and a fault manager for performing the fault detection operation of comparing the first write-in data with the second write-in data during the dual modular redundancy mode, wherein the first write-in data is written to the main memory by using a first data cache, and the first data cache is managed using a dirty bit indicating whether to synchronize with the main memory.

Description

[0001] MULTI-CORE PROCESSOR AND CACHE MANAGEMENT METHOD THEREOF [0002]

The present invention relates to a processor, and more particularly, to a multicore processor including a plurality of processors and a cache management method thereof.

An application area of a central processing unit (hereinafter referred to as a CPU) has been extensively applied to all fields of the system semiconductor. A processor can read a program from a main memory and perform an operation according to a procedure. The processor can then store the result of the operation (i.e., the result of the operation) in the main memory. To improve performance and speed of data exchange between the processor and the main memory, a cache may be placed between the processor and main memory. Some of the processing results of the processor or programs stored in the main memory may be stored in the cache. The cache is much faster to read and write than main memory, represented by DRAM. In addition, when using a cache located between the processor and the main memory, it is possible to monitor the operation error of the processor or correct the monitored error.

In recent years, the use of multi-core technology and cache memory has become important in order to provide high performance and high reliability required in a system. In addition, technologies for providing multicore technology and cache coherency are actively applied to various mobile devices according to high performance requirements. In a multi-core CPU that requires such high performance and high reliability, a technology for recognizing and recovering a CPU fault is absolutely necessary.

The present invention provides a cache structure or a structure of a processor capable of easily detecting and correcting faults in a multi-core system having a variable redundancy function using a cache memory.

A multicore processor connected to a main memory according to an embodiment of the present invention and having a dual modular redundancy mode in which each of the processors performs the same task executes the task to generate first write data, A first processor that writes the first write data to the main memory or a peripheral device after an error detection operation on the data, generates the second write data by performing the task, and after the error detection operation on the second write data A second processor for interrupting transmission of the second write data to the main memory or a peripheral device, and performing the error detection operation for comparing the first write data and the second write data in the dual modular redundancy mode Wherein the first write data comprises a first data cache Use is written to the main memory or the peripheral device, in which said first data cache is managed by using the dirty bit indicating whether a synchronization with the main memory.

A cache management method of a multicore processor having a dual modular redundancy mode in which a first processor and a second processor perform the same task according to an embodiment of the present invention includes the steps of: Comparing the first write data with the second write data generated as a result of execution of the task from the second processor, and storing the first write data in the first data cache and the second write data in the second data cache And writing the first write data stored in the first data cache to the main memory according to a result of the comparison, wherein a write operation from the second data cache to the main memory is interrupted.

The processor system according to the embodiment of the present invention performs efficient error detection and correction of a multicore having a variable redundancy function. Thus, the high reliability of the multicore processor can be provided.

1 is a block diagram illustrating a multicore processor according to an embodiment of the present invention.
2 is a block diagram illustrating in more detail the functionality of a dual core processor in a dual modular redundancy (DMR) mode of the present invention.
3 is a flowchart briefly showing the operation of the error manager of FIG.
4 is a flow chart showing the operation of the reading core.
5 is a flow chart showing the operation of the trailing core.
6 is a block diagram illustrating the functionality of a dual core processor in a dual core (DC) mode of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

1 is a block diagram illustrating a multicore processor according to an embodiment of the present invention. Referring to FIG. 1, the multicore processor 100 of the present invention includes a first processor 110, a second processor 120, an error manager 130, a recovery module 140, and a reset module 150 can do. The multicore processor 100 accesses the main memory 200 or the peripheral device 300 to write or read data.

The multicore processor 100 of the present invention can operate in two operation modes of a dual-core (DC) mode and a dual-modular redundancy (DMR) mode. In the dual core (DC) mode, the first processor 110 and the second processor 120 each independently process the task and access the main memory 200 or the peripheral device 300 independently. On the other hand, in the dual modular redundancy (DMR) mode, the first processor 110 operates as a leading core and the second processor 120 operates as a trailing core. That is, in the dual modular redundancy (DMR) mode, the first processor 110 and the second processor 120 perform the same task. However, in the dual modular redundancy (DMR) mode, only the first processor 110, which is a leading core, has write access to the main memory 200. [ In the dual modular redundancy (DMR) mode, the first processor 110 has write or read access rights to the peripheral device 300. In the dual modular redundancy (DMR) mode, the second processor 120, which is the trailing core, only has the read permission to the main memory 200 and applies the operation result to the main memory 200, It is controlled so as not to be changed.

The first processor 110 may include a first processor core 112 and a first cache unit 114. The first processor core 112 performs various operations for performing a task within the first processor 110. [ The first cache unit 114 provides a cache function to the first processor core 112.

In the dual-core (DC) mode, the first processor 110 exchanges data Data1 with the main memory 200 or the peripheral device 300 using the first cache unit 114. [ The exchanged data Data1 includes read data read from the main memory 200 and write data generated by the first processor 110 and written into the main memory 200. [ For example, the first processor 110 reads a program loaded in the main memory 200 and sequentially executes the program. At this time, the first processor 110 stores data to be frequently read or data to be updated in the first cache unit 114. Further, the first processor 110 stores the data generated from the execution result of the program in the first cache unit 114. [ The data cached in the first cache unit 114 may include a dirty bit indicating whether the data is coincident with the main memory 200 or the peripheral device 300. [ Whether or not data to be updated on the first cache unit 114 by the dirty bit is synchronized with the main memory 200 is managed. The first cache unit 114 may include a first error detector 116 for detecting if there is an error in the data of the first cache unit 114. The first error detector 116 detects an error in the data stored in the first cache unit 114 and transfers the trap signal F_trap1 for restoring the error to the recovery module 140. [

On the other hand, in the dual modular redundancy (DMR) mode, data stored in the first cache unit 114 of the first processor 110 is also transferred to the error manager 130. Then, the data whose error detection has been completed by the error manager 130 will be transferred to the main memory 200. Particularly, in the dual modular redundancy (DMR) mode, the first processor 110 can read data from the main memory 200 or the peripheral device 300. The read data provided from the main memory 200 is stored in the first cache unit 114 and transferred to the error manager 130. [ The error manager 130 transfers the data read from the peripheral device 300 among the delivered read data to the second cache unit 124 of the second processor 120. That is, in the dual modular redundancy (DMR) mode, the first processor 110 may have access to write or read data to or from the main memory 200 or the peripheral device 300. The first processor 110 reads the programs loaded in the main memory 200 and sequentially executes them. At this time, the first processor 110 stores data to be read at high speed or frequently in the first cache unit 114.

The second processor 120 may include a second processor core 122 and a second cache unit 124. The second processor core 122 performs operations to process all of the programs within the second processor 120. The second cache unit 124 provides a cache function to the second processor core 112. The second processor 120 exchanges data Data2 with the main memory 200 or the peripheral device 300 only in the dual core (DC) mode.

In the dual-core (DC) mode, the second processor 120 reads and sequentially executes the programs loaded in the main memory 200. At this time, the second processor 120 stores the data to be updated at a high speed or frequently in the second cache unit 124. The second processor 120 stores the data generated from the execution result of the program in the second cache unit 124. [ In a dual core (DC) mode that operates independently of the first processor 110, the data cached in the second cache unit 124 may include a dirty bit for synchronization with the main memory 200 have. The second cache unit 124 may include a second error detector 126 for detecting whether there is an error in the data cached in the second cache unit 124. The second error detector 126 detects an error in the data stored in the second cache unit 124 and transfers the trap signal F_trap2 to the recovery module 140 for recovering the error.

On the other hand, in the dual modular redundancy (DMR) mode, the writing of data stored in the second cache unit 124 of the second processor 120 to the main memory 200 is interrupted and transferred to the error manager 130 only. The error manager 130 compares the data (including the address) transmitted from the first processor 110 with the data transmitted from the second processor 120 to determine the error of the multicore processor 100. The data returned from the error manager 130 is stored in the second cache unit 124. [ However, in the dual modular redundancy (DMR) mode, the second processor 120 reads data from the main memory 200 but does not write data to the main memory 200. Therefore, in the dual modular redundancy (DMR) mode, the dirty bit management for the main memory 200 of the second cache unit 124 need not be performed. In addition, in the dual modular redundancy (DMR) mode, the second processor 120 does not access the peripheral device 300. The error manager 130 receives the dual And may be provided with register information DMR_EN for activating the modular redundancy (DMR) mode. If the value of the DMR register (not shown) of the first processor 110 and the second processor 120 is provided as an enable (DMR_EN), the error manager 130 performs an error detection operation according to the dual modular redundancy (DMR) . That is, the error manager 130 compares data provided from the first processor 110 and the second processor 120 in the dual modular redundancy (DMR) mode to determine whether the operation is error-free. The error manager 130 determines that the operation error of the dual core processor 100 is an error when the data provided from the first processor 110 and the second processor 120 are not the same. Then, the error manager 130 transmits an error flag signal Fault_flag to the recovery module 140. On the other hand, if the value of the DMR register (not shown) written in the first processor 110 and the second processor 120 is provided as the disable (DMR_DIS), the error manager 130 can detect a dual core Lt; RTI ID = 0.0 > mode < / RTI >

When an operation error of the first processor 110 and the second processor 120 is detected, the recovery module 140 performs all control operations to recover the detected error. In the dual-core (DC) mode, the recovery module 140 may perform an error recovery operation in response to the error trap signal F_Trap1 from the first error detector 116 of the first processor 110. [ In addition, the recovery module 140 may perform the error recovery operation in response to the error trap signal F_Trap2 from the second error detector 126 of the second processor 120. [ In addition, in the dual modular redundancy (DMR) mode, the recovery module 140 can perform the error recovery operation in response to the error flag signal Fault_flag provided from the error manager 130.

The reset module 150 may reset the first processor 110 or the second processor 120 under the control of the recovery module 140. In addition, the reset module 150 may generate a system reset (RST_SYS) signal to perform a reset of the system including the dual core processor 100 under the control of the recovery module 140.

The main memory 200 may store various data generated from an operating system (OS), application programs, and the dual core processor 100. The main memory 200 may be accessed from both the first processor 110 and the second processor 120 in the dual core (DC) mode. However, in the dual modular redundancy (DMR) mode, reading and writing to the main memory 200 of the first processor 110 corresponding to the leading core is allowed. In the dual modular redundancy (DMR) mode, the second processor 120 corresponding to the trailing core is only allowed to read the main memory 200.

As described above, the dual core processor 100 of the present invention has different operation modes of the dual core (DC) mode and the dual modular redundancy (DMR) mode. The caches managed by the first processor 110 and the second processor 120 may be differentially managed according to the respective modes. In particular, according to the error manager 130 of the present invention, errors can be easily detected by monitoring the caches of the first processor 110 and the second processor 120 in the dual modular redundancy (DMR) mode. That is, in the dual modular redundancy (DMR) mode, the second processor 120, which is a trailing core, processes the program but operates the cache in such a manner that writing to the main memory 200 is interrupted. Therefore, the performance of error detection and recovery in the dual modular redundancy (DMR) mode can be improved.

2 is a block diagram illustrating in more detail the functionality of a dual core processor in a dual modular redundancy (DMR) mode of the present invention. Referring to FIG. 2, in the dual modular redundancy (DMR) mode, the first processor 110 operates as a leading core and the second processor 120 operates as a trailing core. The error manager 130 detects an operation error based on data provided from the cache of the first processor 110 and the second processor 120.

For operation in accordance with the dual modular redundancy (DMR) mode, the first cache unit 114 included in the first processor 110 includes a first write buffer 111, a first DMR register 113, A cache 115, a first error detector 116, and a first data cache 117. The second cache unit 124 included in the second processor 120 includes a second write buffer 121, a second DMR register 123, a second instruction cache 125, a second error detector 126, And a second data cache 127.

First, the first processor core 112 and the second processor core 122 write DMR enable (DMR_EN) to the DMR registers 113 and 123, respectively, to activate the dual modular redundancy (DMR) mode. Then, the first processor 110 and the second processor 120, which independently perform the task in the dual core mode, switch their operation to the leading core and the trailing core, respectively. That is, in the dual modular redundancy (DMR) mode, the first processor core 112 and the second processor core 122 perform the same task. At this time, the operating frequencies of the first processor 110 and the second processor 120 may be different. For example, the operating frequency of the first processor 110, which is a leading core, may be greater than the operating frequency of the second processor 120, which is a trailing core. In addition, depending on the values of the DMR registers 113 and 123, the error manager 130 may activate an error detection operation that compares the data generated by the first processor 110 and the second processor 120 with each other.

In the dual modular redundancy (DMR) mode, the first processor 110 operating as a leading core can write or read data to or from the main memory 200. That is, the first processor 110 transfers the write address Waddr and the write data Wdata to the main memory 200 or receives the read address Waddr and the read data Rdata from the main memory 200 . On the other hand, the second processor 120 is only allowed to read in the main memory 200 in the dual modular redundancy (DMR) mode. The second processor 120 generates a write address Waddr and write data Wdata in a dual modular redundancy (DMR) mode. However, in the dual modular redundancy (DMR) mode, the second processor 120 does not transfer the write address Waddr and the write data Wdata to the main memory 200. Instead, in the dual modular redundancy (DMR) mode, the second processor 120 provides the write address Waddr and the write data Wdata only to the error manager 130.

More specifically, the first processor core 112, which operates as a reading core in the dual modular redundancy (DMR) mode, generates a write address Waddr and write data Wdata and writes them into the first write buffer 111 something to do. Then, the write address Waddr and the write data Wdata written in the first write buffer 111 are transferred to the error manager 130. [ Likewise, the second processor core 122, which operates with the trailing core, will perform the same task as the first processor core 112. The second processor core 122 will generate the write address Waddr and the write data Wdata and write it into the second write buffer 121. [ Then, the write address Waddr and the write data Wdata written in the second write buffer 121 are transmitted to the error manager 130. [

In the dual modular redundancy (DMR) mode, the error manager 130 compares write addresses Waddr and write data Wdata provided from the first write buffer 111 and the second write buffer 121, respectively. After the comparison, the error manager 130 returns the write address Waddr and the write data Wdata to the first data cache 117 and the second data cache 127. If the write address Waddr and the write data Wdata provided from the first write buffer 111 and the second write buffer 121 are different from each other, the error manager 130 determines that the operation error is an error. The error manager 130 will then send an error flag or error trap information to the recovery module 140 (see FIG. 1). At this time, the first error detector 116 included in the first cache unit 114 and the second error detector 126 included in the second cache unit 124 are connected to the first data cache 117, And error trap information to the recovery module 140. In this case,

The write address Waddr and the write data Wdata stored in the first data cache 117 are transferred to the main memory 200 using a dirty bit in both the dual core DC mode and the dual modular redundancy mode, Lt; / RTI > However, in the dual modular redundancy (DMR) mode, the write address Waddr and the write data Wdata stored in the second data cache 127 do not need to apply a dirty bit. This is because data writing from the second data cache 127 to the main memory 200 does not occur in the dual modular redundancy (DMR) mode.

In the dual modular redundancy (DMR) mode, the read address Raddr_M and the read data Rdata_M transferred from the main memory 200 are stored in the first data cache 117 and the second data cache 127. The first data cache 117 and the read address Raddr_M and the read data Rdata_M stored in the second data cache 127 will be transmitted to the error manager 130. On the other hand, the read address Raddr_P and the read data Rdata_P transmitted from the peripheral device 300 in the dual modular redundancy (DMR) mode are first stored in the first data cache 117 in advance. The read address Raddr_P and the read data Rdata_P stored in the first data cache 117 will be transferred to the second data cache 127 after being transferred to the error manager 130.

In particular, in the dual modular redundancy (DMR) mode, the operating frequency of the first processor 110, which is the leading core, may be greater than the operating frequency of the second processor 120, which is the trailing core. In the dual modular redundancy (DMR) mode, the first processor 110 and the second processor 120 can perform independent read operations in the main memory 200, respectively. Therefore, in the dual modular redundancy (DMR) mode, the processing times of the first processor 110 and the second processor 120 may be randomly varied even if the same task is performed due to different operating frequencies. Due to the asynchronism caused by the difference in the operating frequencies, temporal redundancy can be additionally provided.

In addition, the read address (Raddr_P) and the read data (Rdata_P) transmitted from the peripheral device (300) are stored first in the first data cache (117). The read address Raddr_P and the read data Rdata_P stored in the first data cache 117 will be transferred to the second data cache 127 after being transferred to the error manager 130.

In the dual modular redundancy (DMR) mode, the error manager 130 compares the write address Waddr of the first processor 110 with the write data Wdata of the second processor 120, Occurrence. The error manager 130 then returns the write address Waddr and the write data Wdata to the data caches 117 and 127 of the first and second processors 110 and 120, respectively. At this time, only the write address Waddr and the write data Wdata of the first data cache 117 corresponding to the leading core will be transferred to the main memory 200.

3 is a flowchart briefly showing the operation of the error manager of FIG. Referring to FIG. 3, the error manager 130 may compare the data of the first processor 110 and the second processor 120, which perform the same task, in the dual modular redundancy (DMR) mode to detect an error . In the dual modular redundancy (DMR) mode, the first processor 110 and the second processor 120 perform the same task but can operate at different operating frequencies. For example, the operating frequency of the first processor 110, which is the leading core in the dual modular redundancy (DMR) mode, may be higher than the operating frequency of the second processor 120, which is the trailing core.

In step S110, the error manager 130 reads the DMR registers 113 and 123 included in the first cache unit 114 and the second cache unit 124, respectively. The DMR registers 113 and 123 are set by the first processor core 112 and the second processor core 122, respectively.

In step S120, the error manager 130 refers to the values stored in the DMR registers 113 and 123 to perform an operation branch. If the values stored in the DMR registers 113 and 123 are each the enable state DMR_EN (YES direction), the procedure moves to step S140. On the other hand, if the values stored in the DMR registers 113 and 123 are not the enable state (DMR_EN), respectively, the procedure moves to step S130.

In step S130, the error manager 130 will perform the functions of the previous dual core mode. For example, the error manager 130 will only serve to provide a reset signal (RST) signal to the first cache unit 114 and the second cache unit 124. [

In step S140, the error manager 130 receives the write address Waddr and the write data Wdata provided from the first write buffer 111 and the second write buffer 121, respectively.

In step S150, the error manager 130 compares write addresses Waddr and write data Wdata generated by the first processor 110 and the second processor 120 that have performed the same task. If the write addresses Waddr and write data Wdata generated by the first processor 110 and the second processor 120 are the same (YES direction), the procedure moves to step S150. On the other hand, if the write addresses Waddr and write data Wdata generated by the first processor 110 and the second processor 120 are different (No direction), the procedure moves to step S170.

The error manager 130 transfers the write address Waddr and the write data Wdata to the first data cache 117 and the second data cache 127 in step S160. The write address Waddr and the write data Wdata provided in the first data cache 117 can be updated using the dirty bit. However, the data in the second data cache 127 need not be synchronized with the main memory 200 utilizing the dirty bit. This is because, in the dual modular redundancy (DMR) mode, writing of data in the second data cache 127 to the main memory 200 is interrupted. Thereafter, the procedure returns to step S140 for additional error detection.

In step S170, the error manager 130 determines that an error has occurred in the operation of the dual modular redundancy (DMR) mode, and transmits an error flag or error trap information to the recovery module 140 (see FIG. 1). At this time, the first error detector 116 included in the first cache unit 114 and the second error detector 126 included in the second cache unit 124 are connected to the first data cache 117, And the second data cache 127, and to transmit the error trap information to the recovery module 140.

The operation of the error manager 130 for performing error detection and recovery in a dual modular redundancy (DMR) mode in which the first processor 110 and the second processor 120 perform the same task has been briefly described. The error manager 130 will compare the incoming data only in the dual modular redundancy (DMR) mode to detect operational errors.

4 is a flowchart briefly showing the operation of the first processor corresponding to the leading core. Referring to FIG. 4, the first processor 110 performs a task independently of the second processor 120 in a dual core (DC) mode. On the other hand, the first processor 110 performs the same task as the second processor 120 in the dual modular redundancy (DMR) mode. That is, the first processor 110 operating as a leading core can access the main memory 200 regardless of the operation mode.

In step S210, the first processor 110 monitors whether a request for execution of a dual modular redundancy (DMR) mode by software or a user request is received. If it is determined that an execution request of the dual modular redundancy (DMR) mode exists (YES direction), the procedure moves to step S220. However, if it is determined that there is no execution request of the dual modular redundancy (DMR) mode (No direction), the procedure moves to step S215.

In step S215, the first processor 110 will control the first cache unit 114 in accordance with the dual core (DC) mode. That is, the first processor 110 transfers the write address Waddr and write data Wdata written in the first write buffer 111 to the first data cache 117 without transferring the write address Waddr and write data Wdata to the error manager 130 . The first processor 110 may transmit the read address Raddr and the read data Rdata from the main memory 200 to the first processor core 112 without passing through the error manager 130. [

In step S220, the first processor 110 sets the DMR register 113 in response to the execution request of the dual modular redundancy (DMR) mode. The first processor 110 will write the enable state (DMR_EN) to the DMR register 113. The error manager 130 will then perform an error detection operation that is activated in a dual modular redundancy (DMR) mode.

The first processor 110 writes the write address Waddr and the write data Wdata generated in the first processor core 112 in the first write buffer 111 in step S230. The first processor 110 transfers the write address Waddr and the write data Wdata written in the first write buffer 111 to the error manager 130. [ The error manager 130 will perform the error detection operation according to the dual modular redundancy (DMR) mode using the write address Waddr and the write data Wdata. The error manager 130 will then return the write address Waddr and the write data Wdata to the first processor 110.

The first processor 110 writes the write address Waddr and the write data Wdata returned from the error manager 130 in the first data cache 117 in step S240. The first processor 110 can manage the write address Waddr and the write data Wdata of the first data cache 117 using dirty bits.

The first processor 110 writes the updated write data Wdata in the first data cache 117 to the main memory 200 or the peripheral device 300 in step S250.

In step S260, the first processor 110 monitors whether a reset signal RST is provided. A reset signal RST may be provided if a reset to the first processor 110 is required due to an error detected by the error manager 130 or the first error detector 116. [ If there is a reset signal RST (YES direction), all operations of the first processor 110 will end. On the other hand, if the reset signal RST is not present (No direction), the procedure will return to step S210 for monitoring the operating mode of the first processor 110. [

5 is a flowchart briefly showing the operation of the second processor corresponding to the trailing core; Referring to FIG. 5, the second processor 120 performs a task independently of the first processor 110 in a dual core (DC) mode. On the other hand, the second processor 120 performs the same task as the first processor 110 in the dual modular redundancy (DMR) mode. The second processor 120 operating as a trailing core can write or read data in the main memory 200 in the dual core DC mode. However, in the dual modular redundancy (DMR) mode, 120 to the main memory 200, and writing will be interrupted.

In step S310, the second processor 120 monitors whether a request for execution of a dual modular redundancy (DMR) mode by software or a user request is received. If it is determined that an execution request of the dual modular redundancy (DMR) mode exists (YES direction), the procedure moves to step S320. However, if it is determined that there is no execution request of the dual modular redundancy (DMR) mode (No direction), the procedure moves to step S315.

In step S315, the second processor 120 will control the second cache unit 124 in dual core (DC) mode. That is, the second processor 120 transfers the write address Waddr and the write data Wdata written in the second write buffer 121 to the second data cache 127 without transferring the write address Waddr and the write data Wdata to the error manager 130 . The second processor 120 directly writes the write address Waddr and the write data Wdata of the second data cache 127 in the dual core mode to the main memory 200 and the peripheral device 300 . In the dual-core (DC) mode, the second processor 120 reads the read address Raddr and the read data Rdata from the main memory 200 via the second processor core 122).

In step S320, the second processor 120 sets the second DMR register 123 in response to the execution request of the dual modular redundancy (DMR) mode. The second processor 120 will write the DMR mode to the second DMR register 123 in the enabled state (DMR_EN). The error manager 130 will then perform an error detection operation that is activated in a dual modular redundancy (DMR) mode.

The second processor 120 writes the write address Waddr and the write data Wdata generated in the second processor core 122 in the second write buffer 121 in step S330. The second processor 120 transfers the write address Waddr and the write data Wdata written in the second write buffer 121 to the error manager 130. [ The error manager 130 will detect an error in the dual modular redundancy (DMR) mode using the write address Waddr and write data Wdata. The error manager 130 will then return the write address Waddr and the write data Wdata to the second processor 120.

The second processor 120 writes the write address Waddr and the write data Wdata returned from the error manager 130 in the second data cache 127 in step S340. At this time, since the write address Waddr and the write data Wdata stored in the second data cache 127 do not have to be written to the main memory 200 or the peripheral device 300, It does not need to be done.

In step S350, the second processor 120 monitors whether a reset signal RST is provided. A reset signal RST may be provided if a reset to the second processor 120 is required due to an error detected by the error manager 130 or the second error detector 126. [ If there is a reset signal RST (YES direction), all operations of the second processor 120 will be terminated. On the other hand, if the reset signal RST is not present (NO direction), the procedure will return to step S310 for monitoring the operating mode of the second processor 120. [

The operations of the first processor 110, the second processor 120, and the error manager 130 in the dual modular redundancy (DMR) mode have been briefly described above. In the dual modular redundancy (DMR) mode, the first processor 110 and the second processor 120 perform the same task. In another embodiment, in the dual modular redundancy (DMR) mode, the first processor 110 and the second processor 120 may perform the same task at different operating frequency conditions. The error manager 130 may compare data from the first processor 110 and the second processor 120 that have performed the same task to detect whether an error has occurred.

Figure 6 is a block diagram illustrating the functionality of a dual core processor in a dual core (DC) mode of the present invention. 6, in the dual-core (DC) mode, the first processor 110 and the second processor 120 perform tasks independently of each other, and independently perform the tasks in the main memory 200 or the peripheral device 300, Lt; / RTI > At this time, the error detecting operation of the error manager 130 is inactivated. Here, the configurations of the first processor core 112, the first cache unit 114, the second processor core 122, the second cache unit 124, and the error manager 130 are substantially the same as those of FIG. 2 same. However, as the DMR mode of the DMR registers 113 and 123 is set to the disabled state (DMR_DIS), the first processor 110 and the second processor 120 can independently access the main memory 200 .

The first cache unit 114 included in the first processor 110 includes a first write buffer 111, a DMR register 113, a first instruction cache 115, a first error detector 116, 1 < / RTI > The second cache unit 124 included in the second processor 120 includes a second write buffer 121, a second DMR register 123, a second instruction cache 125, a second error detector 126, And a second data cache 127.

In the dual core (DC) mode, the first processor core 112 and the second processor core 122 write the DMR mode to the DMR registers 113 and 123, respectively, in the disabled state (DMR_DIS). Then, the first processor 110 and the second processor 120 independently perform a task in a dual core (DC) mode. The error manager 130 will stop the comparison operation on the data generated in the first processor 110 and the second processor 120. [

In the dual core (DC) mode, the first processor 110 may operate in the same manner as the dual modular redundancy (DMR) mode except for the operation of transferring data to the error manager 130. That is, the first processor 110 writes data in the main memory 200 and reads data from the main memory 200 regardless of the error manager 130. That is, the write address Waddr and the write data Wdata generated by the first processor core 112 can be directly transferred from the first write buffer 111 to the first data cache 117. The write address Waddr and the write data Wdata stored in the first data cache 117 can be written in the main memory 200. [

In the dual core (DC) mode, the second processor 120 can generate data regardless of the operation of the first processor 110 and write the generated data to the main memory 200 or the peripheral device 300 have. That is, the second processor 120 writes data to the main memory 200 or the peripheral device 300 regardless of the task of the error manager 130 or the first processor 110, Or reads data from the peripheral device 300. For example, the write address Waddr and the write data Wdata generated by the second processor core 122 can be directly transferred from the second write buffer 121 to the second data cache 117. The write address Waddr and the write data Wdata stored in the second data cache 127 may be written to the main memory 200 or the peripheral device 300. [

In the dual core mode, the error manager 130 is deactivated, and the first processor 110 and the second processor 120 perform tasks independently of each other, and the main memory 200, Or the peripheral device 300, as shown in FIG.

In order to explain the features of the present invention, the dual-core processor 100 has been described as an example of a multicore processor. However, it will be appreciated that multiple processors are not limited to dual core processors. That is, three or more processors may be able to operate as the leading and trailing cores according to each mode of operation. At this time, the error manager 130 may compare the data stored in the cache of each processor to detect the presence of an error.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

Claims (17)

CLAIMS 1. A multicore processor, connected to a main memory or a peripheral device, having a dual modular redundancy mode in which each of the processors performs the same task:
A first processor for performing the task to generate first write data and writing the first write data to the main memory or the peripheral device after an error detection operation for the first write data;
A second processor for performing the task to generate second write data and for interrupting writing of the second write data to the main memory or the peripheral device after an error detection operation for the second write data; And
And an error manager for performing the error detection operation for comparing the first write data and the second write data in the dual modular redundancy mode,
Wherein the first write data is written to the main memory using a first data cache and the first data cache is managed using a dirty bit indicating whether to synchronize with the main memory. The method according to claim 1,
The first processor comprising:
A first processor core for generating the first write data; And
And a first cache unit including the first data cache for transferring the first write data to the main memory in the dual modular redundancy mode. 3. The method of claim 2,
Wherein the first cache unit comprises:
A first write buffer for storing the first write data transferred from the first processor core;
A first DMR register coupled to the first write buffer, the first DMR register indicating whether the dual modular redundancy mode is activated; And
And a first error detector for detecting an error of the first write data stored in the first data cache. The method of claim 3,
The second processor comprising:
A second processor core for generating the second write data; And
And a second cache unit for providing said second write data to said error manager in said dual modular redundancy mode, but forbidden to write to said main memory. 5. The method of claim 4,
The second cache unit comprising:
A second write buffer for storing the second write data and transferring the stored second write data to the error manager;
A second DMR register, coupled to the second write buffer, for writing whether to activate the dual modular redundancy mode; And
And a second data cache for storing the second write data returned from the error manager. 6. The method of claim 5,
Wherein the second data cache does not generate a dirty bit for the second write data. 6. The method of claim 5,
Wherein the second cache unit further comprises a second error detector for detecting an error of the second write data stored in the second data cache. 6. The method of claim 5,
Wherein the error manager executes the error detection operation when a value stored in each of the first DMR register and the second DMR register indicates the dual modular redundancy mode. The method according to claim 1,
In a dual core mode, the first processor and the second processor perform different tasks, and the error manager deactivates the error detection operation. The method according to claim 1,
Further comprising a recovery module for receiving an error flag signal generated by the error manager according to a result of the error detection operation and correcting errors of the first processor and the second processor. 11. The method of claim 10,
And a reset module for resetting the first processor and the second processor under the control of the recovery module. The method according to claim 1,
Wherein in the dual modular redundancy mode, the first processor and the second processor operate at different operating frequencies. 13. The method of claim 12,
Wherein in the dual modular redundancy mode, the operating frequency of the first processor is higher than the operating frequency of the second processor. A cache management method for a multicore processor having a dual modular redundancy mode in which a first processor and a second processor perform the same task, the method comprising:
Comparing the first write data generated as a result of the task from the first processor with the second write data generated as a result of performing the task from the second processor;
Storing the first write data in a first data cache and the second write data in a second data cache; And
And writing the first write data stored in the first data cache to a main memory or a peripheral device according to a result of the comparison,
Wherein a write operation from the second data cache to the main memory or the peripheral device is blocked. 15. The method of claim 14,
Wherein the dirty bit for managing the update of the first write data is stored in the first data cache. 15. The method of claim 14,
And generating an error trap signal for correcting an operation error of the first processor and the second processor when the first write data and the second write data differ from each other in the comparing step . 15. The method of claim 14,
Wherein in the dual modular redundancy mode, the operating frequency of the first processor is higher than the operating frequency of the second processor.

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