KR20180065855A - Digital analog converter achieving small peak value of discharging current and method of operating the same - Google Patents

Abstract

Disclosed are a digital analog converter which can perform all types of discharging within one phase while reducing a peak current, and an operation method thereof. The digital analog converter comprises: an amplifier; a charging device connected to one of input terminals of the amplifier; and a discharging control unit for differentially discharging a charging voltage of the charging device into first and second discharging sections. A time constant of the first discharging section is greater than that of the second discharging section.

Description

TECHNICAL FIELD [0001] The present invention relates to a digital analog converter for realizing a small peak current and a method of operating the same. [0002]

The present invention relates to a digital-to-analog converter that performs all discharges in one phase while realizing a small peak current and an operation method thereof.

Delta-Sigma analog-to-digital converters (ADCs) typically require a digital-to-analog converter (DAC) that converts the digital output of a quantizer to analog and feeds back the analog signal to a loop filter.

Conventionally, a digital-to-analog converter having an NRZ-type output waveform is used. However, since the jitter is very sensitive to the jitter of the clock signal, the performance of the delta-sigma ADC is drastically reduced.

To improve this, various DACs have been proposed. Generally, the sensitivity to jitter is improved, but the peak current increases and the circuit becomes complicated.

KR 10-1634929 B

The present invention provides a digital-to-analog converter capable of performing all discharges within one phase while lowering the peak current and an operation method thereof.

According to an aspect of the present invention, there is provided a digital-to-analog converter comprising: an amplifier; A charging device coupled to one of the inputs of the amplifier; And a discharging controller for discharging the charging voltage of the charging device by dividing the charging voltage into a first discharging period and a second discharging period. Here, the time constant in the first discharge interval is larger than the time constant in the second discharge interval.

A digital-to-analog converter according to another embodiment of the present invention includes an amplifier; A charging device coupled to one of the inputs of the amplifier; A resistor connected to the charging element; A second switch coupled to the charging element and connected in parallel with the resistor with respect to the charging element; And a third switch having one side connected to the resistor and the second switch and the other side connected to the ground. Here, in the first discharge interval, the second switch is turned off and the third switch is turned on, so that the discharge current from the charge element is discharged to the ground via the resistor and the third switch, The second switch is turned on and the third switch is kept on, so that the discharging current from the charging device is discharged to the ground through the second switch and the third switch.

A method of operating a digital-to-analog converter according to an embodiment of the present invention includes discharging a charging voltage of a charging device through a first resistor during a first discharging period; And discharging the charging voltage of the charging device through a second resistor during a second discharging period. Here, the first resistor is larger than the second resistor, and the charging voltage of the charging device is discharged within one phase.

A digital-to-analog converter and a method of operating the same according to the present invention perform discharging by dividing a first discharge interval and a second discharge interval so that a time constant in the first discharge interval is larger than a time constant in the second discharge interval It is possible to perform all discharges in one phase while lowering the peak current.

1 is a circuit diagram showing a DAC according to an embodiment of the present invention.
2 is a circuit diagram showing a DAC for comparison with the DAC of the present invention.
3 is a diagram showing the capacitor charging voltage of the SCR DAC of FIG. 2 and the DAC of the present invention (FIG. 1).
4 is a diagram showing the capacitor charging voltage of the SCR DAC of FIG. 2 and the DAC of the present invention (FIG. 1) in a semi- log plot.
5 is a graph showing the feedback current of the DAC as a function of time.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In this specification, the terms " comprising ", or " comprising " and the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps. Also, the terms " part, " " module, " and the like described in the specification mean units for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software .

The present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC used in a delta-sigma analog-to-digital converter (ADC).

Specifically, the delta sigma ADC requires a DAC that converts a digital signal output from a quantizer having a resolution of 1 bit or several bits to an analog signal and then feeds back the analog signal to the input of the loop filter. The DAC of the present invention, Can be used for ADC.

The DAC of the present invention can have a circuit structure that has a simple structure and reduces the peak current during discharge. Particularly, the DAC can smoothly discharge within one phase while reducing the peak current.

Further, the DAC of the present invention can discharge electric charges filled in the capacitor with two time constants.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a DAC according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a DAC for contrast with the DAC of the present invention.

1, the DAC of this embodiment includes an operational amplifier 100, a first switch SW1, a charging capacitor C _DAC as a charging element, a capacitor C ₁ as a feedback element, and a discharge control section 102 as a feedback element. . ≪ / RTI >

The discharge control unit 102 may include a peak current control unit 110, a second switch SW2, and a third switch SW3.

The first switch SW1 is connected between the power supply voltage V _ref and the first node n1 and is turned on at the time of charging operation.

The peak current controller 110 serves to reduce the peak value (peak current) of the discharge current I _DAC during the discharge, and may be made of, for example, a resistor R _DAC . However, the peak current controller 110 can be modified in various ways as long as the peak current is reduced.

The resistor R _{DAC is} connected between the first node n1 and the second node n2.

The charge capacitor C _DAC may be connected to the second node n2 and the negative terminal of the OP amplifier 100 and is a charge element.

The positive terminal of the OP amplifier 100 may be connected to ground.

According to one embodiment, the negative terminal of the OP amplifier 100 may form a virtual ground due to negative feedback.

A capacitor (C ₁₎ is connected between the output terminal of the OP amp 100 and the negative extreme, that the third node (n3).

The second switch SW2 is connected in parallel with the resistor R _DAC between the second node n2 and the first node n1 and is used for quick discharge.

That is, the discharge can be sequentially performed through the first path through the resistor R _DAC and the second path through the second switch SW2. As a result, the charge charged in the charge capacitor C _DAC can be discharged with two time constants. A detailed description thereof will be described later.

The switch SW3 is connected between the first node n1 and the ground, and is turned on at the time of discharging.

Hereinafter, a circuit operation of the DAC having such a structure will be described.

Referring back to FIG. 1, in the first period? 1, the first switch SW1 and the second switch SW2 are turned on and the third switch SW3 is turned off. As a result, the power supply voltage V _ref is charged to the charge capacitor C _DAC as a path through the switches SW1 and SW2. That is, the first section? 1 is a charging section.

Then, a discharging operation is performed in the second section (? 2, first discharge section). Specifically, in the second period? 2, the third switch SW3 is turned on and the first switch SW1 and the second switch SW2 are turned off.

As a result, a current corresponding to the charging voltage of the charging capacitor C _DAC is discharged through the resistor R _DAC and the third switch SW3. In this case, the discharge current I _DAC is expressed by the following equation (1).

Here, R _ON is the resistance of the third switch SW3. Each of the switches SW1 to SW3 has R _ON .

On the other hand, if there is no resistor R _DAC as shown in FIG. 2, the discharge current I _DAC is expressed by the following equation (2).

That is, the peak value (peak current) of the discharge current I _DAC is reduced due to the resistance R _DAC .

However, when discharging through a resistor (R _DAC ) for one phase, a complete discharge may not be performed in one phase.

Accordingly, the DAC of the present invention induces a rapid discharge by a path not passing through the resistor (R _DAC ) after the discharge has progressed to some extent through the resistor (R _DAC ) so that the discharge is smoothly performed in one phase.

According to one embodiment, discharge to another path can be made in the third section (? 3, second discharge section).

Specifically, in the third period? 3, the second switch SW2 is turned on, the third switch SW3 is kept in the on state, and the first switch SW1 is kept in the off state. As a result, the discharge current I _DAC is discharged through the second switch SW2 and the third switch SW3. In this case, the effective resistance value is 2R _ON .

As a result, in the third section? 3, a discharge is performed faster than the second section? 2. In this case, since the voltage of the charge capacitor C _DAC is sufficiently away, the magnitude of the discharge current I _DAC does not increase excessively.

Further, the time constant at the second section? 2 and the time interval at the third section? 3 are different. That is, discharge is performed by using two time constants.

According to one embodiment, the time constant at the second section? 2 is larger than the time constant at the third section? 3, and as a result, the peak current is reduced at the second section? 2, Discharge can be performed.

In summary, the DAC of this embodiment has two discharge sections, and in the first discharge section, the peak value of the discharge current (I _DAC ) is lowered, and in the second discharge section, the time constant is decreased to perform a quick discharge. As a result, the DAC can perform a smooth discharge in one phase while lowering the peak value of the discharge current (I _DAC ).

In a method aspect, a method of operating a DAC includes discharging a charging voltage of a charging device through a first resistor during a first discharge interval, and discharging a charging voltage of the charging device through a second resistor during a second discharging interval . Here, the first resistor is larger than the second resistor, and the charging voltage of the charging device is discharged within one phase. Also, the second resistor may be a resistance of the switch.

Hereinafter, the experimental results will be described.

FIG. 3 is a diagram showing the capacitor charging voltage of the SCR DAC of FIG. 2 and the DAC of the present invention (FIG. 1), and FIG. 4 is a graph of the capacitor charging voltage of the DAC of FIG. FIG. 5 is a diagram showing the feedback current of the DAC as a function of time. FIG.

Was used as the _{R ON C DAC = T S /} 10 in the SCR DAC (bottom line), in the DAC (top line) of the present invention _{(R ON + R DAC) C} DAC = T S /3.5, 2R ON = T S / 20 was used. And, in the case of SCR DAC 0 <t <T _s a whole corresponds to the φ2, the case of the present invention, _{DAC 0 <t <T s /} 2 is equivalent to the φ2, and _{T s / 2 <t <T} S that corresponds to φ3 .

As shown in FIG. 3, the voltage profile of the SCR DAC has one exponential function, whereas the DAC of the present invention has two exponential functions.

Initially, the SCR DAC discharges faster, but at 3 the DAC of the present invention discharges at a steep slope. As a result, the DAC of the present invention can perform a full discharge within one phase like the SCR DAC. This discharge can also be seen in the graph seen in the semigloss plot of FIG.

Referring to FIG. 5, the SCR DAC initially has a very high peak current due to the exponential function discharge, whereas the DAC of the present invention divides into two intervals and discharges at different time constants (RC constants) It can be confirmed that the peak current is very small.

On the other hand, the components of the above-described embodiment can be easily grasped from a process viewpoint. That is, each component can be identified as a respective process. Further, the process of the above-described embodiment can be easily grasped from the viewpoint of the components of the apparatus.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

100: OP amp 102: Discharge control section
110: Peak current controller

Claims (10)

amplifier;
A charging device coupled to one of the inputs of the amplifier; And
And a discharging controller for discharging the charging voltage of the charging device into a first discharging period and a second discharging period,
Wherein the time constant in the first discharge interval is greater than the time constant in the second discharge interval. The digital-to-analog converter according to claim 1, wherein the digital-to-analog converter is used in a delta-sigma analog-to-digital converter (ADC)
Wherein the discharge control unit comprises:
A resistor connected to the charging element;
A second switch connected to the charging element and connected in parallel with the resistor with respect to the charging element; And
And a third switch having one side connected to the resistor and the second switch and the other side connected to the ground. The charging device according to claim 2, wherein in the first discharging interval, a discharging current from the charging device is discharged through the resistor and the third switch, and in the second discharging interval, And discharging through the third switch. 3. The digital-to-analog converter as claimed in claim 2, wherein the input of the amplifier connected to the charging element operates as a virtual ground. 3. The method of claim 2,
Further comprising a first switch connected between the resistor and the power supply voltage,
Wherein the first switch and the second switch are turned on and the third switch is turned off during a charging period so that the charging element is charged by the path through the first switch and the second switch. amplifier;
A charging device coupled to one of the inputs of the amplifier;
A resistor connected to the charging element;
A second switch coupled to the charging element and connected in parallel with the resistor with respect to the charging element; And
And a third switch having one side connected to the resistor and the second switch and the other side connected to the ground,
The second switch is turned off and the third switch is turned on so that the discharge current from the charging element is discharged to the ground through the resistor and the third switch in the first discharge interval, The second switch is turned on and the third switch is kept on, so that the discharging current from the charging element is discharged to the ground via the second switch and the third switch. The method according to claim 6,
Further comprising a first switch connected between the resistor and the power supply voltage,
Wherein the first switch and the second switch are turned on and the third switch is turned off during a charging period so that the charging element is charged by the path through the first switch and the second switch. The digital-to-analog converter according to claim 6, wherein the time constant in the first discharge interval is greater than the time constant in the second discharge interval. Discharging a charging voltage of the charging device through a first resistor during a first discharging period; And
Discharging the charging voltage of the charging element through a second resistor during a second discharging period,
Wherein the first resistor is greater than the second resistor and the charging voltage of the charging device is discharged within one phase. 10. The method of claim 9, wherein the second resistor is a resistor of the switch, the first resistor and the switch being connected in parallel with respect to the charging element.

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