KR20180062062A - Memory system and operating method thereof - Google Patents

Abstract

The present technique includes a memory system capable of quickly finding an error section when an error occurs during descriptor execution and an operation method thereof. The memory system comprises: a semiconductor device in which data is stored; and a memory controller sequentially processing tasks included in a descriptor to communicate with the semiconductor device, detecting an error section by checking the tasks in a reverse direction when an error occurs in the tasks, and reprocessing the tasks included in the detected error section.

Description

[0001] The present invention relates to a memory system and an operating method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system and a method of operating the same, and more particularly, to a memory system that performs a descriptor and a method of operating the same.

BACKGROUND OF THE INVENTION Memory systems are widely used as data storage devices for digital devices such as computers, digital cameras, MP3 players, and smart phones. Such a memory system may include a semiconductor device in which data is stored and a memory controller for controlling the semiconductor device. When the digital devices are referred to as a host, the memory controller can transmit various information including the command and data between the host and the memory device.

In recent years, as the portability of digital devices improves, the amount of data usage is also increasing. Due to the increase in data, a semiconductor device may include a plurality of memory devices. As the number of memory devices increases, the memory controller may perform descriptors that include various tasks.

An embodiment of the present invention provides a memory system and a method of operating the memory system that can quickly find and reprocess an error occurrence section when an error occurs in the execution of the descriptor.

A memory system according to an embodiment of the present invention includes: a semiconductor device in which data is stored; And communicating with the semiconductor device by sequentially processing tasks included in a descriptor and detecting an error section by checking the tasks in the reverse direction when an error occurs in the tasks, And a memory controller for reprocessing tasks included in the detected error period.

A method of operating a memory system according to an embodiment of the present invention includes: determining a processing order of tasks included in a descriptor; Processing the tasks in accordance with the processing order; Determining whether an error has occurred if all of the tasks are processed; If it is determined that an error has occurred, checking the tasks in the reverse order of the processing order to find an error section; And reprocessing the tasks included in the error section according to the processing order.

The present invention can improve the reliability and the operation speed of the memory system by detecting a section in which an error occurs when a descriptor is executed and by performing tasks again.

1 is a view for explaining a memory device according to an embodiment of the present invention.
2 is a diagram for explaining the connection relationship between the memory controller and the semiconductor device shown in FIG.
3 is a diagram for specifically explaining the CPU shown in Fig.
4 is a diagram for explaining a descriptor according to an embodiment of the present invention.
5 is a flowchart illustrating an operation method according to an embodiment of the present invention.
FIG. 6 is a diagram for describing the sequence code setup step of FIG. 5 in detail.
FIG. 7 is a diagram for explaining the step of performing the descriptor of FIG. 5 in detail.
FIG. 8 is a diagram for explaining a case where an error occurs during the execution of the descriptor of FIG. 5.
FIG. 9 is a diagram for explaining the error interval checking step of FIG. 5 in detail.
FIG. 10 is a diagram for explaining the steps of re-performing tasks included in the error section of FIG. 5 in detail.
11 to 13 are views for explaining an operation method according to another embodiment of the present invention.
14 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.
15 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.
16 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.
17 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a view for explaining a memory device according to an embodiment of the present invention.

Referring to FIG. 1, a memory system 10000 may include a semiconductor device 1000 and a memory controller 2000 that can control the semiconductor device 1000.

The memory controller 2000 can control the exchange of data between the host and the semiconductor device 1000. For example, the memory controller 2000 may execute a descriptor including various tasks according to a request of a host. For example, tasks may be internal commands for operations such as program, read, or erase. The semiconductor device 1000 can perform various operations such as program, read, or erase according to a task. In order to perform various operations, the memory controller 2000 includes a buffer memory 2100, a central processing unit (CPU) 2200, a static random access memory (SRAM) 2300, a semiconductor device interface An SD IF 2400, a queue controller 2500, and a host interface 2600. [ The devices included in the memory controller 2000 can communicate with each other via a bus (BUS). The memory controller 2000 may further include various devices necessary for operation in addition to the above-described devices.

Each of the above-described devices will be described in detail as follows.

The buffer memory 2100 may temporarily store some data used when the memory controller 2000 controls the semiconductor device 1000. [ For example, the buffer memory 2100 may temporarily store original data used in a program operation or temporarily store frequently used data when the memory controller 10000 performs an operation.

The CPU 2200 can control communication between the buffer memory 2100, the SRAM 2300, the semiconductor device interface 2400, the queue controller 2500, and the host interface 2600 via the bus BUS. For example, the CPU 2200 controls operations (e.g., wear-leveling, garbage collection, and read refresh, etc.) for efficiently managing the semiconductor device 1000 can do. The CPU 2200 may select a descriptor in response to a task queue received from the queue controller 2500, and sequentially process the tasks included in the selected descriptor. The tasks output from the CPU 2200 can be transferred to the semiconductor device 1000. [ The semiconductor device 1000 may perform operations according to received tasks and output feedback data indicating completion of each operation. The CPU 2200 can determine whether the tasks are completed or whether an error has occurred according to the feedback data. If it is determined that an error has occurred in some of the tasks, the CPU 2200 can detect the errors occurred and re-process the detected tasks. Errors that can occur when processing a task vary. For example, errors may include low voltage detection errors and the like.

The SRAM 2300 can be used as an operation memory of the CPU 2200. The operation memory may be implemented as a non-volatile memory such as a volatile memory or a read only memory (ROM) in addition to the SRAM 2300.

The semiconductor device interface 2400 may transmit task and feedback data between the memory controller 2000 and the semiconductor device 1000. For example, the semiconductor device interface 2400 may transmit the tasks output from the CPU 2200 to the semiconductor device 1000. [ For example, the semiconductor device interface 2400 can transmit the feedback data output from the semiconductor device 1000 to the CPU 2200. [

The queue controller 2500 may output a task queue in response to a command received from a host. The output task queue may be transmitted to the CPU 2200. [ For example, the queue controller 2500 may output a fixed task queue. A task queue may contain information about descriptors.

The host interface 2600 can transmit an external command and data between the host and the memory controller 2000.

The semiconductor device 1000 may be implemented as a volatile memory-based storage device or a non-volatile memory-based storage device. For example, volatile memory based storage devices may include static random access memory (SRAM) and dynamic random access memory (DRAM). For example, a non-volatile memory based storage device may be a flash memory device, an embedded multimedia card (eMMC), a universal flash storage (UFS), a solid state (SSD), RAID (Redundant Array of Independent Disks (RAID) or Redundant Array of Inexpensive Disks (RAID)), Electrically Erasable Programmable Read-Only Memory (EEPROM), Magnetic RAM (MRAM) (RRAM), Nanotube RRAM, Polymer RAM (Random Access Memory), and Polymer RAM (Random Access Memory). : PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory To be implemented.

2 is a diagram for explaining the connection relationship between the memory controller and the semiconductor device shown in FIG.

2, the semiconductor device 1000 may include a plurality of memory device groups (MD1 to MDk, where k is a positive integer). Each of the memory device groups MD1 to MDk may include a plurality of memory devices. The memory device groups MD1 to MDk may communicate with the memory controller 2000 through channels CH1 to CHk. For example, the first memory device group MD1 may communicate with the memory controller 2000 via the first channel CH1.

3 is a diagram for specifically explaining the CPU shown in Fig.

Referring to FIG. 3, the CPU 2200 may include a descriptor controller 210 and a plurality of memories 221 to 232. For example, the memories 221 to 232 include a sequence memory 221, a task memory 222, a process memory 223, a confirm memory 231, And a current memory 232.

The task memory 222 may store various tasks (TC) performed by the descriptor. For example, the tasks TC stored in the task memory 222 may be commands for various operations. The sequence memory 221 may store a sequence code (SC), which is information on an operation order of tasks. For example, the sequence code SC may be updated by the descriptor controller 210 every time the descriptor is executed. The process memory 223 may store a process code (PC), which is information of tasks that have completed operations. For example, the process code PC may be updated by the descriptor controller 210 according to the order in which the operation is completed.

The conform memory 231 can store the confirm code (Co_C), which is the section information that has been operated without error. The current memory 232 may store a current code (Cu_C), which is information on a section in which an error occurs. For example, the tasks included in the descriptor can be processed consecutively for a certain interval. Semiconductor device 1000 may perform operations in accordance with received tasks. When the operation of the last task of the selected section is completed, the semiconductor device 1000 can check whether an error has occurred in the operations performed by the tasks of the selected section, and output the feedback data as a result. The feedback data may include information on whether an error has occurred or not. If an error does not occur in the selected section, a conform code (Co_C) may be set in the last task of the selected section. If an error has occurred in the selected section, a current code (Cu_C) can be set in the last task of the selected section. That is, if all the operations by the tasks of the selected section are performed and then the conform code (Co_C) is given to the last task, it means that no errors have occurred in the tasks of the selected section. Alternatively, if the current code (Cu_C) is given to the last task after all the operations by the tasks of the selected section are performed, it means that an error has occurred in some of the tasks of the selected section.

The descriptor controller 210 may update the sequence code SC according to the task information of the descriptor previously performed. For example, the descriptor controller 210 may reset the operation order of the tasks according to the state of the tasks of the descriptor performed previously, and may assign the sequence codes SC to the respective tasks according to the reset order. For example, the descriptor controller 210 resets the sequence code SC according to the operation time of each task, the state of the semiconductor device 1000 performing the task, and the like, and outputs the reset sequence code SC to each of the tasks And stored in the sequence memory 221 in association with each other. The descriptor controller 210 writes a process code PC, a conform code Co_C or a current code Cu_C in the memories 223 and 231 and 232 in accordance with the feedback data received from the semiconductor memory device 1000 Can be stored.

The above-described descriptors will be described in more detail as follows.

4 is a diagram for explaining a descriptor according to an embodiment of the present invention.

4, sequential codes (S1 to Si; i is a positive integer) for determining the operation order of each task are stored in each of the tasks T1 to Ti in the initial descriptor 41, As shown in FIG. Since the initial descriptor 41 is not in operation, the process code PC may all be set to the initial code P0.

The tasks of the descriptor may be sequentially executed according to the sequence codes S1 to Si. For example, it is assumed that the first sequence code S1 among the first to i-th sequence codes S1 to Si means the first order and the i-th sequence code Si means the last order. It is also assumed that the first to i-th sequence codes S1 to Si correspond to the first to i-th tasks T1 to Ti, respectively. In this case, the first task T1 may be processed first according to the first sequence code S1, the second task T2 may be processed next according to the second sequence code S2, ). In this manner, the first to i-th tasks T1 to Ti can be sequentially processed, and the semiconductor device 1000 can perform operations corresponding to the respective tasks according to the received tasks .

The semiconductor device 1000 outputs feedback data each time the operation is completed and the descriptor controller 210 supplies the process codes P1 to Pi for the tasks to the process memory 223 in FIG. Lt; / RTI > Therefore, after the descriptor is executed (42), the process codes P1 to Pi may be assigned to each of the tasks T1 to Ti.

In addition, all the tasks (T1 to Ti) included in the descriptor can be divided into predetermined intervals, and after the tasks included in each interval are successively performed, an error check operation is performed and no error occurs If so, the tasks included in the next section can be performed continuously. For example, if the first and second tasks T1 and T2 are included in the first to third error check intervals EC1 to EC2 and the third and fourth error check intervals EC2 to EC3 are included in the second to third error check intervals EC1 to EC2, To 5 < th > tasks (T3 to T5) are included. The remaining six to th i-th tasks T6 to Ti may be divided into a plurality of sections.

The first and second tasks T1 and T2 included in the first and second error check intervals EC1 to EC2 may be sequentially performed according to the first and second sequence codes SC1 and SC2 . For example, after the first task T1 is executed, the first process code P1 for the operation result of the first task T1 can be stored, and after the second task T2 is executed The second process code P2 for the operation result of the second task T2 can be stored. If both of the first and second tasks T1 and T2 are completed without error, the confirm code Co_C in the second error check interval EC2 may be stored in the confirm memory (231 of FIG. 3). Then, the third to fifth tasks T3 to T5 included in the second to third error check intervals EC2 to EC3 are sequentially performed according to the third to fifth sequence codes S3 to SC5 . The third to fifth process codes P3 to P5 for the third to fifth tasks T3 to T5 are generated if no error has occurred in all operations for the third to fifth tasks T3 to T5. And the conform code Co_C may be stored in the third error check interval EC3.

If there is a task in which the error has occurred in the third to fifth tasks T3 to T5, the process code is not updated in the task in which the error occurred. That is, the previous process code can be maintained. In addition, a current code Cu_C may be stored in the third error check period EC3. The descriptor controller 210 (FIG. 3) checks and re-processes the tasks in the section in which the error occurs, and if the error does not occur, controls the descriptors so that the tasks included in the next section are processed .

A method of detecting an error-causing task and re-processing the detected tasks will be described in detail as follows.

5 is a flowchart illustrating an operation method according to an embodiment of the present invention.

Referring to FIG. 5, a descriptor controller 210 (FIG. 3) may set up a sequence code SC (510). For example, the sequence code may be updated by the descriptor controller 210 whenever the descriptor is executed. Therefore, the tasks included in the descriptor can be changed in the order of operation according to the sequence code SC.

The descriptor controller 210 may process the tasks sequentially in accordance with the set sequence code SC so that the tasks included in the descriptor are executed in the semiconductor device 1000 (FIG. 1). In this case, the order in which the tasks are executed is assumed to be the forward direction.

If all of the tasks included in the error check interval have been performed, it can be determined whether an error has occurred in the performed tasks (530). If no errors have occurred in the performed tasks (NO), the operation of the tasks is terminated. When the operation of the tasks is ended, the tasks included in the next section can be performed.

If an error has occurred in the performed tasks (e. G.), An error interval check operation may be performed (540). For example, the error interval check operation can be performed in the reverse direction of the sequence code SC. That is, the error section checking operation can be performed in the reverse direction of the sequence code SC in the section in which the current code (Cu_C) and the conform code (Co_C) are inputted. At this time, the descriptor controller 210 can check the process codes (PC) corresponding to the respective tasks. For example, the process codes (PC) are updated when the operation corresponding to the task is completed without error, and the process code is not updated in the task in which the error occurs. Therefore, the previous process code can be held in the corresponding task. That is, since the tasks are sequentially executed according to the sequence code SC, the process codes PC may not be updated from the task in which the error occurs. Therefore, if the process codes PC are checked in the reverse direction of the sequence code SC, the unprocessed process codes PC and the updated process codes PC can be overlapped with each other. That is, a task in which the process codes PC overlap each other can be detected.

Tasks may be reprocessed 550 in the forward direction of the sequence code SC from the task in which the process code PC is duplicated. For example, when a task in which the process code PC is duplicated is detected in step 540, the decryptor controller 210 sequentially processes the tasks in the forward direction according to the sequence code SC from the detected task )can do.

The above-described steps will be described in detail with reference to FIGS. 6 to 10. FIG.

FIG. 6 is a diagram for describing the sequence code setup step of FIG. 5 in detail.

Referring to FIGS. 6 and 5, a sequence code SC may be set according to the state of tasks included in the descriptor. For example, the first sequence code S1 is set up in the third task T3, the second sequence code S2 is set up in the first task T1, the third sequence T3 is set in the second task T2, The code S3 is set up, the fourth sequence code S4 is set up in the sixth task T6, the fifth sequence code S5 is set up in the fifth task T5, the fourth sequence T4 is set up, It is assumed that the sixth sequence code S6 is set up. At this time, error check intervals EC1-EC2 and EC2-EC3 may also be set up. For example, the first error check interval EC1 may be set to a period in which the third task T3 performed in accordance with the first sequence code S1 starts, and the second error check interval EC2 may be set The third error check interval EC3 may be set to a period in which the first task T3 performed according to the second sequence code S2 is terminated and the fourth error check interval EC3 may be set to the fourth task T4 may terminate. The number and order of the sequence codes S1 to S6 to be set up and the first to sixth tasks T1 to T6 and the error check intervals EC1 to EC2 and EC2 to EC3 corresponding thereto can be understood As this is an aid embodiment, it can be set up differently depending on the memory system.

FIG. 7 is a diagram for explaining step 520 of performing the descriptor of FIG. 5 in detail.

7 and 5, the third and first tasks T3 and T1 can be performed in the forward direction 71 according to the first and second sequence codes S1 and S2. First, if the third task T3 is performed without error, the process code PC of the third task T3 can be updated with the first process code P1. Then, if the first task T1 is also executed without error, the process code PC of the first task T1 can be updated with the second process code P2.

Since no error has occurred in the third and first tasks T3 and T1, the first confirm code Co_C1 can be stored in the second error check interval EC2.

FIG. 8 is a diagram for explaining a case where an error occurs during the execution of the descriptor of FIG. 5.

8 and 5, if the third and first tasks T3 and T1 performed in the first and second error check intervals EC1 and EC2 are performed without error, The second, sixth, fifth, and fourth tasks T2, T6, T5, and T4 included in the third error check period EC2-EC3 are executed in accordance with the third to sixth sequence codes S3 to S6 And may be sequentially performed in the forward direction (520 in FIG. 5).

It is assumed that an error has occurred from the fifth task T5 among the second, sixth, fifth, and fourth tasks T2, T6, T5, and T4 that are sequentially executed. In this case, the descriptor controller 210 detects (530) that an error ERROR has occurred in the third error check interval EC3 and stores the first current code Cu_C1 in the third error check interval EC3 have.

FIG. 9 is a diagram for explaining the error interval check operation 540 of FIG. 5 in detail.

Referring to FIG. 9 and FIG. 5, the error interval checking operation can be performed in the order of the interval EC3 from which the first current code Cu_C1 is stored to the interval EC2 in which the first conform code Co_C1 is stored. That is, the error interval check operation can be performed in the reverse order on the sequence of the sequence codes SC. Since it is assumed in FIG. 8 that an error has occurred from the fifth task T5, the second and sixth tasks T2 and T6 can be performed without error. In this case, the process code PC of the second task T2 may be updated to the first process code P1, and the process code PC of the sixth task T6 may be updated to the second process code P2 Can be updated. However, since it is difficult to determine which of the fifth and fourth tasks T5 and T4 performed after the sixth task T6 has caused an error, the error section check operation is performed in the reverse direction of the sequence code SC . This is because the process code (PC) is not updated in the task in which an error occurs, so it is checked from an un-updated process code (PC). Particularly, since a part of the updated process code (PC) and the updated process code (PC) may overlap, in the error section check operation, the process code PC finds a task that overlaps.

The descriptor controller 210 can check the process code (PC) corresponding to the fourth task T4. In the present embodiment, it is assumed that the second process code P2 is stored in the fourth task T4. Then, the descriptor controller 210 can check the program code (PC) corresponding to the fifth task T5. Assuming that the first process code P1 is stored in the fifth task T5, the descriptor controller 210 stores the first process code P1 stored in the fifth task T5 and the fourth process T4 stored in the fourth task T4 And compares the second process code P2. The descriptor controller 210 sets the process code PC of the sixth task T6 to the process codes PC of the fourth and fifth tasks T4 and T5, . As a result of the comparison, if the process code (PC) 92 stored in the sixth task T6 overlaps with the process code (PC) 91 stored in the fourth task T4, the descriptor controller 210 returns to the sixth task T6 It can be determined that an error has occurred in the fifth and fourth tasks T5 and T4. That is, the descriptor controller 210 divides the second and sixth tasks T2 and T6 into a normal operation group (NO) in which the normal operation is performed, and the fifth and fourth tasks T5 and T6 T4) can be classified into an error operation group (EO) in which an error occurs.

FIG. 10 is a diagram for describing reprocessing steps of tasks included in the error section of FIG. 5 in detail.

10 and 5, the descriptor controller 210 sequentially executes the fifth and fourth tasks T5 and T4 included in the error operation group EO in a forward direction in the order of the sequence code SC Can be re-run. For example, if the re-performed operation is terminated without error in the fifth task T5, the process code PC of the fifth task T5 is followed by the second process code P2 of the sixth task T6 And may be updated to the third process code P3. Then, if the operation re-performed in accordance with the fourth task T4 is ended without error, the process code PC of the fourth task T4 is transferred to the fourth process code P3 of the fifth task T5, It can be updated to the process code P4. When the process code PC of the fourth task T4 is updated, an error check operation can be performed again in the third error check interval EC3. The descriptor controller 210 may store the second conform code Co_C2 in the third error check interval EC3 in which the first current code Cu_C1 is stored if it is determined that no error has occurred as a result of the error check operation. For example, the first current code Cu_C1 may be reset and the second confirm code Co_C2 may be newly stored.

6 to 10, the number of tasks included in the error check interval is four. However, the number of tasks may be set differently depending on the memory system. In this regard, a method of executing a descriptor including more tasks in an error check interval will be described based on the above description.

11 to 13 are views for explaining an operation method according to another embodiment of the present invention. 11 to 13, the a to b error check intervals (ECa-ECb, a and b are positive integers) are set, and in the a to b error check intervals ECa to ECb Assume that nine tasks are included. In the present embodiment, it is assumed that the c-th conforming code (Co_Cc) is stored in the a-th error check interval ECa. In the present embodiment, the 10th to 18th sequence codes S10 to S18 are respectively set up in the 20th to 28th tasks T20 to T28, and the 20th to 28th tasks T20 to T28 are set Are sequentially output according to the 10th to 18th sequence codes (S10 to S18) set up.

Referring to FIG. 11, the 20th through 28th tasks T20 through T28 are sequentially processed, and the semiconductor device 1000 performs operations according to the 20th through 28th tasks T20 through T28 And output the feedback data every time each operation ends. The descriptor controller 210 may update the process code (PC) of each task according to the feedback data. If it is determined that an error has occurred as a result of performing an error check operation in the bth error check interval ECb after the operation for the twenty-fifth task T28 is ended, the descriptor controller 210 outputs the bth error check interval ECb, (Cu_Cc) can be stored. The descriptor controller 210 may perform an error interval check operation to determine which task or tasks in the 20th to 28th tasks T20 to T28 have generated an error.

Referring to FIG. 12, the error interval check operation can be performed in the reverse direction of the sequence code SC from the 28th task (T28) performed last. The descriptor controller 210 checks that the process code PC of the 28th task T28 is the third process code P3 and then the process code PC of the 27th task T27 and the 28th task T28, Can be compared with the process code (PC) of FIG.

If the process code PC of the 27th task T27 is the second process code P2, the process codes P2 and P3 of the 27th and 28th tasks T27 and T28 do not overlap with each other, The descriptor controller 210 may compare the process code PC of the 26th task T26 with the 27th and 28th process codes P2 and P3.

If the process code PC of the 26th task T26 is the fifth process code P5, the 26th task T26 of the process codes P2 and P3 of the 27th and 28th tasks T27 and T28 The descriptor controller 210 determines that the process code PC of the 25th task T25 and the 26th to 28th tasks T26 to T28 of the next task, which is the next task, The process codes P5, P2, and P3 of the first embodiment can be compared.

If the process code (PC) of the 25th task (T25) is the eighth process code (P8), the 25th task among the process codes P5, P2 and P3 of the 26th to 28th tasks The descriptor controller 210 determines that the process code PC of the 24th task T24 and the 25th to 28th tasks T25 to T25 of the next task, P8, P5, P2, and P3 of the first to T28 processes.

If the process code PC of the twenty-fourth task T24 is the fifth process code P5, the descriptor controller 210 sets the process codes (PC) 121 of the twenty-fourth task T24 and the twenty-sixth task T26 And 122 overlap each other.

Accordingly, the descriptor controller 210 divides the 20th to 24th tasks T20 to T24 into the normal operation group NO and the 25th to 28th tasks T25 to T28 divide the error operation group EO ).

Referring to FIG. 13, the descriptor controller 210 may sequentially re-execute the 25th to 28th tasks (T25 to T28) included in the error operation group EO in the forward direction in accordance with the sequence code SC. The process code PC for the 25th to 28th tasks (T25 to T28) is completed by the 6th to 9th process codes P6 To P9) may be stored. If it is determined that no error has occurred as a result of re-performing the error check operation in the bth error check interval ECb, the descriptor controller 210 sets the error check interval ECb in which the c-th current code (Cu_Cc) And can store the d-conform code (Co_Cd).

As described above, since an error section of tasks being executed in a descriptor can be quickly found and errors can be re-executed, the reliability and the operation speed of the memory system can be improved.

14 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.

14, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device . The memory system 30000 may include a semiconductor device 1000 and a memory controller 2000 that can control the operation of the semiconductor device 1000. The memory controller 2000 can control the data access operation of the semiconductor device 1000 such as a program operation, an erase operation or a read operation under the control of a processor 3100. [ In addition, the memory controller 2000 can detect an error in a descriptor being executed and re-execute tasks in an area where an error has occurred.

Data programmed into the semiconductor device 1000 may be output through a display (Display) 3200 under the control of the memory controller 2000.

The radio transceiver 3300 can transmit and receive radio signals through the antenna ANT. For example, the wireless transceiver 3300 may change the wireless signal received via the antenna ANT to a signal that can be processed by the processor 3100. The processor 3100 may thus process the signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 2000 or display 3200. The controller 3500 can program the signal processed by the processor 3100 to the semiconductor device 1000. [ In addition, the wireless transceiver 3300 may convert the signal output from the processor 3100 into a wireless signal, and output the modified wireless signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100 and includes a touch pad, A pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 is connected to the display 3200 so that data output from the memory controller 2000, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output via the display 3200. [ Can be controlled.

The memory controller 2000 capable of controlling the operation of the semiconductor device 1000 may be implemented as part of the processor 3100 and may also be implemented as a separate chip from the processor 3100. [

15 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

15, the memory system 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant ), A portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a semiconductor device 1000 and a memory controller 2000 that can control the data processing operation of the semiconductor device 1000.

A processor 4100 may output data stored in the semiconductor device 1000 through a display 4300 according to data input through an input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 can control the overall operation of the memory system 40000 and can control the operation of the memory controller 2000. The memory controller 2000 capable of controlling the operation of the semiconductor device 1000 according to the embodiment may be implemented as a part of the processor 4100 or a chip separate from the processor 4100. [

16 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.

16, the memory system 50000 can be implemented as an image processing apparatus, such as a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with a digital camera.

The memory system 50000 includes a memory controller 2000 capable of controlling the data processing operations of the semiconductor device 1000 and the semiconductor device 1000, such as a program operation, an erase operation, or a read operation.

The image sensor 5200 of the memory system 50000 can convert the optical image into digital signals and the converted digital signals can be transmitted to the processor 5100 or the memory controller 2000. [ Under the control of the processor 5100, the converted digital signals may be output through a display 5300 or may be stored in the semiconductor device 1000 through the memory controller 2000. The data stored in the semiconductor device 1000 may also be output through the display 5300 under the control of the processor 5100 or the memory controller 2000. [

The memory controller 2000 capable of controlling the operation of the semiconductor device 1000 according to the embodiment may be implemented as a part of the processor 5100 or a chip separate from the processor 5100. [

17 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

Referring to FIG. 17, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a semiconductor device 1000, a memory controller 2000, and a card interface 7100.

The memory controller 2000 can control the exchange of data between the semiconductor device 1000 and the card interface 7100. [ According to an embodiment, the card interface 7100 may be an SD (secure digital) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 7100 can interface data exchange between the host 60000 and the memory controller 2000 according to the protocol of the host (HOST) 60000. According to the embodiment, the card interface 7100 can support USB (Universal Serial Bus) protocol and IC (InterChip) -USB protocol. Here, the card interface may mean hardware that can support the protocol used by the host 60000, software installed on the hardware, or a signal transmission method.

When the memory system 70000 is connected to the host interface 6200 of the host 60000 such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set- The interface 6200 may perform data communication with the semiconductor device 1000 through the card interface 7100 and the memory controller 2000 under the control of a microprocessor (μP) 340.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

10000: memory system 1000: semiconductor device
2000: memory controller 2100: buffer memory
2200: CPU 2300: SRAM
2400: Semiconductor device interface 2500: Queue controller
2600: Host interface 210: Descriptor controller
221: Sequence memory 222: Task memory
223: process memory 231: conform memory
232: Current memory

Claims (20)

A semiconductor device in which data is stored; And
The method comprising: communicating with the semiconductor device and sequentially processing tasks included in a descriptor, detecting an error interval by checking the tasks in the reverse direction when an error occurs in the tasks, And a memory controller for reprocessing tasks included in the error interval.
The memory controller according to claim 1,
A queue controller for outputting a task queue in response to an external command received from the host; And
And a CPU (Central Processing Unit) that processes the descriptor in response to the task queue.
3. The apparatus according to claim 2,
A descriptor controller for controlling the descriptor in response to the task queue; And
And memories for storing various codes required for the descriptor processing.
4. The apparatus of claim 3,
A task memory for storing the tasks;
A sequence memory for storing a sequence code which is information on a processing order of the tasks;
A process memory for storing process codes, which are information on completion of the tasks;
A confirm memory for storing a conform code which is information of an interval in which no error occurs; And
And a current memory for storing a current code which is information of a section in which an error has occurred.
5. The method of claim 4,
Wherein the tasks stored in the task memory are commands for various operations performed on the semiconductor device.
5. The method of claim 4,
The sequence code is updated according to the processing state of the task each time the descriptor is executed,
Wherein the tasks are sequentially processed according to the sequence code.
5. The method of claim 4,
Wherein the process memory is sequentially updated according to an order of the tasks that have been processed.
5. The method of claim 4,
Wherein the reconfirmation code is assigned to the last processed task among the tasks processed without error if all the tasks included in the error check interval among the tasks are processed without errors.
5. The method of claim 4,
Wherein the current code is stored in a memory assigned to the last processed task among the tasks processed in the error check interval when an error occurs in some tasks included in the error check interval among the tasks.
10. The method of claim 9,
The current code is reset if an error does not occur after the tasks included in the error check interval are reprocessed,
And the confirm code is assigned to the last processed task among the reprocessed tasks.
The apparatus of claim 3, wherein the descriptor controller comprises:
Sequentially processes the tasks included in the error check interval among the tasks included in the descriptor,
Checking whether an error has occurred in the error check interval if the last task among the tasks included in the error check interval is processed,
If it is determined that the error has occurred, an error section check operation and a re-process operation are performed,
And sequentially processes the tasks included in the next error check interval if it is determined that no error has occurred.
12. The method of claim 11,
Wherein the descriptor controller checks the tasks in the reverse direction from the last processed task among the tasks in the error check interval determined to have generated the error.
13. The method of claim 12,
Wherein the descriptor controller checks the process code assigned to each of the tasks.
14. The method of claim 13,
Wherein the descriptor controller sequentially reprocesses the next processed task of the later detected task among the duplicated tasks when the tasks having overlapping process codes are detected.
Determining a processing order of tasks included in the descriptor;
Processing the tasks in accordance with the processing order;
Determining whether an error has occurred if all of the tasks are processed;
If it is determined that an error has occurred, checking the tasks in the reverse order of the processing order to find an error section; And
And reprocessing the tasks included in the error section according to the processing order.
16. The method of claim 15,
Wherein the processing order of the tasks is changed according to a state of the tasks performed in a previous operation of the descriptor.
16. The method of claim 15,
Wherein process codes are sequentially assigned to tasks each time the tasks are executed without errors.
18. The method of claim 17,
Wherein the previously assigned task codes are held in tasks in which an error has occurred among the tasks.
19. The method of claim 18,
Comparing the process codes with each other; And
And designating, as the error section, the task from the processed task after the overlapped task to the last processed task when the tasks to which the overlapping process codes are assigned are detected.
20. The method of claim 19,
Further comprising: re-processing the tasks and determining whether the error has occurred.

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