KR20180059651A - Electro Luminance Display Device And Sensing Method For Electrical Characteristic Of The Same - Google Patents

Abstract

The present invention provides an electroluminescence display device for reducing a sensing time consumed for obtaining an average I-V curve of a display panel, and a method for sensing an electrical property thereof. According to an embodiment of the present invention, the electroluminescence display device comprises: a timing control part distributing N gradation data (N is a positive integer equal to or more than 2) within one frame; a data voltage generating part converting the N gradation data into N gradation sensing data voltages, and supplying the N gradation sensing data voltages to the display panel within the one frame; and a sensing part sensing an electrical property of the display panel based on the N gradation sensing data voltages, and outputting N gradation digital sensing data within the one frame.

Description

TECHNICAL FIELD [0001] The present invention relates to an electroluminescence display device and a method of sensing an electrical property thereof,

The present invention relates to an electroluminescence display and a method of sensing an electrical characteristic thereof.

Various flat panel display devices are being developed and sold. Among them, an electroluminescent display device is divided into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. Particularly, an active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a light emitting efficiency, a luminance and a viewing angle This is a great advantage.

The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form and adjusts the luminance of an input image implemented in pixels according to gray levels of image data. The driving TFT controls the driving current flowing in the OLED according to the voltage applied between its gate electrode and the source electrode. The light emission amount of the OLED is determined according to the driving current, and the brightness of the image is determined by the light emission amount of the OLED.

The electrical characteristics of the pixel such as the threshold voltage Vth of the driving TFT, the electron mobility of the driving TFT, and the threshold voltage of the OLED are factors for determining the driving current Ids, Should be. However, electrical characteristics between the pixels may be varied due to various causes such as process characteristics, time-varying characteristics, and the like. Such electric characteristic deviations lead to a luminance deviation, which is a limitation in realizing a desired image.

In order to compensate for the luminance deviation between pixels, an external compensation technique for sensing the electrical characteristics of pixels and correcting the digital data of the input image based on the sensing result is known. In order for the luminance deviation to be compensated, a current change by? Y must be ensured when the data voltage applied to the pixel is changed by? X. Therefore, the external compensation technique is to realize the same brightness by calculating Δx for each pixel and applying the same driving current to the OLED. That is, the external compensation technique adjusts the gray level value to compensate for the brightness of each pixel.

The external compensation technique may include a compensation algorithm that obtains one average panel current (I) -voltage (V) curve through multiple sensing and compensates the I-V curve of each pixel to match the average panel I-V curve. In order to obtain the average panel I-V curve, digital sensing data for N (N is a positive integer of 2 or more) gradations is required. At this time, the sensing data of N gradations is obtained through the sensing time corresponding to the N frame time, and the sensing time increases as N increases. Therefore, in order to reduce the tact time, it is necessary to reduce the sensing time.

Accordingly, it is an object of the present invention to provide an electroluminescent display device and a method of sensing an electrical characteristic thereof, which can reduce a sensing time required to obtain an average I-V curve of a display panel.

In order to achieve the above object, an EL display device according to an embodiment of the present invention includes a timing controller for distributing N (N is a positive integer equal to or larger than 2) tone data within one frame; A data voltage generating unit for converting the N gray-scale data into sensing data voltages for N gray-scale levels, and supplying the sensing data voltages for N gray-scale levels to the display panel in one frame; And a sensing unit for sensing the electrical characteristics of the display panel based on the data voltages for sensing the N gradations and outputting N gradation digital sensing data in one frame.

According to another aspect of the present invention, there is provided a method of sensing an electrical characteristic of an electroluminescent display device, comprising: distributing N (N is a positive integer equal to or larger than 2) tone data within one frame; Converting the N gray-scale data into sensing data voltages of N gray-scale levels, and supplying the sensing data voltages of N gray-scale levels to the display panel in one frame; And sensing the electrical characteristics of the display panel based on the data voltages for sensing the N gradations, and outputting digital sensing data of N gradations in one frame.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is a block diagram illustrating an external compensation circuit according to an embodiment of the present invention.
3 is a flowchart illustrating an external compensation method according to an embodiment of the present invention.
4A is a diagram showing deriving a reference curve equation in the external compensation method of FIG.
FIG. 4B is a diagram showing the average IV curve of the display panel and the IV curve of the compensation target pixel in the external compensation method of FIG. 3. FIG.
FIG. 4C is a diagram showing an average IV curve of a display panel, an IV curve of a compensation target pixel, and an IV curve of a compensated pixel in the external compensation method of FIG.
5 to 7 are diagrams showing various implementations of the external compensation module.
FIG. 8 is a view showing a sensing scheme for obtaining sensing data of N gray levels as an undesirable embodiment of the present invention.
FIGS. 9A and 9B are diagrams illustrating a sensing scheme for obtaining sensing data of N gray levels in one frame as a sensing scheme according to an embodiment of the present invention.
FIGS. 10A and 10B are diagrams illustrating a sensing scheme for obtaining sensing data of N gray levels in one frame as a sensing scheme according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, an electroluminescent display device will be described mainly with respect to an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to the organic light emitting display, but can be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention. 2 is a block diagram illustrating an external compensation circuit according to an embodiment of the present invention. 3 is a flowchart illustrating an external compensation method according to an embodiment of the present invention. 4A is a diagram showing deriving a reference curve equation in the external compensation method of FIG. FIG. 4B is a graph showing an average I-V curve of a display panel and an I-V curve of a compensation target pixel in the external compensation method of FIG. FIG. 4C is a graph showing an average I-V curve of a display panel, an I-V curve of a compensation target pixel, and an I-V curve of a compensated pixel in the external compensation method of FIG.

1 and 2, an electroluminescent display device according to an embodiment of the present invention includes a display panel 10, a driver IC (D-IC) 20, a compensation IC 30, a host system 40, And a storage memory 50, as shown in FIG.

The display panel 10 is provided with a plurality of pixels PXL and a plurality of signal lines. The signal lines include a plurality of data lines for supplying analog data voltages to the pixels PXL, a plurality of gate lines for supplying gate signals to the pixels PXL, a plurality of sensing lines . ≪ / RTI > According to the pixel (PXL) structure, the sensing line may be omitted, and in this case, sensing may be performed through the data line. The analog data voltage includes a display data voltage (Vdata-DIS) and a sensing data voltage (Vdata-SEN). The electrical characteristics of the pixel PXL include the threshold voltage of the driving TFT, the electron mobility of the driving TFT, and the operating point voltage of the OLED.

The pixels PXL of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel PXL may be connected to any one of the data lines, to at least one of the gate lines, and to one of the sensing lines. Each pixel PXL is configured to receive a high potential driving power supply VDD and a low potential driving power supply VSS from a power generation unit. To this end, the power generator may supply the high-potential driving power to the pixel PXL through the high-potential pixel power supply wiring or the pad portion. Further, the power generator may supply the low-potential driving power to the pixel PXL through the low-potential pixel power supply wiring or the pad portion.

The gate driver 15 may separately generate a gate signal necessary for display driving and a gate signal necessary for sensing driving.

The gate driver 15 may generate a gate signal for display during display driving and supply the generated gate signal to the gate line. The display gate signal is a signal synchronized with the writing timing of the display data voltage (Vdata-DIS).

The gate driver 15 can generate a sensing gate signal during sensing driving and supply it to the gate line. The sensing gate signal is a signal synchronized with the writing timing and the sensing timing of the sensing data voltage (Vdata-SEN).

The gate driver 15 may be formed directly on the lower substrate of the display panel 10 by a gate-driver In Panel (GIP) method. The gate driver 15 is formed in a non-display area (i.e., a bezel area) outside the pixel array in the display panel 10, and can be formed in the same TFT process as the pixel array.

The driver IC (D-IC) 20 is connected to the data line and the sensing line of the display panel 10. The driver IC (D-IC) 20 includes a timing control section 21 and a data driver 25.

The timing control unit 21 refers to timing signals input from the host system 40 such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE It is possible to generate a gate timing control signal GDC for controlling the operation timing of the gate driving unit 15 and a data timing control signal DDC for controlling the operation timing of the data driving unit 25. [

The data timing control signal DDC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driver 25. The source sampling clock is a clock signal that controls sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the data driver 25.

The gate timing control signal GDC may include, but is not limited to, a gate start pulse, a gate shift clock, and the like. The gate start pulse is applied to the stage that produces the first output to activate the operation of the stage. The gate shift clock is a clock signal commonly inputted to the stages, and is a clock signal for shifting the gate start pulse.

The timing controller 21 can control a sensing mode for sensing driving and a display mode for driving the display according to a predetermined control sequence.

In the sensing mode, the preset gradation data is converted into a sensing data voltage, applied to the pixels PXL, and the electrical characteristic of the pixel PXL is sensed to generate digital sensing data S-DATA. In the display mode, the input image data to be written in the pixels PXL is corrected based on the digital sensing data (S-DATA) acquired through the sensing mode, and the corrected image data is converted into the display data voltage Vdata-DIS And applies them to the pixels PXL.

The timing controller 21 may generate timing control signals for driving the display and timing control signals for sensing driving differently. But is not limited thereto. Under the control of the timing control section 21, the sensing drive is performed in the vertical blank period during the display drive, or in the power on sequence period before the display drive is started, or in the power off sequence period after the display drive is finished . But the present invention is not limited thereto, and the sensing driving can be performed in the vertical active period during the display driving.

The vertical blanking period is a period in which input image data is not written, and is arranged between vertical active periods in which input image data for one frame is written. The power-on sequence period means a transient period from when the driving power is turned on until the input image is displayed. The power-off sequence period means a transient period from the end of the display of the input image until the driving power is turned off.

The timing control unit 21 can control all operations for sensing driving according to a predetermined sensing process. That is, the sensing operation may be performed in a state where only the screen of the display device is turned off during the period in which the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like. But is not limited thereto.

The data driver 25 includes a sensing unit 22 and a data voltage generator 23.

The data voltage generator 23 may include a digital-to-analog converter (DAC) and an output buffer (not shown) for converting a digital signal into an analog signal. The DAC generates a display data voltage (Vdata-DIS) or a sensing data voltage (Vdata-SEN). The output buffer buffers and outputs the data voltages (Vdata-DIS, Vdata-SEN) input from the DAC.

The data voltage generator 23 converts the corrected video data (V-DATA) into analog gamma voltages using the DAC, and outputs the converted data voltages to the data lines (Vdata-DIS) as display data voltages Supply. The display data voltage Vdata-DIS supplied to the data lines 140 is applied to the pixels PXL in synchronization with the turn-on timing of the display gate signal. The gate-source voltage of the drive TFT provided in the pixels PXL is programmed by the display data voltage Vdata-DIS, and the drive current flowing to the drive TFT in accordance with the gate-source voltage of the drive TFT is determined.

The data voltage generating unit 23 generates a predetermined sensing data voltage (Vdata-SEN) by using the DAC, and supplies the data voltage to the data lines during sensing driving. During the sensing operation, the sensing data voltage (Vdata-SEN) supplied to the data lines is applied to the pixels PXL in synchronization with the turn-on timing of the sensing gate signal. The gate-source voltage of the drive TFT provided in the pixels PXL is programmed by the sensing data voltage Vdata-SEN, and the drive current flowing to the drive TFT in accordance with the gate-source voltage of the drive TFT is determined.

The sensing unit 22 can sense the electrical characteristics of the pixel PXL according to the sensing data voltage Vdata-SEN at the time of sensing driving. The sensing unit 22 may include a sensing unit and an analog-to-digital converter (ADC).

The sensing unit may be a voltage sensing type including a sample-and-hold unit, or a current sensing type including a current integrator and a sample-and-hold unit. The sensing unit samples the driving current flowing through the driving TFT during sensing driving, and supplies the sampled result to the ADC.

The ADC converts the analog sampling signal input from the sensing unit into a digital signal and outputs digital sensing data (S-DATA) representing the electrical characteristics of the pixel (PXL).

The ADC can be implemented as a flash-type ADC, an ADC using a tracking technique, or an ADC with a successive approximation register type. The ADC supplies the digital sensing data (S-DATA) obtained at the sensing operation to the storage memory (50). The storage memory 50 stores digital sensing data (S-DATA). The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

The compensation IC (30) includes a compensation memory (32) and a compensation section (34). The compensation unit 34 calculates an offset and a gain for each pixel on the basis of the digital sensing data S-DATA read from the storage memory 50, (Or corrects) the digital image data to be input to the driver IC 20, and supplies the modulated digital image data (V-DATA) to the driver IC 20. [ To this end, the compensating unit 34 may include a parameter calculating unit 31 and a data correcting unit 33.

3 to FIG. 4C, the parameter operation unit 31 calculates a parameter for all the pixels based on the digital sensing data (S-DATA) of N (N is a positive integer equal to or larger than 2) (I) -voltage (V) curve for each pixel, and compensating the IV curve of each pixel to match the average panel IV curve.

Specifically, the parameter computing unit 31 applies a known least squares method (least square method) to the sensing result for a plurality of gradations (for example, 7 gradations including A to F) as shown in FIG. 3 and FIG. 4A The following Equation 1 corresponding to the average panel IV curve is derived (S1). The result of sensing for a plurality of gradations (for example, 7 gradations including A to F) can be obtained based on gradation data GDATA of a plurality of gradations preliminarily distributed by the timing controller 21. [

In Equation 1, "a" is the electron mobility of the drive TFT, "b" is the threshold voltage of the drive TFT, and "c" indicates the physical property value of the drive TFT. " a " and " b " are values that vary with aging, whereas " c "

The parameter operation unit 31 calculates the current value I1 and I2 and the gray scale value (X and Y gradation) (i.e., the data voltage values (Vdata1 and Vdata2)) measured at two points as shown in Figs. 3 and 4B A 'value and a b' value, which are parameter values of the pixel PXL, are calculated (S2).

In the above equation (2), the parameter operation unit 31 can calculate the a 'value and the b' value, which are parameter values of the pixel PXL using the quadratic equation.

The parameter operation unit 31 may calculate an offset and a gain to make the I-V curve of the pixel coincide with the average panel I-V curve as shown in FIG. 3 and FIG. 4C (S3). The offset (Offset) and gain (Gain) after the compensation is completed are shown in the following Equation (3). In Equation (3), " Vcomp " indicates a compensation voltage at a digital level.

The compensation memory 32 stores an offset and a gain of each pixel PXL calculated by the parameter calculator 31. [ The compensation memory 32 may be a RAM (Random Access Memory), for example, a DDR SDRAM (Double Data Rate Synchronous Dynamic RAM), but is not limited thereto.

The data correction unit 33 corrects the digital image data to be input to the pixel PXL based on the offset and the gain read from the compensation memory 32 in step S4. To this end, the data correction unit 33 may include a multiplier 33A and an adder 33B. The multiplier 33A multiplies the input digital image data by a gain, and supplies the result to the adder 33B. The adder 33B adds an offset to the output result of the multiplier 33A and outputs the result as corrected digital image data (V-DATA).

The host system 40 can supply digital image data to be inputted to the pixels PXL of the display panel 10 to the compensation IC 30. [ The host system 40 can further supply the user input information such as the digital brightness information to the compensation IC 30. [ The host system 40 may be implemented as an application processor.

5 to 7 are diagrams showing various implementations of the external compensation module.

5, the electroluminescent display device of the present invention includes a driver IC (D-IC) 20 mounted on a chip on film (COF) for implementing an external compensation module, A storage memory 50 and a power supply IC (P-IC) 60 mounted on a flexible printed circuit board (FPCB), and a host system 40 mounted on a system printed circuit board (SPCB) can do.

The driver IC (D-IC) 20 may further include a compensation unit 32 and a compensation memory 32 in addition to the timing control unit 21, the sensing unit 22, and the data voltage generation unit 23. [ This external compensation module is a driver IC (D-IC) 20 and a compensation IC ('30' in FIG. The power IC (P-IC) 60 generates various driving power sources necessary for operating the external compensation module.

6, the electroluminescent display device of the present invention includes a driver IC (D-IC) 20 mounted on a chip-on-film (COF) and a flexible printed circuit board (FPCB) A storage memory 50 and a power source IC (P-IC) 60, and a host system 40 mounted on a system print substrate (SPCB).

The external compensation module of Fig. 6 is different from Fig. 5 in that the compensation unit 31 and the compensation memory 32 are mounted on the host system 40 without being mounted on the driver IC (D-IC) The external compensation module of Fig. 6 is meaningful in that the compensation IC ('30' in Fig. 1) is integrated into the host system 40 and can simplify the configuration of the driver IC (D-IC) have.

7, the electroluminescent display device of the present invention includes a driver IC (D-IC) 20 mounted on a chip-on-film (COF) and a flexible printed circuit board (FPCB) (Not shown) can be provided that includes a mounted storage memory 50, a compensation IC 30, a compensation memory 32 and a power IC (P-IC) 60 and a host system 40 mounted on a system printed circuit board (SPCB) have.

The external compensation module of Fig. 7 further simplifies the structure of the driver IC 20 by mounting only the voltage generator 23 and the sensor 21 on the driver IC 20, and the timing controller 31 and the compensator 32 Is mounted on the compensation IC 30 manufactured separately. The compensation IC 30, the storage memory 50, and the compensation memory 32 are mounted on the flexible printed circuit board (FPCB) to facilitate the up-loading and down-loading of the compensation value.

FIG. 8 is a view showing a sensing scheme for obtaining sensing data of N gray levels as an undesirable embodiment of the present invention.

Referring to FIG. 8, in order to obtain one average panel current (I) -voltage (V) curve for all the pixels of the panel as described above, it is necessary to sense current data of N gradations through sensing a plurality of times. The sensing scheme of Fig. 8 requires sensing time of N frames in order to sense current data of N gradations because current data of one gradation is sensed in one frame. For example, assuming that N is 7, the sensing scheme of FIG. 8 requires a sensing time of 7 frames in order to sense current data of 7 gradations including A to F. According to the sensing scheme of FIG. 8, as N increases, the sensing time required to obtain one average panel current (I) -voltage (V) curve increases.

FIGS. 9A and 9B are diagrams illustrating a sensing scheme for obtaining sensing data of N gray levels in one frame as a sensing scheme according to an embodiment of the present invention.

9A and 9B, a sensing method according to an embodiment of the present invention distributes N gray-scale data within one frame and senses current data of N gray-scale levels through one frame sensing. According to this, there is an advantage that the sensing time can be reduced to 1 / N as compared with the sensing method of FIG.

In order to implement such a sensing scheme, the timing controller (21 'in FIG. 1) distributes N (N is a positive integer of 2 or more) tone data within one frame. The timing controller 21 can divide the display panel into N virtual display blocks and map N gray scale data ('GDATA' in FIG. 1) to N virtual display blocks.

The timing controller 21 can map N gray-scale data within one frame to N virtual display blocks in the order of gray-scale size in reverse order, with reference to one side of the display panel. For example, assuming that N is 7, the timing controller 21 divides the display panel into seven virtual display blocks (BL1 to BL7) as shown in Fig. 9A. When the upper side of the display panel is used as a reference, (A to F) in the reverse order of the gradation size.

On the other hand, when one side of the display panel is used as a reference, the timing controller 21 can map N gray-scale data within one frame to N virtual display blocks in order of gray scale size. For example, assuming that N is 7, the timing controller 21 divides the display panel into seven virtual display blocks (BL1 to BL7) as shown in Fig. 9B. When the upper side of the display panel is used as a reference, (A to F) can be mapped in the order of gray scale.

On the other hand, although not shown in the figure, the timing control section 21 may randomly map N gray-scale data to N virtual display blocks.

As described above, the timing controller 21 maps the N gray-scale data to the N virtual display blocks according to the gradation size order, the gradation size reverse order, or randomly according to the stain characteristics of the display panel, An optimal average panel current (I) -voltage (V) curve can be obtained.

On the other hand, the timing controller 21 allocates two frames for sensing, maps N gray-scale data to N virtual display blocks in the order of gray-scale size (or in reverse order) in the first frame, By mapping the data to the N virtual display blocks in grayscale size reverse order (or sequential order), the accuracy of sensing can be further improved.

The data voltage generating unit (23 'in FIG. 1 and FIG. 2) converts N gradation data into sensing data voltages of N gradations, and supplies sensing data voltages of N gradations to the display panel in one frame do.

The sensing unit ('22' in FIGS. 1 and 2) senses the electrical characteristics of the display panel (ie, current data of N gradations) based on the sensing data voltages of N gradations, (&Apos; S-DATA ' in Fig. 1 and Fig. 2).

FIGS. 10A and 10B are diagrams illustrating a sensing scheme for obtaining sensing data of N gray levels in one frame as a sensing scheme according to another embodiment of the present invention.

10A and 10B, a sensing method according to another embodiment of the present invention distributes N gray-scale data within one frame, and senses current data of N gray-scale levels through one frame sensing. According to this, there is an advantage that the sensing time can be reduced to 1 / N as compared with the sensing method of FIG.

In order to implement such a sensing scheme, the timing controller (21 'in FIG. 1) distributes N (N is a positive integer of 2 or more) tone data within one frame. The timing control unit 21 can map N gray-scale data ('GDATA' in FIG. 1) to different display lines of the display panel a plurality of times within one frame. Here, the " display line " means not a physical signal line but a set of pixels consisting of pixels P adjacent in the horizontal direction to each other.

The display lines to which the N grayscale data are applied are physically close to each other and have substantially similar characteristics. That is, it has an effect similar to that in which N gray-scale data is applied to one pixel. Applying N gray-scale data for each of the N display lines through a plurality of mappings provides an effect similar to applying N gray-scale data to all the pixels of the display panel. Therefore, the present invention can obtain an optimum average panel current (I) -voltage (V) curve that meets the panel characteristics even through one-frame sensing.

The timing control section 21 can map N gray-scale data within one frame to display lines of the display panel a plurality of times in the order of gray-scale size, with reference to one side of the display panel. For example, assuming that N is 7, the timing controller 21 sets seven gradation data (A to F) on the display lines (..., HL1 To HL7, HL8 to HL14, ...) a plurality of times (total number of display lines / 7) in the order of gray scale.

On the other hand, when one side of the display panel is used as a reference, the timing control section 21 can map N gray-scale data in one frame to display lines of the display panel a plurality of times in reverse order of gray-scale size. For example, assuming that N is 7, the timing controller 21 sets seven gradation data (A to F) on the display lines (..., HL1 To HL7, HL8 to HL14, ...) a plurality of times (the total number of display lines / 7) in reverse order of the gray-scale size.

On the other hand, although not shown in the figure, the timing control section 21 may randomly map N gray-scale data to N virtual display blocks.

As described above, the timing controller 21 maps N gradation data to different display lines in order of gradation size, gradation size, or random order according to the stain characteristics of the display panel, (I) -voltage (V) curve of the average panel current.

On the other hand, the timing controller 21 allocates 2 frames for sensing, maps N gradation data in the first frame to the different display lines in the order of gradation size (or in reverse order), and in the second frame, Are mapped to different display lines in a grayscale size reverse order (or sequential order), the accuracy of sensing can be further improved.

The data voltage generating unit (23 'in FIG. 1 and FIG. 2) converts N gradation data into sensing data voltages of N gradations, and supplies sensing data voltages of N gradations to the display panel in one frame do.

The sensing unit ('22' in FIGS. 1 and 2) senses the electrical characteristics of the display panel (ie, current data of N gradations) based on the sensing data voltages of N gradations, (&Apos; S-DATA ' in Fig. 1 and Fig. 2).

As described above, according to the present invention, N gray-scale data used for obtaining the average IV curve of the display panel is distributed within one frame, and N gray-scale current data is sensed through one frame sensing, Can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 20: Driver IC
15: Gate driver 21: Timing controller
22: sensor 23: data voltage generator
30: Compensation IC 40: Host system
50: Storage memory

Claims (18)

A timing control section for distributing N (N is a positive integer equal to or larger than 2) tone data in one frame;
A data voltage generating unit for converting the N gray-scale data into sensing data voltages for N gray-scale levels, and supplying the sensing data voltages for N gray-scale levels to the display panel in one frame; And
And a sensing unit sensing the electrical characteristics of the display panel based on the sensing data voltages of N gradations and outputting N sensing gray scale data within one frame. The method according to claim 1,
Wherein the timing control unit comprises:
Wherein the display panel is divided into N virtual display blocks and the N gray-scale data is mapped to the N virtual display blocks. 3. The method of claim 2,
Wherein the timing control unit comprises:
And the N gray-scale data are mapped to the N virtual display blocks in order of gray scale size, with reference to one side of the display panel. 3. The method of claim 2,
Wherein the timing control unit comprises:
And mapping the N pieces of gray-scale data to the N virtual display blocks in a reverse order of the gray-scale size, with reference to one side of the display panel. 3. The method of claim 2,
Wherein the timing control unit comprises:
The N gray-scale data is mapped to the N virtual display blocks in the gray scale order in the first frame, and the N virtual display areas in the second frame subsequent to the first frame, And maps the blocks in a reverse order of the gradation size. The method according to claim 1,
Wherein the timing control unit comprises:
And maps the N gray-scale data to different display lines of the display panel a plurality of times. The method according to claim 6,
Wherein the timing control unit comprises:
And the N number of gradation data is mapped to the display line of the display panel a plurality of times in the order of the gradation size based on one side of the display panel. The method according to claim 6,
Wherein the timing control unit comprises:
And the N number of gray-scale data is mapped to the display line of the display panel a plurality of times in reverse order of the gray-scale size, with reference to one side of the display panel. The method according to claim 6,
Wherein the timing control unit comprises:
Wherein the N-th gray-scale data is mapped to the display line of the display panel a plurality of times in the order of gray-scale size when one side of the display panel is used as a reference, and in the second frame subsequent to the first frame, In a reverse order of the gradation size. Distributing N (N is a positive integer equal to or larger than 2) tone data in one frame;
Converting the N gray-scale data into sensing data voltages of N gray-scale levels, and supplying the sensing data voltages of N gray-scale levels to the display panel in one frame; And
Sensing the electrical characteristics of the display panel based on the data voltages for sensing the N gradations, and outputting the N sensed digital sensing data in one frame. 11. The method of claim 10,
The step of distributing N (N is a positive integer of 2 or more) tone data in one frame includes:
Dividing the display panel into N virtual display blocks and mapping the N gray-scale data to the N virtual display blocks. 12. The method of claim 11,
Wherein the N gray-scale data are mapped to the N virtual display blocks in order of gray-scale size, with reference to one side of the display panel. 12. The method of claim 11,
Wherein the N grayscale data are mapped to the N virtual display blocks in the first frame and the N virtual display blocks in the second frame subsequent to the first frame with reference to one side of the display panel, And mapped in blocks in gradation size in reverse order. 12. The method of claim 11,
Wherein the N gray-scale data is randomly mapped to the N virtual display blocks. 11. The method of claim 10,
The step of distributing N (N is a positive integer of 2 or more) tone data in one frame includes:
And mapping the N gray-scale data to different display lines of the display panel a plurality of times. 16. The method of claim 15,
Wherein the N gray-scale data is mapped to the display line of the display panel a plurality of times in the order of gray-scale size, with reference to one side of the display panel. 17. The method of claim 16,
Wherein the N gray-scale data is mapped to a display line of the display panel in reverse order of a plurality of gray-scale sizes, with reference to one side of the display panel. 17. The method of claim 16,
Wherein the N grayscale data is mapped to the display line of the display panel a plurality of times in the order of gray-scale size, with respect to one side of the display panel, and in the second frame subsequent to the first frame, Wherein the plurality of display lines are mapped to display lines in reverse order of a plurality of gray-scale sizes.

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