KR20180042358A - Three-dimensional NAND device including support pedestal structures for buried source lines and method of manufacturing the same - Google Patents

Abstract

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers positioned over a substrate, and an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along the same horizontal direction and adjacent to the common conductive straining structure. Each memory stack structure straddles the vertical interface between the conductive rail structure and the support matrix. The semiconductor channels in each memory stack structure are in contact with their respective conductive rail structures and support matrices.

Description

Three-dimensional NAND device including support pedestal structures for buried source lines and method of manufacturing the same

Related Applications

This application is a continuation-in-part of U.S. Patent Application No. 15 / 225,492, filed August 1, 2016, and U.S. Patent Application No. 15 / 225,492, entitled U.S. Patent Application No. 15 / 017,961, filed February 8, And U.S. Patent Application No. 15 / 017,961, which claims priority from U.S. Patent Application No. 62 / 258,250, filed on November 20, 2015, the entire contents of which are incorporated herein by reference The entirety of which is hereby incorporated by reference.

This disclosure relates generally to the field of semiconductor devices, and more specifically, to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabrication thereof.

Three-dimensional vertical NAND strings with 1 bit per cell are described in T. Endoh et al., &Quot; Novel Ultra High Density Memory with A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell ", IEDM Proc. (2001) 33-36.

According to an aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of electrically conductive layers and insulating layers located on a substrate; An array of memory stack structures, each memory stack structure comprising a semiconductor channel extending through an alternating stack and laterally surrounded by a memory film and a memory film; And a source conductive layer in contact with the lower portion of the sidewalls of each semiconductor channel and positioned between the alternating stack and the substrate. The source conductive layer includes a plurality of conductive rail structures extending along the first horizontal direction and laterally spaced from each other.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. A layer of matrix material comprising a plurality of channels extending along a first horizontal direction is formed over the substrate. A plurality of sacrificial rail structures are formed in the plurality of channels. Alternating stacks of insulating layers and spacer material layers are formed over the matrix material layer and the sacrificial rail structures. Memory stack structures are formed through portions of the alternating stack and sacrificial rail structures. Each of the memory stack structures includes a respective memory film and a respective semiconductor channel. A backside trench extending through the alternating stack is formed. The surfaces of the sacrificial rail structures are physically exposed below the back trenches. A plurality of sacrificial rail structures are selectively removed with respect to the layer of matrix material to form a plurality of laterally extending cavities. Portions of the memory film physically exposed to the side extension cavities are removed without removing portions of the memory film that are in contact with the layer of matrix material. A source conductive layer is formed in the bottom portion of the backside trench and in the plurality of lateral extension cavities and in contact with the sidewalls of the semiconductor channels.

According to one aspect of the disclosure, a three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers disposed on a substrate, an array of memory stack structures, each memory stack structure extending through an alternating stack, A semiconductor channel surrounded laterally by the memory film, and support structures located between the alternating stack and the substrate. The device may also include a source conductive layer under the alternating stack and over the substrate and in contact with the support structures.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. A layer comprising support pedestal structures and sacrificial material portions is formed over the substrate. Alternating stacks of insulating layers and spacer material layers are formed over the support pedestal structures and sacrificial material portions. The memory stack structures are formed through alternating stacks. Each of the memory stack structures includes a respective portion of the memory film and a respective semiconductor channel and protrudes into a respective sacrificial material portion. The sacrificial material portions are removed without removing the support pedestal structures to form at least one lateral extending cavity. Portions of the memory film physically exposed to the at least one lateral extension cavity are removed without removing portions of the memory film that are in contact with the support pedestal structures. Conductive rail structures are formed in at least one lateral extension cavity and on the sidewalls of the semiconductor channels.

According to one aspect of the disclosure, there is provided a three-dimensional memory device comprising: an alternating stack of electrically conductive layers and insulating layers disposed over a substrate; An array of memory stack structures, each memory stack structure comprising a semiconductor channel extending through an alternating stack and laterally surrounded by a memory film and a memory film; And an array of dielectric pillars positioned between the alternating stack and the substrate.

According to another aspect of the present disclosure, a method of manufacturing a three-dimensional memory device is provided. A sacrificial matrix layer is formed over the substrate. A sacrificial matrix layer is patterned to form an array of cavities. An array of dielectric pillars is formed by filling an array of cavities with a dielectric fill material. Alternating stacks of dielectric layers and spacer material layers are formed over the array of dielectric pillars and the sacrificial matrix layer. An array of memory stack structures is formed through alternating stack and sacrificial matrix layers. A sacrificial matrix layer is replaced with a source conductive layer.

1 is a vertical cross-sectional view of a first exemplary structure after forming a lower source insulator layer, a sacrificial matrix layer, and an upper source insulator layer, according to a first embodiment of the present disclosure;
2 is a vertical cross-sectional view of a first exemplary structure after forming an array of via cavities through a sacrificial matrix layer, according to a first embodiment of the present disclosure;
3 is a vertical cross-sectional view of a first exemplary structure after forming an array of dielectric pillars, according to a first embodiment of the present disclosure;
4A-4C are cross-sectional views of a first embodiment of the first, second, and third exemplary configurations, respectively, according to a first embodiment of the present disclosure, Horizontal cross-sections of an exemplary structure. The zigzag vertical planes (X-X ') correspond to the planes of the vertical cross-sectional view of Fig.
5 is a vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers, according to a first embodiment of the present disclosure;
6 is a vertical cross-sectional view of a first exemplary structure after forming memory openings extending through an alternate stack, according to a first embodiment of the present disclosure;
Figures 7A-7C illustrate an array of dielectric pillars, and an array of memory openings, respectively, for a first, second, and third exemplary configurations, according to a first embodiment of the present disclosure. 6 is a horizontal cross-sectional view of the first exemplary structure of Fig. The zigzag vertical planes (X-X ') correspond to the planes of the vertical cross-sectional view of Fig.
Figures 8A-8D are sequential vertical cross-sectional views of a memory opening in a first exemplary structure during various processing steps used to form a memory stack structure, in accordance with a first embodiment of the present disclosure;
Figure 9 is a vertical cross-sectional view of a first exemplary structure after forming memory stack structures, in accordance with a first embodiment of the present disclosure;
10 is a vertical section of a first exemplary structure after forming a set of stepped surfaces and a retro-stepped dielectric material portion, according to a first embodiment of the present disclosure; .
11 is a vertical cross-sectional view of a first exemplary structure after forming through-stack dielectric support pillars, according to a first embodiment of the present disclosure;
12A is a vertical cross-sectional view of a first exemplary structure after forming backside trenches, in accordance with a first embodiment of the present disclosure;
Figure 12b is a see-through top-down view of the first exemplary structure of Figure 12a. The zigzag vertical plane (A-A ') is the plane of the vertical section of Figure 12A for the case of the first exemplary configuration.
Figures 13A-13C illustrate an array of dielectric pillails, and an array of memory openings, respectively, for a first, second, and third exemplary configurations, according to a first embodiment of the present disclosure. Sectional views of the first exemplary structure of Figure 12A. Zigzag vertical planes (X-X ') correspond to the planes of the vertical cross-sectional view of Figure 12 (a).
Figure 14 is a vertical cross-sectional view of a first exemplary structure after forming back recesses, according to a first embodiment of the present disclosure;
15 is a vertical cross-sectional view of a first exemplary structure after replacing sacrificial material layers with electrically conductive layers, according to a first embodiment of the present disclosure;
16 is a vertical cross-sectional view of a first exemplary structure after forming an insulating spacer, in accordance with a first embodiment of the present disclosure;
17 is a vertical cross-sectional view of a first exemplary structure after forming a source line cavity by removing a sacrificial matrix layer, according to a first embodiment of the present disclosure;
18 is a vertical cross-sectional view of a first exemplary structure after forming a continuous source structure, in accordance with a first embodiment of the present disclosure;
19 is a vertical cross-sectional view of a first exemplary structure after forming various contact via structures, in accordance with a first embodiment of the present disclosure;
Figure 20 is a graph illustrating the magnitude of stresses to memory stack structures for various configurations of dielectric pillars, in accordance with embodiments of the present disclosure;
Figure 21 is a perspective view of a second exemplary structure having a cutout region for exemplary purposes after forming a source conductive layer, sacrificial material portions, and optional dielectric liner, in accordance with a second embodiment of the present disclosure;
Figure 22 is a perspective view of a second exemplary structure having a cutout region after forming support pedestal structures, in accordance with a second embodiment of the present disclosure;
23 is a perspective view of a second exemplary structure having a cutout region after forming alternating stacks of insulating layers and spacer material layers, according to a second embodiment of the present disclosure;
Figure 24 is a perspective view of a second exemplary structure having a cutout region after forming memory openings, in accordance with a second embodiment of the present disclosure;
Figure 25 is a perspective view of a second exemplary structure having a cutout region after forming memory stack structures, in accordance with a second embodiment of the present disclosure;
Figure 26 is a perspective view of a second exemplary structure having a cutout region after forming a back contact trench, in accordance with a second embodiment of the present disclosure;
Figure 27 is a perspective view of a second exemplary structure having a cutout region after removing sacrificial material portions and forming laterally extending cavities, in accordance with a second embodiment of the present disclosure;
28 is a perspective view of a second exemplary structure having a cutout region after removing physically exposed portions of memory films, according to a second embodiment of the present disclosure;
Figure 29 is an enlarged view of an area of the second exemplary structure of Figure 28;
Figure 30 is a perspective view of a second exemplary structure having a cutout region after forming a doped semiconductor material layer, according to a second embodiment of the present disclosure;
31 is a vertical cross-sectional view of the second exemplary structure shown in FIG. 30;
32 is a vertical cross-sectional view of a second exemplary structure after removing portions of the doped semiconductor material layer from within the backside contact trench and above the alternate stack and forming the drain regions, in accordance with a second embodiment of the present disclosure;
33 is a vertical cross-sectional view of a second exemplary structure after forming the backside recesses by removing spacer material layers, according to a second embodiment of the present disclosure;
34 is a vertical cross-sectional view of a second exemplary structure after forming the electrically conductive layers in the backside recesses, according to a second embodiment of the present disclosure;
35A is a vertical cross-sectional view of a second exemplary structure after forming an insulating spacer and a rear contact via structure, according to a second embodiment of the present disclosure;
35B is a horizontal cross-sectional view of a second exemplary structure along plane B-B 'in Fig. 35A. Fig. The plane A-A 'corresponds to the plane of the vertical sectional view of Fig. 35A.
36 is a vertical cross-sectional view of a second exemplary structure after forming additional contact via structures, in accordance with a second embodiment of the present disclosure;
37 is a vertical cross-sectional view of a third exemplary structure after forming an optional insulator layer, an optional blanket conductor layer, and a layer of matrix material, according to a third embodiment of the present disclosure;
Figure 38 is a vertical cross-sectional view of a third exemplary structure after forming a plurality of channels in the upper portion of the matrix material layer, according to the third embodiment of the present disclosure;
39 is a vertical cross-sectional view of a third exemplary structure after forming sacrificial liners and sacrificial rail structures in a plurality of channels, according to a third embodiment of the present disclosure;
40A is a plan view of the third exemplary structure of FIG. 39 when a first exemplary configuration for sacrificial rail structures is used for the third exemplary structure; FIG. The vertical plane (X-X ') represents the plane of the vertical sectional view of FIG.
40B is a plan view of the third exemplary structure of FIG. 39 when a second exemplary configuration for sacrificial rail structures is used for the third exemplary structure; The vertical plane (X-X ') represents the plane of the vertical sectional view of FIG.
41 is a vertical cross-sectional view of a third exemplary structure after forming an optional dielectric etch stop layer and an optional source interconnect layer, in accordance with a third embodiment of the present disclosure;
FIG. 42 illustrates a cross-sectional view of an embodiment of a semiconductor memory device in accordance with the third embodiment of the present disclosure, after forming the memory recesses to penetrate the arbitrary source interconnect layer, the optional dielectric etch stop layer, and the sacrificial rail structures and partially penetrate the matrix material layer. 3 is a vertical sectional view of a third exemplary structure;
43A is a plan view of the third exemplary structure of FIG. 42 when a first exemplary configuration for sacrificial rail structures is utilized for the third exemplary structure; FIG. The vertical plane (X-X ') represents the plane of the vertical sectional view of FIG.
43B is a plan view of the third exemplary structure of FIG. 42 when a second exemplary configuration for sacrificial rail structures is used for the third exemplary structure; The vertical plane (X-X ') represents the plane of the vertical sectional view of FIG.
44 is a vertical cross-sectional view of a third exemplary structure after forming an isolation dielectric layer by a non-conformal deposition method, according to a third embodiment of the present disclosure;
45 is a vertical cross-sectional view of a third exemplary structure after planarization of an isolation dielectric layer, according to a third embodiment of the present disclosure;
46 is a vertical cross-sectional view of a third exemplary structure after forming a first alternating stack of first insulating layers and first spacer material layers, according to a third embodiment of the present disclosure;
Figure 47 is a cross-sectional view of a first alternate stack, an optional source connecting layer, an optional dielectric etch stop layer, and sacrificial rail structures, according to a third embodiment of the present disclosure, Sectional view of a third exemplary structure after forming memory openings.
48a is a plan view of the third exemplary structure of Fig. 47 when a first exemplary configuration for sacrificial rail structures is utilized for the third exemplary structure; Fig. The vertical plane (X-X ') represents the plane of the vertical sectional view of Fig.
Figure 48B is a plan view of the third exemplary structure of Figure 47 when a second exemplary configuration for sacrificial rail structures is used for the third exemplary structure; The vertical plane (X-X ') represents the plane of the vertical sectional view of Fig.
49 is a vertical cross-sectional view of a third exemplary structure after forming first memory opening fill portions in first memory openings, according to a third embodiment of the present disclosure;
50 is a cross-sectional view of a third alternate stack, a second alternate stack, and a second alternate stack, according to a third embodiment of the present disclosure, including a second alternate stack, second memory opening fill structures to fill second openings through the second alternate stack, Sectional view of a third exemplary structure after forming third memory opening fill structures that fill third through openings.
51 is a vertical cross-sectional view of a third exemplary structure after forming inter-tier memory openings by removing memory opening fill structures, in accordance with a third embodiment of the present disclosure;
Figure 52 is a vertical cross-sectional view of a third exemplary structure after forming memory stack structures, dielectric cores, and drain regions, according to a third embodiment of the present disclosure;
53 is a vertical cross-sectional view of a third exemplary structure after forming a backside trench, according to a third embodiment of the present disclosure;
FIG. 54A is a top view of the third exemplary structure of FIG. 53 when a first exemplary configuration for sacrificial rail structures is utilized for the third exemplary structure; FIG. The vertical plane (X-X ') represents the plane of the vertical section of FIG.
FIG. 54B is a plan view of the third exemplary structure of FIG. 53 when a second exemplary configuration for sacrificial rail structures is utilized for the third exemplary structure; FIG. The vertical plane (X-X ') represents the plane of the vertical section of FIG.
55A and 55B are vertical cross-sectional views of a third exemplary structure after forming the semiconductor spacers and dielectric spacers in the backside trenches, according to a third embodiment of the present disclosure;
56 is a vertical cross-sectional view of a third exemplary structure after extending the backside trench through the source connection layer and forming the semiconductor oxide spacer, according to the third embodiment of the present disclosure;
Figure 57a is a plan view of the third exemplary structure of Figure 56 when a first exemplary configuration for sacrificial rail structures is used for the third exemplary structure; The vertical plane (X-X ') represents the plane of the vertical cross-sectional view of Figure 56.
FIG. 57B is a plan view of the third exemplary structure of FIG. 56 when a second exemplary configuration for sacrificial rail structures is utilized for the third exemplary structure; FIG. The vertical plane (X-X ') represents the plane of the vertical cross-sectional view of Figure 56.
58 is a vertical cross-sectional view of a third exemplary structure after forming lateral extending cavities by removing sacrificial rail structures, according to a third embodiment of the present disclosure;
59 is a vertical cross-sectional view of a third exemplary structure after removing sacrificial liners and portions of an optional dielectric etch stop layer, according to a third embodiment of the present disclosure;
60A is a vertical cross-sectional view of a third exemplary structure in the case where a first process sequence is used, including deposition of a doped semiconductor material layer, in accordance with a third embodiment of the present disclosure;
60B is a vertical cross-sectional view of an alternative arrangement for a third exemplary structure in which drain select gate structures are formed prior to forming the doped semiconductor material layer, according to the third embodiment of the present disclosure;
61 is a vertical cross-sectional view of a third exemplary structure after removing vertical portions of the doped semiconductor material layer to form the source conductive layer in the case of the first processing sequence, according to the third embodiment of the present disclosure;
62 is a vertical cross-sectional view of a third exemplary structure after forming a semiconductor oxide portion in the case of a first processing sequence, according to a third embodiment of the present disclosure;
63 is a vertical cross-sectional view of a third exemplary structure after forming the backside recesses in the case of the first processing sequence, according to the third embodiment of the present disclosure;
64 is a vertical cross-sectional view of a third exemplary structure after forming the electrically conductive layers and the continuous layer of conductive material in the case of the first process sequence, according to the third embodiment of the present disclosure;
65 is a vertical cross-sectional view of a third exemplary structure after removing a continuous layer of conductive material in the case of a first processing sequence, according to a third embodiment of the present disclosure;
FIG. 66 is a vertical cross-sectional view of a third exemplary structure after forming a dielectric separator structure in the case of a first process sequence, according to a third embodiment of the present disclosure; FIG.
67 is a vertical cross-sectional view of a third exemplary structure when a second process sequence is utilized that utilizes removal of semiconductor spacers, dielectric spacers, and semiconductor oxide spacers, in accordance with a third embodiment of the present disclosure;
68 is a vertical cross-sectional view of a third exemplary structure after forming the source conductive layer by selective semiconductor deposition in the case of the second process sequence, according to the third embodiment of the present disclosure;
69 is a vertical cross-sectional view of a third exemplary structure after a recess etch in the case of a second process sequence, according to a third embodiment of the present disclosure;
70 is a vertical cross-sectional view of a third exemplary structure after forming a semiconductor oxide portion in the case of a second processing sequence, according to a third embodiment of the present disclosure;
71 is a vertical cross-sectional view of a third exemplary structure after forming back recesses in the case of a second process sequence, according to a third embodiment of the present disclosure;
72 is a vertical cross-sectional view of a third exemplary structure after forming the electrically conductive layers and the continuous layer of conductive material in the case of the second process sequence, according to the third embodiment of the present disclosure;
73 is a vertical cross-sectional view of a third exemplary structure after forming a dielectric separator structure in the case of a second process sequence, according to a third embodiment of the present disclosure;
74 is a vertical cross-sectional view of an alternate embodiment of a third exemplary structure after forming a dielectric separator structure, according to a third embodiment of the present disclosure;
75A is a horizontal cross-sectional view of a third exemplary structure in a first configuration along the horizontal plane (A-A ') of FIG. 74, according to a third embodiment of the present disclosure;
75B is a horizontal cross-sectional view of a third exemplary structure in a first configuration along the horizontal plane (B-B ') of FIG. 74, according to a third embodiment of the present disclosure;
75C is a horizontal cross-sectional view of a third exemplary structure in a first configuration along the horizontal plane (C-C ') of FIG. 74, according to a third embodiment of the present disclosure;
75D is a horizontal cross-sectional view of a third exemplary structure in a first configuration along the horizontal plane (D-D ') of FIG. 74, according to a third embodiment of the present disclosure;
Figure 75E is a horizontal cross-sectional view of a third exemplary structure in a first configuration along the horizontal plane (E-E ') of Figure 74, according to a third embodiment of the present disclosure;
76A is a horizontal cross-sectional view of a third exemplary structure in a second configuration along the horizontal plane (A-A ') of FIG. 74, according to the third embodiment of the present disclosure;
FIG. 76B is a horizontal cross-sectional view of a third exemplary structure in a second configuration along the horizontal plane (B-B ') of FIG. 74, according to a third embodiment of the present disclosure;
76C is a horizontal cross-sectional view of a third exemplary structure in a second configuration along the horizontal plane (C-C ') of FIG. 74, according to a third embodiment of the present disclosure;
76D is a horizontal cross-sectional view of a third exemplary structure in a second configuration along the horizontal plane (D-D ') of FIG. 74, according to the third embodiment of the present disclosure;
76E is a horizontal cross-sectional view of a third exemplary structure in a second configuration along the horizontal plane (E-E ') of FIG. 74, according to a third embodiment of the present disclosure;

As discussed above, the present disclosure is directed to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabrication thereof, and various aspects thereof are described below. Embodiments of the present disclosure may be embodied in a variety of forms including multi-level memory structures, including non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices including a plurality of NAND memory strings . ≪ / RTI > The drawings are not drawn to scale. Multiple instances of an element may be duplicated, wherein a single instance of the element is exemplified unless the absence of duplication of elements is not explicitly stated or otherwise explicitly indicated. Ordinates such as " first ", "second ", and" third "are used merely to identify similar elements, and different ordinances may be used throughout the specification and claims of the present disclosure. As used herein, a first element located "on " a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, when there is a physical contact between the surface of the first element and the surface of the second element, the first element is "directly over" the second element.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the underlying or over the structure, or may have a smaller extent than the underlying, or overlying, extent of the structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be positioned between a pair of any horizontal planes that are between the top surface and the bottom surface of the continuous structure or that are on the top surface and bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate can be a layer, can include one or more layers on the substrate, and / or can have one or more layers on the substrate, above the substrate, and / or below the substrate.

As used herein, a "field effect transistor" refers to any semiconductor device having a semiconductor channel, through which current flows at a current density modulated by an external electric field. As used herein, "active region" refers to the source region of a field effect transistor or the drain region of a field effect transistor. The "top active region" refers to the active region of a field effect transistor located above another active region of the field effect transistor. The "bottom active region" refers to the active region of a field effect transistor located below another active region of the field effect transistor. A monolithic three-dimensional memory array is a memory array in which a plurality of memory levels are formed above a single substrate, such as a semiconductor wafer, without any intervening substrates. The term "monolithic" means that layers at each level of the array are deposited directly above the layers at levels below each of the arrays. Alternatively, two-dimensional arrays may be separately formed and then packaged together to form a non-monolithic memory device. For example, as described in U. S. Patent No. 5,915, 167 entitled " Three-dimensional Structure Memory ", non-monolithic memory structures are formed by forming memory levels on individual substrates and stacking memory levels vertically, Eclipse type memories were constructed. These memories are not true monolithic three dimensional memory arrays, since the memory levels may initially be formed on separate substrates, although the substrates may be thinned or removed from memory levels prior to bonding. The various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and may be fabricated using various embodiments described herein.

Referring to FIG. 1, a first exemplary structure according to a first embodiment of the present disclosure, which may be used to fabricate a device structure including, for example, vertical NAND memory devices, is illustrated. The first exemplary structure includes a substrate that can be a semiconductor substrate (e.g., a semiconductor substrate, such as a monocrystalline silicon wafer). The substrate may comprise a substrate semiconductor layer 10. The substrate semiconductor layer 10 is a semiconductor material layer and includes at least one elemental semiconductor material (e.g., silicon such as monocrystalline silicon), at least one III-V compound semiconductor material, at least one II- , At least one organic semiconductor material, or other semiconductor materials known in the art.

As used herein, "semiconductor material" is 1.0 x 10 ^-6 S / cm to 1.0 x 10 ⁵ refers to a material having a conductivity in the range of S / cm, and at a suitable doping by a dopant electric 1.0 It is possible to produce a doped material having an electrical conductivity in the range of S / cm to 1.0 x 10 < ⁵ > S / cm. As used herein, an "electrical dopant" is a p-type dopant that adds holes to valance bands in a band structure, or a conduction band in a band structure. Type dopant that adds electrons. As used herein, "conductive material" refers to a material having an electrical conductivity of greater than 1.0 x 10 ⁵ S / cm. As used herein, "insulating material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0 x ^10-6 S / cm. All measurements of electrical conductivities are made under standard conditions. The substrate semiconductor layer 10 may include at least one doped well (not explicitly shown) having a substantially uniform dopant concentration.

The first exemplary structure may have multiple regions for manufacturing different types of devices. These regions may include, for example, a memory array region 100, a contact region 300, and a peripheral device region 200. In one embodiment, the substrate semiconductor layer 10 may include at least one doped well in the memory array region 100. As used herein, "doped well" refers to a portion of a semiconductor material having a doping of substantially the same conductivity type (which may be p-type or n-type) and a dopant concentration at substantially the same level. The doped well may be the same as the substrate semiconductor layer 10 or may be a part of the substrate semiconductor layer 10. The conductivity type of the doped well is referred to herein as the first conductivity type, which may be p-type or n- type. The dopant concentration level of the doped well is referred to herein as the first dopant concentration level. In one embodiment, the first dopant concentration level may be in the range of 1.0 x 10 ¹⁵ / cm ³ to 1.0 x 10 ¹⁸ / cm ³ , but smaller and larger dopant concentration levels may also be used. As used herein, the dopant concentration level refers to the average dopant concentration for a given region.

Peripheral devices 210 may be formed on or on a portion of the substrate semiconductor layer 10 located within the peripheral device region 200. Peripheral devices may include various devices used to operate the memory devices to be formed in the memory array area 100 and may include driver circuits for various components of, for example, memory devices. Peripheral devices 210 may include passive components, such as, for example, field effect transistors and / or resistors, capacitors, inductors, diodes, and the like.

The lower source insulating layer 12 may be formed on the substrate semiconductor layer 10. The lower source insulating layer 12 provides electrical isolation from the substrate semiconductor layer 10 of a subsequent source structure to be formed subsequently. Isolated lower source layer 12 is, for example, may comprise silicon oxide and / or dielectric metal oxide (such as _{HfO 2, ZrO 2, LaO 2} ). Thickness of the lower source insulating layer 12 may be in the range of 3 nm to 30 nm, but smaller thicknesses and larger thicknesses may also be used.

A sacrificial matrix layer 14 may be formed over the lower source insulating layer 14. [ The sacrificial matrix layer 14 includes a material that can be selectively removed with respect to the materials of the upper source insulating layer and the insulating spacer to be selectively formed with respect to the material of the lower source insulating layer 12 and subsequently. For example, the sacrificial matrix layer 14 may comprise a semiconductor material such as a polysilicon or a silicon-germanium alloy, or may comprise an amorphous carbon, an organic polymer, or an inorganic polymer. The sacrificial matrix layer 14 may be deposited by chemical vapor deposition, physical vapor deposition, or spin coating. The thickness of the sacrificial matrix layer 14 may be in the range of 10 nm to 60 nm, but smaller thicknesses and larger thicknesses may also be used.

An optional upper source insulating layer 16 may be formed over the sacrificial matrix layer 14. [ The upper source insulating layer 16 provides electrical isolation of subsequent source structures to be subsequently formed, from the subsequently formed electrically conductive layers. The upper source insulating layer 16 may comprise, for example, silicon oxide and / or a dielectric metal oxide (such as HfO ₂ , ZrO ₂ , LaO ₂ , etc.). Thickness of the upper source insulating layer 16 may be in the range of 3 nm to 30 nm, but smaller thicknesses and larger thicknesses may also be used. If the subsequent alternating stack to be formed on the top source insulating layer 16 starts with a sacrificial material layer, then the top source insulating layer 16 is preferably included. When the subsequent alternating stack to be formed on the upper source insulating layer 16 starts with an insulating layer, the upper source insulating layer 16 is optional and the first insulating material of the alternating stack functions as the upper source insulating layer 16 That is, it can be identified as the upper source insulating layer 16. Although the present disclosure is described using an embodiment different from the lowermost insulating layer of the alternate stack in which the upper source insulating layer 16 is to be formed later, the same embodiments as the lowermost insulating layer 16 are clearly contemplated have.

Referring to FIG. 2, a photoresist layer (not shown) may be applied over the top source insulating layer 16 and patterned in a lithographic fashion to form an array of openings therethrough. The pattern of arrays of openings in the photoresist layer may be transferred through the top source insulating layer 16 and the sacrificial layer 14 by anisotropic etching, such as reactive ion etching. The lower source insulating layer 12 may be used as an etching stop layer. If desired, the etch may continue through the bottom source insulating layer 12 to the top surface of the substrate semiconductor layer 10 or into the top surface. An array of via cavities 19 may be formed in the sacrificial matrix layer 14. The cavities 19 may extend up to the top surface of the substrate semiconductor layer 10 or into the substrate semiconductor layer 10 through the bottom source insulating layer 12 to the bottom source insulating layer 12. The array of via cavities 19 may have a periodic pattern. In one embodiment, each via cavity 19 may have substantially vertical sidewalls and / or may have a substantially circular horizontal cross-sectional shape. In one embodiment, each via cavity 19 may have a substantially cylindrical shape. In one embodiment, the array of via cavities 19 may be a two-dimensional periodic array of instances of a unit cell structure. The photoresist layer may be subsequently removed, for example, by ashing.

Referring to FIG. 3, a dielectric fill material is deposited in an array of via cavities 19, for example, by chemical vapor deposition or spin coating. The dielectric filler material may include, for example, silicon oxide (such as doped silicate glass or undoped silicate glass), dielectric metal oxide, silicon nitride, organosilicate glass, or combinations thereof. For example, the dielectric filler material may comprise silicon oxide. Surplus portions of the deposited dielectric fill material can be removed from above the horizontal plane including the top surface of the top source insulating layer 16 by a planarization process, which can utilize recess etch and / or chemical mechanical planarization.

The remaining portions of the dielectric fill material filling the via cavities 19 constitute an array of dielectric pillar 20. The array of dielectric pillars 20 may have a periodic pattern. In one embodiment, each dielectric pillar 20 may have substantially vertical sidewalls and / or may have a substantially circular horizontal cross-sectional shape. In one embodiment, each dielectric pillar 20 may have a substantially cylindrical shape. In one embodiment, the array of dielectric pillars 20 may be a two-dimensional periodic array of instances of a unit cell structure. The upper surfaces of the dielectric pillars 20 and the upper surface of the upper source insulating layer 16 may be coplanar - that is, they may be located in the same Euclidean plane.

Figures 4A-4C illustrate various exemplary patterns that may be used for arrays of dielectric pillars 20. [ Specifically, FIGS. 4A-4C illustrate an array of dielectric pillars 20 for first, second, and third exemplary configurations, respectively. The pattern illustrated in Fig. 4A is referred to herein as a zigzag pattern, the pattern illustrated in Fig. 4B is referred to herein as a lattice pattern, and the pattern illustrated in Fig. 4C is referred to herein as a diagonal pattern. The zigzag pattern may include zigzag rows of dielectric pillars 20 (i.e., serrated rows). The rows may extend parallel to the word line direction or parallel to the bit line direction. The lattice pattern may comprise a plurality of linear rows and columns of pillars 20 forming rectangular or square unit cells of pillars 20. The diagonal pattern may include a plurality of parallel diagonal rows of pillars 20 extending at an angle of 30 to 60 degrees, such as about 45 degrees, for the bit line direction and the word line direction. The rows form unit cells of a parallelogram shape with no right angle. The periodicity of each pattern can be selected to correspond to the pattern of memory openings to be formed subsequently. In one embodiment, the periodicity of each pattern of dielectric pillars 20 may be equal to, or an integer multiple of, the periodicity of memory openings to be formed subsequently along the same direction.

5, alternate stacks of first material layers (which may be insulating layers 32) and second material layers (which are referred to as spacer material layers) are formed over the top source insulating layer 16. As used herein, "material layer" refers to a layer comprising material throughout the layer. In one embodiment, the alternating stack may comprise spacer material layers positioned between the insulating layers 32 and a pair of respective vertically adjacent insulating layers 32. As used herein, a "spacer material layer" refers to a layer of material located between two different material layers, i. E., A layer of material above and a layer of material below. The spacer material layers may be formed as electrically conductive layers, or may be replaced with electrically conductive layers in subsequent processing steps.

As used herein, the alternating stack of first elements and second elements refers to a structure in which instances of first elements and instances of second elements alternate. Each instance of the first of the plurality of alternating elements not adjacent to the end is adjacent to the two instances of the second elements on either side and the end of the plurality of alternating elements Each of the second elements is adjacent to two instances of the first elements on both sides. The first elements may have the same thickness between them, or they may have different thicknesses. The second elements may have the same thickness therebetween, or they may have different thicknesses. A plurality of alternating first and second material layers may start with an instance of the first material layers or with an instance of the second material layers and may begin with an instance of the first material layers or with an instance of the second material layers . In one embodiment, instances of the first elements and instances of the second elements may form a repeating unit with periodicity within a plurality of alternating elements.

Each first material layer comprises a first material, and each second material layer comprises a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer (i.e., spacer material layers) may be a sacrificial material layer 42. In this case, the stack may comprise a plurality of alternating insulating layers 32 and sacrificial material layers 42 and may be formed of alternating stacks of in-process stacks, including insulating layers 32 and sacrificial material layers 42, -process alternating stack. As used herein, an "alternating stack" of first and second elements is a structure in which the instances of the first element and the instances of the second element are alternating along the same direction, such as the vertical direction. As used herein, a "prototype" structure or "in-process" structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified. Thus alternating stacks 32 and 42 in the process may be formed on the layer stack of lower source insulator layer 12, sacrificial matrix layer 14, and upper source insulator layer 16.

In alternate embodiments, alternate stacks 32 and 42 may include insulating layers 32 of a first material and sacrificial material layers 42 of a second material different from the materials of insulating layers 32 . The first material of the insulating layers 32 may be at least one insulating material. Accordingly, each insulating layer 32 can be an insulating material layer. The insulating materials that may be used for the insulating layers 32 include silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric material dielectric metal oxides and silicates thereof, commonly known as high-k dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof But are not limited to, organic insulating materials. In one embodiment, the first material of the insulating layers 32 may be silicon oxide.

The second material of the sacrificial material layers 42 is a sacrificial material that can be selectively removed relative to the first material of the insulating layers 32. As used herein, when the removal process removes the first material at a rate that is at least twice the removal rate of the second material, removal of the first material is "optional" for the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material for the second material.

The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of sacrificial material layers 42 may be subsequently replaced with electrically conductive electrodes, which may, for example, function as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers 42 may be silicon nitride or spacer material layers comprising a semiconductor material, including at least one of silicon and germanium.

As an illustrative example, the insulating layers 32 may comprise silicon oxide, and the sacrificial material layers may comprise silicon nitride. As used herein, a silicon nitride, or silicon nitride material, comprises at least one Group IV element in which silicon accounts for more than 50 atomic percent of at least one Group IV element and nitrogen is responsible for more than 50 atomic percent of the non- Group element and at least one non-metallic element. Thus, the silicon nitrides include Si ₃ N ₄ and silicon oxynitride where the atomic concentration of nitrogen is greater than the atomic concentration of oxygen. As used herein, a silicon oxide, or silicon oxide material, comprises at least one Group IV element in which silicon accounts for more than 50 atomic percent of at least one Group IV element and oxygen is responsible for more than 50 atomic percent of the non- Group element and at least one non-metallic element. The silicon oxides include silicon dioxide, an oxide of silicon-germanium alloy in which the atomic concentration of silicon is greater than the atomic concentration of germanium, a silicon oxynitride in which the atomic concentration of oxygen is greater than the atomic concentration of nitrogen, and (phosphosilicate glass, Silicate glass, borophosphosilicate glass, organosilicate glass, and the like). The first material of the insulating layers 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, when silicon oxide is used for the insulating layers 32, tetraethyl orthosilicate (TEOS) can be used as the precursor material for the CVD process. The second material of sacrificial material layers 42 may be formed by, for example, CVD or atomic layer deposition (ALD).

Thicknesses of the insulating layers 32 and sacrificial material layers 42 may be in the range of 20 nm to 50 nm but may be less than the thickness of each insulating layer 32 and of each sacrificial material layer 42 And larger thicknesses may be used. The number of repetitions of the pairs of insulating layer 32 and the sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 may be in the range of 2 to 1,024, and typically 8 to 256, Can also be used. The upper and lower gate electrodes in the stack may function as select gate electrodes. In one embodiment, each sacrificial material layer 42 in alternating stacks 32 and 42 may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

Optionally, an insulating cap layer 70 may be formed on the alternating stacks 32, 42. The insulating cap layer 70 includes a dielectric material that is different from the material of the sacrificial material layers 42. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that may be used for the insulating layers 32, as described above. The insulating cap layer 70 may have a greater thickness than each of the insulating layers 32. The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

Referring to Figure 6, a lithographic material stack (not shown) comprising at least a photoresist layer may be formed over the insulating cap layer 70 and the alternating stacks 32 and 42, and a lithographic method As shown in FIG. The pattern in the lithographic material stack is passed through the optional insulating cap layer 70 and through the entirety of the alternating stacks 32 and 42 by at least one anisotropic etching using the patterned lithographic material stack as an etch mask And the upper source insulating layer 16, the sacrificial matrix layer 14, and the lower source insulating layer 12. In this case, An insulating cap layer 70 under the openings in the patterned lithographic material stack, alternating stacks 32 and 42, an upper source insulating layer 16, a sacrificial matrix layer 14, and a lower source insulating layer 12, Are etched to form memory openings (49). In other words, the pattern in the patterned lithographic material stack is passed through the optional insulating cap layer 70, through the entirety of the alternating stacks 32 and 42, and through the top source insulating layer 16, the sacrificial matrix layer 14 ) And transferring the substrate semiconductor layer 10 partially through the lower source insulating layer 12 and optionally forming the memory openings 49. The chemistry of the anisotropic etch process used to etch the materials of the alternating stacks 32 and 42 alternately occurs to optimize the etching of the first and second materials in the alternating stacks 32 and 42 . The anisotropic etch may be, for example, a series of reactive ion etches. Optionally, the lower source insulating layer 12 may be used as an etch stop layer. The sidewalls of the memory openings 49 may be substantially vertical or may be tapered. The patterned lithographic material stack may be subsequently removed, for example, by ashing.

Figures 7a-7c illustrate the sacrificial material layer 14, the array of dielectric pillars 20, and the memory openings 49, respectively, in horizontal cross-sections along a horizontal plane through the sacrificial material layer 14, First, second, and third exemplary configurations for the array. In one embodiment, the array of dielectric pillars 20 and the array of memory openings 49 collectively constitute a two-dimensional periodic array of multiple instances of a unit cell structure ("U"). The unit cell structure U includes a plurality of memory openings 49 (such as four memory openings as illustrated in Figures 7A-7C) and at least one dielectric pillar 20 (as illustrated in Figure 7A) Two dielectric pillars 20 consisting of one complete pillar in the unit cell and one quarter of the four pillars in the apexes of the unit cell, or two dielectric pillars 20 in the unit cell, as illustrated in Figs. 7B and 7C, Which may be a single dielectric pillar 20 comprised of 1/4 of the four pillars at the apexes of the pillar). In one embodiment, the array of memory openings 49 may comprise a hexagonal array of memory openings 49. In one embodiment, The ratio of the total number of the plurality of memory openings 49 in the unit cell structure U to the total number of at least one dielectric pillar 20 in the unit cell structure U is in the range of 2 to 4 Can be. For example, the ratio may be 2 as illustrated in Figure 7a, or 4 as illustrated in Figure 7b, or 3 as illustrated in Figure 7c.

A memory stack structure may be formed in each memory opening 49 in subsequent processing steps. FIGS. 8A-8D illustrate a process for forming a memory stack structure in the memory opening 49. FIG. Although specific embodiments of the formation of memory stack structures are illustrated herein, embodiments in which different types of memory stack structures are formed are specifically contemplated herein.

Referring to FIG. 8A, a memory opening 49 is illustrated. The memory opening 49 penetrates the stack of layers of insulating cap layer 70, alternating stacks 32 and 42 and upper source insulating layer 16, sacrificial matrix layer 14 and lower source insulating layer 12 And optionally into the upper portion of the substrate < RTI ID = 0.0 > semiconductor < / RTI > The recess depth of the bottom surface of each memory opening 49 with respect to the top surface of the substrate semiconductor layer 10 may range from 0 nm to 30 nm, but larger recess depths may also be used. Optionally, sacrificial material layers 42 may be partially recessed laterally to form lateral recesses (not shown), for example, by isotropic etching.

Referring to FIG. 8B, a set of layers for forming a memory film is deposited in each memory opening. The set of layers may include, for example, an optional outer blocking dielectric layer 502L, an optional inner blocking dielectric layer 503L, a charge storage element layer 504L, and a tunneling dielectric layer 506L .

Specifically, each of the outer and inner blocking dielectric layers 502L and 503L may comprise at least one dielectric material, which may be silicon oxide, a dielectric metal oxide, or a combination thereof. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one non-metal element, such as at least one metal element, oxygen, and nitrogen. In one embodiment, at least one of the outer and inner blocking dielectric layers 502L, 503L may comprise a dielectric metal oxide having a dielectric constant greater than 7.9, i. E., A dielectric constant greater than the dielectric constant of silicon nitride . Non-limiting examples of the dielectric metal oxides are aluminum oxide (Al ₂ O _3), hafnium oxide (HfO _2), lanthanum oxide (LaO _2), yttrium oxide (Y ₂ O _3), tantalum oxide (Ta ₂ O _5), Their silicates, their nitrogen doped compounds, their alloys, and their stacks. Dielectric metal oxides may be deposited by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or a combination thereof. Additionally or alternatively, at least one of the outer and inner blocking dielectric layers 502L and 503L may comprise silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the barrier dielectric layers 502L and 503L may comprise a stack of aluminum oxide and silicon oxide. Each of the outer and inner barrier dielectric layers 502L and 503L may be formed by a conformal deposition method such as a low pressure chemical vapor deposition, an atomic layer deposition, or a combination thereof. The thickness of the blocking dielectric layers 502L, 503L may be in the range of 1 nm to 30 nm, but smaller thicknesses and larger thicknesses may also be used.

The charge storage element layer 504L may comprise a single layer of a charge trapping material comprising a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage element layer 504L may be formed as a plurality of electrically isolated portions (e.g., floating gates) by being formed in the lateral recesses into, for example, Or a conductive material such as doped polysilicon or metal material to be patterned. In one embodiment, the charge storage element layer 504L comprises a silicon nitride layer.

The charge storage element layer 504L may be formed as a single memory material layer of homogeneous composition or may comprise a stack of multiple memory material layers. The plurality of memory material layers, when utilized, may be formed of a material such as conductive materials (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or tungsten silicide, molybdenum silicide, tantalum silicide, (E.g., a metal silicide such as nickel silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material comprising at least one element semiconductor element or at least one compound semiconductor material) Spaced apart floating gate material layers. Alternatively or additionally, the charge storage element layer 504L may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage element layer 504L may comprise conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage element layer 504L may be formed by any suitable deposition technique for depositing, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) . Thickness of charge storage element layer 504L may be in the range of 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used.

Tunneling dielectric layer 506L includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling may be performed via hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer. The tunneling dielectric layer 506L may comprise one or more of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum and hafnium oxides), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / / RTI > In one embodiment, the tunneling dielectric layer 506L may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly known as ONO stacks. In one embodiment, the tunneling dielectric layer 506L may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. Thickness of the tunneling dielectric layer 506L may be in the range of 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used.

As an illustrative example, the optional outer blocking dielectric layer 502L may comprise a dielectric metal oxide such as aluminum oxide and the inner blocking dielectric layer 503L may comprise a dielectric oxide of a semiconductor material such as silicon oxide . The charge storage element layer 504L may comprise any type of charge storage material and may be formed as a continuous material layer comprising a charge trapping material or may be formed, for example, by a conformal deposition process and an anisotropic etch May be formed of a plurality of vertically isolated charge trapping material portions located at respective levels of sacrificial material layers 42 by being deposited in regions recessed by the combination. The tunneling dielectric layer 506L includes a material that can be used as a tunneling dielectric material, which may be, for example, a silicon oxide or ONO stack.

A semiconductor channel layer 60L may be deposited over the tunneling dielectric layer 506L. The semiconductor channel layer 60L may comprise at least one elemental semiconductor material, at least one Group III-V compound semiconductor material, at least one Group II-VI compound semiconductor material, at least one organic semiconductor material, And other semiconductor materials. In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polysilicon. The semiconductor channel layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). Thickness of the semiconductor channel layer 60L may be in the range of 2 nm to 10 nm, but smaller thicknesses and larger thicknesses may also be used. The cavity 49 'is formed in the volume of each memory opening 49 that is not filled with the deposited material layers 502L, 503L, 504L, 506L, 60L.

Referring to FIG. 8C, a dielectric material may be deposited to fill the cavity 49 'in each memory opening 49. The dielectric material may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self planarization deposition process such as spin coating. Exemplary dielectric materials that may be used to fill the cavities 49 'include silicon oxide (undoped silicate glass or doped silicate glass) and organosilicate glass.

Surplus portions of the dielectric material, the semiconductor channel layer 60L, the tunneling dielectric layer 506L, the charge storage element layer 504L, and the barrier dielectric layers 502L and 503L, A planarization process may be performed to remove it from above the horizontal plane. A recess etch and / or a chemical mechanical planarization process may be used. Each remaining portion of the outer blocking dielectric layer 502L in the memory opening constitutes the outer blocking dielectric 502. Each remaining portion of the inner blocking dielectric layer 503L within the memory opening constitutes the inner blocking dielectric 503. Each remaining portion of the charge storage element layer 504L in the memory opening is filled with charge storage elements 504 (either as a single continuous memory material layer (charge storage layer) or at each level of the sacrificial material layers 42 Which may be embodied as discrete charge storage material portions. In one embodiment, portions of a single continuous memory material layer, including charge trapping dielectric material (such as silicon nitride), located at the levels of sacrificial material layers 42 constitute charge storage elements, The portions of the same single continuous memory material layer located at each level of the memory cell 32 provide electrical isolation between vertically adjacent charge storage elements. Each remaining portion of the tunneling dielectric layer 506L in the memory opening constitutes a tunneling dielectric 506. Each remaining portion of the semiconductor channel layer 60L in the memory opening constitutes a semiconductor channel 60, including a vertical semiconductor channel extending along the vertical direction. Each remaining portion of the dielectric material constitutes a dielectric core 62. Each adjacent set of optional outer isolation dielectric 502, inner isolation dielectric 503, a set of charge storage elements 504, and a tunnel dielectric 506 collectively constitute the memory film 50.

8D, each of the dielectric cores 62 may be vertically recessed, for example, by a recess etch for the memory film 50. The recess etch of the dielectric core 62 may or may not be selective for the semiconductor channel 60. Drain regions 63 may be formed by depositing a doped semiconductor material within each recessed region above dielectric cores 62. [ The doped semiconductor material can be, for example, doped polysilicon. Surplus portions of the deposited semiconductor material may be removed from above the top surface of the insulating cap layer 70 by, for example, chemical mechanical planarization (CMP) or recess etching to form the drain regions 63 have. Each set of memory film 50 and semiconductor channel 60 located within the same memory opening constitutes a memory stack structure 55.

FIG. 9 illustrates a first exemplary structure including multiple instances of the exemplary memory stack structure 55 of FIG. 8D. Each memory stack structure 55 includes at least one optional blocking dielectric 502, 503 (which may include an outer blocking dielectric 502 and an inner blocking dielectric 503) from outside to inside, Charge storage elements 504 (implemented as vertically spaced portions of the memory material layer located at the levels of each sacrificial material layer 42), a tunneling dielectric 506, and semiconductor channels 60 ). Although the present disclosure is described using an exemplary configuration for a memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including polycrystalline semiconductor channels.

Referring to FIG. 10, an optional first contact level dielectric layer 71 may be formed over the substrate semiconductor layer 10. As an optional feature, a first contact level dielectric layer 71 may or may not be formed. When first contact level dielectric layer 71 is formed, first contact level dielectric layer 71 may be formed of silicon oxide, silicon nitride, silicon oxynitride, porous or non-porous organosilicate glass (OSG) And combinations thereof. When an organosilicate glass is used, the organosilicate glass may or may not be doped with nitrogen. A first contact level dielectric layer 71 may be formed on a horizontal plane including the top surface of the insulating cap layer 70 and the top surfaces of the drain regions 63. The first contact level dielectric layer 71 may be deposited by chemical vapor deposition, atomic layer deposition (ALD), spin-coating, or a combination thereof. The thickness of the first contact level dielectric layer 71 may be in the range of 10 nm to 300 nm, but smaller thicknesses and larger thicknesses may also be used.

In one embodiment, the first contact level dielectric layer 71 may be formed as a layer of dielectric material having a uniform thickness throughout. The first contact level dielectric layer 71 may be formed as a single layer of dielectric material or may be formed as a stack of multiple layers of dielectric material. Alternatively, the formation of the first contact level dielectric layer 71 may be combined with the formation of at least one line level dielectric layer (not shown). Although the present disclosure is described using an embodiment in which the first contact level dielectric layer 71 is a separate structure from the optional second contact level dielectric layer or at least one line level dielectric layer to be deposited subsequently, Embodiments in which dielectric layer 71 and at least one line level dielectric layer are formed in the same process step and / or as the same material layer are specifically contemplated herein.

In one embodiment, a first contact level dielectric layer 71, an insulating cap layer 70, alternating stacks 32 and 42, and an upper source insulating layer 16, a sacrificial matrix layer 14, The layer stack of layer 12 may be removed from the peripheral device region 200, for example, by a masked etch process. In addition, a stepped cavity can be formed in the contact region 300 by patterning a portion of the alternating stacks 32, As used herein, a "stepped cavity" refers to a cavity having stepped surfaces. As used herein, "stepped surfaces" means that each horizontal surface is adjacent a first vertical surface extending upwardly from a first edge of the horizontal surface and extending downwardly from a second edge of the horizontal surface Refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces so as to be adjacent to the second vertical surface. "Step" refers to the vertical shift of the height of a set of adjacent surfaces.

The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in step as a function of the vertical distance from the top surface of the substrate < RTI ID = 0.0 > In one embodiment, a stepped cavity can be formed by repeatedly performing a set of processing steps. One set of processing steps may include, for example, a first type of etching process that vertically increases the depth of the cavity by one or more levels, and a second type of etching process that laterally extends the area to be vertically etched in the first type of subsequent etching process Two types of etching processes may be included. As used herein, the "level" of a structure comprising an alternating stack is defined as the relative position of a pair of first and second material layers in the structure. After formation of all the stepped surfaces, the masking material layers used to form the stepped surfaces can be removed, for example, by ashing. Multiple photoresist layers and / or multiple etch processes may be used to form stepped surfaces.

A dielectric material such as silicon oxide is deposited on the stepped cavity and on the peripheral devices 210 in the peripheral device region 200. [ Surplus portions of the deposited dielectric material may be removed from above the top surface of the first contact level dielectric layer 71, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material on the substrate semiconductor layer 10 in the peripheral device region 200 that fills the stepped cavity in the contact region 300 has a dielectric material portion 65 with an inverse step . As used herein, an "inverted stepped" element refers to an element having a monotonically increasing horizontal cross-sectional area as a function of stepped surfaces and the vertical distance from the top surface of the substrate where the element is present. When silicon oxide is used as the dielectric material, the silicon oxide of the inverted-step dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F. [ The top surface of the dielectric material portion 65 with the inverted step can be a coplanar with the top surface of the first contact level dielectric layer 71.

The regions over the peripheral devices 210 and the regions above the stepped cavities may be simultaneously filled with the same dielectric material or may be filled with the same dielectric material or different dielectric materials in different processing steps. The cavities on the peripheral devices 210 may be filled with a dielectric material before, simultaneously with, or after, filling the cavities on the stepped surfaces of the contact area 300 with dielectric material. Although the present disclosure is described using an embodiment wherein the cavity in the peripheral device region 200 and the stepped cavity in the contact region 300 are filled simultaneously, the cavity in the peripheral device region 200 and the contact region 300 are filled in different processing steps are clearly contemplated herein.

11, through-stack dielectric support pillars 7P extend through the inverted-step dielectric material portion 65 and / or through the first contact level dielectric layer 71 and / (32, 42). In one embodiment, the through-stack dielectric support pillars 7P may be formed in the contact region 300 located adjacent to the memory array region 100. Through-stack dielectric support pillars 7P may be formed, for example, through a dielectric material portion 65 with an inverted step and / or through alternating stacks 32 and 42 and through at least the substrate semiconductor layer 10, And by filling the openings with a dielectric material that is resistant to the etch chemistry to be used to remove the sacrificial material layers 42. [

In one embodiment, the through-stack dielectric support pillars 7P may comprise a dielectric metal oxide, such as silicon oxide and / or aluminum oxide. In one embodiment, a portion of the dielectric material deposited on the first contact level dielectric layer 71 at the same time as the deposition of the through-stack dielectric support pill 7P overlies the first contact level dielectric layer 71, Layer 73 as shown in FIG. Each of the through-stack dielectric support pillars 7P and the second insulating cap layer 73 is an arbitrary structure. Accordingly, a second insulating cap layer 73 may or may not be present on the insulating cap layer 70 and the dielectric material portion 65 with the inverted step. The first contact level dielectric layer 71 and the second insulating cap layer 73 are collectively referred to herein as at least one contact level dielectric layer 71,73. In one embodiment, at least one contact level dielectric layer 71,73 may comprise both the first and second contact level dielectric layers 71,73 and may be formed at any additional via level And optionally a dielectric layer. In another embodiment, at least one contact level dielectric layer 71,73 may comprise only a first contact level dielectric layer 71 or a second insulating cap layer 73, and any subsequent portions Lt; RTI ID = 0.0 > dielectric < / RTI > Alternatively, the formation of the first and second contact level dielectric layers 71,73 may be omitted, and at least one via-level dielectric layer may be formed later, i. E. After the formation of the first source contact via structure have.

The second insulating cap layer 73 and the through-stack dielectric support pillars 7P can be formed as a single continuous structure of an integrated structure, i.e. without any material interface therebetween. In another embodiment, the portion of the dielectric material deposited on top of the first contact level dielectric layer 71 at the same time as the deposition of the through-stack dielectric support pill 7P is deposited by, for example, chemical-mechanical planarization or recess etching Can be removed. In this case, there is no second insulating cap layer 73 and the top surface of the first contact level dielectric layer 71 can be physically exposed.

Referring to Figures 12A and 12B, a photoresist layer (not shown) may be applied over at least one contact level dielectric layer 71,73 and a lithographic method may be used to form openings in the spaces between the memory blocks As shown in FIG. In one embodiment, each opening in the photoresist layer may have a rectangular shape such that the pair of sidewalls of the opening extend laterally along the first horizontal direction.

The pattern of openings in the photoresist layer is formed by at least one contact level dielectric layer 71,73, a dielectric material portion 65 with inverted step, alternating stacks 32,42, and an optional top source insulator layer 16 The backside trenches 79 may be formed between each pair of neighboring clusters of memory stack structures 55 by transferring (if any) The sacrificial matrix layer 14 may be physically exposed at the bottom of each backside trench 79. The clusters of memory stack structures 55 may be laterally spaced by the backside trenches 79. Each cluster of memory stack structures 55 constitutes a memory block with portions of the alternate stack 32, 42 surrounding the cluster. The memory block may be laterally bounded by a pair of backside trenches 79. 12A is a vertical sectional view along the zigzag vertical plane (X-X ') in Fig. 12B. 12B is a perspective plan view in which the underlying elements are shown in dashed lines.

13A illustrates a horizontal cross-sectional view of a dashed rectangular area ("M") of the first exemplary structure of FIG. 12B along a horizontal plane comprising the sacrificial matrix layer 14 shown in FIG. 12A. 13A corresponds to a first (i. E., Zigzag) configuration for the array of dielectric pillars 20 and the array of memory stack structures 55. Figures 13b and 13c show corresponding horizontal cross sections for the second and third configurations. The direction of the zigzag rows of the pillars 20 in Figures 12B and 13A extends in the bit line direction perpendicular to the trench 79 extension direction and the word line direction. However, in other embodiments, the direction of the zigzag rows of the pillars 20 in Figures 12B and 13A may be as much as 90 degrees to extend perpendicularly to the bit line direction and parallel to the trench 79 extension direction and the word line direction. Can be rotated.

The array of dielectric pillars 20 and the array of memory stack structures 55 collectively includes a plurality of memory cell stack structures 55 and a plurality of unit cell structures U1 comprising at least one dielectric pillar 20. The array of dielectric pillars 20, Dimensional periodic array of instances of < RTI ID = 0.0 > The array of memory stack structures 55 may include a hexagonal array of memory stack structures 55. The ratio of the total number of the plurality of memory stack structures 55 in the unit cell structure U1 to the total number of at least one dielectric pillar 20 in the unit cell structure U1 may be in the range of 2 to 4.

14, the backside recesses 43 can be formed by removing the sacrificial material layers 42, which are selective for the insulating layers 32 and the sacrificial matrix layer 14. Specifically, an etchant is used to selectively etch the second material of the sacrificial material layers 42 with respect to the first material of the insulating layers 32 and the sacrificial matrix layer 14, for example, Trenches < RTI ID = 0.0 > 79 < / RTI > Back recesses 43 are formed in the volumes from which the sacrificial material layers 42 are removed. Removal of the second material of the sacrificial material layers 42 may be accomplished by depositing a first material of the insulating layers 32, a material of the through-stack dielectric support pill 7P, a material of the dielectric material portion 65 having a step- May be selective for the semiconductor material of the semiconductor layer 10, the material of the sacrificial matrix layer 14, and the material of the outermost layer of the memory stack structures 55 (such as the outer blocking dielectrics 502) . In one embodiment, sacrificial material layers 42 may comprise silicon nitride, and sacrificial matrix layer 14 may comprise polysilicon or amorphous silicon and may include insulating layers 32, And the reverse stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxides.

Each backside recess 43 may be a side extension cavity having a side dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each rear recess 43 may be greater than the height of the rear recess 43. [ A plurality of backside recesses 43 may be formed in the volumes of the second material of the sacrificial material layers 42, the material of the silicon oxide layer 501, and the material of the silicon nitride layer 502 removed. The memory openings in which the memory stack structures 50 and 60 are formed are referred to herein as front recesses or front cavities in contrast to the backside recesses 43. In one embodiment, memory array region 100 includes an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above (e.g., above substrate semiconductor layer 10) the substrate. In this case, each backside recess 43 may define a space for accommodating a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of back surface recesses 43 may extend substantially parallel to the upper surface of the substrate semiconductor layer 10. [ The backside recess 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the underlying insulating layer 32. In one embodiment, each backside recess 43 may have a uniform height throughout. In one embodiment, an optional back-off dielectric, such as an aluminum oxide dielectric, may be deposited into the backside recesses 43 to contact the exposed portions of the memory film 50 in the backside recesses 43 . In this embodiment, one or both of the front barrier dielectric layers 502 and / or 503 may be omitted.

Referring to FIG. 15, at least one metallic material may be deposited on the backside recesses to form the electrically conductive layers 46. Optionally, a back-off dielectric layer (not shown) may be formed on the physically exposed surfaces of the memory stack structures 55 and insulating layers 32 prior to deposition of the at least one metallic material. In one embodiment, the at least one metallic material is a conductive metal nitride layer comprising a conductive metal nitride such as TiN, TaN, or WN, or a conductive metal carbide layer comprising a conductive metal carbide such as TiC, TaC, or WC. ) Conductive metal compound layer. The conductive metal compound layer can be used as a barrier material layer, i.e. as a material layer that serves as a diffusion barrier for impurity atoms or gases, and / or as an adhesion promoter layer, i.e. for the insulating layers 32 (If no dielectric layer is used) or a metal material that functions as a material layer for enhancing adhesion of subsequent layers (if a back-off dielectric layer is used) for the back-facing dielectric layer. The conductive metal compound layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the conductive metal compound layer may range from 1 nm to 6 nm, but smaller thicknesses and larger thicknesses may also be used.

In one embodiment, the at least one metallic material may further comprise a metal layer. The metal layer may be deposited on the remaining portions of the backside recesses 43, on the sidewalls of the backside trenches 79, and on the top surface of the at least one contact level dielectric layer 71, An elemental metal or an intermetallic alloy. The metal layer can be deposited as a continuous metal layer directly over the surfaces of the conductive metal compound layer. The metal layer may be deposited by a conformal deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The remaining portions of the backside recesses 43 may be filled with a metal layer. The thickness of the deposited metal, as measured on the sidewalls of the back trenches 79, is such that the volume of each of the backside recesses 43 is filled with a random combination of backside blocking dielectric layer, metal compound layer, and metal layer May be greater than one half of the maximum height of the remaining portions of the backside recesses 43, as shown in FIG.

The metal layer may comprise a metal such as W, Co, Al, Cu, Ru, Au, Pt, or combinations thereof. The metal layer may be deposited by a chemical vapor deposition (CVD) process using a metal containing precursor gas or an atomic layer deposition (ALD) process. In one embodiment, the metal-containing precursor gas may be fluorine-free, ie, fluorine-free. Chemical vapor deposition or atomic layer deposition of a metal utilizes a metal precursor that can be easily evaporated to leave a high purity metal on the surface without causing surface damage. In one embodiment, an organometallic compound having relatively high vapor pressures and good thermal stability can be used as the metal precursor gas to deposit the metal without requiring hydrogen.

The vertically extending portions of the deposited metal material (s) can cover the entire sidewall of the backside trench 79. When deposited, the vertically extending portion of the deposited metal material (s) can be continuously adjacent to the metal portions located in each pair of vertically adjacent back recesses 43, and at least one contact level May be adjacent to the horizontal portion of the metal layer above the dielectric layers (71, 73).

An etching process may be performed to remove at least one metal material from above the at least one contact level dielectric layer 71,73 and from the sidewalls of the backside trenches 79. [ The etching process may include an isotropic etching step, an anisotropic etching step, or a combination thereof. In an illustrative example, reactive ion etching using at least one halide containing gas such as CHF ₃ , CClF ₃ , CF ₄ , SF ₆ , SiF ₄ , Cl ₂ , NF ₃ can be used in the etching process. Optionally, oxidants such as O ₂ or O ₃ may be used in combination with at least one halide-containing gas. Electrically conductive layers 46 remain around each backside trench 79 as discrete layers that are electrically isolated from each other.

16, insulating spacers 74 are formed on the sidewalls of each backside trench 79 by deposition of a continuous layer of dielectric material and anisotropic etching to remove horizontal portions of the continuous dielectric material layer . Each insulating spacer 74 includes a dielectric material, which may include, for example, silicon oxide, silicon nitride, a dielectric metal oxide, a dielectric metal oxynitride, or a combination thereof. Though the thickness of each insulating spacer 74, as measured at the lower end portion of the insulating spacer 74, may be in the range of 1 nm to 50 nm, smaller thicknesses and larger thicknesses may also be used . In one embodiment, the thickness of the insulating spacer 74 may be in the range of 3 nm to 10 nm.

Each insulating spacer 74 has insulating sidewalls of the insulating layers 32 and the electrically conductive layers 46 and an outer sidewall contacting the sidewalls of the upper source insulating layer 16. In addition, each insulating spacer 74 can contact the surface of the sacrificial matrix layer 14. Each insulating spacer 74 may thus be formed on the periphery of the respective back trenches 79 and on a portion of the sacrificial matrix layer 14 and on the sidewalls of the upper source insulator layer 16.

Referring to Figure 17, a sacrificial matrix layer 14 is formed over an array of dielectric pillars 20, a lower source insulating layer 12, an upper source insulating layer 16, -Stack dielectric pillar structures 7P, and insulating spacers 74, as shown in FIG. The sacrificial matrix layer 14 is preferably removed after formation of the electrically conductive layers 46. In one embodiment, the array of dielectric pillars 20, the bottom source insulating layer 12, the top source insulating layer 16, the through-stack dielectric pillar structures 7P, The sacrificial matrix layer 14 may comprise a semiconductor material (such as amorphous silicon, polysilicon, or a silicon-germanium alloy), amorphous carbon, or an organic or inorganic polymer. For example, if the sacrificial matrix layer 14 comprises polysilicon, the sacrificial material layer 14 may be deposited over the array of dielectric pillars 20, the bottom source insulating layer 12, the top source insulating layer 16, Wet etching using potassium hydroxide (KOH) can be used to selectively remove the through-stack dielectric pillar structures 7P, and the insulating spacers 74. [ The sidewalls of the memory stack structures 55 may be physically exposed to the source line cavity 15. In addition, the sidewalls of the dielectric pillars 20 can be physically exposed to the source line cavity 15.

The physically exposed portions of each memory film 50 may be removed after the sacrificial matrix layer 14 is removed. The physically exposed portions of the memory film 50 may be removed by isotropic etching, such as, for example, wet etching. Thus, the sidewalls of the semiconductor channels 60 are physically exposed at the level of the source line cavity 15. The remaining portions of each memory film 50 below the physically exposed sidewalls of the respective semiconductor channel 60 are connected to a memory film (not shown) located below the semiconductor channel 60 and above the source line cavity 15 50, and the same set of dielectric materials. Optionally, the annular source region 61 may be formed by introducing electrical dopants into the lower portion of each semiconductor channel 60 by plasma doping or gas phase doping.

Generally, depositing a polysilicon material portion on the annularly exposed portion of each semiconductor channel 60 and / or depositing an annularly exposed portion of each of the semiconductor channels 60 located at the level of the source line cavity 15 A polycrystalline silicon structure (implemented as source region 61) may be provided at the lower end of each semiconductor channel 60 by doping. Three types of polysilicon (including p + type polysilicon, undoped polysilicon, and n + type polysilicon) can be selected for a polysilicon structure that can function as polysilicon source region 61 . Table 1 provides a summary of the erase and read mechanisms for each type of polysilicon used for the source region 61.

The p + polysilicon source region may use combine erase, while other types of source regions may use GIDL erase. Advantages of embodiments of the present disclosure include, but are not limited to, preventing stack collapse using edge device area enhancement (due to the formation of dielectric pillars 20). The removal of the sacrificial matrix layer 14 does not require the use of reactive ion etching, but an isotropic etch process can be used to remove the sacrificial matrix layer 14.

18, at least one conformal deposition method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, and / or electroless plating to form the source line cavity 15 At least one conductive material is deposited. In one embodiment, the at least one conductive material may comprise a metal liner material such as a conductive metal nitride or a conductive metal carbide, and a metal filler material such as W, Cu, Al, Co, Ru, and alloys thereof . For example, a metal filler material layer 76A including a metal liner material layer 76A including a metal liner material to fill the source line trench 15 and back trench 79 during the same set of deposition processes, (76B) can be deposited. Portions of at least one conductive material above the horizontal plane, including the top surface of at least one contact level dielectric layer (71, 73), may be removed by a planarization process. In one embodiment, the planarization process may be a chemical mechanical planarization (CMP) process that utilizes one of the at least one contact level dielectric layer 71, 73 as a stop layer. A continuous source structure 76 may be formed within each successive volume of at least one backside trench 79 connected to source line trench 15 and source line trench 15. [ The source line trench 15 may be coupled to a plurality of backside trenches 79 and the continuous source structure 76 may include a source line trench 15 and a plurality of backside trenches 79. In one embodiment, Lt; RTI ID = 0.0 > volume. ≪ / RTI > The continuous source structures 76 may function as a source contact structure, or a combination of a source structure and a source contact structure.

The portion of each successive source structure 76 that fills the source line cavity 15 is referred to herein as the source conductive layer 76L. Thus, the source matrix layer 14 is replaced with a source conductive layer 76L extending in the horizontal direction parallel to the upper surface of the substrate (i.e., the substrate semiconductor layer 10). The source conductive layer 76L may contact the sidewalls of each dielectric pillar 20 in the array of dielectric pillar 20. Each portion of the continuous source structure 76 filling the backside trench 79 constitutes the source conductive via structure 76V. Each source conductive via structure 76Vt extends vertically through an alternating stack 32, 46 perpendicular to the top surface of the substrate 10. The continuous source structure 76 is an integral structure that does not have any interface between any of the source conductive via structures 76V and the source conductive layer 76L. As used herein, an "integral structure" refers to a single continuous structure that is not divided into a plurality of physically disjoined portions. As used herein, "interface" refers to differences in material composition that can be detected by analytical means (such as transmission electron microscopy, scanning electron microscopy, and / or secondary ion mass spectroscopy) Refers to a microscopic interface between two elements, characterized by the presence, or the presence of interfacial material.

Thus, a continuous source structure 76 can be formed by simultaneously filling the source line cavity 15 and the at least one backside trench 79 with at least one conductive material. Each source conductive via structure 76V is formed on the inner sidewall of the respective isolation spacer 74. [ A source line structure 76L including a polysilicon layer or a doped region deposited on the exposed sidewalls of each semiconductor channel 60 may be formed directly on the source region 61. [

19, a photoresist layer (not shown) may be applied over the top layer of the first exemplary structure (which may be, for example, a second insulating cap layer 73) 100, the peripheral device region 200, and the contact region 300, as shown in FIG. The locations and shapes of the various openings are selected to correspond to the electrical nodes of the various devices to be electrically contacted by the contact via structures. In one embodiment, a single photoresist layer may be used to pattern all openings corresponding to the contact via cavities to be formed, and all contact via cavities may be patterned using at least one anisotropic Can be simultaneously formed by an etching process. In another embodiment, a plurality of photoresist layers can be used in combination with a plurality of anisotropic etch processes to form different sets of contact via cavities having different patterns of openings in the photoresist layers. The photoresist layer (s) can be removed after each anisotropic etch process that transfers the pattern of openings in the respective photoresist layer through the underlying dielectric material layers and to the top surface of the respective electrically conductive structure have.

As an illustrative example, drain contact via cavities are formed above each memory stack structure 55 in the memory array region 100 such that the top surface of the drain region 63 is physically exposed at the bottom of each drain contact via cavity . The wordline contact via cavities are spaced apart from the stepped surfaces of the alternating stacks 32 and 46 so that the top surface of the electrically conductive layer 46 is physically exposed at the bottom of each wordline contact via cavity in the contact area 300. [ As shown in FIG. The device contact via cavity may be formed to each electrical node of the peripheral devices 210 to be contacted by the contact via structure in the peripheral device region 200. [

Various via cavities may be filled with at least one conductive material, which may be a combination of an electrically conductive metal liner material (such as TiN, TaN, or WN) and a metal filler material (such as W, Cu, or Al). Surplus portions of at least one conductive material may be removed from above at least one contact level dielectric layer 71,73 by a planarization process, which may include, for example, chemical mechanical planarization (CMP) and / Can be removed. Drain contact via structures 88 may be formed on the respective drain regions 63. [ Wordline contact via structures 84 may be formed on the respective electrically conductive layers 46. [ Peripheral device contact via structures 8P may be formed on the respective nodes of the peripheral devices 210. [ Additional metal interconnect structures (not shown) and interlayer dielectric material layers (not shown) may be formed over the first exemplary structure to provide electrical wiring between the various contact via structures.

A first exemplary structure according to embodiments of the present disclosure may include a three dimensional memory device. The three-dimensional memory device includes an alternate stack of electrically conductive layers 46 and insulating layers 32 positioned over the substrate 10, and an array of memory stack structures 55. Each memory stack structure 55 extends through alternating stacks 32 and 46 and includes a memory channel 50 and a semiconductor channel 60 laterally surrounded by the memory film 50. The memory stack 50 includes a memory channel 50, The three-dimensional memory device may further include an array of dielectric pillars 20 positioned between the alternating stacks 32, 46 and the substrate 10. A continuous source structure 76 may be provided that includes a source conductive layer 76L that horizontally extends and surrounds each dielectric pillar 20 in the array of dielectric pillars 20 laterally. The continuous source structure 76 may further include a source conductive via structure 76V that extends vertically through alternating stacks 32 and 46. The continuous source structure 76 may be an integral structure without an interface between the source conductive via structure 76V and the source conductive layer 76L. The source conductive layer 76L may comprise a buried source line or electrode, while the source conductive via structure 76V may comprise a source local interconnect.

The three dimensional memory device includes a lower source insulator layer 12 positioned between the substrate 10 and the source conductive layer 76L, a top source insulator layer 76 located between the source conductive layer 76L and the alternating stacks 32 and 46, An insulating spacer 16, and an insulating spacer 74 laterally surrounding the source conductive via structure 76V. In one embodiment, the continuous source structure 76 includes a metal dielectric liner 76A that contacts the sidewalls of the array of dielectric pillars 20 and extends above the top surface of alternating stacks 32 and 46, And a conductive fill material portion 76B surrounded by a dielectric liner 76A.

A surface region having a step difference can be provided in the contact region 300. The end portions of the electrically conductive layers 46 form steps with stepped surface areas. The source conductive layer 76L may extend laterally further than any of the electrically conductive layers 46. [ In one embodiment, the continuous source structure 76 may contact at least one of the outer sidewalls of each source region 61 and the annular bottom surface of the memory film 50.

In one embodiment, each dielectric pillar 20 in the array of dielectric pillars 20 has a top surface located at or below a first horizontal plane comprising the lowermost surface of the alternating stacks 32, 46 And may have a lowermost surface located at or above a second horizontal plane comprising the top surface of the substrate 10. In one embodiment, the array of dielectric pillars 20 may comprise silicon oxide. The dielectric pillars 20 ending under the alternating stacks 32 and 46 are different from the through-stack dielectric support pillars 7P extending through the entirety of the alternating stacks 32 and 46.

In one embodiment, the monolithic three-dimensional memory device comprises a vertical NAND device located on a substrate, and the electrically conductive layers 46 comprise or are electrically connected to a respective word line of the NAND device. In one embodiment, the substrate 10 comprises a silicon substrate, and the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located on a silicon substrate. At least one memory cell at a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell at a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may include an integrated circuit including a driver circuit for a memory device located thereon.

The array of monolithic three-dimensional NAND strings may include a plurality of semiconductor channels 60. At least one end portion of each semiconductor channel of the plurality of semiconductor channels (60) extends substantially perpendicular to the upper surface of the substrate. The array of monolithic three-dimensional NAND strings may comprise a plurality of charge storage elements. Each charge storage element may be located adjacent to a respective semiconductor channel of a plurality of semiconductor channels 60. The array of monolithic three-dimensional NAND strings may include a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode positioned at a first device level and a second control gate electrode positioned at a second device level.

Referring to FIG. 20, the graph illustrates the magnitude of stresses to memory stack structures 55 for various configurations of dielectric pillars, in accordance with embodiments of the present disclosure. The unit of vertical axis (relative to the magnitude of the stress) is arbitrary. Quot; Ref "refers to a configuration in which no array of dielectric pillars 20 is present. The term "diagonal layout" refers to the third configuration of the array of dielectric pillars 20. The term "zigzag layout" refers to the first configuration of the array of dielectric pillars 20.

The array of dielectric pillars 20 reduces mechanical stresses to provide stable structures during the fabrication process. The simulation data of FIG. 20 was obtained by assuming that the 100 layers in alternating stacks 32 and 46 utilize a linear iteration boundary condition. Based on computer simulations of finger tilting and stresses on the dielectric pillars 20 under unbalanced capillary forces, the risk of finger tilting amplitude, or finger collapse, is reduced by 25% in the zigzag layout .

A first exemplary embodiment of the present disclosure utilizes a continuous source structure 76 as the bottom connection to the semiconductor channels 60 in the memory openings 49. The array of dielectric pillars 20 provides structural protection from mechanical stresses to the memory stack structures 55 during formation of the source conductive layer 76L.

The array of dielectric pillars 20 can be used to prevent collapse of the source line cavity 15 and to enable the formation of a continuous source structure 76 that includes the source conductive layer 76L. Although the presence of the dielectric pillars 20 may adversely affect the source-side contact resistance, deterioration of the source-side contact resistance can be managed at the densities illustrated in Figs. 13A to 13C.

The dielectric pillars 20 are support pedestal structures made up essentially of a dielectric material. The source conductive layer 76L is below the alternating stacks 32 and 46 and above the substrate comprising the substrate semiconductor layer 10. [ The source conductive layer 76L is electrically shorted to the lower end of each semiconductor channel of the semiconductor channels 60. [ As the support pedestal structures, the dielectric pillars 20 are in contact with the source conductive layer 76L and are located under the alternating stacks 32, 46.

According to another aspect of the present disclosure, an embodiment is disclosed in which support pedestal structures can be provided as a semiconductor material or a dielectric material. For example, support pedestal structures may be provided as doped semiconductor material portions. In one embodiment, the support pedestal structures may be formed as rail structures. As used herein, a rail structure refers to a structure that extends laterally along the horizontal direction and has a uniform height.

Referring to FIG. 21, a second exemplary structure according to a second embodiment of the present disclosure is illustrated. The second exemplary structure includes a substrate 8, which may be a semiconductor substrate, a conductive substrate, or an insulator substrate. The substrate 8 may have a thickness sufficient to provide structural support for the elements formed thereon. In one embodiment, the thickness of the substrate 8 may range from 50 micrometers to 1 mm, but smaller thicknesses and larger thicknesses may also be used. In one embodiment, the substrate 8 may be a single crystal substrate or a semiconductor substrate such as a polycrystalline substrate. Semiconductor devices (such as the peripheral devices 210 described above) may be formed in a peripheral device region (not shown) of the substrate 8 before or after the formation of the memory devices to be described below. These semiconductor devices may include peripheral devices that may be utilized to support the operation of memory devices to be subsequently formed on the substrate 8.

An insulator layer 120 may be formed over the substrate 8. Insulator layer 120 includes a dielectric material such as silicon oxide. The thickness of the insulator layer 120 may be in the range of 10 nm to 300 nm, but smaller thicknesses and larger thicknesses may also be used.

A source conductive layer 140 (e.g., source line or source electrode) may be formed over the insulator layer 120. The source conductive layer 140 includes a conductive material, which may include a metal material, a heavily doped semiconductor material, a metal-semiconductor alloy (such as a metal silicide), or a combination thereof. In one embodiment, the source conductive layer 140 may comprise a tungsten silicide layer or a vertical stack of a conductive metal nitride layer (such as a TiN layer) and a metal layer (such as a tungsten layer), from top to bottom. The source conductive layer 140 may be formed by conformal or non-conformal deposition and may be formed as a planar material layer having a uniform thickness throughout.

The sacrificial material portions 151 may include a plurality of sacrificial material portions 151 that extend along the first horizontal direction hd1 (e.g., the word line direction) and laterally spaced from each other along the second horizontal direction hd2 Structures may be formed. The sacrificial material portions 151 may be formed by depositing a sacrificial material layer as a layer of planar material, applying and patterning a photoresist layer thereon, and an anisotropic etch process (such as a reactive ion etch process) And then transferring the pattern of the planar material through the planar material layer. The source conductive layer 140 may serve as a stop layer for an anisotropic etching process. Each remaining portion of the sacrificial material layer constitutes a sacrificial material portion 151. The photoresist layer may be subsequently removed, for example, by ashing.

In one embodiment, the width of each sacrificial material portion 151 may be selected to be about the center-to-center distance between pairs of neighboring rows of memory openings to be formed later along the first horizontal direction hd1. In one embodiment, the spacing between each pair of adjacent sacrificial material portions 151 can be about the center-to-center distance between pairs of neighboring rows of memory openings to be formed later along the first horizontal direction hd1 . In one embodiment, the sacrificial material portions 151 may form a one-dimensional periodic array along the second horizontal direction hd2 and may have a periodicity of the one-dimensional array (i. E., The width of the sacrificial material portion 151, The sum of the spacing between pairs of sacrificial material portions 151) may be equal to twice the inter-row distance between the memory openings to be formed subsequently.

The sacrificial material portions 151 may comprise a semiconductor material or a dielectric material. In one embodiment, the sacrificial material layer and the sacrificial material portions 151 formed therefrom comprise a semiconductor material that is not intentionally doped. Intentionally undoped semiconductor material may be intrinsic or may have low concentrations of electrical dopants due to incorporation of dopants at trace levels during deposition. As used herein, "undoped semiconductor material" collectively refers to semiconductor materials comprising an intrinsic semiconductor material and electrical dopants with an atomic concentration of less than 1.0 x 10 ¹⁶ / cm ³ . An undoped semiconductor material may be formed by intentionally not incorporating electrical dopants during deposition of the semiconductor material.

In one embodiment, the undoped semiconductor material is a heavily doped semiconductor material, i. E. Having a conductivity of greater than 1.0 x 10 ⁵ S / cm (e.g., having a dopant concentration of greater than 1.0 x 10 ¹⁹ / cm ³ ) Or may be a material that can be selectively removed with respect to the underlying semiconductor material. In one embodiment, the undoped semiconductor material of sacrificial material portions 151 may be amorphous silicon, polycrystalline or amorphous germanium, an amorphous silicon-germanium alloy, or a polycrystalline silicon-germanium alloy containing germanium at atomic concentrations greater than 40% . ≪ / RTI >

In other embodiments, the sacrificial material layer and sacrificial material portions 151 may comprise a dielectric material. In this case, the dielectric material of the sacrificial material portions 151 may be selected from materials that can be selectively removed with respect to the materials of the support pillars structures to be formed subsequently and selectively with respect to alternate stacks to be formed at a later time. For example, the sacrificial material portions 151 may comprise a dielectric material such as porous or non-porous organosilicate glass (OSG), amorphous carbon, or diamond-like carbon (DLC).

The dielectric liner 153 may optionally be formed as a layer of conformal material on top surfaces and sidewalls of the sacrificial material portions 151 and on physically exposed surfaces of the source conductive layer 140. The dielectric liner 153 may comprise a diffusion barrier material such as silicon nitride. The thickness of the optional dielectric liner 153 may range from 3 nm to 10 nm, but smaller thicknesses and larger thicknesses may also be used. The upper portions of the dielectric liner 153 are not shown in the cutout area of Figure 21 and all elements are removed from the drawing to more clearly illustrate the elements below the lower horizontal plane of the cutout area, . Linear trenches 159 are present between each pair of adjacent sacrificial material portions 151.

Referring to FIG. 22, support pedestal structures 156 are formed in the line trenches 159. A semiconductor material or a dielectric material may be deposited into the line trenches 159. Exemplary semiconductor materials that can be used for the support pedestal structure 156 is 1.0 x 10 ¹⁹ / cm ³ greater than, and preferably from 1.0 x 10 ²⁰ / cm ³ greater than (e.g., 5 x 10 ¹⁹ / cm ³ to Doped silicon (e. G., Amorphous silicon or polysilicon) containing boron at an atomic concentration of 5 x 10 ²¹ / cm ³ . In this case, to enable selective removal of the sacrificial material portions 151 relative to the support pedestal structures 156 in an etchant such as trimethyl-2-hydroxyethyl ammonium hydroxide (TMY), a support pedestal Boron doped silicon of structures 156 may be used in combination with sacrificial material portions 151 that include undoped amorphous silicon.

Exemplary insulator materials that may be utilized for the support pedestal structures 156 include undoped silicate glass (i.e., silicon oxide), doped silicate glass, silicon nitride, and dielectric metal oxide. In this case, the support pedestal structures 156 may be rail structures comprising a dielectric material and the sacrificial material portions 151 may be selectively removed relative to the support pedestal structures 156 (organosilicate glass , Amorphous carbon, or diamond-like carbon).

Surplus portions of the deposited material may be removed from above the horizontal plane including the top surface of the sacrificial material portions 151 by the planarization process. The planarization process may include a recess etch process and / or a chemical mechanical planarization. Each remaining portion of the deposited material in the line trenches 159 constitutes a support pedestal structure 156. Each support pedestal structure 156 may be a rail structure that extends laterally along the first horizontal direction. In one embodiment, the horizontal portions of the dielectric liner 153 may be removed from above the top surfaces of the sacrificial material portions 151 by a planarization process. In this case, the top surfaces of the sacrificial material portions 151 may be coplanar with the top surfaces of the support pedestal structures 156 (i.e., within the same plane). If a dielectric liner 153 is formed in the process step of Figure 21, a U-shaped portion of the dielectric liner 153 may be present between each support pedestal structure 156 and the source conductive layer 140.

Layers 151, 153, and 156 including support pedestal structures 156 and sacrificial material portions 151 are formed on the source conductive layer 140. In one embodiment, the support pedestal structures 156 may include a first semiconductor material having a doping of a first conductivity type (which may be p-type or n-type) and the sacrificial material portions 152 And an undoped semiconductor material (such as amorphous undoped silicon). In an exemplary example, the first semiconductor material may comprise a p-doped silicon-containing material, and the undoped semiconductor material may comprise an undoped silicon-containing material.

23, an alternating stack of first material layers and second material layers is formed over the upper surfaces of the support pedestal structures 156 and the sacrificial material portion 151. As shown in FIG. As used herein, "material layer" refers to a layer comprising material throughout the layer. As used herein, the alternating stack of first elements and second elements refers to a structure in which instances of first elements and instances of second elements alternate. Each instance of the first elements that is not a terminal element of the plurality of alternating elements is adjacent to two instances of the second elements on both sides and the second element of the plurality of alternating elements Each of which is adjacent to two instances of the first elements on both sides. The first elements may have the same thickness between them, or they may have different thicknesses. The second elements may have the same thickness therebetween, or they may have different thicknesses. A plurality of alternating first and second material layers may start with an instance of the first material layers or with an instance of the second material layers and may begin with an instance of the first material layers or with an instance of the second material layers . In one embodiment, instances of the first elements and instances of the second elements may form a repeating unit with periodicity within a plurality of alternating elements.

Each first material layer comprises a first material, and each second material layer comprises a second material different from the first material. In one embodiment, each first layer of material may be an insulating layer 32, and each second layer of material may include a spacer material 32 that provides a vertical spacing between each pair of vertically adjacent insulating layers 32. In one embodiment, Layer. In one embodiment, the spacer material layers may be formed as electrically conductive layers.

In another embodiment, the spacer material layers may be formed as sacrificial material layers 42. In this case, as in the first embodiment, the stack may include a plurality of alternating insulating layers 32 and sacrificial material layers 42, and may include insulating layers 32 and sacrificial material layers 42 And constitutes a prototype stack of alternating layers that contain. As used herein, a "prototype" structure or "in-process" structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified.

In alternate embodiments, alternate stacks 32 and 42 may include insulating layers 32 of a first material and sacrificial material layers 42 of a second material different from the materials of insulating layers 32 . The first material of the insulating layers 32 may be at least one insulating material. Accordingly, each insulating layer 32 can be an insulating material layer. The insulating materials that may be used for the insulating layers 32 include silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials , Dielectric metal oxides and silicates thereof commonly known as high-k dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof, and organic insulating materials But are not limited to these. In one embodiment, the first material of the insulating layers 32 may be silicon oxide.

The second material of the sacrificial material layers 42 is a sacrificial material that can be selectively removed relative to the first material of the insulating layers 32. As used herein, when the removal process removes the first material at a rate that is at least twice the removal rate of the second material, removal of the first material is "optional" for the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material for the second material.

The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of sacrificial material layers 42 may be subsequently replaced with electrically conductive electrodes, which may, for example, function as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers 42 may be silicon nitride or spacer material layers comprising a semiconductor material, including at least one of silicon and germanium.

In one embodiment, the insulating layers 32 may comprise silicon oxide, and the sacrificial material layers may comprise silicon nitride sacrificial material layers. The first material of the insulating layers 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, when silicon oxide is used for the insulating layers 32, tetraethyl orthosilicate (TEOS) can be used as the precursor material for the CVD process. The second material of sacrificial material layers 42 may be formed by, for example, CVD or atomic layer deposition (ALD).

The portions of the conductive material to be subsequently formed by the replacement of the sacrificial material layers 42 may be removed from the surface of the sacrificial material layers (not shown) such that they may function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three- 42 may be suitably patterned. The sacrificial material layers 42 may include portions having a strip shape extending substantially parallel to the top surface of the substrate 8.

Thicknesses of the insulating layers 32 and sacrificial material layers 42 may be in the range of 20 nm to 50 nm but may be less than the thickness of each insulating layer 32 and of each sacrificial material layer 42 And larger thicknesses may be used. The number of repetitions of the pairs of insulating layer 32 and the sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 may be in the range of 2 to 1,024, and typically 8 to 256, Can also be used. The upper and lower gate electrodes in the stack may function as select gate electrodes. In one embodiment, each sacrificial material layer 42 in alternating stacks 32 and 42 may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

It is understood that although the present disclosure is described using an embodiment in which the second material layers are formed as sacrificial material layers, the second material layers may be formed as electrically conductive layers. In this case, the processing steps used to replace the sacrificial material layers with the electrically conductive layers may be omitted.

The upper end of the alternating stacks 32 and 42 may end with an instance of the insulating layer 32. Alternatively, the upper end of the alternating stacks 32 and 42 may end with an instance of a sacrificial material layer 42, and an insulating cap layer 70 with a greater thickness may be formed on the alternating stacks 32 and 42 . The insulating cap layer 70 may have the same composition as the insulating layers 32 and may have a greater thickness than the insulating layers 32. The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer. Alternate stacks 32 and 42 and insulating cap layer 70 are not shown in the cutout region to illustrate the elements beneath the lower bottom surface of the cutout area.

Cavities (not shown) with stepped portions and dielectric material portions (not shown) with inverted steps can be formed on alternate stacks 32 and 42 using the same methods as in the first embodiment. Dielectric support pillars may be formed as in the first embodiment.

Referring to Figure 24, a lithographic material layer (not shown) comprising at least a photoresist layer may be formed over the insulating cap layer 70 and patterned in a lithographic fashion to form openings therein. A pattern in the lithographic material layer is formed through the insulating cap layer 70 by an anisotropic etch process and through the entire alternate stack 32 and 42 and into the support pedestal structures 156 and into the sacrificial material portion 151 Can be transferred. The alternate stacks 32 and 42 and the upper portion of the layer comprising the support pedestal structures 156 and the sacrificial material portion 151 are etched in the regions below the openings in the patterned lithographic material layer during an anisotropic etching process Removed. In one embodiment, the bottom surfaces of the memory openings 49 may be vertically spaced from the top surface of the source conductive layer 140. The chemistry of the anisotropic etch process used to etch through the materials of the alternating stacks 32 and 42 may alternately occur to optimize the etching of the first and second materials in alternating stacks 32 and 42. The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 may be substantially vertical or may be tapered. The patterned lithographic material stack may be subsequently removed, for example, by ashing.

In one embodiment, each of the memory openings 49 may extend through a portion of each of the support pedestal structures 156 and a portion of its respective sacrificial material portion 151. In one embodiment, the memory openings 49 may be arranged in rows extending along the first horizontal direction hd1. The rows of memory openings 49 may be laterally spaced along the second horizontal direction hd2. The position of each row of memory openings 49 is selected such that each memory opening 49 in the row straddles a neighboring pair of support pedestal structure 156 and sacrificial material portion 151. [ .

The materials of the support pedestal structures 156 and sacrificial material portions 151 are partially removed during formation of the memory openings 49. [ In one embodiment, the memory openings 49 have a generally cylindrical shape with a horizontal cross-sectional shape of a closed shape providing recessed surfaces towards the geometric center of the circle, ellipse, . As used herein, a "geometric center" of an element is the center of mass of a hypothetical object having the same shape and location as the element and having a uniform density throughout. In this case, concave sidewalls may be formed on the support pedestal structures 156 and additional concave sidewalls may be formed on the sacrificial material portions 151 during formation of the memory openings 49. [ Each concave sidewall on the support pedestal structures 156 and sacrificial material portions 151 may be substantially vertical. As used herein, "dimpled sidewall" refers to a set of continuous side walls that are located in the same vertical plane and that include the planar side walls adjacent the concave side walls. Each of the support pedestal structures 156 may include a pair of dimpled sidewalls, each dimpled sidewall including respective planar vertical sidewalls adjacent to the respective concave vertical sidewalls. Likewise, each of the sacrificial material portions 151 may include a pair of dimpled sidewalls, each dimpled sidewall including respective planar vertical sidewalls adjacent to their respective concave vertical sidewalls.

Each of the memory openings 49 may comprise a sidewall (or a plurality of sidewalls) extending substantially perpendicular to the top surface of the substrate semiconductor layer 8. The area in which the array of memory openings 49 is formed is referred to herein as the memory array area. Each of the memory openings 49 may have a lateral dimension (such as a diameter or major axis) in the range of 30 nm to 120 nm, although smaller lateral dimensions and larger lateral dimensions may also be used have.

Referring to Figure 25, a memory film 50 may be formed in each memory opening 49 by sequential deposition of a set of component layers. A set of component layers are deposited on the sacrificial dielectric layer 52, the charge storage element layer 54, and the tunneling dielectric layer 56, in an order from outside to inside and in sequential deposition at each memory opening 49. [ . ≪ / RTI >

Specifically, blocking dielectric layer 52 comprises at least one dielectric material, which may be silicon oxide, a dielectric metal oxide, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant of greater than 7.9. Additionally or alternatively, blocking dielectric layer 52 may comprise silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise a stack of aluminum oxide and silicon oxide. The thickness of the blocking dielectric layer 52 may range from 1 nm to 30 nm, but smaller thicknesses and larger thicknesses may also be used.

The charge storage element layer 54 may comprise a single layer of a charge trapping material, including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage element layer 54 may be formed as a plurality of electrically isolated portions (e. G., Floating gates) by being formed in the lateral recesses into, for example, Or a conductive material such as doped polysilicon or metal material to be patterned.

Alternatively, the charge storage element layer 54 may be formed as a single memory material layer of homogeneous composition, or it may comprise a stack of multiple memory material layers. The plurality of memory material layers, when utilized, may be formed of a material such as conductive materials (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or tungsten silicide, molybdenum silicide, tantalum silicide, (E.g., a metal silicide such as nickel silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material comprising at least one element semiconductor element or at least one compound semiconductor material) Spaced apart floating gate material layers. In one embodiment, the charge storage element layer 54 comprises a silicon nitride layer. Alternatively or additionally, the charge storage element layer 54 may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage element layer 54 may comprise conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage element layer 54 may be formed by any suitable deposition technique for depositing, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) . The thickness of the charge storage element layer 54 may range from 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used.

Tunneling dielectric layer 56 includes a dielectric material through which charge tunneling may be performed under appropriate electrical bias conditions. The tunneling dielectric layer 56 may be formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / / RTI > In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly known as ONO stacks. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used.

The memory film 50 is formed as a continuous layer stack above the sidewalls and recessed horizontal surfaces of each support pedestal structure 156 and directly over the sidewalls and recessed horizontal surfaces of each sacrificial material portion 151 .

The semiconductor channel layer 60L may be deposited on the memory film 50. [ The semiconductor channel layer 60L may comprise at least one elemental semiconductor material, at least one Group III-V compound semiconductor material, at least one Group II-VI compound semiconductor material, at least one organic semiconductor material, And other semiconductor materials. In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polysilicon. The semiconductor channel layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). Thickness of the semiconductor channel layer 60L may be in the range of 2 nm to 10 nm, but smaller thicknesses and larger thicknesses may also be used.

The semiconductor channel layer 60L may be removed from above the alternate stack at this point in time or at a later point in the process so that the remaining vertical portion of the semiconductor channel layer 60L forms the semiconductor channel 60. [ Likewise, the layers of the memory film 50 may be removed from the top surface of the memory stack at this point or at a later point in the process. A drain region 63 may be formed at this point or at the top of the semiconductor channel 60 at a later point in the process. A portion of the memory film 50 in the same memory opening 49 and a portion of the semiconductor channel layer 60L constitute the memory stack structures 50 and 60. [ Each memory stack structure 50,60 includes a vertical portion of the memory film 50 and a vertical portion of the semiconductor channel layer 60L. The cavity may be in a volume of each memory opening 49 that is not filled with the deposited material layers 52, 54, 56, 60L.

Depositing a dielectric material in the cavities in the memory openings 49, removing the horizontal portions of the deposited dielectric material from above the alternating stacks 32 and 42, and vertically recessing the deposited dielectric material A dielectric core 62 may be formed in each memory opening 49. [ Each remaining portion of the dielectric material constitutes a dielectric core 62.

26, a photoresist layer (not shown) is formed on the insulating cap layer 70 (e.g., when the semiconductor channel layer 60L is still above the top of the alternating stack) And is patterned lithographically to form at least one elongated openings extending along the second horizontal direction hd2. A pattern in the photoresist layer is deposited over the stacked material layers 52, 54, 56, 60L (if still present) over alternating stacks 32, 42 to form at least one back contact trench 79 May be transferred through a layer comprising a horizontal portion, an insulating cap layer 70, alternating stacks 32 and 42, and support pedestal structures 156 and sacrificial material portions 151. The general pattern of the at least one back contact trench 79 is similar to that of the first embodiment except that in the second exemplary structure the dielectric pillars 20 are replaced by a combination of support pedestal structures 156 and sacrificial material portions 151 May be the same as that illustrated in Fig. 12B.

At least one back contact trench 79 extends through the alternating stacks 32 and 42 and into the support pedestal structures 156 and the sacrificial material portions 151. At least one back contact trench 79 may divide the existing support pedestal structures 156 and a subset of sacrificial material portions 151 or each of them into a plurality of portions. The side pedestal structures 156 and the sidewalls of the sacrificial material portions 151 are physically exposed during the formation of the at least one back contact trench 79, such as by being divided by the at least one back contact trench 79. [ do.

27, the outermost layers (such as intercept dielectric layer 52) of support pedestal structures 156, alternating stacks 32 and 42, source conductive layer 140, and memory film 50 The side extension cavities 157 are formed by removing the sacrificial material portions 151 without removing the sacrificial material portions 151. [ In one embodiment, the alternate stacks 32 and 42 and the source conductive layer 140 and the outermost layers of the memory film 50 are selectively and selectively coupled to the pedestal structures 156 and the dielectric liner An etchant may be used that selectively etches the material of the sacrificial material portions 151 for at least one of the sacrificial material portions 151. [

In one embodiment, the sacrificial material portions 151 may comprise undoped semiconductor material, and the support pedestal structures 156 may include a heavily doped semiconductor material having a dopant concentration greater than ¹ x 10 ¹⁹ / cm ³ . In this case, the sacrificial material portions 151 can be removed without removing the support pedestal structures 156 using a wet etch process that selectively removes undoped semiconductor material relative to the doped semiconductor material . In one embodiment, the doped semiconductor material is a p-doped silicon-containing material such as boron-doped amorphous silicon containing boron at an atomic concentration greater than 1.0 x 10 ¹⁹ / cm ³ (such as greater than 1.0 x 10 ²⁰ / cm ³ ) Material, and the undoped semiconductor material comprises an undoped silicon-containing material (such as amorphous silicon that is not doped), and the wet etch process comprises depositing a solution comprising trimethyl-2hydroxyethyl ammonium hydroxide (TMY) And is used as an etching agent. Trimethyl-2-hydroxyethyl ammonium hydroxide (TMY) etches undoped silicon at a high selectivity for boron doped silicon.

In the case where dielectric liner 153 is present in the second exemplary structure, the sidewalls of dielectric liner 153 may optionally be removed by isotropic etching (such as wet etching). If the dielectric liner 153 comprises silicon nitride, the sidewalls of the dielectric liner 153 may be removed by wet etching using phosphoric acid. The duration of the etching process can be selected such that the horizontal portion of the dielectric liner 153 remains between each support pedestal structure 156 and the source conductive layer 140. Alternatively, dielectric liner 153 may remain substantially intact. In this case, a U-shaped dielectric liner 153 having a horizontal portion and a pair of vertical portions extending upward from the edges of the horizontal portion may be present on each support pedestal structure 156. Alternatively, a dielectric liner 153 may not be formed in the processing steps of FIG. In this case, the support pedestal structures 156 may contact the top surface of the source conductive layer 140.

28 and 29, portions of the memory film 50 that are physically exposed to the side extension cavities 157 may be removed by removing portions of the memory film 50 that are in contact with the support pedestal structures 156 , The semiconductor channel layer 60L (or the channel 60 when the layer 60L is removed from the top of the alternating stack) is selectively removed. Isotropic etching is used to physically expose the lower portion of each side wall of the semiconductor channel (which is the vertical portion of the semiconductor channel layer 60L in the memory opening) and to remove the physically exposed portions of the memory film 50 . The duration of the isotropic etch can be controlled to prevent removal of the memory film 50 from regions between the semiconductor channels and the support pedestal structures 156. The sidewalls of the semiconductor channel layer 60L are physically exposed when parts of the memory film 50 physically exposed to the side extension cavities 157 are removed.

Referring to FIGS. 30 and 31, a doped semiconductor material layer 150L may be deposited by at least one of the back contact trenches 79 and laterally extending cavities 157 by a conformal deposition process. The doped semiconductor material layer 150L may be a conductive material, that is, a material having a conductivity of greater than 1.0 x 10 ⁵ S / cm and a dopant atom concentration of greater than 1.0 x 10 ¹⁹ / cm ³ (p-doped silicon or n Doped < / RTI > silicon) doped semiconductor material. The doped semiconductor material layer 150L may be formed as a single continuous structure. In one embodiment, the support pedestal structures 156 may comprise a first semiconductor material having a doping of a first conductivity type, and the doped semiconductor material layer 150L may comprise a second conductivity type < RTI ID = 0.0 >Lt; RTI ID = 0.0 > type < / RTI > doping. The first conductivity type may be p-type, the second conductivity type may be n-type, or vice versa.

Each portion of the doped semiconductor material layer 150L filling the lateral extension cavity 157 constitutes a conductive rail structure. Each of the conductive rail structures includes dimpled sidewalls that include their respective concave vertical sidewalls and their respective planar vertical sidewalls adjacent. The concave vertical sidewalls in the dimple-shaped sidewalls of the conductive rail structures are in contact with the sidewalls of the semiconductor channels, which are vertical portions of the semiconductor channel layer 60L in the memory openings.

A vertical portion of the doped semiconductor material layer 150L is present at the periphery of each back contact trench 79. [ A horizontal portion of the doped semiconductor material layer 150L is present on the insulating cap layer 70. [ A vertically extending cavity extending through the alternating stacks 32, 42 is present in each back contact trench 79.

Each vertically recessed volume on the dielectric cores 62 is doped with a doped semiconductor material layer (not shown) that protrudes downward from the horizontal portion of the doped semiconductor material layer 150L on the uppermost surface of the semiconductor channel layer 60L 150L). ≪ / RTI > A material filling the laterally extending cavities 157 and a material filling the vertically recessed volume above the dielectric cores 62 may be formed simultaneously.

32, portions of the doped semiconductor material layer 150L may be removed from the sidewalls of each back contact trench 79, for example, by isotropic etching or anisotropic etching, . The horizontal portions of the memory film 50 on the horizontal portions of the semiconductor channel layer 60L and the insulating cap layer 70 or the dielectric material portion (s) 65 with the inverted step are removed by at least one anisotropic etch Process and / or at least one isotropic etch process. In an exemplary embodiment, removing portions of the material of the doped semiconductor material layer 150L from the at least one back contact trench and depositing the materials of the doped semiconductor material layer 150L and the semiconductor channel layer 60L, Removing from above the upper surface of the substrate 70 can be performed by wet etching using potassium hydroxide (KOH).

Each volume of side extension cavities 157 is filled with a respective conductive rail structure 150, which is the remaining portion of the doped semiconductor material layer 150L. Each remaining vertical portion of the semiconductor channel layer 60L constitutes a semiconductor channel 60.

Removing the horizontal portions of the memory film 50 from above the top surface of the insulating cap layer 70 may be performed by a series of wet etch processes that sequentially remove the component layers within the memory film 50. The memory film 50 is divided into a plurality of memory films 50, and each memory film is located entirely within its respective memory opening. Each memory film 50 in its memory opening may extend continuously from the top surface of the insulating cap layer 70 into the source conductive layer 140 and may include conductive rail structures 150 and support pedestal structures & 156 at the level of the opening. The conductive rail structure 150 contacts the sidewalls of the semiconductor channel 60 in the memory film 50 through openings in the memory film 50 at the level of the conductive rail structure. The openings in the memory film 50 are located only on one side of the memory film 50 and the other side of the memory film contacts the recessed horizontal surface of the source conductive layer 140 from the top surface of the insulating cap layer 70 To the horizontal bottom surface of the memory film 50, which is the bottom surface of the memory film 50.

Each adjacent semiconductor channel 60 and the pair of memory films 50 constitute a memory stack structure 55. Each memory stack structure 55 is located within the memory opening 49 and extends vertically through alternating stacks 32 and 42. Each semiconductor channel 60 is a channel of a vertical field effect transistor. Each conductive rail structure 150 is a common source region for a plurality of vertical field effect transistors (e.g., NAND strings) including semiconductor channels 60 immediately adjacent to their respective conductive rail structures 150 . Each sacrificial material portion 151 can be replaced with a conductive rail structure 150. [

Each remaining portion of the doped semiconductor material layer 150L above each dielectric core 62 contacts the top of each of the semiconductor channels 60 and constitutes a drain region 63. The conductive rail structures 150 and a drain region 63, each of which may have a doping of the same conductivity type, 1.0 x 10 such as ²⁰ / cm ³ greater than, 1.0 x 10 ¹⁹ / cm ³ in excess water, the same in one Can contain the same electrical dopant at atomic concentration. Thus, the conductive rail structures 150 and drain regions 63 can be formed simultaneously using the same set of processing steps. The semiconductor channels 60 may not be doped or may have a doping of the opposite conductivity type of the conductive type of conductive rail structures 150 and drain regions 63. [ Alternatively, the drain regions 63 and channel 60 are formed earlier in the process as described above.

33, an etchant that selectively etches the second material of the sacrificial material layers 42 with respect to the first material of the insulating layers 32 may be etched using at least one backside trench (e.g., 79). ≪ / RTI > Back recesses 43 are formed in the volumes from which the sacrificial material layers 42 are removed. Removal of the second material of the sacrificial material layers 42 may be accomplished by removing the first material of the insulating layers 32, the material of the at least one dielectric support pillar 7P, the material of the dielectric material portion 65 having the inverted step, May be selective for the doped semiconductor material of structures 150, the material of source conductive layer 140, and the material of the outermost layer of memory films 50 (such as blocking dielectric layer 52). In one embodiment, the sacrificial material layers 42 may comprise silicon nitride, and the materials of the dielectric layers 32, the at least one dielectric support pillar 7P, and the dielectric material portion 65 with the inverted step Silicon oxides and dielectric metal oxides. Alternatively, the support pillars 7P may include dummy memory stack structures including a channel and a memory film, wherein the channel is not electrically connected to the bit line.

The etch process that selectively removes the second material of the sacrificial material layers 42 with respect to the first material of the insulating layers 32 and the outermost layer of the memory films 50 may be a wet etch process using a wet etch solution Or a gas phase (dry etch process) in which the etchant is introduced into the at least one backside trench 79 in a vapor phase. For example, where the sacrificial material layers 42 comprise silicon nitride, the etching process may be performed by an exemplary process wherein the exemplary structure selectively etches silicon nitride to silicon oxide, silicon, and various other materials used in the art Lt; RTI ID = 0.0 > wet etching < / RTI > tank containing phosphoric acid. At least one dielectric support pillar 7P, inverted stepped dielectric material portion 65, and memory stack structures 55 are formed such that the backside recesses 43 are previously occupied by the sacrificial material layers 42 Provides structural support while remaining in volume.

Each backside recess 43 may be a side extension cavity having a side dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each rear recess 43 may be greater than the height of the rear recess 43. [ A plurality of backside recesses 43 may be formed in a volume in which the second material of the sacrificial material layers 42 is removed. The memory openings 49 in which the memory stack structures 55 are formed are referred to herein as front recesses or front cavities in contrast to the backside recesses 43. In one embodiment, memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above a substrate comprising a substrate semiconductor layer 8. In this case, each backside recess 43 may define a space for accommodating a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 may extend substantially parallel to the upper surface of the substrate. The backside recess 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the underlying insulating layer 32. In one embodiment, each backside recess 43 may have a uniform height throughout. Optionally, a backplane dielectric layer can be formed in the backside recesses.

34, at least one metallic material may be deposited on the backside recesses 43, on the sidewalls of at least one of the back contact trenches 79, and on the top surface of the insulating cap layer 70 . As used herein, a metal material refers to an electrically conductive material comprising at least one metal element.

The metal material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The metal material may be selected from the group consisting of an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, Combinations or stacks of these. Non-limiting exemplary metallic materials that can be deposited in the plurality of backside recesses 43 include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metal material may comprise a metal such as tungsten and / or a metal nitride. In one embodiment, the metallic material for filling the plurality of backside recesses 43 may be a combination of a titanium nitride layer and a tungsten fill material. In one embodiment, the metallic material may be deposited by chemical vapor deposition.

A plurality of electrically conductive layers 46 may be formed in the plurality of back recesses 43 and adjacent metal material layers (not shown) may be formed on the sidewalls of each back contact trench 79, Layer 70 as shown in FIG. Thus, each sacrificial material layer 42 can be replaced with an electrically conductive layer 46. [ There is a backside cavity in the portion of each backside contact trench 79 that is not filled with an optional backside isolation dielectric layer and an adjacent metallic material layer.

Deposited metal materials of adjacent electrically conductive material layers are etched away from the sidewalls of each back contact trench 79 and from above the insulating cap layer 70, for example, by isotropic etching. Each remaining portion of the deposited metal material in the backside recesses 43 constitutes the electrically conductive layer 46. Each electrically conductive layer 46 may be a conductive line structure. Thus, sacrificial material layers 42 are replaced with electrically conductive layers 46.

Each electrically conductive layer 46 is a combination of a plurality of control gate electrodes located at the same level and a plurality of control gate electrodes located at the same level electrically interconnecting-that is, electrically short-circuiting Function. The plurality of control gate electrodes in each electrically conductive layer 46 are control gate electrodes for vertical memory devices including memory stack structures 55. In other words, each electrically conductive layer 46 may be a word line that serves as a common control gate electrode for a plurality of vertical memory devices.

35A and 35B, a layer of insulating material may be formed on the at least one back contact trench 79 and over the insulating cap layer 70 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer comprises an insulating material such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicate glass, or combinations thereof. In one embodiment, the insulating material layer may comprise silicon oxide. The insulating material layer may be formed by, for example, low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer may be in the range of 1.5 nm to 60 nm, but smaller thicknesses and larger thicknesses may also be used. Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the insulating cap layer 70 and at the bottom of each back contact trench 79. [ Each remaining portion of the layer of insulating material constitutes an insulating spacer 74. After formation of the electrically conductive layers 46, respective insulating spacers 74 are formed on the sidewalls of the respective back contact trenches 79 and on the sidewalls of the conductive rail structures 150. In one embodiment, the sidewall of each conductive rail structure 150 may contact the lower end portion of the outer side wall of the insulating spacer 74.

A back contact via structure 76 may be formed in the cavity inside each insulating spacer 74. [ Each back contact via structure 76 may fill its respective cavity in its respective insulating spacer 74. [ The contact via structures 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of each back contact trench 79. [ For example, the at least one conductive material may include a conductive liner (not separately shown) and a conductive fill material portion (not separately shown). The conductive liner may include a conductive metal liner, such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive liner may range from 3 nm to 30 nm, but smaller thicknesses and larger thicknesses may also be used. The portion of the conductive filler material may comprise a metal or metal alloy. For example, the portion of the conductive filler material may comprise W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

At least one conductive material may be planarized using the insulating cap layer 70 over alternating stacks 32 and 46 as a stop layer. If a chemical mechanical planarization (CMP) process is used, the insulating cap layer 70 may be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in back contact trenches 79 constitutes back contact via structure 76. Each back contact via structure 76 may be formed immediately above the top surface of the source contact layer 140, which may be electrically shorted to the conductive rail structures 150. Each back contact via structure 76 is formed within a portion of a back contact trench 79 that is not filled with an insulating spacer 74.

36, additional contact via structures 88, 86, 8P may be formed through the second insulating cap layer 73 and optionally through a dielectric material portion 65 having an inverted step . For example, drain contact via structures 88 may be formed on each drain region 63 through the second insulating cap layer 73. Word line contact via structures 86 may be formed on the electrically conductive layers 46 through the second insulating cap layer 73 and through the dielectric material portion 65 with the inverted step. Peripheral device contact via structures 8P can be formed directly above the respective nodes of the peripheral devices through the dielectric material portion 65 with the inverted step.

According to one aspect of the present disclosure, alternating stacks 32 and 46 of electrically conductive layers 46 and insulating layers 32 located on a substrate 8, an array of memory stack structures 55, Each memory stack structure 55 extending through the memory stack 50 and the memory channel 50 and including the semiconductor channel 60 surrounded laterally by the memory stack 50 and the memory stack 50, Such as support pedestal structures 156 positioned between the substrate 8 and the substrate 8, are provided. The device may also include a source conductive layer 140 below the alternating stacks 42 and 46 and above the substrate 8 and in contact with the support structures 156.

In one embodiment, the three-dimensional memory device extends laterally along the first horizontal direction hd1 and contacts the upper surface of the source conductive layer 140 and has a conductive Rail structures 150. In one embodiment, each of the conductive rail structures 150 includes dimpled sidewalls that include respective planar vertical sidewalls adjacent their respective concave vertical sidewalls. In one embodiment, each semiconductor channel 60 contacts the sidewalls of its respective conductive rail structure 150, and each memory film 50 contacts the sidewalls of its respective support pedestal structure 156.

In one embodiment, the top surfaces of the support pedestal structures 156 may be in the same horizontal plane as the top surfaces of the conductive rail structures 150. In one embodiment, the support pedestal structures 156 may comprise a first semiconductor material having a doping of a first conductivity type, and the conductive rail structures 150 may include a second conductivity type, Doped < / RTI > semiconductor material.

In one embodiment, the three-dimensional memory device includes a back contact via structure 76 in contact with the top surface of the source conductive layer 140. Insulation spacers 74 may laterally surround the backside via structure 76 and contact the top surface of the source conductive layer 140. The conductive rail structures 150 may extend laterally along the first horizontal direction hd1 and may contact the upper surface of the source conductive layer 140 and may be in contact with the sidewalls of the semiconductor channels 60 can do. Conductive rail structures 150 may be laterally spaced from back contact via structure 76 by insulating spacers 74.

In one embodiment, each of the support pedestal structures 156 includes dimpled sidewalls that include their respective concave vertical sidewalls and their respective planar vertical sidewalls. In one embodiment, each of the concave vertical sidewalls of the support pedestal structures 156 contacts the outer sidewall of the respective memory film 50.

In one embodiment, the three-dimensional memory device includes a vertical NAND device located above the substrate 8. The electrically conductive layers 46 may comprise, or be electrically connected to, the respective word line of the NAND device. The substrate 8 may comprise a silicon substrate. A vertical NAND device may include an array of monolithic three-dimensional NAND strings on a silicon substrate. At least one memory cell at a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell at a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may include an integrated circuit including a driver circuit for a memory device located thereon.

The array of monolithic three-dimensional NAND strings may include a plurality of semiconductor channels 60. At least one end portion of each semiconductor channel of the plurality of semiconductor channels (60) extends substantially perpendicular to the upper surface of the substrate (8). The array of monolithic three-dimensional NAND strings may include a plurality of charge storage elements (such as those implemented as portions of the charge storage element layer 54 located at each level of the electrically conductive layers 46). Each charge storage element is positioned adjacent to a respective semiconductor channel of a plurality of semiconductor channels (60). The array of monolithic three-dimensional NAND strings may include a plurality of control gate electrodes having a strip shape extending substantially parallel to an upper surface of the substrate, wherein the plurality of control gate electrodes are arranged at least at a first device level A first control gate electrode and a second control gate electrode positioned at a second device level.

Each of the conductive rail structures 150 may function as a common source region for a plurality of field effect transistors including semiconductor channels 60 in contact with the conductive rail structure 150. The support structures 156 provide structural support while replacing the sacrificial material portions 151 with the conductive rail structures 150. Optionally, a subset of electrically conductive layers 46 (such as bottom-most electrically conductive layer 46) may be used as the source select gate electrode during operation of the vertical three-dimensional memory device. By increasing the height of the sacrificial material portions 150 and thereby increasing the height of the conductive rail structures 150, the distance between each semiconductor channel 60 and the conductive rail structures 150 The contact area between the source regions (such as may be implemented as the source region 150) may be increased.

Each contact area between the conductive rail structure 150 and the semiconductor channel 60 may include a curved vertical surface. The angular spread of the curved vertical surface from the vertical axis passing through the geometric center of the memory stack structure 55 including the semiconductor channel 60 may be in the range of 90 to 270 degrees, May range from 45 degrees to 315 degrees. By providing an increased contact area between the source region and the semiconductor channel without increasing the size of the memory openings, the structures of the present disclosure provide a larger on-current (< RTI ID = 0.0 > on-current < / RTI > Alternatively, the structures of the present disclosure may be used to reduce lateral dimensions of memory openings and memory stack structures while maintaining on-current for vertical field effect transistors at the operating level.

Referring to FIG. 37, a top view of a portion of the present disclosure, including a stack of a substrate 8, an optional insulator layer 120, an optional blanket conductor layer 136, and a matrix material layer 138, A third exemplary structure according to three embodiments is illustrated. The substrate 8 may be the same as the substrate 8 of the second embodiment. The optional insulating layer 120, if present, may be the same as the insulating layer 120 of the second embodiment.

The optional blanket conductor layer 136 may comprise a metal, a metal alloy, a conductive metal nitride, a metal-semiconductor alloy (such as a silicide), or a heavily doped semiconductor material with a conductivity greater than 1.0 x 10 ⁵ S / cm . The optional blanket conductive layer 136 may be a blanket layer, i.e., an unpatterned layer, having a uniform thickness throughout. In one embodiment, the optional blanket conductor layer 136 may comprise a metal-semiconductor alloy (such as tungsten silicide) or a metal (such as tungsten). The thickness of the optional blanket conductive layer 136 may range from 3 nm to 100 nm, but smaller thicknesses and larger thicknesses may also be used.

The matrix material layer 138 includes a conductive material such as a doped semiconductor material or a metal material (such as a metal, a metal alloy, a conductive metal nitride, or a metal-semiconductor alloy). In one embodiment, the matrix material layer 138 comprises, a semiconductor material layer is doped to a high concentration, such as, a polysilicon layer having a conductivity of 1.0 x 10 ⁵ S / cm is exceeded. The thickness of the matrix material layer 138 may be in the range of 50 nm to 500 nm, but smaller thicknesses and larger thicknesses may also be used. A conformal or non-conformal deposition process may be used to deposit the layer of matrix material 138. The conductive type of the matrix material layer 138 may be p-type or n-type.

Referring to Figure 38, for example, a photoresist layer may be applied over the layer of matrix material 138, lithographically patterning the photoresist layer to form line patterns with spaces having uniform widths, and By transferring the pattern in the photoresist layer into the upper portion of the matrix material layer 138 by anisotropic etching, a plurality of channels (i. E., Trench shaped recesses < RTI ID = (Recesses) 141 are formed. The plurality of channels 141 may have a uniform width and a uniform spacing to form a one-dimensional periodic pattern. Each channel 141 may extend along the same horizontal direction, referred to herein as a first horizontal direction. Each channel 141 may have substantially the same vertical cross-sectional shape along a direction perpendicular to the first horizontal direction. The depth of each channel 141 can range from 30 nm to 300 nm, but smaller depths and larger depths can also be used. The width of each channel 141 may range from 60 nm to 240 nm, but smaller widths and larger widths may also be used. The pitch of the channels 141 along the horizontal direction perpendicular to the first horizontal direction may be in the range of 120 nm to 480 nm, but smaller pitches and larger pitches may also be used.

Referring to Figures 39, 40A, and 40B, sacrificial liner 154 may be optionally formed on the sidewalls of channels 141. 40A is a top view of the third exemplary structure of FIG. 39 in a first exemplary configuration. Figure 40B is a top view of the third exemplary structure of Figure 39 in a second exemplary configuration. The sacrificial liner 154 may comprise a dielectric material such as silicon oxide and may have a thickness in the range of 1 nm to 10 nm, although smaller thicknesses and larger thicknesses may also be used. To form sacrificial rail structures 144, the remaining volumes of channels 141 that are not filled with sacrificial liner 154 may be filled with a sacrificial material such as silicon nitride.

As an illustrative example, a layer of dielectric material (such as a silicon oxide layer) may be conformally deposited just above the sidewalls and bottom surfaces of the channels 141 and above the matrix material layer 138. A sacrificial material layer (such as a silicon nitride layer) may be deposited on the remaining volumes of the channels 141. A planarization process (such as chemical mechanical planarization (CMP) and / or recess etch) is performed to remove portions of the sacrificial material layer and the dielectric material layer from above the horizontal plane including the top surface of the matrix material layer 138 . Each remaining portion of the dielectric material layer includes sacrificial liners 154, and each remaining portion of the sacrificial material layer includes sacrificial rail structures 144. Each sacrificial rail structure 144 may be formed as a periodic array extending horizontally along the first horizontal direction and having a uniform width and uniform pitch along the horizontal direction perpendicular to the first horizontal direction. As used in the third embodiment, the first horizontal direction is the extension direction of the sacrificial rail structures. The first horizontal direction in this embodiment may differ from the bit line direction by 10 to 80 degrees (i.e., extend in the "XY" direction), as shown in Figs. 40A and 40B, May be parallel to the bit line direction (i.e., extend in the "Y" direction). Each sacrificial rail structure 144 may have a substantially rectangular horizontal cross-sectional shape that is invariant under parallel motion along the first horizontal direction.

Referring to Figure 41, an optional dielectric etch stop layer 145 and an optional source connecting layer 146 may be formed over the matrix material layer 138 and the plurality of sacrificial rail structures 144. The optional dielectric etch stop layer 145 includes a dielectric material such as silicon oxide, silicon nitride, or dielectric metal oxide (such as aluminum oxide) and may be deposited by a conformal or non-conformal deposition process. The thickness of the dielectric etch stop layer 145 may be in the range of 1 nm to 10 nm, but smaller thicknesses and larger thicknesses may also be used.

The optional source coupling layer 146 may be a heavily doped semiconductor material having the same conductivity type of doping as the matrix material layer 138 or may be an elemental metal, an intermetallic alloy (such as a metal silicide) , ≪ / RTI > TiN, or TaN) conductive metal nitride. In one embodiment, the source connection layer 146 may comprise a doped semiconductor material, such as polysilicon, having a conductivity of greater than 10 ⁵ S / cm, such as heavily doped silicon. The thickness of the source connection layer 146 may range from 50 nm to 500 nm, but smaller thicknesses and larger thicknesses may also be used. To provide a conductive structure extending to the contact region 300 to electrically contact the source conductive layer to be subsequently formed and to enable electrical contact between the source connection layer 146 and the contact via structure to be subsequently formed, A connection layer 146 may be used. A source connection layer 146 comprising a conductive material is formed over the plurality of sacrificial rail structures 144 and the matrix material layer 138.

Referring to Figures 42, 43A, and 43B, memory recesses 149 may be formed through optional source interconnect layer 146, optional dielectric etch stop layer 145, and sacrificial rail structures 144 And partially penetrating the matrix material layer 138. Figure 43A is a top view of the third exemplary structure of Figure 42 in a first exemplary configuration. Figure 43B is a top view of the third exemplary structure of Figure 42 in a second exemplary configuration. For example, applying a photoresist layer over the optional source connection layer 146, lithographically patterning the periodic arrays of openings in the photoresist layer, and patterning the pattern in the photoresist layer by an anisotropic etch process By passing through the optional source connection layer 146, the optional dielectric etch stop layer 145, and the sacrificial rail structures 144 and partially penetrating the matrix material layer 138, (149) may be formed. The photoresist layer may be subsequently removed, for example, by ashing.

Each memory recess 149 may be a cavity having a substantially uniform horizontal cross-sectional shape that is invariant under vertical translation. The substantially uniform horizontal cross-sectional shape may be circular, elliptical, generally egg-shaped, polygonal, or any other shape having a closed curvilinear periphery. The memory recesses 149 may be formed of clusters. Each cluster of memory recesses 149 may be arranged as a two-dimensional periodic array such as a hexagonal array. Arrays of neighboring memory recesses 149 may be spaced apart from each other by a gap 179, which may extend laterally along a direction different from the first horizontal direction. For example, the gap 179 may extend in the word line direction (i.e., in the "X" direction) perpendicular to the bit line direction (i.e., perpendicular to the "Y" direction). In a first configuration, the direction in which the gap 179 between the arrays of neighboring memory recesses 149 extends horizontally is between about 10 degrees and about 80 degrees, for example, Lt; / RTI > may be at non-orthogonal angles other than zero (such as 60 degrees as illustrated). In a second configuration, the direction in which the gap 179 between the arrays of neighboring memory recesses 149 extends horizontally is parallel to the bit line direction and perpendicular to the first horizontal direction, i.e., the sacrificial rail structures 144 ) Perpendicular to the longitudinal direction.

The orientation of each array of memory recesses 149 may be selected such that each of the memory recesses straddles the interface between the sacrificial rail structure 144 and the matrix material layer 138. In one embodiment, recessed sidewalls of the sacrificial rail structure 144, recessed sidewalls of the matrix material layer 138, and recessed planar surfaces of the matrix material layer 138 are physically located around each memory recess 149, Lt; / RTI > The sacrificial rail structure 144 has a recessed sidewall 144 as measured from the vertical edge to the other vertical edge with respect to the vertical axis passing through the geometric center of the respective memory recess 149 to which the recessed sidewall is physically exposed. The range of azimuthal angles of each physically exposed concave sidewall of each of the first and second regions may range from about 45 degrees to about 270 degrees, but smaller azimuth angles and larger azimuth angles may also be used. In one embodiment, the direction in which the nearest neighbor memory recesses 149 in the longitudinal direction of the sacrificial rail structures 144 are aligned or the direction in which the second nearest neighbor memory recesses 149 are aligned So that each array of memory recesses 149 can be oriented. Thus, a row of memory recesses 149 arranged along the first horizontal direction may straddle the interface between the sacrificial rail structure 144 and the matrix material layer 138.

The position, size, shape, and orientation of each memory recess 149 in the horizontal plane will be determined by the position, size, shape, and orientation in the horizontal plane of the corresponding memory opening to be subsequently formed through at least one alternate stack in a subsequent process , Shape, and orientation. In one embodiment, the same lithographic mask for forming memory openings through each alternate stack in subsequent processing steps can be used to form memory recesses 149 in this processing step.

44, isolation dielectric layer 148 may be formed by a non-conformal deposition process such as high density plasma chemical vapor deposition (HDP) or plasma enhanced chemical vapor deposition (PECVD). The dielectric material of the isolation dielectric layer 148 is deposited to greater thicknesses on more horizontal surfaces on the vertical surfaces and each memory recess 149 is deposited on the upper surfaces of the memory recesses 149, And is sealed by portions of the dielectric material. A memory cavity 147, which is sealed by the dielectric material of the isolation dielectric layer 148, may be formed in each memory recess 149. The isolation dielectric layer 148 extends continuously over the source connection layer 146 without any openings therethrough. Alternatively, memory recesses 149 may be conformally filled with at least one insulating material. Alternatively, the memory recesses 149 may be filled with a sacrificial material, which may be a semiconductor material or a conductive material, conformally or non-conformally. In one embodiment, the material filling the memory recesses 149 may be a material that functions as an etch stop material for the material of the matrix material layer 138.

45, the isolation dielectric layer 148 may be planarized by, for example, chemical mechanical planarization (CMP), to remove the dimples over the memory cavities 147. Referring to FIG. The top surface of the isolation dielectric layer 148 may be planar after the planarization process-that is, in a horizontal plane. Though the thickness of the isolation dielectric layer 148 above the source connection layer 146 may be in the range of 60 nm to 300 nm, smaller thicknesses and larger thicknesses may also be used.

Referring to Figure 46, a first alternating stack of first insulating layers 32 and first spacer material layers 42 may be formed over isolation dielectric layer 148. The first alternating stacks 32 and 42 may be identical to the alternating stacks 32 and 42 of the first and second embodiments. If the first alternating stacks 32 and 42 include all levels of control gate electrodes to be subsequently formed, the processing steps of FIG. 6 may be performed to form the insulating cap layer 70. If any additional alternating stacks are to be formed at a later time, the formation of the insulating cap layer 70 may be delayed.

47, first memory openings 49 are formed through the volumes of first alternating stacks 32 and 42 and isolation dielectric layer 148 and underlying memory recesses 149 . 48A is a top view of the third exemplary structure of FIG. 47 in a first exemplary configuration for sacrificial rail structures 144. FIG. 48B is a top view of the third exemplary structure of FIG. 47 in a second exemplary configuration for sacrificial rail structures 144. FIG. In one embodiment, the pattern of the first memory openings 49 may be the same as the pattern of the memory recesses 149. In other words, the peripheries of the first memory openings 49 in the horizontal cross-section are the same as those of the memory recesses 149 within tolerances of overlay variations and critical dimension (CD) variations inherent in lithographic alignment. It can overlap with peripheral portions.

To form the portions of the first memory openings 49 located at the levels of the first alternating stack 32 and 42, anisotropic The same anisotropic etching process as the etching process can be used. The anisotropic etch can be subsequently expanded by altering the etch chemistry to etch through the dielectric material of the isolation dielectric layer 148 to connect to the memory cavities 147 or without altering the etch chemistry. Anisotropic etching may continue until the dielectric material of isolation dielectric layer 148 is removed from the recessed surfaces and sidewalls of memory recesses 149. Alternatively, isotropic etching (such as wet etch) may be used to remove the dielectric material of the isolated dielectric layer from the recessed surfaces and sidewalls of the memory recesses. The photoresist layer may be subsequently removed, for example, by ashing. Optionally, a joint region having a wider lateral dimension than the portions underlying each of the first memory openings 49 may be formed on the upper portion of the uppermost insulating layer 32 using methods known in the art. As shown in FIG.

49, the surface portions of the source connection layer 146 (where the source connection layer 146 comprises a semiconductor material such as doped silicon) and the surface portions of the matrix material layer 138 Such as silicon oxide liner (s), at the bottom portions of each first memory opening 49 by oxidation of the material layer 138 (e.g., where the material layer 138 comprises a semiconductor material such as doped silicon) 31 may be formed.

The first memory opening fill material is deposited into the first memory openings 49 by a conformal deposition process, such as low pressure chemical vapor deposition. The first memory opening fill material includes materials of the first alternating stacks 32 and 42 and materials that can be selectively removed with respect to the semiconductor oxide liner (s) 31. For example, the first memory opening fill material may comprise a semiconductor material (such as polysilicon or amorphous silicon), a carbon containing material (such as amorphous or diamond like carbon), an organic or inorganic polymer (such as a silicon based polymer) Porous or non-porous organosilicate glass. Surplus portions of the first memory opening filler materials are removed from above the top surface of the first alternating stack 32, 42, for example, by chemical mechanical planarization. Each remaining portion of the first memory opening filler material in the first memory openings 49 constitutes first memory opening filler portions 33. In one embodiment, the first memory opening fill portions 33 comprise a semiconductor material. Stepped surfaces (not shown) may be formed through the first alternating stack 32, 42 in the contact area 300. (Which may be identical to the dielectric material portions 65 with the inverse steps of the first and second embodiments) is formed on the stepped surface of the first alternating stack 32, 42 As shown in FIG. The first alternate stacks 32, 42 and the structures embedded therein are collectively referred to as a first tier structure.

Referring to FIG. 50, a plurality of alternating stacks 132, 142, 232, 242 and at least one additional set of memory opening fill portions 133, May be randomly repeated at least once. For example, at least one other alternating stack 132, 142, 232, 242 may include a second alternating stack 132, 142 that includes second insulating layers 132 and second spacer material layers 142, Third alternate stacks 232 and 242 that include third alternating layers 232 and third spacer material layers 242. In some embodiments, The second insulating layers 132 and third insulating layers 232 may be the same in composition and thickness as the first insulating layers 32. The second spacer layers 142 and third spacer layers 242 may be the same in composition and thickness as the first spacer layers 42.

After formation of the second alternate stacks 132 and 142, second memory openings may be formed in the regions above the first memory opening filled portions 33. In one embodiment, the pattern of second memory openings may be identical to the pattern of first memory opening fill portions 33 (which is the same as the pattern of first memory openings 49). In other words, the peripheries of the second memory openings in the horizontal cross-section can overlap with the peripheries of the first memory openings 49 within the tolerances of overlay variations and critical dimension (CD) variations inherent in lithographic alignment have. Second memory opening fill portions 133 are formed in the second memory openings. The second memory opening fill portions 133 may comprise any material that may be utilized for the first memory opening fill portions 33 and may be made of the same material as the first memory opening fill portions 33, And may include materials different therefrom. Stepped surfaces (not shown) may be formed through the second alternating stacks 132 and 142 in the contact area 300. [ A dielectric material portion (not shown) having a second inverse step can be formed on the stepped surfaces of the second alternating stack 132, 142. The second alternate stacks 132 and 142 and the structures embedded therein are collectively referred to as a second tier structure.

Third alternate stacks 232 and 242 may be formed later. If the third alternating stacks 232 and 242 are topmost alternating stacks, an insulating cap layer 70 may be formed at the top of the third alternating stacks 232 and 242. Stepped surfaces (not shown) may be formed through the third alternating stack 232, 242 in the contact area 300. A dielectric material portion (not shown) with a third inverse step can be formed on the stepped surfaces of the third alternating stack 232, 242. The third alternate stacks 232 and 242 and the structures embedded therein are collectively referred to as a third tier structure. Third memory openings 249 may be formed in the regions above the second memory opening fill portions 133. [ In one embodiment, the pattern of the third memory openings 249 may be identical to the pattern of the second memory opening fill portions 133 (which is the same as the pattern of the first memory openings 49). In other words, the peripheries of the third memory openings 249 in the horizontal cross-section can overlap with the peripheral portions of the second memory openings within the tolerances of overlay variations and critical dimension (CD) variations inherent in lithographic alignment have.

Although the present disclosure is described using one embodiment in which three alternate stacks are formed on the substrate 8, it will be appreciated that by repeating or not repeating the process sequence of Figures 46, 47, and 49, Numerical alternating stacks may also be used.

51, second memory opening fill portions 133 and first memory opening fill portions 33 may be formed of materials of alternating stacks 32, 42, 132, 142, 232, 242, Layer 70, and the semiconductor oxide liner 31. In one embodiment, Subsequently, the semiconductor oxide liner 31 can be removed, for example, by an isotropic etching process. Inter-tier memory openings 349 extend through the third, second, and first tier structures and through the source connecting layer 146 and sacrificial rail structures 144 and into the matrix material layer 138 partially As shown in FIG. Each inter-tier memory opening 349 is a memory opening that extends through a plurality of tier structures. Instead of inter-tier memory openings 349, memory openings extending through a single alternating stack may be formed if only a single alternating stack, i.e., first alternate stack 32, 42 is used. Each of the inter-tier memory openings 349 may straddle the interface between the sacrificial rail structure 344 and the matrix material layer 138.

The recessed sidewalls of the sacrificial rail structure 144, the recessed sidewalls of the matrix material layer 138, and the recessed planar surface of the matrix material layer 138 are spaced apart from the upper surface of the insulating cap layer 70, May be physically exposed at the bottom portion of each memory opening (such as each inter-tier opening 349) that extends between the material layers 138. Is measured from the vertical edge to the other vertical edge with respect to the vertical axis passing through the geometric center of the respective memory opening (such as the respective inter-tier memory opening 349) where the concave side wall of the sacrificial rail structure 144 is physically exposed The range of azimuth angles of each physically exposed concave sidewall of the sacrificial rail structure 144, such as, for example, may range from about 45 degrees to about 270 degrees, but smaller azimuth angles and larger azimuth angles may also be used .

Referring to Figure 52, the processing steps of Figures 8B-8D are performed to form a memory stack structure 55, a dielectric core 62, and a drain region 63 in each of the inter-tier memory openings 349 . Each memory stack structure 55 includes a memory film 50 and a semiconductor channel 60. Each memory film 50 may have the same layer stack as in the first embodiment, or may have the same layer stack as in the second embodiment. Each memory stack structure 55 is formed through portions of alternate stacks 32, 42, 132, 142, 232, 242 and sacrificial rail structures 144.

Optionally, additional structures, such as drain side selection gate electrodes and / or additional dielectric material layers (not shown) (similar to elements 87 shown in Figure 74 but not shown in Figure 52) Layer 70 as shown in FIG. Alternatively, as will be described in greater detail below, one or more of the top sacrificial material layers 42 may be replaced by an electrically conductive layer 46 that functions as a drain-side select gate electrode. Optionally, a contact level dielectric layer 80 comprising a dielectric material may be formed over the insulating cap layer 70.

Referring to Figures 53, 54A and 54B, a back trench 79 is formed through contact level dielectric layer 80, insulating cap layer 70, tier structures, and isolation dielectric layer 148 . For example, a photoresist layer (not shown) may be formed over the contact level dielectric layer 80 and may be lithographically patterned to form elongate openings, and the contact level dielectric layer 80, Anisotropic etching may be performed to form openings through layer 70, tier structures, and isolation dielectric layer 148. In one embodiment, the source extension layer 146 may be used as an etch stop layer during anisotropic etching. The backside trenches 79 extend laterally along the direction of the gaps between the arrays of memory stack structures 55. The lengthwise horizontal direction of back trench 79 is referred to herein as a second horizontal direction (e.g., word line direction). The angle between the first horizontal direction (which is the longitudinal direction of sacrificial rail structures 144) and the second horizontal direction may be non-zero and non-orthogonal, as illustrated in Figure 54A, . In other words, the first horizontal direction in this embodiment may be different by 10 degrees to 80 degrees from the bit line direction (i.e., including the "XY" direction), as illustrated in Fig. 54A, May be perpendicular to the word line direction (i. E. May include a "Y" direction perpendicular to the "X" direction), as shown in FIG.

55A and 55B, semiconductor spacers 172 and dielectric spacers 174 may be sequentially formed in the periphery of the respective back trenches 79. Semiconductor spacers 172 comprise a semiconductor material such as polysilicon or amorphous silicon and are formed by depositing a layer of doped semiconductor material on back trench 79 and on contact level dielectric layer 80, Can be formed by anisotropically etching the doped semiconductor material layer by anisotropic etching to remove the horizontal portions of the layer as shown in Figure 55B. In one embodiment, the thickness of the semiconductor spacer 172 may be in the range of 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used. The dielectric spacers 174 include a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride and are formed by depositing a layer of conformal dielectric material over the semiconductor spacers 172 and then depositing a layer of conformal dielectric material, May be formed by anisotropically etching the conformal dielectric material layer by an anisotropic etch to remove them as shown in Figure 55b. In one embodiment, the thickness of the dielectric spacer 174 may be in the range of 2 nm to 20 nm, but smaller thicknesses and larger thicknesses may also be used. Alternatively, a stack of doped semiconductor material layers and conformal dielectric material layers may be sequentially formed as shown in FIG. 55A, and semiconductor spacers 172 and dielectric spacers 174 Anisotropic etching may be performed to remove horizontal portions of the stack of doped semiconductor material layer and conformal dielectric material layer. There is a backside cavity 79 'in the pair of semiconductor spacers 172 and dielectric spacers 174 in each backside trench 79.

Referring to Figures 56, 57A, and 57B, to etch through the source connection layer 146 (where the source connection layer 146 is used) and under each back trench 79, Other anisotropic etching may be performed to physically expose portions of each of the top surfaces of the sacrificial rail structures 144. In the case where the source connection layer 146 comprises a semiconductor material, each of the physically exposed sidewalls of the source connection layer 146 is formed by oxidation of the surface portions of the physically exposed sidewalls of the source connection layer 146 A semiconductor oxide spacer 176 may be formed. Thermal oxidation or plasma oxidation may be used to form the semiconductor oxide spacers 176. [

58, isotropic etching may be performed to remove the sacrificial rail structures 144 from underneath the backside trenches 79. As shown in FIG. For example, if the sacrificial rail structures 144 include silicon nitride, sacrificial rail structures 144 may be formed over the contact level dielectric layer 80, the insulating cap layer 70, the dielectric spacers 174, To selectively remove the spacer 176, the sacrificial liner 154, and the dielectric etch stop layer 145, a wet etch process using high temperature phosphoric acid may be used. The lateral extension cavities 143 are formed in the volumes of the sacrificial rail structures 144 by removal of the sacrificial rail structures 144. The matrix material layer 138 is not removed during isotropic etching. Thus, a plurality of sacrificial rail structures 144 are selectively removed with respect to the matrix material layer 138 to form a plurality of laterally extending cavities 143.

59, portions of the memory film 50 that are physically exposed to the side extension cavities 143 and portions of the optional dielectric etch stop layer 145 may be etched using, for example, a series of isotropic etch processes Lt; / RTI > For example, a series of isotropic etch processes may be performed on the materials of the memory films 50, that is, the intercept dielectric layer (502, 503, or 52 of Figure 8C), the charge storage element layer (504 of Figure 8C, Of the tunneling dielectric layer (506 of Figure 8C or 56 of Figure 25). The sacrificial liner 154 and dielectric spacer 174 may be removed incidentally during removal of the memory films 50. [ A series of isotropic etch processes remove portions of the memory film 50 that are physically exposed to the side extension cavities 143 without removing portions of the memory film 50 that are in contact with the matrix material layer 138 . The side walls of the semiconductor channel 60 are exposed in the side extension cavities 143.

Subsequently, a source conductive layer can be formed. A source conductive layer (e.g., a direct strap contact type source electrode) may be formed using a non-selective semiconductor deposition process, such as in the case of a first process sequence to be described later, Lt; / RTI > may be formed using an optional semiconductor deposition process as in the case of the second process sequence to be performed. 60A, 60B, and 61-66 illustrate a first processing sequence. 67 to 73 illustrate a second processing sequence.

Referring to Figs. 60A and 60B, the step of forming a doped semiconductor material layer 166L is illustrated when a first process sequence is used. 60A shows a third exemplary structure in a configuration illustrated in FIG. 59, i.e., a configuration in which drain select level gate electrodes are not formed above the insulating cap layer 70 prior to formation of the contact level dielectric layer 80 .

60B illustrates an alternative configuration for the third exemplary structure in which drain select level gate electrodes 87 are formed after formation of the insulating cap layer 70 and prior to formation of the contact level dielectric layer 80 have. In this case, drain select level semiconductor pillars 85, drain select level gate dielectrics 82, and drain select level gate electrodes 87 may be formed on the drain regions 63. A drain select level dielectric material layer 802 and an optional via level dielectric material layer 804 may be formed over the drain select level gate electrodes 87. Drain select level dielectric material layer 802 and via level dielectric material layer 804 are collectively referred to as contact level dielectric material layer 80. [

The doped semiconductor material layer 166L includes a doped semiconductor material such as doped polysilicon. In one embodiment, the doped semiconductor material layer 166L has a conductivity type that is greater than 1.0 x 10 ⁵ S / cm and has a conductivity type that is the same as the conductive type of the matrix material layer 138 and the source connection layer 146, Lt; RTI ID = 0.0 > doped < / RTI > semiconductor material. The doped semiconductor material layer 166L may be deposited by a conformal deposition process, such as low pressure chemical vapor deposition (LPCVD). In one embodiment, the backside trench 79 may have a tapered profile such that the top portion of the backside trench 79 has a greater width than the bottom portion of the backside trench 79.

In one embodiment, the thickness of the doped semiconductor material layer 166L is selected to be greater than half the width of the backside trench 79 at the bottom portion and less than half the width of the backside trench 79 at the top portion . The doped semiconductor material layer 166L may be merged at the bottom of the back trench 79 and not at the top of the back trench 79. In this case, there may be a wedge-shaped backside cavity within each backside trench 79 after formation of the doped semiconductor material layer 166L. Each side extension cavity 143 may be at least partially filled with a doped semiconductor material layer 166L. In one embodiment, an encapsulated cavity 167 may be formed in the unfilled volume of each side extension cavity 143 below the backside trench 79. In one embodiment, a doped semiconductor material layer 166L may be formed directly on the inner surface of each semiconductor spacer 172.

Referring to FIG. 61, to remove portions of the doped semiconductor material layer 166L located above the horizontal plane, including the bottom surface of the lowermost spacer material layer, which may be the lowermost sacrificial material layer 42, isotropic or anisotropic Etching can be performed. The vertical portions of the doped semiconductor material layer 166L may be removed from within the respective backside trenches 79. [ Each remaining portion of the doped semiconductor material layer 166L includes a source conductive layer 166 that functions as a source of vertical field effect transistors including semiconductor channels 60 in the memory stack structures 55 . The semiconductor spacers 172 may be removed from above the top surface of the source conductive layer 166 during isotropic etching. Any remaining portion of the semiconductor spacer 172 may be located below a horizontal plane that includes the top surface of the source conductive layer 166. [

A source conductive layer 166 is formed in the lower portion of the backside trench 79 and in the plurality of lateral extension cavities 143 and on the sidewalls of the semiconductor channels 60. The source conductive layer 166 may be formed through an opening in the source connection layer 146 and may be formed directly on the sidewalls and portions of the bottom surface of the source connection layer 146.

Each source conductive layer 166 includes a plurality of conductive rail structures 166A extending along the first horizontal direction and laterally spaced from one another. A plurality of conductive rail structures 166A are formed in the plurality of lateral extension cavities 143. [ In other words, the conductive rail structures 166A extending in the first horizontal direction in this embodiment may be different from the bit line direction and the word line direction by 10 degrees to 80 degrees (i.e., extending in the "XY" direction) ), Parallel to the bit line direction and perpendicular to the word line direction (i.e. may include a "Y" direction perpendicular to the "X" direction). Each source conductive layer 166 also includes a conductive straddling structure 166B extending along a second horizontal direction that is different from the first horizontal direction (e.g., in the word line "X" direction) . A conductive straining structure 166B is formed in the lower portion of the backside trench 79. [ Each of the conductive rail structures 166A is adjacent to the conductive strapping structure 166B. The conductive strapping structure 166B straddles each of the conductive rail structures 166A. In other words, the conductive strapping structure 166B extends in the longitudinal direction of each conductive rail structure 166A, which extends in both directions along the first horizontal direction to "straddle " the conductive rail structure 166A And extends away from the lengthwise sidewalls. Each source conductive layer 166 is formed as an integral structure, i.e., a single continuous structure.

Referring to Figure 62, a third exemplary structure is illustrated for a first processing sequence. Specifically, the semiconductor oxide portion 175 can be formed by converting the surface portion of the source conductive layer 166 into a semiconductor oxide material. For example, if the source conductive layer 166 comprises doped polysilicon, the semiconductor oxide portion 175 may comprise doped silicon oxide. In one embodiment, a semiconductor oxide portion 175 is formed on top of the conductive straining structure 166B of the source conductive layer 166 and on the lowermost spacer material layer (i. E., The bottom sacrificial material layer 42 )). ≪ / RTI >

63, spacer material layers (which may include first sacrificial material layers 42, second sacrificial material layers 142, and third sacrificial material layers 242) may be deposited on insulating layers 32, 132 The backside recesses 43 are formed by selective removal of the semiconductor oxide portions 175, 232, the contact level dielectric layer 80, the insulating cap layer 70, and the semiconductor oxide portion 175. The same processing steps as the processing steps of Fig. 14 or the processing steps of Fig. 33 can be used.

64, a back-off dielectric layer (not shown) may be conformally deposited on the back-side recesses and on the sidewalls of the back-side trench 79. Electrically conductive layers 46 are formed by depositing at least one conductive material on the remaining volumes of backside recesses 43, on peripheral portions of backside trench 79, and on contact level dielectric layer 80. [ And a continuous conductive material layer 46L may be formed. The continuous conductive material layer 46L refers to a portion of at least one conductive material deposited outside the backside recesses 43. [ The same processing steps as the processing steps of FIG. 15 or the processing steps of FIG. 34 may be used to form the electrically conductive layers 46.

Referring to Fig. 65, a continuous layer of conductive material 46L may be removed by recess etching, which may be isotropic etching, anisotropic etching, or a combination thereof. The back cavity 79 'is present above the semiconductor oxide portion 175 in each backside trench 79.

Referring to FIG. 66, a dielectric material is deposited in the backside cavity 79 'to form a dielectric separator structure 78. Surplus portions of the dielectric material deposited above the horizontal plane, including the top surface of the contact level dielectric material layer 80, may be removed by a planarization process, which may utilize, for example, chemical mechanical planarization or recess etch. have.

67, which corresponds to the steps of FIGS. 67 to 73 and is used in place of the first processing sequence corresponding to the steps of FIGS. 6A, 6B and 61 to 66, Steps are illustrated. To remove the semiconductor spacers 172 from the sidewalls of the backside trenches 79, an isotropic etch may be performed on the third exemplary structure illustrated in FIG.

68, a source conductive layer 166 may be formed by selective semiconductor deposition of a doped semiconductor material. In this case, the matrix material layer 138 comprises a doped semiconductor material, and the doped semiconductor material of the source conductive layer 166 has the same conductivity type of doping as the matrix material layer 138.

During the selective semiconductor deposition process, semiconductor precursor gases (such as silane, disilane, dichlorosilane, trichlorosilane, germane, etc.), dopant gases (such as diborane, phosphine, arsine, stibin, Etchant gas such as hydrogen chloride gas may flow into the process chamber simultaneously or in a repeating sequence with at least one optional carrier gas (such as hydrogen, nitrogen, and / or argon). Amorphous surfaces (such as dielectric layers 32, sacrificial material layers 42, 142, 242, insulating cap layer 70, and dielectric surfaces of contact level dielectric layer 80) And polycrystalline semiconductor surfaces of optional source coupling layer 146). ≪ / RTI > By setting the etch rate by the etchant gas to be between the deposition rate of the semiconductor material on the amorphous surface and the deposition rate of the semiconductor material on the crystalline semiconductor surfaces (e.g., by selecting the appropriate flow rate for the etchant gas The doped semiconductor material does not grow from the dielectric surfaces of the insulating layers 32, the sacrificial material layers 42, 142, 242, the insulating cap layer 70, and the contact level dielectric layer 80 But may only grow from the crystalline semiconductor surfaces of the matrix material layer 138 and the optional source coupling layer 146.

Thus, the optional semiconductor material deposition process deposits a doped semiconductor material (e.g., polysilicon) on the semiconductor surfaces and does not grow from the dielectric surfaces. The source conductive layer 166 may be formed through an opening in the source connection layer 146 and may be formed directly on the sidewalls and portions of the bottom surface of the source connection layer 146.

Each source conductive layer 166 includes a plurality of conductive rail structures 166A extending along the first horizontal direction and laterally spaced from one another. A plurality of conductive rail structures 166A are formed in the plurality of lateral extension cavities 143. [ Each source conductive layer 166 also includes a conductive strapping structure 166B that extends along a second horizontal direction that is different from the first horizontal direction. The conductive straining structure 166B is formed in the lower portion of the backside trench 79, as previously described. Each source conductive layer 166 is formed as an integral structure, i.e., a single continuous structure. In one embodiment, an encapsulated cavity 167 may be formed in the unfilled volume of each side extension cavity 143 below the backside trench 79.

69, in order to improve the planarity of the top surface of the source conductive layer 166 and to improve the planarity of the top surface of the source conductive layer 166 to the bottom-most spacer material layer, i.e. the lowermost first sacrificial material layer 42, The top surface of the conductive straining structure 166B of the source conductive layer 166 may optionally be recessed to ensure that it is provided below a horizontal plane including the bottom surface of the source conductive layer 166. [

70, the upper portion of the source conductive layer 166 (e.g., the upper portion of the conductive straining structure 166B) is converted to a semiconductor oxide material by, for example, thermal oxidation or by plasma oxidation The process steps of FIG. 62 may be performed to form the semiconductor oxide portion 175 by etching.

71, spacer material layers (which may include first sacrificial material layers 42, second sacrificial material layers 142, and third sacrificial material layers 242) may be deposited on insulating layers 32, 132 , 232, insulating cap layer 70, and semiconductor oxide portion 175 are selectively removed to form backside recesses 43. [ The same processing steps as the processing steps of Fig. 14 or the processing steps of Fig. 33 can be used.

72, a back-off dielectric layer (not shown) may be conformally deposited on the back-side recesses and on the sidewalls of the back-side trench 79. By depositing at least one conductive material on the remaining volumes of the backside recesses 43, on peripheral portions of the backside trench 79, and on the insulating cap layer 70, the electrically conductive layers 46 and < RTI ID = 0.0 & A continuous conductive material layer 46L may be formed. The continuous conductive material layer 46L refers to a portion of at least one conductive material deposited outside the backside recesses 43. [ The same processing steps as the processing steps of FIG. 15 or the processing steps of FIG. 34 may be used to form the electrically conductive layers 46.

Referring to FIG. 73, a continuous layer of conductive material 46L may be removed by recess etching, which may be isotropic etching, anisotropic etching, or a combination thereof. The backside cavity is on the semiconductor oxide portion 175 in each backside trench 79. A dielectric material is deposited in the backside cavity to form the dielectric separator structure 78. (Or above a horizontal plane comprising the contact level dielectric material layer 80 when a contact level dielectric material layer 80 is used), including a top surface of the insulating cap layer 70 Surplus portions of the material may be removed, for example, by a planarization process, which may utilize chemical mechanical planarization or recess etch.

74, a vertical cross-sectional view of an alternative embodiment (including drain select level gate electrodes 87) of a third exemplary structure after formation of a dielectric separator structure 78 is illustrated.

75A-75E illustrate a cross-sectional view along the various horizontal section planes (A-A ', B-B', C-C ', D-D', and E-E ' And the second horizontal direction are non-orthogonal to each other) in a first configuration.

76A through 76E are views of a plurality of horizontal cross-sectional planes A-A ', B-B', C-C ', D-D', and E-E ' And the second horizontal direction are orthogonal to one another) in a second configuration. The location of the bit lines 90 is shown in broken lines in Figures 74, 75E and 76E. The bit lines 90 are parallel to or perpendicular to the first horizontal direction which is perpendicular to the word line (e.g., "X") direction and extends in the direction of the conductive rail structures 166A, (E.g., "Y") direction, which may be different from the bit line (e.g., 60 degrees, etc.). The bit lines 90 are electrically connected to the drain regions through their drain contact via contact structures 88. In this third embodiment, the matrix material layer 138 functions as a support structure (e.g., a support pedestal structure) as previously described in connection with the first and second embodiments.

Various exemplary structures of the present disclosure may include a three-dimensional memory device. The three-dimensional memory device includes alternating stacks of electrically conductive layers 46 and insulating layers 32 (132, if present, 232, if present) located over the substrate 8; An array of memory stack structures 55- each memory stack structure 55 includes a semiconductor channel 60 extending through an alternating stack and surrounded laterally by a memory film 50 and a memory film 50 -; And source conductive layers 76L, 150, 166 that are in contact with the lower portion of the sidewalls of each semiconductor channel 60 and located between the alternating stack and the substrate 8. The source conductive layers 76L, 150, 166 may be doped semiconductor material layers.

In one embodiment, the source conductive layer 166 includes a plurality of conductive rail structures 166A extending along a first horizontal direction and laterally spaced from one another; And a conductive strapping structure 166B extending along a second horizontal direction different from the first horizontal direction, wherein each conductive rail structure 166A is adjacent to the conductive strapping structure 166B have. Conductive rail structures 166A may serve as source regions of the memory device or as source electrodes when a doped source region is formed at the bottom of the semiconductor channel 60. [

In one embodiment, the three-dimensional memory device may include a support structure that includes a matrix material layer 138 laterally surrounding the bottom portion of each of the memory stack structures. A plurality of conductive rail structures 166A are located in the plurality of channels 141 in the matrix material layer 138 extending along the first horizontal direction.

In one embodiment, the convex sidewalls and bottom surfaces of each memory film 50 contact the matrix material layer 138. In one embodiment, the convex sidewalls of each semiconductor channel 60 are in contact with the concave sidewalls of their respective conductive rail structures 166A, wherein a vertical axis passing through the geometric center of the memory stack structure 55, The azimuthal angle between the two vertical edges of the contact area between the convex sidewalls and the respective conductive rail structure 166A as measured about the center of the conductive rail structure 166A is in the range of 45 degrees to 270 degrees. In one embodiment, the matrix material layer 138 comprises a first doped semiconductor material and is electrically shorted to the source conductive layer 166. [ In one embodiment, the entire source conductive layer 166 includes a second doped semiconductor material that extends continuously over each portion of the source conductive layer 166 and has the same conductivity type as the first doped semiconductor material Or may be an integral structure including, e.g.

In one embodiment, each side wall of the plurality of conductive rail structures 166A includes a set of concave vertical sidewall portions and a set of planar vertical sidewall portions adjacent to each other, Material layer 138, and each concave vertical sidewall portion is in contact with its respective semiconductor channel 60. In one embodiment, the entire lower surface of the plurality of conductive rail structures 166A are recessed surfaces of the matrix material layer 138 located above the horizontal plane, including the lower surface of the layer of matrix material 138 / RTI >

In one embodiment, the conductive strapping structure 166B is on each of the plurality of conductive rail structures 166A, adjacent to the top portion of each of the plurality of conductive rail structures 166A, Lt; RTI ID = 0.0 > 166A. ≪ / RTI >

The plurality of bit lines 90 extend in the bit line direction (i.e., the "Y" direction) and the electrically conductive layers 46 extend in the word line direction And extending word lines. The conductive straining structure 166B also extends in the wordline direction parallel to the wordline direction and perpendicular to the bitline direction. In one embodiment, the first horizontal direction (i. E., The "XY" direction in which the conductive rail structures 166A extend) is greater than both the word line direction and the bit line direction, For example, it differs from 30 degrees to 60 degrees. In other words, when the first horizontal direction is different from the word line direction by N degrees (for example, 10 degrees or 30 degrees), the first horizontal direction is 90-N degrees (for example, 80 degrees or 60 degrees) It is different. In another embodiment, the first horizontal direction is parallel to the bit line direction and the conductive rail structures 166A are parallel to the bit lines 90.

The source connection layer 146 may be positioned between the plurality of conductive rail structures 166A and the alternating stack. The source connection layer 146 may contact the side walls of the conductive strapping structure 166B and laterally surround the memory stack structures 55. [

Peripheral devices 210 may be located below or adjacent memory device area 100 including memory stack structures 55 and may use additional electrical contacts (not shown) And may be in electrical contact with the source connection layer 146.

A dielectric separator structure 78 comprising a dielectric material may extend vertically through the entire alternate stack and may be over the entire area of the conductive strapping structure 166B. The dielectric material of the dielectric separator structure 78 produces less mechanical stress from the interior of the backside trench 79 than a similar volume of metallic material portion within the backside trench 79. Thus, by providing the dielectric separator structure 78 instead of the metal material portion in the backside trench, the mechanical stress of the three-dimensional memory device can be mitigated.

In one embodiment, the three-dimensional memory device comprises a vertical NAND device located on a substrate 8, and the electrically conductive layers 46 comprise or are electrically connected to a respective word line of the NAND device, ) May comprise a silicon substrate. In one embodiment, the vertical NAND device comprises an array of monolithic three-dimensional NAND strings on a silicon substrate, and at least one memory cell at a first device level of the array of monolithic three-dimensional NAND strings comprises a monolithic And is positioned over another memory cell at a second device level of the array of three-dimensional NAND strings, wherein the silicon substrate comprises an integrated circuit comprising driver circuitry for a memory device located thereon. In one embodiment, the electrically conductive layers 46 include a plurality of controls having a strip shape extending substantially parallel to the top surface of the substrate (e.g., along a first horizontal direction between pairs of backside trenches 79) Gate electrodes, and the plurality of control gate electrodes may include at least a first control gate electrode positioned at a first device level and a second control gate electrode positioned at a second device level. In one embodiment, the array of monolithic three-dimensional NAND strings comprises: a plurality of semiconductor channels 60, at least one end portion of each of the semiconductor channels of the plurality of semiconductor channels 60, Substantially vertically extending, and a plurality of charge storage elements (such as those implemented as portions of the charge storage element layers 504, 54). Each charge storage element may be located adjacent to a respective semiconductor channel of a plurality of semiconductor channels 60.

The source conductive layers 76L, 150, 166 of the various embodiments of the present disclosure can serve as common source electrodes for vertical field effect transistors including semiconductor channels 60 in the memory stack structures 55 have. By avoiding the formation of metal structures in the backside trenches 79, the mechanical stress level of the three dimensional memory device can be significantly reduced. The source conductive layers 76L, 150, 166 may be contacted by a source electrode contact via structure (not shown) that may be provided in the contact region 300. [

While the foregoing is directed to certain preferred embodiments, it will be understood that the invention is not so limited. Those of ordinary skill in the art will recognize that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present invention. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims (22)

As a three-dimensional memory device,
An alternating stack of electrically conductive layers and insulating layers disposed over a substrate;
An array of memory stack structures, each memory stack structure extending through the alternate stack and including a memory film and a semiconductor channel laterally surrounded by the memory film; And
A source conductive layer disposed between the alternating stack and the substrate and in contact with a bottom portion of a sidewall of each semiconductor channel,
Wherein the source conductive layer comprises a plurality of conductive rail structures extending along a first horizontal direction and laterally spaced from each other. 2. The method of claim 1 wherein the source conductive layer further comprises a conductive straddling structure extending along a second horizontal direction different from the first horizontal direction, Wherein the conductive straining structure is adjacent to the conductive straining structure. 3. The three dimensional memory device of claim 2, further comprising a support structure comprising a layer of matrix material laterally surrounding the bottom portion of each of the memory stack structures. The method of claim 3,
The plurality of conductive rail structures being located in a plurality of channels in the layer of matrix material extending along the first horizontal direction;
And a convex sidewall and a bottom surface of each memory film are in contact with the matrix material layer. 4. The method of claim 3, wherein the convex sidewalls of each of the semiconductor channels are in contact with the concave sidewalls of their respective conductive rail structures and are spaced apart from each other by a predetermined distance, as measured about a vertical axis passing through the geometric center of the memory stack structure, Wherein an azimuth angle between two vertical edges of a contact area between the convex sidewalls and the respective conductive rail structure is in the range of 45 degrees to 270 degrees. The method of claim 3,
The matrix material layer comprising a first doped semiconductor material and electrically shorted to the source conductive layer;
Wherein the entire source conductive layer is an integral structure that extends continuously over each portion of the source conductive layer and comprises a second doped semiconductor material having the same conductivity type as the first doped semiconductor material, Memory device. The method of claim 3,
Each sidewall of the plurality of conductive rail structures includes a set of concave vertical sidewall portions and a set of planar vertical sidewall portions adjacent to each other;
Each of the planar vertical sidewall portions being in contact with the layer of matrix material;
Each of said concave vertical sidewall portions being in contact with a respective semiconductor channel;
Wherein all of said bottom surfaces of said plurality of conductive rail structures are in contact with recessed surfaces of said matrix material layer located above a horizontal plane comprising a bottom surface of said layer of matrix material. 3. The method of claim 2, wherein the conductive strapping structure is on each of the plurality of conductive rail structures, adjacent to a top portion of each of the plurality of conductive rail structures, Dimensional memory device. The memory device of claim 8, further comprising a plurality of bit lines extending in a bit line direction, the electrically conductive layers including word lines extending in a word line direction perpendicular to the bit line direction, . 10. The method of claim 9,
The first horizontal direction being different from both the word line direction and the bit line direction;
Wherein the conductive straining structure extends in the word line direction. 10. The method of claim 9,
The first horizontal direction being parallel to the bit line direction;
Wherein the conductive straining structure extends in the word line direction. 3. The method of claim 2,
A source connection layer located between the plurality of conductive rail structures and the alternate stack, the source connection layer contacting the sidewalls of the conductive strapping structure and laterally surrounding the memory stack structures; And
A dielectric separator structure overlying the entire region of the conductive straining structure, the dielectric separator structure including a dielectric material, the dielectric separator structure extending vertically through the entire alternate stack,
Wherein the memory device further comprises: The method according to claim 1,
Said three dimensional memory device comprising a vertical NAND device located above said substrate;
The electrically conductive layers comprising or electrically connected to a respective word line of the NAND device;
The substrate comprising a silicon substrate;
Wherein the vertical NAND device comprises an array of monolithic three-dimensional NAND strings on the silicon substrate;
At least one memory cell at a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell at a second device level of the array of monolithic three-dimensional NAND strings;
The silicon substrate comprising an integrated circuit comprising driver circuitry for the memory device located thereon;
Wherein the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate and wherein the plurality of control gate electrodes comprise at least a first control A gate electrode and a second control gate electrode located at the second device level;
Wherein the array of monolithic three-dimensional NAND strings comprises:
A plurality of semiconductor channels, at least one end portion of each semiconductor channel of the plurality of semiconductor channels extending substantially perpendicular to an upper surface of the substrate; and
A plurality of charge storage elements, each charge storage element being located adjacent a respective semiconductor channel of the plurality of semiconductor channels,
Dimensional memory device. A method of forming a three-dimensional memory device,
Forming a matrix material layer on the substrate, the matrix material layer including a plurality of channels extending along a first horizontal direction;
Forming a plurality of sacrificial rail structures in the plurality of channels;
Forming an alternating stack of insulator layers and spacer material layers over the matrix material layer and the sacrificial rail structures;
Forming memory stack structures through portions of the alternating stack and the sacrificial rail structures, each of the memory stack structures including a respective memory film and a respective semiconductor channel;
Forming a backside trench extending through the alternating stack, the surfaces of the sacrificial rail structures being physically exposed beneath the backside trench;
Selectively removing said plurality of sacrificial rail structures relative to said matrix material layer to form a plurality of lateral extension cavities;
Removing portions of the memory film physically exposed to the lateral extending cavities without removing portions of the memory film that are in contact with the layer of matrix material; And
Forming a source conductive layer in the bottom portion of the backside trench and in the plurality of lateral extension cavities and in contact with the sidewalls of the semiconductor channels
/ RTI > 15. The device of claim 14, wherein the source conductive layer comprises:
A plurality of conductive rail structures extending along a first horizontal direction and laterally spaced from each other and formed in the plurality of side extension cavities; And
A conductive strapping structure extending along a second horizontal direction different from the first horizontal direction and formed in a lower portion of the rear trench;
Wherein each of the conductive rail structures is adjacent to the conductive strained ring structure. 15. The method of claim 14, further comprising: forming memory openings through the alternate stack and through the upper portion of the layer of matrix material, each of the memory openings having a respective sacrificial rail structure and the matrix material And straddles the interface between the layers. 15. The device of claim 14, wherein the source conductive layer comprises:
Depositing a layer of doped semiconductor material in the plurality of lateral extension cavities and the backside trench using a conformal deposition process, wherein the backside cavity, which is not filled with the doped semiconductor material layer, ≪ / RTI > And
Isotropically removing vertical portions of the doped semiconductor material layer from within the backside trench, the remaining portion of the doped semiconductor material layer comprising the source conductive layer,
≪ / RTI > 15. The method of claim 14,
Wherein the matrix material layer comprises a semiconductor material;
Wherein the source conductive layer is formed by an optional semiconductor material deposition process that deposits a semiconductor material on semiconductor surfaces and does not grow from dielectric surfaces. 15. The method of claim 14, further comprising forming a source connection layer comprising a conductive material over the plurality of sacrificial rail structures and the matrix material layer, wherein the alternate stack is formed over the source connection layer, Wherein a source conductive layer is formed through the opening in the source connection layer. 15. The method of claim 14,
Forming a semiconductor oxide portion on top of the source conductive layer and below a level of the lowermost spacer material layer in the alternating stack;
Forming the backside recesses by selectively removing the spacer material layers with respect to the insulating layers; And
Forming electrically conductive layers in the backside recesses
≪ / RTI > 21. The method of claim 20,
Forming a backside cavity over the semiconductor oxide portion after formation of the electrically conductive layers; And
Forming a dielectric separator structure by filling the backside cavity with a dielectric material;
≪ / RTI > 15. The method of claim 14,
Said three dimensional memory device comprising a vertical NAND device located above said substrate;
Wherein the spacer material layers are formed as electrically conductive layers or replaced with electrically conductive layers;
The electrically conductive layers comprising or electrically connected to a respective word line of the NAND device;
The substrate comprising a silicon substrate;
Wherein the vertical NAND device comprises an array of monolithic three-dimensional NAND strings on the silicon substrate;
At least one memory cell at a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell at a second device level of the array of monolithic three-dimensional NAND strings;
The silicon substrate comprising an integrated circuit comprising driver circuitry for the memory device located thereon;
Wherein the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate and wherein the plurality of control gate electrodes comprise at least a first control A gate electrode and a second control gate electrode located at the second device level;
Wherein the array of monolithic three-dimensional NAND strings comprises:
A plurality of semiconductor channels, at least one end portion of each semiconductor channel of the plurality of semiconductor channels extending substantially perpendicular to an upper surface of the substrate; and
A plurality of charge storage elements, each charge storage element being located adjacent a respective semiconductor channel of the plurality of semiconductor channels,
≪ / RTI >

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