CN108140643B

CN108140643B - Three-dimensional NAND device including support pedestal structure for buried source line and method of fabricating the same

Info

Publication number: CN108140643B
Application number: CN201680055147.8A
Authority: CN
Inventors: 张彤; J.阿尔斯梅尔; J.卡伊; J.刘; 张艳丽
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2015-11-20
Filing date: 2016-11-17
Publication date: 2022-03-15
Anticipated expiration: 2036-11-17
Also published as: KR101944229B1; CN108140643A; KR20180042358A

Abstract

A three-dimensional memory device includes an array of memory stack structures, an alternating stack of conductive and insulating layers located over a substrate. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along the same horizontal direction and adjacent to the common conductive cross-over structure. Each memory stack structure bridges a vertical interface between a conductive rail structure and a supporting substrate. The semiconductor channel in each memory stack structure contacts a respective conductive rail structure and a supporting matrix.

Description

Three-dimensional NAND device including support pedestal structure for buried source line and method of fabricating the same

Cross Reference to Related Applications

This application is a partial continuation of U.S. patent application serial No. 15/225,492 filed on day 1/8/2016 in 2016, which is a partial continuation of U.S. patent application serial No. 15/017,961 filed on day 8/2/2016, which claims the benefit of priority to U.S. provisional patent application serial No. 62/258,250 filed on day 20/11/2015, the entire contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabricating the same.

Background

A three-dimensional vertical NAND string With one bit per Cell is disclosed in a new Ultra High Density Memory With Stacked Surrounding Gate Transistor (S-SGT) Structured Cell published by t.endoh et al in IEDM procedures (2001)33-36 under the title "new Ultra High Density Memory With a Stacked Surrounding Gate Transistor (S-SGT) Structured Cell".

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of conductive layers and insulating layers over a substrate; an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film; and a source conductive layer contacting a bottom portion of the sidewalls of each semiconductor channel and located between the alternating stack and the substrate. The source conductive layer includes a plurality of conductive rail structures extending along a first horizontal direction and laterally spaced apart from each other.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. A host material layer including a plurality of channels extending along a first horizontal direction is formed over a substrate. A plurality of sacrificial rail structures are formed in the plurality of trenches. Alternating stacks of insulator layers and spacer material layers are formed over the matrix material layers and the sacrificial rail structures. A memory stack structure is formed through portions of the alternating stack and sacrificial rail structures. Each of the memory stack structures includes a respective memory film and a respective semiconductor channel. Forming backside trenches extending through the alternating stack. The surface of the sacrificial rail structure is physically exposed under the backside trench bottom. The plurality of sacrificial rail structures are removed selectively to the layer of matrix material to form a plurality of laterally extending cavities. Portions of the memory film that are physically exposed to the laterally extending cavities are removed without removing portions of the memory film that contact the layer of matrix material. A source conductive layer is formed in the lower portion of the backside trench and the plurality of laterally extending cavities and contacts sidewalls of the semiconductor channel.

According to an aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of conductive layers and insulating layers over a substrate; an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film; and a support structure positioned between the alternating stack and the substrate. The device may also include a source conductive layer underlying the alternating stack and overlying the substrate and in contact with the support structure.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. A layer including a support pedestal structure and a sacrificial material portion is formed over a substrate. Alternating stacks of insulator layers and layers of spacer material are formed over the support base structure and the sacrificial material portions. A memory stack structure is formed through the alternating stack. Each of the memory stack structures includes a respective portion of the memory film and a respective semiconductor channel, and protrudes into a respective sacrificial material portion. The sacrificial material portion is removed without removing the support pedestal structure to form at least one laterally extending cavity. Portions of the memory film physically exposed to the at least one laterally extending cavity are removed without removing portions of the memory film in contact with the support pedestal structure. A conductive track structure is formed in the at least one laterally extending cavity and on sidewalls of the semiconductor channel.

According to an aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of conductive layers and insulating layers over a substrate; an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film; and an array of dielectric pillars located between the alternating stack and the substrate.

According to another aspect of the present disclosure, a method of manufacturing a three-dimensional memory device is provided. A sacrificial matrix layer is formed over the substrate. The sacrificial matrix layer is patterned to form an array of cavities. An array of dielectric pillars is formed by filling the array of cavities with a dielectric fill material. Alternating stacks of insulator layers and spacer material layers are formed over the array of dielectric pillars and the sacrificial matrix layer. An array of memory stack structures is formed through the alternating stacks and the sacrificial matrix layer. The sacrificial substrate layer is replaced by a source conductive layer.

Drawings

Fig. 1 is a vertical cross-sectional view of a first exemplary structure after forming a lower source insulator layer, a sacrificial matrix layer, and an upper source insulator layer, according to a first embodiment of the present disclosure.

Fig. 2 is a vertical cross-sectional view of a first exemplary structure after forming an array of via cavities through a sacrificial matrix layer according to a first embodiment of the present disclosure.

Fig. 3 is a vertical cross-sectional view of a first exemplary structure after forming an array of dielectric pillars, according to a first embodiment of the present disclosure.

Fig. 4A-4C are horizontal cross-sectional views of the first exemplary structure of fig. 3 through an array of sacrificial material layers and dielectric pillars, respectively, for first, second, and third exemplary configurations, according to a first embodiment of the present disclosure. The zigzag vertical plane X-X' corresponds to the plane of the vertical cross-sectional view of fig. 3.

Fig. 5 is a vertical cross-sectional view of a first exemplary structure after forming an alternating stack of insulating layers and sacrificial material layers according to a first embodiment of the present disclosure.

Fig. 6 is a vertical cross-sectional view of a first example structure after forming memory openings extending through alternating stacks according to a first embodiment of the present disclosure.

Fig. 7A-7C are horizontal cross-sectional views of the first exemplary structure of fig. 6 through an array of sacrificial material layers, dielectric pillars, and memory openings for first, second, and third exemplary configurations, respectively, according to a first embodiment of the present disclosure. The zigzag vertical plane X-X' corresponds to the plane of the vertical cross-sectional view of fig. 6.

Figures 8A-8D are sequential vertical cross-sectional views of a memory opening within a first exemplary structure during various processing steps used to form a memory stack structure according to a first embodiment of the present disclosure.

Figure 9 is a vertical cross-sectional view of a first example structure after forming a memory stack structure, according to a first embodiment of the present disclosure.

Fig. 10 is a vertical cross-sectional view of a first example structure after forming a set of stepped surfaces and portions of backward stepped dielectric material according to a first embodiment of the present disclosure.

Figure 11 is a vertical cross-sectional view of a first example structure after forming through-stack dielectric pillars, according to a first embodiment of the present disclosure.

Fig. 12A is a vertical cross-sectional view of a first exemplary structure after forming backside trenches, according to a first embodiment of the present disclosure.

Fig. 12B is a perspective top view of the first exemplary structure of fig. 12A. The zigzag vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 12A for the case of the first exemplary configuration.

Fig. 13A-13C are horizontal cross-sectional views of the first exemplary structure of fig. 12A through an array of sacrificial material layers, dielectric pillars, and memory openings for the first, second, and third exemplary configurations, respectively, according to the first embodiment of the present disclosure. The zigzag vertical plane X-X' corresponds to the plane of the vertical cross-sectional view of fig. 12A.

Fig. 14 is a vertical cross-sectional view of the first exemplary structure after forming a backside concavity according to the first embodiment of the present disclosure.

Fig. 15 is a vertical cross-sectional view of a first exemplary structure after replacing a sacrificial material layer with a conductive layer according to a first embodiment of the disclosure.

Fig. 16 is a vertical cross-sectional view of a first exemplary structure after forming insulating spacers according to a first embodiment of the present disclosure.

FIG. 17 is a vertical cross-sectional view of the first exemplary structure after forming a source line cavity by removing a sacrificial matrix layer, according to the first embodiment of the disclosure.

Fig. 18 is a vertical cross-sectional view of the first exemplary structure after forming a continuous source structure according to the first embodiment of the present disclosure.

Fig. 19 is a vertical cross-sectional view of a first exemplary structure after forming various contact via structures, in accordance with a first embodiment of the present disclosure.

Figure 20 is a graph illustrating the magnitude of stress on memory stack structures for various configurations of dielectric pillars, according to an embodiment of the present disclosure.

Fig. 21 is a perspective view of a second exemplary structure having a cut-out region for illustrative purposes after forming a source conductive layer, a sacrificial material portion, and an optional dielectric liner according to a second embodiment of the present disclosure.

Fig. 22 is a perspective view of a second exemplary structure having a cut-out region after forming a support base structure according to a second embodiment of the present disclosure.

Fig. 23 is a perspective view of a second exemplary structure having cut-out regions after forming an alternating stack of insulating layers and spacer material layers according to a second embodiment of the present disclosure.

Fig. 24 is a perspective view of a second exemplary structure having a cut-out region after forming a reservoir opening according to a second embodiment of the present disclosure.

Fig. 25 is a perspective view of a second exemplary structure having a cut-out region after forming a memory stack structure according to a second embodiment of the present disclosure.

Fig. 26 is a perspective view of a second exemplary structure having a cut-out region after forming a backside contact trench in accordance with a second embodiment of the present disclosure.

Fig. 27 is a perspective view of a second exemplary structure having a kerf region after removal of sacrificial material portions and formation of laterally extending cavities according to a second embodiment of the present disclosure.

FIG. 28 is a perspective view of a second exemplary structure having a cut-out region after removal of a physically exposed portion of a memory film according to a second embodiment of the present disclosure.

Fig. 29 is an enlarged view of an area of the second exemplary structure of fig. 28.

Fig. 30 is a perspective view of a second exemplary structure having a kerf region after forming a layer of doped semiconductor material according to a second embodiment of the present disclosure.

Fig. 31 is a vertical cross-sectional view of the second exemplary structure shown in fig. 30.

Figure 32 is a vertical cross-sectional view of the second exemplary structure after removing portions of the layers of doped semiconductor material from within the backside contact trench and from above the alternating stack and forming a drain region according to the second embodiment of the present disclosure.

Fig. 33 is a vertical cross-sectional view of a second exemplary structure after backside recesses have been formed by removing a layer of spacer material according to a second embodiment of the present disclosure.

Fig. 34 is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer in a backside recess according to a second embodiment of the present disclosure.

Fig. 35A is a vertical cross-sectional view of a second exemplary structure after forming insulating spacers and backside contact via structures according to a second embodiment of the present disclosure.

FIG. 35B is a horizontal cross-sectional view of the second exemplary structure along plane B-B' in FIG. 35A. Plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 35A.

Fig. 36 is a vertical cross-sectional view of a second exemplary structure after forming an additional contact via structure according to a second embodiment of the present disclosure.

Fig. 37 is a vertical cross-sectional view of a third exemplary structure after forming an optional insulator layer, an optional blanket conductor (blanket conductor) layer, and a matrix material layer, in accordance with a third embodiment of the present disclosure.

Fig. 38 is a vertical cross-sectional view of a third exemplary structure after forming a plurality of channels in an upper portion of a layer of matrix material according to a third embodiment of the present disclosure.

Figure 39 is a vertical cross-sectional view of a third exemplary structure after forming sacrificial liners and sacrificial rail structures in a plurality of trenches, according to a third embodiment of the present disclosure.

Fig. 40A is a top view of the third exemplary structure of fig. 39 with the first exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 39.

Fig. 40B is a top view of the third exemplary structure of fig. 39 with the second exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 39.

Fig. 41 is a vertical cross-sectional view of a third exemplary structure after forming an optional dielectric etch stop layer and an optional source connection layer, in accordance with a third embodiment of the present disclosure.

Fig. 42 is a vertical cross-sectional view of the third exemplary structure after forming a memory recess through the optional source connection layer, the optional dielectric etch stop layer, and the sacrificial rail structure and partially through the layer of matrix material according to the third embodiment of the invention.

Fig. 43A is a top view of the third exemplary structure of fig. 42, with the first exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 42.

Fig. 43B is a top view of the third exemplary structure of fig. 42 with the second exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 42.

Figure 44 is a vertical cross-sectional view of a third exemplary structure after forming an isolation dielectric layer by a non-conformal deposition method according to a third embodiment of the present disclosure.

Figure 45 is a vertical cross-sectional view of a third exemplary structure after planarization of an isolation dielectric layer, according to a third embodiment of the present disclosure.

Fig. 46 is a vertical cross-sectional view of a third exemplary structure after forming a first alternating stack of first insulating layers and first spacer material layers according to a third embodiment of the present disclosure.

Fig. 47 is a vertical cross-sectional view of a third exemplary structure after forming a first memory opening through the first alternating stack, the optional source connection layer, the optional dielectric etch stop layer, and the sacrificial rail structure and partially through the layer of matrix material according to a third embodiment of the present disclosure.

Fig. 48A is a top view of the third exemplary structure of fig. 47 with the first exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 47.

Fig. 48B is a top view of the third exemplary structure of fig. 47 with the second exemplary configuration for a sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 47.

Fig. 49 is a vertical cross-sectional view of a third exemplary structure after forming a first memory opening fill portion in a first memory opening, according to a third embodiment of the present disclosure.

Fig. 50 is a vertical cross-sectional view of a third example structure after forming a second alternating stack, a second memory opening fill structure filling a second opening through the second alternating stack, a third alternating stack, and a third memory opening fill structure filling a third opening through the second alternating stack according to a third embodiment of the present disclosure.

Fig. 51 is a vertical cross-sectional view of a third exemplary structure after an interlayer memory opening is formed by removing a memory opening fill structure according to a third embodiment of the present disclosure.

Figure 52 is a vertical cross-sectional view of a third exemplary structure after forming a memory stack structure, a dielectric core, and a drain region, according to a third embodiment of the present disclosure.

Fig. 53 is a vertical cross-sectional view of a third exemplary structure after forming a backside trench, in accordance with a third embodiment of the present disclosure.

Fig. 54A is a top view of the third exemplary structure of fig. 53 with the first exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 53.

Fig. 54B is a top view of the third exemplary structure of fig. 53 with the second exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. The vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 53.

Fig. 55A and 55B are vertical cross-sectional views of a third exemplary structure after forming semiconductor spacers and dielectric spacers within backside trenches, according to a third embodiment of the present disclosure.

Figure 56 is a vertical cross-sectional view of the third exemplary structure after the backside trenches are extended through the source connection layer and the semiconductor oxide spacers are formed, in accordance with the third embodiment of the present disclosure.

Fig. 57A is a top view of the third exemplary structure of fig. 56 with the first exemplary configuration for the sacrificial rail structure being used for the third exemplary structure. Vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 56.

Fig. 57B is a top view of the third exemplary structure of fig. 56 with the second exemplary configuration for a sacrificial rail structure being used for the third exemplary structure. Vertical plane X-X' represents the plane of the vertical cross-sectional view of fig. 56.

Fig. 58 is a vertical cross-sectional view of a third exemplary structure after forming a laterally extending cavity by removing a sacrificial rail structure according to a third embodiment of the present disclosure.

Figure 59 is a vertical cross-sectional view of a third exemplary structure after removing portions of the sacrificial liner and optional dielectric etch stop layer, according to a third embodiment of the present disclosure.

Figure 60A is a vertical cross-section of a third exemplary structure employing a first process sequence including deposition of a layer of doped semiconductor material according to a third embodiment of the present disclosure.

Figure 60B is a vertical cross-sectional view of an alternative configuration for a third exemplary structure in which a drain select gate structure is formed prior to forming a layer of doped semiconductor material according to a third embodiment of the present disclosure.

Fig. 61 is a vertical cross-section of a third exemplary structure in the case of a first processing sequence after removing vertical portions of the layer of doped semiconductor material to form a source conductive layer according to a third embodiment of the present disclosure.

Fig. 62 is a vertical cross-section of a third exemplary structure in the case of a first processing sequence after forming a semiconductor oxide portion, according to a third embodiment of the present disclosure.

Fig. 63 is a vertical cross-section of a third exemplary structure in the case of a first processing sequence after forming a backside recess, according to a third embodiment of the present disclosure.

Fig. 64 is a vertical cross-section of a third exemplary structure in the case of a first processing sequence after forming a conductive layer and a continuous conductive material layer according to a third embodiment of the present disclosure.

Fig. 65 is a vertical cross-section of a third exemplary structure with a first processing sequence after removal of the continuous conductive material layer according to a third embodiment of the present disclosure.

Fig. 66 is a vertical cross-section of a third exemplary structure with a first processing sequence after forming a dielectric spacer structure according to a third embodiment of the present disclosure.

Fig. 67 is a vertical cross-section of a third exemplary structure with a second processing sequence for removing the semiconductor spacers, dielectric spacers, and semiconductor oxide spacers employed, in accordance with a third embodiment of the present disclosure.

Fig. 68 is a vertical cross-section of a third exemplary structure in the case of a second process sequence after formation of a source conductive layer by selective semiconductor deposition according to a third embodiment of the present disclosure.

Fig. 69 is a vertical cross-section of a third exemplary structure with a second processing sequence after a recess etch, according to a third embodiment of the present disclosure.

Figure 70 is a vertical cross-section of a third exemplary structure with a second processing sequence after forming a semiconductor oxide portion according to a third embodiment of the present disclosure.

Fig. 71 is a vertical cross-section of a third exemplary structure in the case of a second processing sequence after forming a backside recess, according to a third embodiment of the present disclosure.

Fig. 72 is a vertical cross-section of a third exemplary structure in the case of a second processing sequence after forming a conductive layer and a continuous conductive material layer according to a third embodiment of the present disclosure.

Fig. 73 is a vertical cross-section of a third exemplary structure with a second processing sequence after forming the dielectric separator structure according to a third embodiment of the present disclosure.

Fig. 74 is a vertical cross-sectional view of an alternative embodiment of the third exemplary structure after forming the dielectric spacer structure according to the third embodiment of the present disclosure.

Fig. 75A is a horizontal cross-section of a third example structure in a first configuration along the horizontal plane a-a' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 75B is a horizontal cross-section of a third exemplary structure in a first configuration along the horizontal plane B-B' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 75C is a horizontal cross-section of a third example structure in a first configuration along the horizontal plane C-C of fig. 74, according to a third embodiment of the present disclosure.

Fig. 75D is a horizontal cross-section of a third exemplary structure in a first configuration along the horizontal plane D-D' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 75E is a horizontal cross-section of a third example structure in a first configuration along the horizontal plane E-E' of fig. 74, in accordance with a third embodiment of the present disclosure.

Fig. 76A is a horizontal cross-section of a third example structure in a second configuration along the horizontal plane a-a' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 76B is a horizontal cross-section of a third example structure in a second configuration along the horizontal plane B-B' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 76C is a horizontal cross-section of a third example structure in a second configuration along the horizontal plane C-C of fig. 74, according to a third embodiment of the present disclosure.

Fig. 76D is a horizontal cross-section of a third exemplary structure in a second configuration along the horizontal plane D-D' of fig. 74, according to a third embodiment of the present disclosure.

Fig. 76E is a horizontal cross-section of a third example structure in a second configuration along the horizontal plane E-E' of fig. 74, in accordance with a third embodiment of the present disclosure.

Detailed Description

As discussed above, the present disclosure relates to three-dimensional memory structures, such as vertical NAND strings and other three-dimensional devices, and methods of fabricating the same, various aspects of which are described below. Embodiments of the present disclosure may be employed to form various structures including multilevel memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional monolithic memory array devices including a plurality of NAND memory strings. The figures are not drawn to scale. Unless explicitly described or otherwise clearly indicated to the contrary by the absence of a duplication of an element, multiple instances of an element may be duplicated where a single instance of the original is shown. Ordinal numbers such as "first," "second," and "third" are used only to identify similar elements, and different ordinal numbers may be employed in the specification and claims of the present disclosure. As used herein, a first element that is "on" a second element may be located on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly on" a second element if there is physical contact between a surface of the first element and a surface of the second element.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Further, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers in the substrate, and/or may have one or more layers on, above, and/or below the substrate.

As used herein, "field effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows with a current density modulated by an external electric field. As used herein, "active region" refers to a source region of a field effect transistor or a drain region of a field effect transistor. "top active region" refers to an active region of a field effect transistor that is located above another active region of the field effect transistor. "bottom active region" refers to an active region of a field effect transistor that is located below another active region of the field effect transistor. A monolithic three dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. Conversely, a two-dimensional array may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithically stacked memories have been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. patent No. 5,915,167, entitled "three-dimensional structure memory. The substrate may be thinned or removed from the memory levels prior to bonding, but such memories are not true monolithic three dimensional memory arrays because the memory levels are initially formed on separate substrates. The various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated employing the various embodiments described herein.

Referring to fig. 1, a first exemplary structure according to a first embodiment of the present disclosure is shown that may be used, for example, to fabricate a device structure containing a vertical NAND memory device. The first exemplary structure includes a substrate, which may be a semiconductor substrate (e.g., a semiconductor substrate such as a single crystal silicon wafer). The substrate may include a substrate semiconductor layer 10. The substrate semiconductor layer 10 is a layer of semiconductor material and may comprise at least one elemental semiconductor material (e.g., silicon, such as monocrystalline silicon), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

As used herein, "semiconductor material" is meant to have a composition of from 1.0 x 10^-6S/cm to 1.0X 10⁵A material having an electrical conductivity in the range of S/cm and which, when suitably doped with an electrical dopant, is capable of yielding a material having a conductivity in the range of from 1.0S/cm to 1.0X 10⁵A doping material of conductivity in the range of S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure (band structure), or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10⁵S/cm of conductivity. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity of less than 1.0 x 10^-6S/cm of material. All conductivity measurements were performed under standard conditions. The substrate semiconductor layer 10 may include at least one doped well (not expressly shown) having a substantially uniform dopant concentration therein.

The first exemplary structure may have multiple regions for establishing different types of devices. Such regions may include, for example, memory array region 100, contact region 300, and peripheral device region 200. In one embodiment, the substrate semiconductor layer 10 may include at least one doped well in the memory array region 100. As used throughout this document, "doped well" refers to a portion of a doped semiconductor material having the same conductivity type (which may be p-type or n-type) and substantially the same level of dopant concentration. The doped well may be the same as the substrate semiconductor layer 10 or may be part of the substrate semiconductor layer 10. The conductivity type of the doped well, referred to herein as the first conductivity type, may be p-type or n-type. The dopant concentration level of the doped well is referred to herein as a first dopant concentration level. In one embodiment, the first dopant concentration level may be from 1.0 × 10¹⁵/cm³To 1.0X 10¹⁸/cm³Although lesser and greater dopant concentration levels may also be employed. As used herein, a dopant concentration level refers to the average dopant concentration of a given region.

The peripheral device 210 may be formed in or on a portion of the substrate semiconductor layer 10 located within the peripheral device region 200. The peripheral devices may include various devices used to operate the memory device to be formed in the memory array region 100, and may include, for example, driver circuits for various components of the memory device. Peripheral devices 210 may include, for example, field effect transistors and/or passive components such as resistors, capacitors, inductors, diodes, and the like.

A lower source insulating layer 12 may be formed over the substrate semiconductor layer 10. The lower source insulating layer 12 provides electrical isolation of the subsequently formed continuous source structure from the substrate semiconductor layer 10. The lower source insulating layer 12 may comprise, for example, silicon oxide and/or a dielectric metal oxide (such as HfO)₂、ZrO₂、LaO₂Etc.). The thickness of the lower source insulating layer 12 may be in the range from 3nm to 30nm, although lesser and greater thicknesses may also be employed.

A sacrificial matrix layer 14 may be formed over the lower source insulating layer 14. The sacrificial matrix layer 14 comprises a material that can be removed selectively to the material of the lower source insulating layer 12 and to the subsequently formed upper source insulating layer and insulating spacers. For example, the sacrificial matrix layer 14 may comprise a semiconductor material such as polysilicon or a silicon germanium alloy, or may comprise amorphous carbon, an organic polymer, or an inorganic polymer. The sacrificial matrix layer 14 may be deposited by chemical vapor deposition, physical vapor deposition, or spin coating. The thickness of the sacrificial substrate layer 14 may be in the range of 10nm to 60nm, although lesser and greater thicknesses may also be employed.

An optional upper source insulating layer 16 may be formed over the sacrificial matrix layer 14. The upper source insulating layer 16 provides electrical isolation of the continuous source structure to be subsequently formed from the conductive layer to be subsequently formed. The upper source insulating layer 16 may comprise, for example, silicon oxide and/or a dielectric metal oxide (such as HfO)₂、ZrO₂、LaO₂Etc.). The thickness of the upper source insulating layer 16 may range from 3nm to 30nm, although lesser and greater thicknesses may also be employed. The upper source insulating layer 16 is preferably included if the subsequent alternating stack to be formed over the upper source insulating layer 16 begins with a layer of sacrificial material. The upper source insulating layer 16 is optional if the subsequent alternating stack to be formed over the upper source insulating layer 16 begins with an insulating layer, and the first insulating material of the alternating stack may serve (i.e., may be identified as) the upper source insulating layer 16. Although the present disclosure is described with embodiments in which the upper source insulating layer 16 is different from the bottommost insulating layer of the alternate stack to be formed subsequently, embodiments in which the upper source insulating layer 16 is the same as the bottommost insulating layer are explicitly contemplated.

Referring to fig. 2, a photoresist layer (not shown) may be applied over the upper source insulating layer 16 and may be lithographically patterned to form an array of openings therein. The pattern of the array of openings in the photoresist layer may be transferred through the upper source insulating layer 16 and the sacrificial matrix layer 14 by an anisotropic etch, such as a reactive ion etch. The lower source insulating layer 12 may be employed as an etch stop layer. If desired, the etching may continue through the lower source insulating layer 12 to or into the top surface of the substrate semiconductor layer 10. An array of via cavities 19 may be formed in the sacrificial substrate layer 14. The cavity 19 may extend to the lower source insulating layer 12, through the lower source insulating layer 12 to the top surface of the substrate semiconductor layer 10 or into the substrate semiconductor layer 10. The array of via cavities 19 may have a periodic pattern. In one embodiment, each via cavity 19 may have substantially vertical sidewalls and/or may have a substantially circular horizontal cross-sectional shape. In one embodiment, each through-hole cavity 19 may have a substantially cylindrical shape. In one embodiment, the array of via cavities 19 may be a two-dimensional periodic array of instances of a cell structure (unit cell structure). The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 3, a dielectric fill material is deposited in the array of via cavities 19, for example by chemical vapor deposition or spin coating. The dielectric fill material may include, for example, silicon oxide (such as doped silicate glass or undoped silicate glass), dielectric metal oxide, silicon nitride, organosilicate glass, or a combination thereof. For example, the dielectric fill material may include silicon oxide. Excess portions of the deposited dielectric fill material may be removed from above the level including the top surface of the upper source insulating layer 16 by a planarization process, which may employ a recess etch and/or chemical mechanical planarization.

The remaining portion of the dielectric fill material filling the via cavity 19 constitutes an array of dielectric pillars 20. The array of dielectric pillars 20 may have a periodic pattern. In one embodiment, each dielectric pillar 20 may have substantially vertical sidewalls and/or may have a substantially circular horizontal cross-sectional shape. In one embodiment, each media column 20 may have a substantially cylindrical shape. In one embodiment, the array of dielectric pillars 20 may be a two-dimensional periodic array of instances of a cell structure. The top surfaces of the dielectric pillars 20 and the top surface of the upper source insulating layer 16 may be coplanar, i.e., may lie within the same Euclidean plane.

Fig. 4A-4C illustrate various exemplary patterns that may be used for the array of dielectric pillars 20. In particular, fig. 4A-4C illustrate arrays of dielectric pillars 20 for first, second, and third exemplary configurations, respectively. The pattern shown in fig. 4A is referred to herein as a zigzag pattern, the pattern shown in fig. 4B is referred to herein as a grid pattern, and the pattern shown in fig. 4C is referred to herein as a diagonal pattern. The zigzag pattern may include zigzag rows (i.e., zigzag rows of serrations) of dielectric pillars 20. The rows may extend parallel to the word line direction or parallel to the bit line direction. The grid pattern may include a plurality of linear rows and columns of pillars 20 that form rectangular or square cells of pillars 20. The diagonal pattern may include a plurality of parallel diagonal rows of pillars 20 extending at an angle of 30 to 60 degrees (such as about 45 degrees) relative to the bit line and word line directions. These rows form a parallelogram-shaped cell lacking right angles. The periodicity of each pattern may be selected to be commensurate with the pattern of memory openings to be subsequently formed. In one embodiment, the periodicity of each pattern of dielectric pillars 20 may be the same as or an integer multiple of the periodicity of memory openings to be subsequently formed along the same direction.

Referring to fig. 5, an alternating stack of first material layers (which may be insulating layers 32) and second material layers (which are referred to as spacer material layers) is formed over the upper source insulating layer 16. As used herein, "layer of material" refers to a layer that includes material throughout its entirety. In one embodiment, the alternating stack may include insulating layers 32 and a layer of spacer material between each vertically adjacent pair of insulating layers 32. As used herein, "spacer material layer" refers to a material layer that is located between two other material layers (i.e., between an upper material layer and a lower material layer). The layer of spacer material may be formed as a conductive layer or may be replaced with a conductive layer in a subsequent processing step.

As used herein, the alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of a first element that is not an alternating plurality of end elements is adjoined on both sides by two instances of a second element, and each instance of a second element that is not an alternating plurality of end elements is adjoined on both sides by two instances of a first element. The first elements may have the same thickness therein, or may have different thicknesses. The second elements may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or begin with an instance of a second material layer and may end with an instance of a first material layer or end with an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within alternating pluralities.

Each first material layer includes a first material and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32 and each second material layer (i.e., spacer material layer) may be a sacrificial material layer 42. In this case, the stack may include alternating ones of the insulating layers 32 and the sacrificial material layers 42, and the in-process (in-process) stack including the insulating layers 32 and the sacrificial material layers 42 is configured. As used herein, an "alternating stack" of first elements and second elements is a structure in which instances of the first elements and instances of the second elements alternate along the same direction (such as a vertical direction). As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein. Thus, the layers (32,42) may be alternately stacked during formation over the layer stack of the lower source insulator layer 12, the sacrificial matrix layer 14, and the upper source insulator layer 16.

In one embodiment, the alternating stack (32,42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material different from the material of the insulating layer 32. The first material of the insulating-material layer 32 may be at least one insulating material. As such, each insulating layer 32 may be a layer of insulating material. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

The second material of the sacrificial material layer 42 is a sacrificial material that can be removed selectively to the first material of the insulating layer 32. As used herein, the removal of a first material is "selective" for a second material if the removal process removes the first material at a rate that is at least twice the rate at which the second material is removed. The ratio of the rate of removal of the first material to the rate of removal of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may serve, for example, as a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polysilicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer comprising silicon nitride or a semiconductor material comprising at least one of silicon and germanium.

In an illustrative example, the insulating layer 32 may comprise silicon oxide and the sacrificial material layer may comprise silicon nitride. As used herein, silicon nitride or silicon nitride material refers to a dielectric compound of at least one group IV element and at least one non-metallic element such that silicon comprises greater than 50 atomic percent of the at least one group IV element and nitrogen comprises greater than 50 atomic percent of the non-metallic element. Thus, silicon nitride includes Si₃N₄And silicon oxynitride in which the atomic concentration of nitrogen is greater than the atomic concentration of oxygen. As used herein, silicon oxide or silicon oxide materialBy material is meant a dielectric compound of at least one group IV element and at least one non-metallic element such that silicon comprises more than 50 atomic percent of the at least one group IV element and oxygen comprises more than 50 atomic percent of the non-metallic element. Silicon oxides include silicon dioxide, oxides of silicon-germanium alloys in which the atomic concentration of silicon is greater than the atomic concentration of germanium, silicon oxynitride in which the atomic concentration of oxygen is greater than the atomic concentration of nitrogen, and doped derivatives thereof (such as phosphosilicate glass, fluorosilicate glass, borophosphosilicate glass, organosilicate glass, and the like). For example, the first material of the insulating layer 32 may be deposited by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The thickness of the insulating layer 32 and the sacrificial material layer 42 may range from 20nm to 50nm, although lesser and greater thicknesses may be employed for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pair of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 may range from 2 to 1024, and typically from 8 to 256, although greater numbers of repetitions may also be employed. The top and bottom gate electrodes in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32,42) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

Optionally, an insulating cap 70 may be formed over the alternating stack (32, 42). The insulating cap layer 70 comprises a dielectric material that is different from the material of the sacrificial material layer 42. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that may be used for the insulating layer 32 as described above. The insulating cap layer 70 may have a greater thickness than each of the insulating layers 32. The insulating cap 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap 70 may be a silicon oxide layer.

Referring to fig. 6, a stack of photolithographic material (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the alternating stack (32,42) and may be photolithographically patterned to form an opening therein. The pattern in the stack of photolithographic material can be transferred through the optional insulating cap layer 70, through the entire alternating stack (32,42), and through the upper source insulating layer 16, the sacrificial matrix layer 14, and the lower source insulating layer 12 by at least one anisotropic etch using the patterned stack of photolithographic material as an etch mask. Portions of the insulating cap layer 70 underlying the openings in the patterned stack of photolithographic material, the alternating stack (32,42), the upper source insulating layer 16, the sacrificial matrix layer 14, and the lower source insulating layer 12 are etched to form the memory openings 49. In other words, the transfer of the pattern in the patterned stack of photolithographic material passes through the optional insulating cap layer 70, through the entire alternating stack (32,42), and through the upper source insulating layer 16, the sacrificial matrix layer 14, and the lower source insulating layer 12, and optionally partially through the substrate semiconductor layer 10 to form the memory opening 49. The chemistry of the anisotropic etching process used to etch through the material of the alternating stack (32,42) may be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch may be, for example, a series of reactive ion etches. Alternatively, the lower source insulating layer 12 may be used as an etch stop layer. The sidewalls of the reservoir opening 49 may be substantially vertical or may be tapered. The patterned stack of photolithographic material may then be removed, for example, by ashing.

Fig. 7A-7C illustrate first, second, and third exemplary configurations of the sacrificial material layer 14, the array of dielectric pillars 20, and the array of memory openings 49, respectively, in cross-sectional views along a horizontal plane through the sacrificial material layer 14. In one embodiment, the array of dielectric pillars 20 and the array of memory openings 49 together comprise a two-dimensional periodic array of multiple instances of the cell structure "U". The cell structure U may include a plurality of memory openings 49 (such as the four memory openings shown in fig. 7A-7C) and at least one dielectric pillar 20 (which may be two dielectric pillars 20 consisting of one integral pillar inside the cell and one quarter of the four pillars at the apex of the cell as shown in fig. 7A or a single dielectric pillar 20 consisting of one quarter of the four pillars at the apex of the cell as shown in fig. 7B and 7C). In one embodiment, the array of memory openings 49 may include a hexagonal array of memory openings 49. In one embodiment, the ratio of the total number of the plurality of memory openings 49 in the unit cell structure U to the total number of the at least one dielectric pillar 20 in the unit cell structure U may be in a range from 2 to 4. For example, as shown in fig. 7A, the ratio may be 2, or as shown in fig. 7B, the ratio may be 4, or as shown in fig. 7C, the ratio may be 3.

A memory stack structure may be formed in each memory opening 49 in a subsequent processing step. Fig. 8A-8D illustrate a process of forming a memory stack structure in the memory opening 49. Although specific embodiments for forming memory stack structures are shown herein, embodiments in which different types of memory stack structures are formed are explicitly contemplated herein.

Referring to fig. 8A, a memory opening 49 is shown. The memory opening 49 extends through the insulating cap layer 70, the alternating stack (32,42) and the layer stack of the upper source insulating layer 16, the sacrificial matrix layer 14 and the lower source insulating layer 12 and optionally into an upper portion of the substrate semiconductor layer 10. The recessed depth of the bottom surface of each memory opening 49 relative to the top surface of the substrate semiconductor layer 10 may be in the range from 0nm to 30nm, although greater recessed depths may also be employed. Alternatively, the sacrificial material layer 42 may be partially laterally recessed to form a lateral recess (not shown), for example by isotropic etching.

Referring to fig. 8B, a set of layers for forming a memory film is deposited within each memory opening. The set of layers may include, for example, an optional outer blocking dielectric layer 502L, an optional inner blocking dielectric layer 503L, a charge storage element layer 504L, and a tunneling dielectric layer 506L.

In particular, each of the outer and inner blocking dielectric layers (502L,503L) may comprise at least one dielectric material, which may be silicon oxide, a dielectric metal oxideOr a combination thereof. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metal element (such as nitrogen). In one embodiment, at least one of the outer and inner blocking dielectric layers (502L,503L) may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). Non-limiting examples of dielectric metal oxides include aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Lanthanum oxide (LaO)₂) Yttrium oxide (Y)₂O₃) Tantalum oxide (Ta)₂O₅) Silicates thereof, nitrogen-doped compounds thereof, and stacks thereof. The dielectric metal oxide can be deposited, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. Additionally or alternatively, at least one of the outer and inner blocking dielectric layers (502L,503L) may comprise silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer (502L,503L) may comprise a stack of aluminum oxide and silicon oxide. Each of the outer and inner blocking dielectric layers (502L,503L) may be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the blocking dielectric layer (502L,503L) may be in the range from 1nm to 30nm, although lesser and greater thicknesses may also be employed.

The charge storage element layer 504L may comprise a single layer of charge trapping material (which includes a dielectric charge trapping material), which may be, for example, silicon nitride. Alternatively, the charge storage element layer 504L may comprise a conductive material, such as doped polysilicon or a metallic material, patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within the lateral recesses. In one embodiment, the charge storage element layer 504L comprises a silicon nitride layer.

The charge storage element layer 504L may be formed as a single layer of memory material of uniform composition, or may include a stack of multiple layers of memory material. If employed, the plurality of memory material layers may include a plurality of spaced-apart floating gate material layers comprising a conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and/or a semiconductor material (e.g., a polycrystalline or amorphous semiconductor material or at least one compound semiconductor material including at least one elemental semiconductor element). Alternatively or additionally, the charge storage element layer 504L may comprise an insulating charge trapping material, such as one or more segments of silicon nitride. Alternatively, the charge storage element layer 504L may include conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage element layer 504L may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage element layer 504L may range from 2nm to 20nm, although lesser and greater thicknesses may also be employed.

The tunneling dielectric layer 506L comprises a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. Depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling may be performed by hot carrier injection or by Fowler-Nordheim (Fowler-Nordheim) tunneling induced charge transfer. Tunneling dielectric layer 506L may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 506L may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 506L may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 506L may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be employed.

In an illustrative example, optional outer blocking dielectric layer 502L may comprise a dielectric metal oxide (such as aluminum oxide) and inner blocking dielectric layer 503L may comprise a dielectric oxide of a semiconductor material (such as silicon oxide). The charge storage element layer 504L may comprise any type of charge storage material and may be formed as a continuous layer of material comprising a charge trapping material, or may be formed as a plurality of vertically isolated charge trapping material portions at each level of the sacrificial material layer 42, deposited in the recessed regions, for example by a combination of a conformal deposition process and anisotropic etching. The tunneling dielectric layer 506L includes a material that may be used as a tunneling dielectric material, which may be, for example, a silicon oxide or ONO stack.

A semiconductor channel layer 60L may be deposited on the tunneling dielectric layer 506L. The semiconductor channel layer 60L includes semiconductor materials such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polysilicon. The semiconductor channel layer 60L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the semiconductor channel layer 60L may be in the range from 2nm to 10nm, although lesser and greater thicknesses may also be employed. A cavity 49' is formed in the volume of each memory opening 49 not filled by the deposited material layer (502L,503L,504L,506L, 60L).

Referring to fig. 8C, a dielectric material may be deposited to fill the cavity 49' within each memory opening 49. The dielectric material may be deposited by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD) or by a self-planarizing deposition process such as spin-on coating. Exemplary dielectric materials that may be used to fill the cavity 49' include silicon oxide (undoped silicate glass or doped silicate glass) and organosilicate glass.

A planarization process may be performed to remove excess portions of the dielectric material, semiconductor channel layer 60L, tunneling dielectric layer 506L, charge storage element layer 504L, and blocking dielectric layers (502L,503L) from above a horizontal plane including the top surface of the insulating cap layer 70. A recess etch and/or chemical mechanical planarization process may be employed. Each remaining portion of outer blocking dielectric layer 502L in the memory opening constitutes an outer blocking dielectric 502. Each remaining portion of the inner blocking dielectric layer 503L in the memory opening constitutes an inner blocking dielectric 503. Each remaining portion of the charge storage element layer 504L in the memory opening includes a charge storage element 504 (which may be implemented as a single continuous layer of memory material (charge storage layer) or as discrete portions of charge storage material at each level of the sacrificial material layer 42). In one embodiment, portions of a single contiguous layer of memory material comprising a charge trapping dielectric material (such as silicon nitride) located at levels of the sacrificial material layer 42 constitute charge storage elements, while portions of the same single contiguous layer of memory material located at each level of the insulating layer 32 provide electrical isolation between vertically adjacent charge storage elements. Each remaining portion of the tunneling dielectric layer 506L in the memory opening constitutes a tunneling dielectric 506. Each remaining portion of the semiconductor channel layer 60L in the memory opening constitutes a semiconductor channel 60, the semiconductor channel 60 including a semiconductor channel extending in a vertical direction. Each remaining portion of the dielectric material constitutes a dielectric core 62. Each contiguous set of optional outer blocking dielectric 502, inner blocking dielectric 503, set of charge storage elements 504, and tunneling dielectric 506 collectively comprise memory film 50.

Referring to fig. 8D, each dielectric core 62 may be vertically recessed, for example, by a concave etch relative to the memory film 50. The recess etch of the dielectric core 62 may be selective to the semiconductor channel 60 or may be non-selective to the semiconductor channel 60. The drain region 63 may be formed by depositing a doped semiconductor material in each recessed region above the dielectric core 62. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from over the top surface of the insulating cap layer 70 to form the drain region 63, for example, by Chemical Mechanical Planarization (CMP) or a recess etch. Each set of the memory film 50 and the semiconductor channel 60 located within the same memory opening constitutes a memory stack structure 55.

Fig. 9 illustrates a first exemplary structure incorporating multiple instances of the exemplary memory stack structure 55 of fig. 8D. Each memory stack structure 55 includes, from the outside to the inside, at least one optional blocking dielectric (502, 503) (which may include an outer blocking dielectric 502 and an inner blocking dielectric 503), a charge storage element 504 (embodied as vertically spaced apart portions of a layer of memory material at the level of each sacrificial material layer 42), which may be a memory element, a tunneling dielectric 506, and a semiconductor channel 60. Although the present disclosure is described with the illustrated configuration of a memory stack structure, the present disclosure may be applied to alternative memory stack structures that include a polycrystalline semiconductor channel.

Referring to fig. 10, an optional first contact level dielectric layer 71 may be formed on the substrate semiconductor layer 10. As an alternative structure, the first contact-level dielectric layer 71 may be formed or not formed. In the case of forming the first contact level dielectric layer 71, the first contact level dielectric layer 71 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, porous or non-porous organosilicate glass (OSG), or a combination thereof. If an organosilicate glass is employed, the organosilicate glass may or may not be doped with nitrogen. A first contact level dielectric layer 71 may be formed over a horizontal plane including the top surface of the insulating cap layer 70 and the top surface of the drain region 63. The first contact level dielectric layer 71 may be deposited by chemical vapor deposition, Atomic Layer Deposition (ALD), spin coating, or a combination thereof. The thickness of the first contact level dielectric layer 71 may be in the range from 10nm to 300nm, although lesser and greater thicknesses may also be employed.

In one embodiment, the first contact level dielectric layer 71 may be formed as a dielectric material layer having a uniform thickness throughout. The first contact-level dielectric layer 71 may be formed as a single dielectric material layer, or may be formed as a stack of multiple dielectric material layers. Alternatively, the formation of the first contact level dielectric layer 71 may be combined with the formation of at least one line level dielectric layer (not shown). While the present disclosure is described with embodiments in which the first contact-level dielectric layer 71 is a separate structure from the optional second contact-level dielectric layer or at least one line-level dielectric layer to be subsequently deposited, embodiments are expressly contemplated herein in which the first contact-level dielectric layer 71 and the at least one line-level dielectric layer are formed in the same processing step and/or as the same material layer.

In one embodiment, the first contact level dielectric layer 71, the insulating cap layer 70, the alternating stack (32,42) and the layer stack of the upper source insulating layer 16, the sacrificial matrix layer 14 and the lower source insulating layer 12 may be removed from the peripheral device region 200, for example, by a masked etching process. In addition, by patterning a portion of the alternating stack (32,42), a stepped cavity may be formed within the contact region 300. As used herein, "stepped cavity" refers to a cavity having a stepped surface. As used herein, "stepped surface" refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts a first vertical surface extending upward from a first edge of the horizontal surface and abuts a second vertical surface extending downward from a second edge of the horizontal surface. "step" refers to a vertical displacement by the height of a set of adjacent surfaces.

The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity is gradually changed with a vertical distance from the top surface of the substrate semiconductor layer 10. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etch process that vertically increases the cavity depth by one or more levels and a second type of etch process that laterally expands the area to be vertically etched in a subsequent first type of etch process. As used herein, a "level" comprising an alternating stacked structure is defined as the relative position of a pair of first and second material layers within the structure. After all the stepped surfaces are formed, the mask material layer used to form the stepped surfaces may be removed, for example, by ashing. Multiple photoresist layers and/or multiple etching processes may be employed to form the stepped surface.

A dielectric material, such as silicon oxide, is deposited in the stepped cavity and over the peripheral 210 in the peripheral region 200. Excess portions of the deposited dielectric material may be removed from over the top surface of the first contact-level dielectric layer 71, for example, by Chemical Mechanical Planarization (CMP). The remaining portion of the deposited dielectric material constitutes a retro-stepped dielectric material portion 65, wherein the remaining portion of the deposited dielectric material fills the stepped cavity in the contact region 300 and covers the substrate semiconductor layer 10 in the peripheral device region 200. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with vertical distance from the top surface of the substrate on which the element resides. If silicon oxide is used as the dielectric material, the silicon oxide of the retro-stepped dielectric material portion 65 may be doped with dopants such as B, P and/or F or may be undoped with dopants such as B, P and/or F. A top surface of the backward stepped dielectric material portion 65 may be coplanar with a top surface of the first contact level dielectric layer 71.

The region above the peripheral device 210 and the region above the stepped cavity may be filled simultaneously with the same dielectric material, or may be filled with the same dielectric material or different dielectric materials in different processing steps. The cavity above peripheral device 210 may be filled with a dielectric material before, simultaneously with, or after the cavity above the stepped surface of contact region 300 is filled with a dielectric material. Although the present disclosure is described with an embodiment in which the cavities in peripheral device region 200 and the stepped cavities in contact region 300 are filled simultaneously, embodiments in which the cavities in peripheral device region 200 and the stepped cavities in contact region 300 are filled in different processing steps are expressly contemplated herein.

Referring to fig. 11, through-stack dielectric pillars 7P may optionally be formed through the retro-stepped dielectric material portions 65 and/or through the first contact level dielectric layers 71 and/or through the alternating stacks (32, 42). In one embodiment, the through-stack dielectric pillars 7P may be formed in a contact region 300 located adjacent to the memory array region 100. For example, the through stack dielectric pillars 7P may be formed by forming openings that extend through the retro-stepped dielectric material portions 65 and/or through the alternating stack (32,42) and extend at least to the top surface of the substrate semiconductor layer 10, and by filling the openings with a dielectric material that is resistant to the etch chemistry to be used to remove the sacrificial material layer 42.

In one embodiment, the through-stack dielectric pillars 7P may comprise silicon oxide and/or a dielectric metal oxide such as aluminum oxide. In one embodiment, a portion of the dielectric material deposited over the first contact level dielectric layer 71 concurrently with the deposition of the through-stack dielectric pillars 7P may be present over the first contact level dielectric layer 71 as a second insulating capping layer 73. Each of the through stack dielectric pillars 7P and the second insulating cap 73 is an optional structure. As such, the second insulating cap 73 may or may not be present over the insulating cap 70 and the backward stepped dielectric material portion 65. The first contact level dielectric layer 71 and the second insulating cap layer 73 are collectively referred to herein as at least one contact level dielectric layer (71, 73). In one embodiment, the at least one contact level dielectric layer (71,73) may include both the first and second contact level dielectric layers (71,73), and optionally any additional via level dielectric layers that may be subsequently formed. In another embodiment, the at least one contact level dielectric layer (71,73) may comprise only the first contact level dielectric layer 71 or the second insulating cap layer 73, and optionally any additional via level dielectric layers that may be subsequently formed. Alternatively, the formation of the first and second contact level dielectric layers (71,73) may be omitted and at least one via level dielectric layer may be formed subsequently, i.e. after the formation of the first source contact via structure.

The second insulating cap layer 73 and the through-stack dielectric pillars 7P may be formed as a single continuous structure of a unitary structure, i.e., without any material interface therebetween. In another embodiment, a portion of the dielectric material deposited over the first contact level dielectric layer 71 concurrently with the deposition of the through-stack dielectric pillars 7P may be removed, for example by chemical mechanical planarization or a recess etch. In this case, the second insulating cap layer 73 is not present, and the top surface of the first contact-level dielectric layer 71 may be physically exposed.

Referring to fig. 12A and 12B, a photoresist layer (not shown) may be applied over at least one contact level dielectric layer (71,73) and may be lithographically patterned to form openings in regions between memory blocks. In one embodiment, each opening in the photoresist layer may have a rectangular shape such that a pair of sidewalls of the opening extend laterally along the first horizontal direction.

A backside trench 79 may be formed between each adjacent pair of clusters of memory stack structures 55 by transferring a pattern of openings in a photoresist layer through at least one contact level dielectric layer (71,73), stepped dielectric material portions 65, alternating stacks (32,42), and optional upper source insulator layer 16 (if present). The sacrificial substrate layer 14 may be physically exposed at the bottom of each backside trench 79. The clusters of memory stack structures 55 may be laterally spaced apart by backside trenches 79. Each cluster of memory stack structure 55 in combination with portions of the alternating stack (32,42) surrounding the cluster constitute a memory block. The memory block may be laterally bounded by a pair of backside trenches 79. Fig. 12A is a vertical cross-sectional view along the vertical plane X-X' of the zigzag in fig. 12B. Fig. 12B is a perspective top view of the underlying element shown in dashed lines.

Fig. 13A shows a horizontal cross-sectional view of the dashed rectangular region "M" of the first exemplary structure of fig. 12B along the horizontal plane shown in fig. 12A that includes the sacrificial substrate layer 14. Fig. 13A corresponds to a first (i.e., zigzag) configuration of the array of dielectric pillars 20 and the array of memory stack structures 55. Fig. 13B and 13C show corresponding horizontal cross-sectional views of the second and third configurations. The direction of the zigzag rows of pillars 20 in fig. 12B and 13A extends in the bit line direction perpendicular to the elongated direction of the trench 79 and the word line direction. However, in another embodiment, the direction of the zigzag rows of pillars 20 in fig. 12B and 13A may be rotated by 90 degrees to extend perpendicular to the bit line direction and parallel to the elongated direction of the trench 79 and the word line direction.

The array of dielectric pillars 20 and the array of memory stack structures 55 together comprise a two-dimensional periodic array of multiple instances of cell structure U1, which cell structure U1 includes multiple memory stack structures 55 and at least one dielectric pillar 20. The array of memory array stack structures 55 may include a hexagonal array of memory stack structures 55. A ratio of a total number of the plurality of memory stack structures 55 in cell structure U1 to a total number of the at least one dielectric pillar 20 in cell structure U1 may be in a range from 2 to 4.

Referring to fig. 14, a backside recess 43 may be formed by removing the sacrificial material layer 42 selective to the insulating layer 32 and the sacrificial matrix layer 14. Specifically, an etchant that etches the second material of the sacrificial material layer 42 selective to the first material of the insulating layer 32 and the sacrificial matrix layer 14 may be introduced into the backside trench 79, for example, using an etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective to: the first material of the insulating layer 32, the material of the through-stack dielectric pillars 7P, the material of the backward stepped dielectric material portion 65, the semiconductor material of the substrate semiconductor layer 10, the material of the sacrificial matrix layer 14, and the material of the outermost layer (such as the outer blocking dielectric 502) of the memory stack structure 55. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, the sacrificial matrix layer 14 may comprise polysilicon or amorphous silicon, and the material of the insulating layer 32, the through-stack dielectric pillars 7P, and the retro-stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

Each dorsal concavity 43 may be a laterally extending cavity having a lateral dimension greater than the vertical extension of the cavity. In other words, the lateral dimension of each dorsal concavity 43 may be greater than the height of the dorsal concavity 43. A plurality of backside recesses 43 may be formed in the volume from which the second material of the sacrificial material layer 42, the material of the silicon oxide layer 501, and the material of the silicon nitride layer 502 are removed. The memory openings in which the memory stack structures (50,60) are formed are referred to herein as front-side recesses or front-side cavities opposite the back-side recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having multiple levels of devices arranged above a substrate (e.g., above a substrate semiconductor layer 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate semiconductor layer 10. The backside recess 43 may be vertically defined by a top surface of the lower insulating layer 32 and a bottom surface of the upper insulating layer 32. In one embodiment, each of the backside concavities 43 may be of uniform height throughout. In one embodiment, an optional backside blocking dielectric, such as an aluminum oxide dielectric, may be deposited into the backside recesses 43 in contact with the exposed portions of the memory film 50 in the backside recesses 43. In this embodiment, one or both of the front-side blocking dielectric layers 502 and/or 503 may be omitted.

Referring to fig. 15, at least one metallic material may be deposited in the backside recess to form a conductive layer 46. Optionally, a backside blocking dielectric layer (not shown) may be formed on the physically exposed surfaces of the memory stack structure 55 and the insulating layer 32 prior to the deposition of the at least one metal material. In one embodiment, the at least one metallic material may comprise a layer of a conductive metallic compound (such as a layer of a conductive metal nitride comprising a conductive metal nitride such as TiN, TaN or WN, or a layer of a conductive metal carbide comprising a conductive metal carbide such as TiC, TaC or WC). The conductive metal compound layer may include a metal material serving as a barrier material layer (i.e., a material layer that serves as a barrier to diffusion of impurity atoms or gases), and/or an adhesion promoter layer (i.e., a material layer that promotes adhesion of subsequent layers to the insulating layer 32 (in the case where a backside barrier dielectric layer is not employed) or to a backside barrier dielectric layer (in the case where a backside barrier dielectric layer is employed)). The conductive metallic compound layer may be deposited by a conformal deposition process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The thickness of the conductive metal compound layer may range from 1nm to 6nm, although lesser and greater thicknesses may also be employed.

In one embodiment, the at least one metallic material may further comprise a metallic layer. The metal layer may comprise an elemental metal or intermetallic alloy that may be deposited in the remaining portions of the backside recesses 43, over the sidewalls of the backside trenches 79, and over the top surface of the at least one contact level dielectric layer (71, 73). The metal layer may be deposited directly on the surface of the conductive metallic compound layer as a continuous metal layer. The metal layer may be deposited by a conformal deposition method such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The remaining portion of the backside recess 43 may be filled with a metal layer. The thickness of the deposited metal as measured on the sidewalls of the backside trenches 79 may be greater than half the maximum height of the remaining portions of the backside recesses 43, such that the entire volume of each backside recess 43 is filled with a combination of an optional backside blocking dielectric layer, a metallic compound layer, and a metal layer.

The metal layer may include a metal such as W, Co, Al, Cu, Ru, Au, Pt, or a combination thereof. The metal layer may be deposited by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process using a metal-containing precursor gas. In one embodiment, the metal-containing precursor gas may be free of fluorine, i.e., contain no fluorine. Chemical vapor deposition or atomic layer deposition of metals employs metal precursors that are easily vaporized to leave high purity metal on the surface without causing surface damage. In one embodiment, organometallic compounds having relatively high vapor pressures and good thermal stability can be used as metal precursor gases to deposit metals without the need for hydrogen.

The vertically extending portion of the deposited metal material(s) may cover the entire sidewalls of the backside trench 79. When deposited, the vertically extending portion of the deposited metallic material(s) may contiguously abut the metallic portions located within each vertically adjacent pair of backside recesses 43, and may abut to the horizontal portion of the metallic layer overlying the at least one contact level dielectric layer (71, 73).

An etch process may be performed to remove at least one metal material from over the at least one contact level dielectric layer (71,73) and from sidewalls of the backside trench 79. The etching process may include an isotropic etching step, an anisotropic etching step, or a combination thereof. In an illustrative example, at least one halide-containing gas (such as CHF) is employed₃、CClF₃、CF₄、SF₆、SiF₄、Cl₂、NF₃) The reactive ion etching of (2) may be used for the etching process. Alternatively, such as O₂Or O₃The oxidizing agent of (a) may be employed in combination with at least one halide-containing gas. The conductive layer 46 remains around each backside trench 79 as a discrete layer that is electrically isolated from each other.

Referring to fig. 16, insulating spacers 74 may be formed on the sidewalls of each backside trench 79 by depositing a continuous layer of dielectric material and anisotropic etching that removes horizontal portions of the continuous layer of dielectric material. Each insulating spacer 74 comprises a dielectric material that may include, for example, silicon oxide, silicon nitride, a dielectric metal oxide, a dielectric metal oxynitride, or a combination thereof. The thickness of each insulating spacer 74, as measured at its bottom portion, may be in the range from 1nm to 50nm, although lesser and greater thicknesses may also be employed. In one embodiment, the thickness of the insulating spacers 74 may be in a range from 3nm to 10 nm.

Each insulating spacer 74 has sidewalls that contact insulating layer 32 and conductive layer 46 and an outer sidewall of the sidewall of upper source insulating layer 16. In addition, each insulating spacer 74 may contact a surface of the sacrificial matrix layer 14. Accordingly, each insulating spacer 74 may be formed at the periphery of a respective backside trench 79 and over a portion of the sacrificial matrix layer 14 and on the sidewalls of the upper source insulator layer 16.

Referring to fig. 17, the sacrificial matrix layer 14 may be removed selective to the array of dielectric pillars 20, the lower source insulating layer 12, the upper source insulating layer 16, the through stacked dielectric pillar structures 7P, and the insulating spacers 74 to form the source line cavities 15. The sacrificial matrix layer 14 is preferably removed after the conductive layer 46 is formed. In one embodiment, the array of dielectric pillars 20, the lower source insulating layer 12, the upper source insulating layer 16, the through stacked dielectric pillar structures 7P, and the insulating spacers 74 may comprise various types of silicon oxide, and the sacrificial matrix layer 14 may comprise a semiconductor material (such as amorphous silicon, polysilicon, or a silicon germanium alloy), amorphous carbon, or an organic or inorganic polymer. For example, if the sacrificial matrix layer 14 comprises polysilicon, a wet etch using potassium hydroxide (KOH) may be employed to remove the sacrificial material layer 14 selective to the array of dielectric pillars 20, the lower source insulating layer 12, the upper source insulating layer 16, the through stacked dielectric pillar structures 7P, and the insulating spacers 74. Sidewalls of the memory stack structure 55 may be physically exposed to the source line cavity 15. Furthermore, the sidewalls of the dielectric pillar 20 may be physically exposed to the source line cavity 15.

After removal of the sacrificial matrix layer 14, the physically exposed portions of each memory film 50 may be removed. For example, the physically exposed portion of the memory film 50 may be removed by isotropic etching such as wet etching. Thus, the sidewalls of the semiconductor channel 60 become physically exposed at the level of the source line cavity 15. The remaining portion of each memory film 50 below the physically exposed sidewalls of the respective semiconductor channel 60 constitutes a dielectric cover plate 58 that is below the semiconductor channel 60 and comprises the same set of dielectric materials as the remaining portion of the memory film 50 that is above the source line cavity 15. Alternatively, the annular source region 61 may be formed by introducing an electrical dopant to a lower portion of each semiconductor channel 60 by plasma doping or gas phase doping.

Typically, a polysilicon structure (embodied as a source region 61) may be provided at the lower end of each semiconductor channel 60 by depositing a polysilicon material portion on the annularly exposed portion of each semiconductor channel 60 at the level of the source line cavity 15 and/or doping the annularly exposed portion of each semiconductor channel 60. Three types of polysilicon (including p + -type polysilicon, undoped polysilicon, and n + -type polysilicon) may be selected for the polysilicon structure, which may be used as the polysilicon source region 61. Table 1 provides an overview of the erase and read mechanisms for each type of polysilicon used for source region 61.

TABLE 1 comparison of various types of Source regions

The p + polysilicon source regions may employ coupled erase, while other types of source regions may employ GIDL erase. Benefits of embodiments of the present disclosure include, but are not limited to, preventing stack collapse with edge device area increase (due to the formation of dielectric pillars 20). The removal of the sacrificial matrix layer 14 does not require the use of reactive ion etching, but an isotropic etching process may be employed to remove the sacrificial matrix layer 14.

Referring to fig. 18, at least one conductive material is deposited by at least one conformal deposition method, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroplating, and/or electroless plating, to form the source line cavity 15. In one embodiment, the at least one conductive material may include a metal liner material, such as a conductive metal nitride or a conductive metal carbide, and a metal filler material, such as W, Cu, Al, Co, Ru, and alloys thereof. For example, a metal liner material layer 76A comprising a metal liner material and a metal fill material layer 76B comprising a metal fill material may be deposited during the same set of deposition processes to fill the source line trenches 15 and the backside trenches 79. Portions of the at least one conductive material above a level including a top surface of the at least one contact level dielectric layer (71,73) may be removed by a planarization process. In one embodiment, the planarization process may be a Chemical Mechanical Planarization (CMP) process employing one of the at least one contact level dielectric layers (71,73) as a stop layer. A continuous source structure 76 may be formed within each continuous volume of the source line trench 15 and at least one backside trench 79 connected to the source line trench 15. In one embodiment, the source line trench 15 may be connected to the plurality of backside trenches 79, and the continuous source structure 76 may fill the entire continuous volume including the source line trench 15 and the plurality of backside trenches 79. The continuous source structure 76 may function as a source contact structure or a combination of a source structure and a source contact structure.

The portion of each continuous source structure 76 that fills the source line cavity 15 is referred to herein as a source conductive layer 76L. Thus, the source matrix layer 14 is replaced by a source conductive layer 76L extending in a horizontal direction parallel to the top surface of the substrate (i.e., the substrate semiconductor layer 10). The source conductive layer 76L may contact the sidewall of each dielectric pillar 20 in the array of dielectric pillars 20. Each portion of the continuous source structure 76 filling the backside trench 79 constitutes a source conductive via structure 76V. Each source conductive via structure 76Vt extends vertically through the alternating stack (32,46) perpendicular to the top surface of the substrate 10. Continuous source structure 76 is a unitary structure without any interface between source conductive via structure 76V and source conductive layer 76L. As used herein, "unitary structure" refers to a single contiguous structure that is not divided into a plurality of physically separate portions. As used herein, "interface" refers to a microscopic interface between two elements characterized by differences in material composition, the presence of voids, or the presence of interface materials that can be detected by analytical means such as transmission electron microscopy, scanning electron microscopy, and/or secondary ion mass spectrometry.

Thus, the continuous source structure 76 may be formed by simultaneously filling the source line cavity 15 and the at least one backside trench 79 with at least one conductive material. Each source conductive via structure 76V is formed on the inner sidewall of a respective insulating spacer 74. The source line structure 76L may be formed directly on the source region 61, which comprises a deposited polysilicon layer on the exposed sidewalls of each semiconductor channel 60 or a doped region in the exposed sidewalls of each semiconductor channel 60.

Referring to fig. 19, a photoresist layer (not shown) may be applied over the topmost layer of the first exemplary structure (which may be, for example, the second insulating cap layer 73), and may be photolithographically patterned to form various openings in the memory array region 100, the peripheral device region 200, and the contact region 300. The locations and shapes of the various openings are selected to correspond to electrical nodes of various devices to be electrically contacted by the contact via structures. In one embodiment, a single photoresist layer may be employed to pattern all openings corresponding to contact via cavities to be formed, and all contact via cavities may be simultaneously formed by at least one anisotropic etching process employing the patterned photoresist layer as an etch mask. In another embodiment, multiple photoresist layers may be employed in conjunction with multiple anisotropic etching processes to form different sets of contact via cavities having different opening patterns in the photoresist layers. The photoresist layer(s) may be removed after a respective anisotropic etch process that transfers the pattern of openings in the respective photoresist layer through the underlying dielectric material layer and to the top surface of the respective conductive structure.

In an illustrative example, a drain contact via cavity may be formed over each memory stack structure 55 in the memory array region 100 such that a top surface of the drain region 63 is physically exposed at a bottom of each drain contact via cavity. The wordline contact via cavities may be formed as stepped surfaces of the alternating stack (32,46) such that a top surface of the conductive layer 46 is physically exposed at the bottom of each wordline contact via cavity in the contact region 300. A device contact via cavity may be formed as each electrical node of peripheral device 210 to be contacted by a contact via structure in peripheral device region 200.

The various via cavities may be filled with at least one conductive material, which may be a combination of a conductive metal liner material (such as TiN, TaN, or WN) and a metal fill material (such as W, Cu, or Al). Excess portions of the at least one conductive material may be removed from over the at least one contact-level dielectric layer (71,73) by a planarization process, which may include, for example, Chemical Mechanical Planarization (CMP) and/or recess etching. Drain contact via structures 88 may be formed on the respective drain regions 63. Word line contact via structures 84 may be formed on the respective conductive layers 46. Peripheral contact via structures 8P may be formed on respective nodes of peripheral device 210. Additional metal interconnect structures (not shown) and interlevel dielectric material layers (not shown) may be formed over the first exemplary structure to provide electrical routing between the various contact via structures.

A first exemplary structure according to embodiments of the present disclosure may include a three-dimensional memory device. The three-dimensional memory device includes an alternating stack of conductive layers 46 and insulating layers 32 over a substrate 10 and an array of memory stack structures 55. Each memory stack structure 55 extends through the alternating stack (32,46) and includes a memory film 50 and a semiconductor channel 60 laterally surrounded by the memory film 50. The three-dimensional memory device may also include an array of dielectric pillars 20 located between the alternating stack (32,46) and the substrate 10. A continuous source structure 76 may be provided that includes a source conductive layer 76L extending horizontally and laterally surrounding each dielectric pillar 20 in the array of dielectric pillars 20. The continuous source structure 76 may also include a source conductive via structure 76V vertically through the alternating stack (32, 46). Continuous source structure 76 may be a unitary structure without an interface between source conductive via structure 76V and source conductive layer 76L. The source conductive layer 76L may include a buried source line or electrode, and the source conductive via structure 76V may include a source local interconnect.

The three-dimensional memory device can include a lower source insulator layer 12 between the substrate 10 and the source conductive layer 76L, an upper source insulator layer 16 between the source conductive layer 76L and the alternating stack (32,46), and an insulating spacer 74 laterally surrounding the source conductive via structure 76V. In one embodiment, the continuous source structure 76 may include a metal dielectric liner 76A and a conductive fill material portion 76B surrounded by the metal dielectric liner 76A, the metal dielectric liner 76A contacting sidewalls of the array of dielectric pillars 20 and extending over a topmost surface of the alternating stack (32, 46).

A stepped surface area may be provided in the contact region 300. The ends of the conductive layer 46 form a stepped surface in the stepped surface region. Source conductive layer 76L may extend laterally further than any conductive layer 46. In one embodiment, the continuous source structure 76 may contact at least one of the outer sidewall of each source region 61 and the annular bottom surface of the memory film 50.

In one embodiment, each dielectric pillar 20 in the array of dielectric pillars 20 may have a topmost surface located at or below a first level including the bottommost surfaces of the alternating stacks (32,46), and may have a bottommost surface located at or above a second level including the top surface of the substrate 10. In one embodiment, the array of dielectric pillars 20 may comprise silicon oxide. The dielectric pillars 20 terminating below the alternating stack (32,46) are distinct from the through-stack dielectric pillars 7P extending through the entire alternating stack (32, 46).

In one embodiment, the monolithic three dimensional memory device comprises a vertical NAND device located above the substrate, and conductive layer 46 comprises or is electrically connected to a respective word line of the NAND device. In one embodiment, the substrate 10 comprises a silicon substrate and the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located above the silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may contain an integrated circuit that includes driver circuitry for the memory devices located thereon.

The array of monolithic three-dimensional NAND strings can include a plurality of semiconductor channels 60. At least one end of each of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the substrate. An array of monolithic three-dimensional NAND strings can include a plurality of charge storage elements. Each charge storage element may be located adjacent a respective one of the plurality of semiconductor channels 60. An array of monolithic three-dimensional NAND strings can include a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of a substrate. The plurality of control gate electrodes includes at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

Referring to fig. 20, a graph of the magnitude of stress on memory stack structures 55 for various configurations of dielectric pillars according to an embodiment of the present disclosure. The unit of the vertical axis (for the magnitude of the stress) is arbitrary. The case labeled "Ref" refers to a configuration in which there is no array of dielectric pillars 20. The case labeled "diagonal layout" refers to the third configuration of the array of dielectric pillars 20. The case labeled "zigzag layout" refers to a first configuration for an array of dielectric pillars 20.

The array of dielectric pillars 20 reduces mechanical stress to provide a stable structure during the fabrication process. The simulated data of fig. 20 was obtained assuming 100 layers within the alternating stack (32,46) using linearly repeating boundary conditions. The magnitude of the finger tilt or risk of finger collapse may be reduced by 25% by the zigzag layout based on computer simulations of the finger tilt and stress on the dielectric posts 20 under unbalanced capillary forces.

The first exemplary structure of the present disclosure employs a continuous source structure 76 as a bottom connection for the semiconductor channel 60 in the memory opening 49. The array of dielectric pillars 20 provides structural protection against mechanical stress on the memory stack structure 55 during formation of the source conductive layer 76L.

The array of dielectric pillars 20 may be used to prevent collapse of the source line cavities 15 and enable the formation of a continuous source structure 76 including a source conductive layer 76L. Although the presence of the dielectric pillar 20 may adversely affect the source side contact resistance, the degradation of the source side contact resistance is manageable at the densities shown in fig. 13A-13C.

The dielectric posts 20 are support pedestal structures that are substantially comprised of a dielectric material. A source conductive layer 76L underlies the alternating stack (32,46) and covers the substrate including the substrate semiconductor layer 10. The source conductive layer 76L is electrically shorted to the bottom end of each of the semiconductor channels 60. As a supporting pedestal structure, the dielectric pillar 20 is in contact with the source conductive layer 76L and is located below the alternating stack (32, 46).

According to another aspect of the present disclosure, an embodiment is disclosed in which the support pedestal structure may be provided as a semiconductor material or a dielectric material. For example, the support pedestal structure may be provided as a doped semiconductor material portion. In one embodiment, the support base structure may be formed as a rail structure. As used herein, a rail structure refers to a structure that extends laterally along a horizontal direction and has a uniform height.

Referring to fig. 21, a second exemplary structure according to a second embodiment of the present disclosure is shown. The second exemplary structure includes a substrate 8 (which may be a semiconductor substrate), a conductive substrate, or an insulator substrate. The substrate 8 may have a thickness sufficient to provide structural support for the elements formed thereon. In one embodiment, the thickness of the substrate 8 may be in a range from 50 microns to 1 millimeter, although lesser and greater thicknesses may also be employed. In one embodiment, substrate 8 may be a semiconductor substrate, such as a single crystal substrate or a polycrystalline substrate. Before or after forming a memory device to be described below, a semiconductor device, such as the peripheral device 210 described above, may be formed in a peripheral device region (not shown) of the substrate 8. Such semiconductor devices may include peripherals that may be used to support the operation of memory devices that are subsequently formed over substrate 8.

An insulator layer 120 may be formed over the substrate 8. Insulator layer 120 comprises a dielectric material such as silicon oxide. The thickness of the insulator layer 120 may range from 10nm to 300nm, although lesser and greater thicknesses may also be employed.

A source conductive layer 140 (e.g., a source line or source electrode) may be formed over the insulator layer 120. The source conductive layer 140 comprises a conductive material (which may comprise a metal material), a heavily doped semiconductor material, a metal-semiconductor alloy (such as a metal silicide), or a combination thereof. In one embodiment, the source conductive layer 140 may include a tungsten silicide layer or a vertical stack of a conductive metal nitride layer (such as a TiN layer) and a metal layer (such as a tungsten layer) from bottom to top. The source conductive layer 140 may be formed by conformal or non-conformal deposition and may be formed as a planar material layer having a uniform thickness throughout.

The sacrificial material portions 151 may be formed as rail structures extending along a first horizontal direction hd1 (e.g., a word line direction) and laterally spaced apart from each other along a second horizontal direction hd2 (e.g., a bit line direction). The sacrificial material portions 151 may be formed by depositing a sacrificial material layer as a planar material layer, applying and patterning a photoresist layer thereon, and transferring the pattern of the photoresist layer through the planar material layer by an anisotropic etching process, such as a reactive ion etching process. The source conductive layer 140 may be used as a stop layer for the anisotropic etching process. Each remaining portion of the sacrificial material layer constitutes a sacrificial material portion 151. The photoresist layer may then be removed, for example, by ashing.

In one embodiment, the width of each sacrificial material portion 151 may be selected to be on the order of the center-to-center distance between adjacent pairs of rows of memory openings that will subsequently be formed along the first horizontal direction hd 1. In one embodiment, the spacing between each adjacent pair of sacrificial material portions 151 may be on the order of the center-to-center distance between adjacent pairs of rows of memory openings that will subsequently be formed along the first horizontal direction hd 1. In one embodiment, the sacrificial material portions 151 may form a one-dimensional periodic array along the second horizontal direction hd2, and the periodicity of the one-dimensional array (i.e., the sum of the width of the sacrificial material portions 151 and the spacing between adjacent pairs of sacrificial material portions 151) may be equal to twice the inter-row distance between memory openings to be subsequently formed.

The sacrificial material portion 151 may include a semiconductor material or a dielectric material. In one embodiment, the sacrificial material layer and the sacrificial material portions 151 formed therefrom comprise semiconductor material that is not intentionally doped. Semiconductor materials that are not intentionally doped may be intrinsic or may have a low concentration of electrical dopant due to dopant incorporation at a microscale during deposition. As used herein,' A "Undoped semiconductor materials "are collectively referred to as intrinsic semiconductor materials and include atomic concentrations of less than 1.0 x 10¹⁶/cm³Of the electrical dopant. Undoped semiconductor materials may be formed by not intentionally incorporating electrical dopants during deposition of the semiconductor material.

In one embodiment, the undoped semiconductor material may be a heavily doped semiconductor material (i.e., having a thickness greater than 1.0 x 10)⁵Doped semiconductor material (e.g., having a conductivity greater than 1.0 x 10) of S/cm¹⁹/cm³Dopant concentration of) selectively removed. In one embodiment, the undoped semiconductor material of the sacrificial material portion 151 may comprise amorphous silicon, polycrystalline or amorphous germanium, an amorphous silicon germanium alloy, or a polycrystalline silicon germanium alloy comprising germanium at an atomic concentration of greater than 40%.

In another embodiment, the sacrificial material layer and the sacrificial material portion 151 may include a dielectric material. In this case, the dielectric material of the sacrificial material portions 151 may be selected from among materials that may be removed selectively to the material of the post structures to be subsequently formed and selectively to the alternating stack to be subsequently formed. For example, the sacrificial material portion 151 may include a dielectric material such as porous or non-porous organosilicate glass (OSG), amorphous carbon, or diamond-like carbon (DLC).

Dielectric liner 153 may optionally be formed as a conformal layer of material over the top surface and sidewalls of sacrificial material portion 151 and on the physically exposed surface of source conductive layer 140. Dielectric liner 153 may comprise a diffusion barrier layer material such as silicon nitride. The thickness of the optional dielectric liner 153 may be in the range from 3nm to 10nm, although lesser and greater thicknesses may also be employed. The top of the dielectric liner 153 is not shown in the cut-out region of fig. 21, from which all elements are removed in order to more clearly show the underlying elements below the bottom level of the cut-out region. A linear trench 159 is present between each adjacent pair of sacrificial material portions 151.

Referring to FIG. 22, the base structure 156 is supported onFormed in the line trench 159. A semiconductor material or a dielectric material may be deposited into the line trenches 159. Exemplary semiconductor materials that may be used to support pedestal structure 156 include boron doped silicon (e.g., amorphous or polycrystalline silicon) comprising an atomic concentration greater than 1.0 x 10¹⁹/cm³And preferably greater than 1.0X 10²⁰/cm³(e.g., 5X 10)¹⁹/cm³To 5X 10²¹/cm³) Boron (b) in the presence of boron. In this case, boron doped silicon of the support pedestal structure 156 may be employed in combination with the sacrificial material portion 151 comprising undoped amorphous silicon to enable etching in an etchant such as trimethyl-2hydroxyethyl ammonium hydroxide (TMY). Wherein the sacrificial material portions 151 are removed selective to the support pedestal structure 156.

Exemplary insulator materials that may be used to support pedestal structure 156 include undoped silicate glass (i.e., silicon oxide), doped silicate glass, silicon nitride, and dielectric metal oxides. In this case, the support base structure 156 may be a rail structure comprising a dielectric material, and the sacrificial material portion 151 comprises a material (such as organosilicate glass, amorphous carbon, or diamond-like carbon) that may be removed selectively to the support base structure 156.

Excess portions of the deposited material may be removed by a planarization process from above the level of the top surface including the sacrificial material portions 151. The planarization process may include a recess etch process and/or chemical mechanical planarization. Each remaining portion of the deposited material in the line trench 159 constitutes a support pedestal structure 156. Each support base structure 156 may be a rail structure extending laterally along the first horizontal direction. In one embodiment, horizontal portions of the dielectric liner 153 may be removed from over the top surface of the sacrificial material portion 151 by a planarization process. In this case, the top surface of the sacrificial material portion 151 may be coplanar with (i.e., within the same plane as) the top surface of the support pedestal structure 156. If the dielectric liner 153 is formed at the processing step of fig. 21, a U-shaped portion of the dielectric liner 153 may be present between each support pedestal structure 156 and the source conductive layer 140.

A layer (151,153,156) including support pedestal structures 156 and sacrificial material portions 151 is formed on source conductive layer 140. In one embodiment, the support pedestal structure 156 may comprise a doped first semiconductor material having a first conductivity type (which may be p-type or n-type), and the sacrificial material portion 152 may comprise an undoped semiconductor material (such as amorphous undoped silicon). In an illustrative example, the first semiconductor material may comprise a p-doped silicon-containing material and the undoped semiconductor material may comprise an undoped silicon-containing material.

Referring to fig. 23, an alternating stack of first and second material layers is formed over the top surfaces of the support pedestal structures 156 and the sacrificial material portions 151. As used herein, a "layer of material" refers to a layer of material throughout its entirety. As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements alternate with instances of the second elements. Each instance of the first element that is not an alternating plurality of end elements is adjoined on both sides by two instances of the second element, and each instance of the second element that is not an alternating plurality of end elements is adjoined by two instances of the first element at both ends. The first elements may have the same thickness therein, or may have different thicknesses. The second elements may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or begin with an instance of a second material layer, and may end with an instance of a first material layer or end with an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within alternating pluralities.

Each first material layer includes a first material and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a spacer material layer that provides vertical spacing between each vertically adjacent pair of insulating layers 32. In one embodiment, the layer of spacer material may be formed as a conductive layer.

In another embodiment, a layer of spacer material may be formed as the layer of sacrificial material 42. In this case, the stack may comprise alternating pluralities of insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack comprising alternating layers of insulating layers 32 and sacrificial material layers 42, as in the first embodiment. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

In one embodiment, the alternating stack (32,42) may include an insulating layer 32 composed of a first material group and a sacrificial material layer 42 composed of a second material different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. As such, each insulating layer 32 may be a layer of insulating material. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides and silicates thereof commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

The second material of the sacrificial material layer 42 is a sacrificial material that can be removed selectively to the first material of the insulating layer 32. As used herein, the removal of a first material is "selective" to a second material if the removal process removes the first material at a rate that is at least twice the rate at which the second material is removed. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

In one embodiment, the insulating layer 32 may comprise silicon oxide and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. For example, the first material of the insulating layer 32 may be deposited by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The sacrificial material layer 42 may be suitably patterned such that portions of conductive material subsequently formed by replacing the sacrificial material layer 42 may serve as conductive electrodes, such as control gate electrodes of a monolithic three-dimensional NAND string memory device to be subsequently formed. The sacrificial material layer 42 may include a portion having a strip shape extending substantially parallel to the top surface of the substrate 8.

While the present disclosure is described with an embodiment in which the second material layer is formed as a sacrificial material layer, it should be understood that the second material layer may be formed as a conductive layer. In this case, the process step of replacing the sacrificial material layer with the conductive layer may be omitted.

The upper ends of the alternating stacks (32,42) may terminate at instances of the insulating layer 32. Alternatively, the upper end of the alternating stack (32,42) may terminate at an instance of the sacrificial material layer 42, and an insulating cap layer 70 having a greater thickness may be formed over the alternating stack (32, 42). The insulating cap layer 70 may have the same composition as the insulating layer 32 and may have a greater thickness than the insulating layer 32. The insulating cap 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap 70 may be a silicon oxide layer. The alternating stack (32,42) and insulating cap 70 are not shown in the cutout region to show the elements below the horizontal bottom surface of the cutout region.

Stepped cavities (not shown) and stepped back dielectric material portions (not shown) may be formed on the alternating stack (32,42) in the same manner as in the first embodiment. The dielectric pillars may be formed as in the first embodiment.

Referring to fig. 24, a layer of photoresist material (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and may be lithographically patterned to form openings therein. The pattern in the layer of photolithographic material may be transferred through the insulating cap layer 70 and through the entire alternating stack (32,42) and into the support pedestal structure 156 and the sacrificial material portions 151 by an anisotropic etching process. The alternating stack (32,42) and the upper portion of the layer comprising the support pedestal structure 156 and the sacrificial material portion 151 are removed in the region below the opening in the patterned photolithographic material layer during the anisotropic etching process. In one embodiment, the bottom surface of the memory opening 49 may be vertically spaced apart from the top surface of the source conductive layer 140. The chemistry of the anisotropic etching process used to etch through the material of the alternating stack (32,42) may be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the reservoir opening 49 may be substantially vertical or may be tapered. The patterned stack of photolithographic material may then be removed, for example, by ashing.

In one embodiment, each memory opening 49 may extend through a portion of a respective support pedestal structure 156 and a portion of a respective sacrificial material portion 151. In one embodiment, the memory openings 49 may be arranged in rows extending along the first horizontal direction hd 1. The rows of memory openings 49 may be laterally spaced apart along the second horizontal direction hd 2. The location of each row of memory openings 49 may be selected such that each memory opening 49 within the row spans an adjacent pair of the support pedestal structure 156 and the sacrificial material portion 151.

During the formation of the memory openings 49, the material of the support pedestal structures 156 and the sacrificial material portions 151 is partially removed. In one embodiment, the reservoir opening 49 may have a generally cylindrical shape (having a horizontal cross-sectional shape that is a circle, an ellipse, a super-ellipse, or a closed shape that provides a concave surface toward the geometric center of the horizontal cross-sectional shape). As used herein, the "geometric center" of an element is the centroid of a hypothetical object having the same shape and position as the element and always having a uniform density. In this case, concave sidewalls may be formed on the support pedestal structure 156 during formation of the memory opening 49, and additional concave sidewalls may be formed on the sacrificial material portion 151. Each of the concave sidewalls on the support base structure 156 and the sacrificial material portion 151 may be substantially vertical. As used herein, "dimpled sidewall" refers to a continuous set of sidewalls, including planar sidewalls that lie in the same vertical plane and abut a concave sidewall. Each of the support base structures 156 may include a pair of dimpled sidewalls, each dimpled sidewall including a respective planar vertical sidewall adjoined by a respective concave vertical sidewall. Similarly, each sacrificial material portion 151 can include a pair of dimpled sidewalls, each dimpled sidewall including a respective planar vertical sidewall adjoined by a respective concave vertical sidewall.

Each of the memory openings 49 may include a sidewall (or sidewalls) that extends substantially perpendicular to the topmost surface of the substrate semiconductor layer 8. The area in which the array of memory openings 49 is formed is referred to herein as the memory array area. Each of the memory openings 49 may have a lateral dimension (such as a diameter or major axis) in a range from 30nm to 120nm, although smaller and larger lateral dimensions may also be employed.

Referring to fig. 25, a memory film 50 may be formed within each memory opening 49 by sequential deposition of a set of component layers. The set of component layers may include an optional blocking dielectric layer 52, a charge storage element layer 54, and a tunneling dielectric layer 56 in each memory opening 49 from the outside to the inside and in sequential order of deposition.

In particular, the blocking dielectric layer 52 includes at least one dielectric material, which may be silicon oxide, a dielectric metal oxide, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9. Additionally or alternatively, the blocking dielectric layer 52 may include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise a stack of aluminum oxide and silicon oxide. The thickness of the blocking dielectric layer 52 may range from 1nm to 30nm, although lesser and greater thicknesses may also be employed.

The charge storage element layer 54 may comprise a single layer of charge trapping material comprising a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage element layer 54 may comprise a conductive material, such as a doped polysilicon or metallic material, patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within the lateral recesses.

Alternatively, the charge storage element layer 54 may be formed as a single memory material layer of uniform composition, or may include a stack of multiple memory material layers. If employed, the plurality of memory material layers may include a plurality of spaced-apart floating gate material layers comprising conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and/or semiconductor material (e.g., a polycrystalline or amorphous semiconductor material or at least one compound semiconductor material including at least one elemental semiconductor element). In one embodiment, the charge storage element layer 54 comprises a silicon nitride layer. Alternatively or additionally, the charge storage element layer 54 may comprise an insulating charge trapping material, such as one or more silicon nitride portions. Alternatively, the charge storage element layer 54 may include conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage element layer 54 may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage element layer 54 may range from 2nm to 20nm, although lesser and greater thicknesses may also be employed.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer 56 may range from 2nm to 20nm, although lesser and greater thicknesses may also be employed.

The memory film 50 may be formed as a continuous layer stack directly on the sidewalls and concave horizontal surfaces of each support pedestal structure 156 and directly on the sidewalls and concave horizontal surfaces of each sacrificial material portion 151.

The semiconductor channel layer 60L may be deposited on the memory film 50. The semiconductor channel layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polysilicon. The semiconductor channel layer 60L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the semiconductor channel layer 60L may be in the range from 2nm to 10nm, although lesser and greater thicknesses may also be employed.

The semiconductor channel layer 60L may be removed from over the alternating stack at this point or at a later point in the process such that the remaining vertical portion of the semiconductor channel layer 60L forms the semiconductor channel 60. Likewise, layers of the memory film 50 may be removed from the top surface of the memory stack at this point or at a later point in the process. A drain region 63 may be formed at the top of the semiconductor channel 60 at this point or at a later point in the process. A portion of the memory film 50 and a portion of the semiconductor channel layer 60L within the same memory opening 49 constitute a memory stack structure (50, 60). Each memory stack structure (50,60) includes a vertical portion of the memory film 50 and a vertical portion of the semiconductor channel layer 60L. A cavity may exist within the volume of each reservoir opening 49 that is not filled by the deposited material layer (52,54,56, 60L).

A dielectric core 62 may be formed within the memory opening 49 by depositing dielectric material in a cavity within the memory opening 49, removing horizontal portions of the deposited dielectric material from over the alternating stack (32,42), and vertically recessing the deposited dielectric material. Each remaining portion of the dielectric material constitutes a dielectric core 62.

Referring to fig. 26, a photoresist layer (not shown) may be applied over the insulating cap layer 70 (e.g., over the horizontal portion of the semiconductor channel layer 60L if the horizontal portion of the semiconductor channel layer 60L is still present over the top of the alternating stack) and photolithographically patterned to form at least one elongated opening extending along the second horizontal direction hd 2. The pattern in the photoresist layer may be transferred through horizontal portions (if still present) of the deposited material layer (52,54,56,60L) overlying the alternating stack (32,42), the insulating cap layer 70, the alternating stack (32,42), and the layer comprising the support pedestal structure 156 and the sacrificial material portions 151 to form at least one backside contact trench 79. The overall pattern of the at least one backside contact trench 79 may be the same as shown in fig. 12B, except that the dielectric pillars 20 are replaced with a combination of support pedestal structures 156 and sacrificial material portions 151 in the second exemplary structure.

At least one backside contact trench 79 extends through the alternating stack (32,42) and into the support pedestal structure 156 and the sacrificial material portion 151. The at least one backside contact trench 79 may divide a subset of or each of the preexisting support pedestal structures 156 and the sacrificial material portions 151 into a plurality of portions. In forming the at least one backside contact trench 79, sidewalls of the support base structure 156 and the sacrificial material portion 151, which are divided by the at least one backside contact trench 79, are physically exposed.

Referring to fig. 27, a laterally extending cavity 157 is formed by removing the sacrificial material portion 151 without removing the support pedestal structure 156, the alternating stack (32,42), the source conductive layer 140, and the outermost layer of the memory film 50, such as the blocking dielectric layer 52. In one embodiment, an etchant may be employed that etches the material of the sacrificial material portions 151 selective to the material of the alternating stack (32,42) and the source conductive layer 140, and the outermost layer of the memory film 50, and selective to at least one of the support pedestal structure 156 and the dielectric liner 153.

In one embodiment, the sacrificial material portion 151 may comprise undoped semiconductor material, and the support pedestal structure 156 may comprise a material having a thickness of greater than 1 x 10¹⁹/cm³A heavily doped semiconductor material of dopant concentration. In this case, the sacrificial material portions 151 may be removed using a wet etch process that removes undoped semiconductor material selective to doped semiconductor material without removing the support pedestal structures 156. In one embodiment, the doped semiconductor material comprises, for example, a material including an atomic concentration greater than 1.0 x 10¹⁹/cm³(such as greater than 1.0X 10)²⁰/cm³) The boron doped amorphous silicon of (a), the undoped semiconductor material comprises an undoped silicon-containing material, such as undoped amorphous silicon, and the wet etching process employs a solution comprising trimethyl-2-hydroxyethylammonium hydroxide (TMY) as an etchant. Trimethyl-2-hydroxyethylammonium hydroxide (TMY) etch doped with respect to boronSilicon is undoped silicon with high selectivity.

In the case where the dielectric liner 153 is present in the second exemplary structure, the sidewalls of the dielectric liner 153 may be optionally removed by isotropic etching (such as wet etching). If the dielectric liner 153 comprises silicon nitride, the sidewalls of the dielectric liner 153 may be removed by wet etching using phosphoric acid. The duration of the etching process may be selected such that a horizontal portion of the dielectric liner 153 remains between each support pedestal structure 156 and the source conductive layer 140. Alternatively, the dielectric liner 153 may remain substantially intact. In this case, a U-shaped dielectric liner 153 having a horizontal portion and a pair of vertical portions extending upward from the edge of the horizontal portion may be present on each support base structure 156. Alternatively, the dielectric liner 153 may not be formed at the processing step of fig. 21. In this case, the support base structure 156 may contact the top surface of the source conductive layer 140.

Referring to fig. 28 and 29, the portion of the memory film 50 physically exposed to the laterally extending cavity 157 is selectively removed from the semiconductor channel layer 60L (or the channel 60 if the layer 60L is removed from the top of the alternating stack) without removing the portion of the memory film 50 that contacts the support pedestal structure 156. An isotropic etch may be used to remove the physically exposed portions of the memory film 50 and physically expose the lower portion of each sidewall of the semiconductor channel (which is the vertical portion of the semiconductor channel layer 60L within the memory opening). The duration of the isotropic etch may be controlled to prevent removal of the memory film 50 from the region between the semiconductor channel and the support pedestal structure 156. Upon removal of the portion of the memory film 50 that is physically exposed to the laterally extending cavity 157, the sidewalls of the semiconductor channel layer 60L are physically exposed.

Referring to fig. 30 and 31, a layer of doped semiconductor material 150L may be deposited in the at least one backside contact trench 79 and the laterally extending cavity 157 by a conformal deposition process. The doped semiconductor material layer 150L may be a conductive material, i.e., may include a material having a thickness greater than 1.0 x 10⁵Sum of electrical conductivity of S/cm greater than 1.0X 10¹⁹Blend of/cm 3A heavily doped semiconductor material (such as p-doped silicon or n-doped silicon) of a heteroatom concentration. The doped semiconductor material layer 150L may be formed as a single continuous structure. In one embodiment, the support pedestal structure 156 may comprise a first semiconductor material having a doping of a first conductivity type, and the layer of doped semiconductor material 150L may comprise a second semiconductor material having a doping of a second conductivity type opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa.

Each portion of the layer 150L of doped semiconductor material filling the laterally extending cavity 157 constitutes a conductive track structure. Each of the conductive track structures includes a dimpled sidewall including a respective planar vertical sidewall adjacent to a respective concave vertical sidewall. The concave vertical sidewall within the dimpled sidewall of the conductive rail structure contacts the sidewall of the semiconductor channel, which is the vertical portion of the semiconductor channel layer 60L in the memory opening.

A vertical portion of the doped semiconductor material layer 150L is present at the periphery of each backside contact trench 79. A horizontal portion of the layer of doped semiconductor material 150L is present over the insulating cap layer 70. A vertically extending cavity extending through the alternating stack (32,42) is present within each backside contact trench 79.

Each vertically recessed volume overlying the dielectric core 62 may be filled with a portion of the doped semiconductor material layer 150L that protrudes downward from a horizontal portion of the doped semiconductor material layer 150L, wherein the horizontal portion of the doped semiconductor material layer 150L overlies a topmost surface of the semiconductor channel layer 60L. The material filling the laterally extending cavities 157 and the material filling the vertically recessed volumes covering the dielectric core 62 may be formed simultaneously.

Referring to fig. 32, portions of the layer of doped semiconductor material 150L are etched back from over the sidewalls of each backside contact trench 79 and the insulating cap 70, for example, by an isotropic etch or an anisotropic etch. Horizontal portions of the semiconductor channel layer 60L and horizontal portions of the memory film 50 overlying the insulating cap layer 70 or the backward stepped dielectric material portion(s) 65 may be removed by at least one etching process, wherein the etching process may include at least one anisotropic etching process and/or at least one isotropic etching process. In an illustrative example, removing portions of the material of the doped semiconductor material layer 150L from inside the at least one backside contact trench and removing the material of the doped semiconductor material layer 150L and the semiconductor channel layer 60L from above the top surface of the insulating cap layer 70 may be performed by a wet etch employing potassium hydroxide (KOH).

Each volume of the laterally extending cavity 157 is filled with a respective conductive track structure 150, which is the remaining part of the layer 150L of doped semiconductor material. Each remaining vertical portion of the semiconductor channel layer 60L constitutes a semiconductor channel 60.

Removing the horizontal portion of the memory film 50 from over the top surface of the insulating cap layer 70 may be performed by a series of wet etch processes that sequentially remove component layers within the memory film 50. The memory film 50 is divided into a plurality of memory films 50, each memory film 50 being integrally located within a respective memory opening. Each memory film 50 in a respective memory opening may extend continuously from the top surface of the insulating cap layer 70 into the source conductive layer 140 and include openings at the level of the conductive rail structures 150 and the support base structures 156. The conductive rail structures 150 contact the sidewalls of the semiconductor channels 60 within the memory film 50 through openings within the memory film 50 at levels of the conductive rail structures. The opening in the memory film 50 is located on only one side of the memory film 50, and the other side of the memory film extends continuously from the top surface of the insulating cap layer 70 to the horizontal bottom surface of the memory film 50 that contacts the recessed horizontal surface of the source conductive layer 140.

Each contiguous pair of semiconductor channel 60 and memory film 50 constitutes a memory stack structure 55. Each memory stack structure 55 is located within a memory opening 49 and extends vertically through the alternating stack (32, 42). Each semiconductor channel 60 is a channel of a vertical field effect transistor. Each conductive rail structure 150 may be a common source region for a plurality of vertical field effect transistors (e.g., NAND strings) that includes the semiconductor channel 60 directly adjacent to the respective conductive rail structure 150. Each sacrificial material portion 151 may be replaced with a conductive track structure 150.

Each remaining portion of the layer of doped semiconductor material 150L over each dielectric core 62 contacts the top of a respective semiconductor channel 60 and constitutes a drain region 63. Each of the conductive track structure 150 and the drain region 63 may have a doping of the same conductivity type and may comprise the same atomic concentration (which may be greater than 1.0 x 10)¹⁹/cm³Such as greater than 1.0 x 10²⁰/cm³) The same electrical dopant. Thus, the conductive track structure 150 and the drain region 63 may be formed simultaneously using the same set of processing steps. The semiconductor channel 60 may be undoped or may have a doping of the opposite conductivity type to that of the conductive track structure 150 and the drain region 63. Alternatively, the drain region 63 and the channel 60 are formed earlier in the process as described above.

Referring to fig. 33, for example, an etchant that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 may be introduced into the at least one backside trench 79 using an etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective to: the first material of the insulating layer 32, the material of the at least one dielectric pillar 7P, the material of the backward stepped dielectric material portion 65, the doped semiconductor material of the conductive track structure 150, the material of the source conductive layer 140, and the material of the outermost layer of the memory film 50 (such as the blocking dielectric layer 52). In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the material of the insulating layer 32, the at least one dielectric pillar 7P, and the retro-stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide. Alternatively, the pillar 7P may include a dummy memory stack structure including a channel and a memory film, wherein the channel is not electrically connected to the bit line.

The etching process that selectively removes the second material of the sacrificial material layer 42 to the first material of the insulating layer 32 and the outermost layer of the memory film 50 may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which an etchant is introduced into the at least one backside trench 79 in a gas phase. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etch bath comprising phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The at least one dielectric pillar 7P, the retro-stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the backside recess 43 is present within the volume previously occupied by the sacrificial material layer 42.

Each dorsal concavity 43 may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each dorsal concavity 43 may be greater than the height of the dorsal concavity 43. A plurality of backside recesses 43 may be formed in the volume from which the second material of the sacrificial material layer 42 is removed. The memory openings 49 in which the memory stack structures 55 are formed are referred to herein as front-side recesses or front-side cavities opposite the back-side recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels arranged above a substrate comprising a substrate semiconductor layer 8. In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 may extend substantially parallel to a top surface of the substrate. The backside recess 43 may be vertically defined by a top surface of the lower insulating layer 32 and a bottom surface of the upper insulating layer 32. In one embodiment, each of the backside recesses 43 may have a uniform height throughout. Optionally, a backside blocking dielectric layer may be formed in the backside recess.

Referring to fig. 34, at least one metal material may be deposited in the backside recess 43, over the sidewalls of the at least one backside contact trench 79, and over the top surface of the insulating cap 70. As used herein, a metallic material refers to a conductive material that includes at least one metallic element.

The metallic material may be deposited by a conformal deposition method, which may be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. The metallic material may be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductively doped semiconductor material, a conductive metal-semiconductor alloy (such as a metal silicide, alloys thereof, and combinations or stacks thereof). Non-limiting exemplary metallic materials that may be deposited in the plurality of backside recesses 43 include tungsten, tungsten nitride, titanium nitride, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material may include a metal such as tungsten and/or a metal nitride. In one embodiment, the metal material used to fill the plurality of backside recesses 43 may be a combination of a titanium nitride layer and a tungsten fill material. In one embodiment, the metallic material may be deposited by chemical vapor deposition.

A plurality of conductive layers 46 may be formed in the plurality of backside recesses 43 and a contiguous layer of metallic material (not shown) may be formed on the sidewalls of each backside contact trench 79 and over the insulating cap layer 70. Thus, each sacrificial material layer 42 may be replaced with a conductive layer 46. A backside cavity is present in the portion of each backside contact trench 79 that is not filled with an optional backside blocking dielectric layer and an adjoining layer of metal material.

For example, by isotropic etching, the deposited metallic material of the contiguous conductive material layer is etched back from the sidewalls of each backside contact trench 79 and from above the insulating cap 70. Each remaining portion of the metal material deposited in the backside recess 43 constitutes a conductive layer 46. Each conductive layer 46 may be a conductive line structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

Each conductive layer 46 may function as a combination of multiple control gate electrodes located at the same level and a word line electrically interconnecting (i.e., electrically shorting) the multiple control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device that includes a memory stack structure 55. In other words, each conductive layer 46 may be a word line that serves as a common control gate electrode for multiple vertical memory devices.

Referring to fig. 35A and 35B, a layer of insulating material may be formed in the at least one backside contact trench 79 and over the insulating capping layer 70 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The layer of insulating material comprises an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the layer of insulating material may comprise silicon oxide. The layer of insulating material may be formed, for example, by Low Pressure Chemical Vapor Deposition (LPCVD) or Atomic Layer Deposition (ALD). The thickness of the layer of insulating material may range from 1.5nm to 60nm, although lesser and greater thicknesses may also be employed. An anisotropic etch is performed to remove horizontal portions of the insulating material layer from over the insulating cap layer 70 and the bottom of each backside contact trench 79. Each remaining portion of the layer of insulating material constitutes an insulating spacer 74. After forming the conductive layer 46, each insulating spacer 74 is formed on the sidewalls of the corresponding backside contact trench 79 and on the sidewalls of the conductive track structure 150. In one embodiment, the sidewall of each conductive rail structure 150 may contact a bottom portion of the outer sidewall of the insulating spacer 74.

Backside contact via structures 76 may be formed within the cavities inside each insulating spacer 74. Each backside contact via structure 76 may fill a respective cavity within a respective insulating spacer 74. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of each backside contact trench 79. For example, the at least one conductive material may include a conductive liner (not separately shown) and a conductive filler material portion (not separately shown). The conductive liner may comprise a conductive metal liner, such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive liner may range from 3nm to 30nm, although lesser and greater thicknesses may also be employed. The conductive filler material portion may comprise a metal or metal alloy. For example, the conductive fill material portion can include W, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

The at least one conductive material may be planarized using an insulating cap layer 70 overlying the alternating stack (32,46) as a stop layer. The insulating cap layer 70 may be used as a CMP stop layer if a Chemical Mechanical Planarization (CMP) process is employed. Each remaining continuous portion of the at least one conductive material in the backside contact trench 79 constitutes a backside contact via structure 76. Each backside contact via structure 76 may be formed directly on a top surface of a source contact layer 140, which may be electrically shorted to a conductive rail structure 150. Each backside contact via structure 76 is formed within a portion of the backside contact trench 79 that is not filled with the insulating spacers 74.

Referring to fig. 36, additional contact via structures (88,86,8P) may be formed through the second insulating cap layer 73 and optionally through the rearward stepped dielectric material portion 65. For example, a drain contact via structure 88 may be formed on each drain region 63 through the second insulating cap layer 73. A word line contact via structure 86 may be formed on the conductive layer 46 through the second insulating cap 73 and through the stepped back dielectric material portion 65. The peripheral contact via structure 8P may be formed directly on a corresponding node of the peripheral through the stepped-back dielectric material portion 65.

According to an aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack (32,46) of conductive layers 46 and insulating layers 32 over a substrate 8, an array of memory stack structures 55, each memory stack structure 55 extending through the alternating stack (32,46) and including a memory film 50 and a semiconductor channel 60 laterally surrounded by the memory film 50, and a support structure, such as a support pedestal structure 156, located between the alternating stack (42,46) and the substrate 8. The device may further include a source conductive layer 140 underlying the alternating stack (42,46) and overlying the substrate 8 and in contact with the support structure 156.

In one embodiment, the three-dimensional memory device includes conductive rail structures 150 that extend laterally along the first horizontal direction hd1, contact a top surface of the source conductive layer 140, and contact sidewalls of the semiconductor channel 60. In one embodiment, each of the conductive rail structures 150 includes a dimpled sidewall comprising a respective planar vertical sidewall adjacent to a respective concave vertical sidewall. In one embodiment, each semiconductor channel 60 contacts a sidewall of a respective conductive rail structure 150, and each memory film 50 contacts a sidewall of a respective support pedestal structure 156.

In one embodiment, the top surface of the support base structure 156 may be in the same horizontal plane as the top surface of the conductive rail structure 150. In one embodiment, the support base structure 156 may comprise a first semiconductor material having a doping of a first conductivity type, and the conductive rail structure 150 comprises a second semiconductor material having a doping of a second conductivity type opposite the first conductivity type.

In one embodiment, the three-dimensional memory device includes a backside contact via structure 76 that contacts a top surface of the source conductive layer 140. Insulating spacers 74 may laterally surround the backside contact via structures 76 and may contact the top surface of the source conductive layer 140. The conductive rail structure 150 may extend laterally along the first horizontal direction hd1, may contact a top surface of the source conductive layer 140, and may contact sidewalls of the semiconductor channel 60. The conductive rail structures 150 may be laterally spaced from the backside contact via structures 76 by insulating spacers 74.

In one embodiment, each of the support base structures 156 includes a dimpled side wall comprising a respective planar vertical side wall adjacent to a respective concave vertical side wall. In one embodiment, each of the concave vertical sidewalls of the support pedestal structures 156 contacts an outer sidewall of a respective memory film 50.

In one embodiment, the three-dimensional memory device comprises a vertical NAND device located above the substrate 8. Conductive layer 46 may include or may be electrically connected to a corresponding word line of the NAND device. The substrate 8 may comprise a silicon substrate. The vertical NAND device can include an array of monolithic three-dimensional NAND strings over a silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may contain an integrated circuit that includes driver circuitry for the memory devices located thereon.

The array of monolithic three-dimensional NAND strings can include a plurality of semiconductor channels 60. At least one end portion of each of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the substrate 8. The array of monolithic three-dimensional NAND strings can include a plurality of charge storage elements (as embodied as portions of charge storage element layer 54 located at each level of conductive layer 46). Each charge storage element is located adjacent a respective one of the plurality of semiconductor channels 60. The array of monolithic three-dimensional NAND strings can include a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of the substrate, the plurality of control gate electrodes including at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

Each of the conductive track structures 150 may serve as a common source region for a plurality of field effect transistors comprising a semiconductor channel 60 contacting the conductive track structure 150. The support structures 156 provide structural support during replacement of the sacrificial material portions 151 with the conductive track structures 150. Optionally, during operation of the vertical three-dimensional memory device, a subset of the conductive layers 46 (such as the bottom-most conductive layer 46) may be used as source select gate electrodes. By increasing the height of the sacrificial material portions 150, the contact area between each semiconductor channel 60 and the source region (as embodied as the conductive track structure 150) may be increased without increasing the size of the memory opening, thereby increasing the height of the conductive track structure 150.

Each contact region between the conductive track structure 150 and the semiconductor channel 60 may comprise a curved vertical surface. The angular spread (i.e., the degree of azimuthal angle) of the curved vertical surface from a vertical axis passing through the geometric center of the memory stack structure 55 including the semiconductor channel 60 may be in the range of 45 degrees to 315 degrees, such as from 90 degrees to 270 degrees. The structure of the present disclosure can provide a greater on current for a vertical field effect transistor of a three-dimensional memory device by providing an increased contact area between the source region and the semiconductor channel without increasing the size of the memory opening. Alternatively, the structure of the present disclosure may be employed to reduce the lateral dimensions of the memory opening and the memory stack structure while keeping the on-current of the vertical field transistor at the operational level.

Referring to fig. 37, a third exemplary structure is shown comprising, from bottom to top, a stack of a substrate 8, an optional insulator layer 120, an optional blanket conductor layer 136, and a matrix material layer 138, according to a third embodiment of the present disclosure. The substrate 8 may be the same as the substrate 8 of the second embodiment. The optional insulator layer 120 (if present) may be the same as the insulator layer 120 of the second embodiment.

Optional blanket conductor layer 136 may comprise a metal, metal alloy, conductive metal nitride, metal-semiconductor alloy (such as a silicide), or have a thickness greater than 1.0 x 10⁵A heavily doped semiconductor material of conductivity S/cm. Optional blanket conductive layer 136 may be a blanket layer, i.e., an unpatterned layer, that is of uniform thickness throughout. In one embodiment, optional blanket conductor layer 136 may comprise a metal-semiconductor alloy (such as tungsten silicide) or a metal (such as tungsten). The thickness of optional blanket conductive layer 136 may range from 3nm to 100nm, although lesser and greater thicknesses may also be employed.

The host material layer 138 includes a conductive material such as a doped semiconductor material or a metallic material (such as a metal, metal alloy, conductive metal nitride, or metal-semiconductor alloy). In one embodiment, the matrix material layer 138 includes a material having a thickness greater than 1.0 x 10⁵A heavily doped layer of semiconductor material of conductivity S/cm, such as a layer of polysilicon. The thickness of the matrix material layer 138 may range from 50nm to 500nm, although lesser and greater thicknesses may also be employed. The layer of matrix material 138 may be deposited using a conformal or non-conformal deposition process. The conductivity type of the matrix material layer 138 may be p-type or n-type.

Referring to fig. 38, a plurality of channels (i.e., recesses such as trench-like depressions) 141 are formed in an upper portion of the matrix material layer 138, for example, by applying a photoresist layer over the matrix material layer 138, photolithographically patterning the photoresist layer to form line patterns having spaces of uniform width, and transferring the patterns in the photoresist layer into the upper portion of the matrix material layer 138 by anisotropic etching. The plurality of channels 141 may have a uniform width and a uniform interval, thereby forming a one-dimensional periodic pattern. Each channel 141 may extend along the same horizontal direction, which is referred to herein as a first horizontal direction. Each of the channels 141 may have substantially the same vertical sectional shape along a direction perpendicular to the first horizontal direction. The depth of each channel 141 may range from 30nm to 300nm, although lesser and greater depths may also be employed. The width of each channel 141 may range from 60nm to 240nm, although smaller and larger widths may also be used. The pitch of the channels 141 along the horizontal direction perpendicular to the first horizontal direction may be in the range from 120nm to 480nm, although smaller and larger pitches may also be employed.

Referring to fig. 39, 40A and 40B, a sacrificial liner 154 may be optionally formed on sidewalls of the trench 141. Fig. 40A is a top view of the third exemplary structure of fig. 39 in a first exemplary configuration. Fig. 40B is a top view of the third exemplary structure of fig. 39 in a second exemplary configuration. Sacrificial liner 154 may comprise a dielectric material such as silicon oxide and may have a thickness in the range of from 1nm to 10nm, although lesser and greater thicknesses may also be employed. The remaining volume of the trench 141 not filled with the sacrificial liner 154 may be filled with a sacrificial material, such as silicon nitride, to form the sacrificial rail structure 144.

In an illustrative example, a layer of dielectric material (such as a silicon oxide layer) may be conformally deposited directly on the sidewalls and bottom surfaces of the trench 141 and over the layer of matrix material 138. A layer of sacrificial material, such as a silicon nitride layer, may be deposited in the remaining volume of the channel 141. A planarization process, such as Chemical Mechanical Planarization (CMP) and/or recess etching, may be performed to remove portions of the sacrificial material layer and the dielectric material layer from above a horizontal plane including the top surface of the matrix material layer 138. Each remaining portion of the layer of sacrificial material includes sacrificial liner 154 and each remaining portion of the layer of sacrificial material includes sacrificial rail structure 144. Each sacrificial rail structure 144 extends horizontally along a first horizontal direction and may be formed as a periodic array having uniform width and uniform spacing along a horizontal direction perpendicular to the first horizontal direction. As used in the third embodiment, the first horizontal direction is the direction of elongation of the sacrificial rail structure. The first horizontal direction in the present embodiment may be different from the bit line direction by 10 to 80 degrees (i.e., extend in the "XY" direction), or may be parallel to the bit line direction (i.e., extend in the "Y" direction), as shown in fig. 40A and 40B, respectively. Each sacrificial rail structure 144 may have a substantially rectangular horizontal cross-sectional shape that is invariant under translation along the first horizontal direction.

Referring to fig. 41, an optional dielectric etch stop layer 145 and an optional source connection layer 146 may be formed over the layer of matrix material 138 and the plurality of sacrificial rail structures 144. Optional dielectric etch stop layer 145 comprises a dielectric material such as silicon oxide, silicon nitride, or a dielectric metal oxide such as aluminum oxide, and may be deposited by a conformal or non-conformal deposition process. The thickness of dielectric etch stop layer 145 may range from 1nm to 10nm, although lesser and greater thicknesses may also be employed.

The optional source connection layer 146 comprises a conductive material, which may be a heavily doped semiconductor material having the same conductivity type doping as the matrix material layer 138, or may be a metallic material, such as an elemental metal, an intermetallic alloy, a metal-semiconductor alloy (such as a metal silicide), or a conductive metal nitride (such as WN, TiN, or TaN). In one embodiment, the source connection layer 146 may include a material having a thickness greater than 10⁵Doped semiconductor material of conductivity S/cm, such as polysilicon, such as heavily doped silicon. The thickness of the source connection layer 146 may range from 50nm to 500nm, although lesser and greater thicknesses may also be employed. The source connection layer 146 may be used to provide a conductive structure that is electrically shorted to a source conductive layer to be subsequently formed and extends to the contact area 300 to enable electrical contact between the source connection layer 146 and the contact via structure to be subsequently formed. A source connecting layer 146 comprising a conductive material between the plurality of sacrificial rail structures 144 and the substrateOver the layer 138.

Referring to fig. 42, 43A and 43B, a memory recess 149 is formed through the optional source connection layer 146, the optional dielectric etch stop layer 145 and the sacrificial rail structure 144 and partially through the layer of matrix material 138. Fig. 43A is a top view of the third exemplary structure of fig. 42 in a first exemplary configuration. Fig. 43B is a top view of the third exemplary structure of fig. 42 in a second exemplary configuration. For example, the memory recess 149 may be formed by applying a photoresist layer over the optional source connection layer 146, photolithographically patterning a periodic array of openings in the photoresist layer, and transferring the pattern in the photoresist layer through the optional source connection layer 146, the optional dielectric etch stop layer 145, and the sacrificial rail structure 144 and partially through the matrix material layer 138 by an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing.

Each memory recess 149 may be a cavity having a substantially uniform horizontal cross-sectional shape that is invariant under vertical translation. The substantially uniform horizontal cross-sectional shape may be circular, elliptical, generally elliptical, polygonal, or may have any other shape that encloses the periphery of a curve. The memory recesses 149 may be formed in clusters. Each cluster of memory recesses 149 may be arranged in a two-dimensional periodic array, such as a hexagonal array. Adjacent arrays of memory recesses 149 may be separated from each other by a gap 179, which gap 179 may extend laterally in a direction different from the first horizontal direction. For example, the gap 179 may extend in a word line direction (i.e., an "X" direction) that is perpendicular to a bit line direction (i.e., perpendicular to a "Y" direction). In a first configuration, the direction along which the gaps 179 between adjacent arrays of memory recesses 149 extend horizontally may be at a non-zero non-orthogonal angle (such as 10 to 80 degrees, e.g., 60 degrees as shown in fig. 43A) relative to the first horizontal direction. In the second configuration, the direction in which the gaps 179 between adjacent arrays of memory recesses 149 extend horizontally may be parallel to the bit line direction and perpendicular to the first horizontal direction, i.e., perpendicular to the length direction of the sacrificial rail structures 144.

The orientation of each array of memory recesses 149 may be selected such that each of the memory recesses bridges an interface between a respective sacrificial rail structure 144 and the layer of matrix material 138. In one embodiment, the recessed sidewalls of the sacrificial rail structures 144, the recessed sidewalls of the matrix material layer 138, and the recessed planar surfaces of the matrix material layer 138 may be physically exposed around each memory recess 149. The degree of azimuthal angle of each physically exposed concave sidewall of the sacrificial rail, as measured from one vertical edge to the other, may be in the range of from about 45 degrees to about 270 degrees, relative to a vertical axis passing through the geometric center of the corresponding memory concave 149 to which the concave sidewall of the sacrificial rail structure 144 is physically exposed, although lesser and greater azimuthal angles may also be employed. In one embodiment, each array of memory dimples 149 can be oriented such that the longitudinal direction of the sacrificial rail structure 144 is parallel to the direction in which the nearest neighbor memory dimple 149 is aligned, or parallel to the direction in which the second nearest neighbor memory dimple 149 is aligned. Thus, rows of memory recesses 149 aligned along the first horizontal direction may bridge the interface between the respective sacrificial rail structures 144 and the layer of matrix material 138.

The position, size, shape, and orientation within the horizontal plane of each memory recess 149 may be the same as the position, size, shape, and orientation within the horizontal plane through at least one corresponding memory opening to be subsequently formed in a subsequent process. In one embodiment, the same photolithographic mask may be used to form the memory recess 149 at this processing step, so as to form a memory opening through the respective alternating stack at a subsequent processing step.

Referring to fig. 44, the isolation dielectric layer 148 may be formed by a non-conformal deposition process such as high density plasma chemical vapor deposition (HDP CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). The dielectric material of the isolation dielectric layer 148 is deposited at a thickness on horizontal surfaces that is greater than the thickness on vertical surfaces, and each memory recess 149 is encapsulated by a portion of the deposited dielectric material grown from an upper periphery of the memory recess 149. A memory cavity 147 sealed by the dielectric material of the isolation dielectric layer 148 may be formed within each memory recess 149. The isolation dielectric layer 148 extends continuously over the source connection layer 146 without passing through any openings. Alternatively, the memory recess 149 may be conformally filled with at least one insulating material. Further alternatively, the memory recess 149 may be conformally or non-conformally filled with any sacrificial material, which may be a semiconductor material or a conductive material. In one embodiment, the material filling the memory recess 149 may be a material that acts as an etch stop material relative to the material of the matrix material layer 138.

Referring to fig. 45, the isolation dielectric layer 148 is planarized, for example by Chemical Mechanical Planarization (CMP), to remove the divots covering the memory cavities 147. After the planarization process, the top surface of the isolation dielectric layer 148 may be planar, i.e., in the horizontal plane. The thickness of the isolation dielectric layer 148 above the source connection layer 146 may be in the range from 60nm to 300nm, although lesser and greater thicknesses may also be employed.

Referring to fig. 46, a first alternating stack of first insulating layers 32 and first spacer material layers 42 may be formed over an isolation dielectric layer 148. The first alternating stack (32,42) may be the same as the alternating stacks (32,42) of the first and second embodiments. If the first alternating stack (32,42) includes all levels of control gate electrodes to be subsequently formed, the steps of fig. 6 may be performed to form an insulating capping layer 70. The formation of the insulating cap layer 70 may be delayed if any additional alternating stacks are subsequently formed.

Referring to fig. 47, a first memory opening 49 may be formed through the volume of the first alternating stack (32,42) and the underlying layers of the isolation dielectric layer 148 and the memory recess 149. Fig. 48A is a top view of the third exemplary structure of fig. 47 in a first exemplary configuration for a sacrificial rail structure 144. Fig. 48B is a top view of the third exemplary structure of fig. 47 in a second exemplary configuration for a sacrificial rail structure 144. In one embodiment, the pattern of first memory openings 49 may be the same as the pattern of memory recesses 149. In other words, the periphery of the first memory opening 49 in the horizontal cross-sectional view may overlap the periphery of the memory recess 149 within the tolerances of the overlay variation and Critical Dimension (CD) variation inherent in lithographic alignment.

The same anisotropic etch process used to form the memory openings 49 of the first or second embodiments may be employed to form the portions of the first memory openings 49 located at the level of the first alternating stack (32, 42). The anisotropic etch may then be extended with the etch chemistry changed (or without changing the etch chemistry) to etch through the dielectric material of the isolation dielectric layer 148 to connect to the memory cavity 147. The anisotropic etch may continue until the dielectric material of the isolation dielectric layer 148 is removed from the recessed surfaces and sidewalls of the memory recesses 149. Alternatively, an isotropic etch (such as a wet etch) may be employed to remove the dielectric material of the isolation dielectric layer from the recessed surfaces and sidewalls of the memory recess. The photoresist layer may be subsequently removed, for example, by ashing. Alternatively, a bonding region having a wider lateral dimension than the underlying portion of the corresponding first memory opening 49 may be formed in the upper portion of the topmost insulating layer 32 using methods known in the art.

Referring to fig. 49, a semiconductor oxide liner 31 such as a silicon oxide liner (in the case where the source connection layer 146 includes a semiconductor material such as doped silicon) and a surface portion of the host material layer 138 (in the case where the host material layer 138 includes a semiconductor material such as doped silicon) may be formed at a bottom portion of each first memory opening 49 by oxidation of the surface portion of the source connection layer 146.

A first memory opening fill material is deposited into the first memory openings 49 by a conformal deposition process such as low pressure chemical vapor deposition. The first memory opening fill material comprises a material that is removable selective to the material of the first alternating stack (32,42) and the semiconductor oxide liner 31. For example, the first memory opening fill material may include a semiconductor material (such as polysilicon or amorphous silicon), a carbon-containing material (such as amorphous carbon or diamond-like carbon), an organic or inorganic polymer (such as a silicon-based polymer), or a porous or non-porous organosilicate glass. Excess portions of the first memory opening fill material are removed from over a topmost surface of the first alternating stack (32,42), for example, by chemical mechanical planarization. Each remaining portion of the first memory opening filling material in the first memory openings 49 constitutes a first memory opening filling portion 33. In one embodiment, the first memory opening filling portion 33 includes a semiconductor material. A stepped surface (not shown) may be formed through the first alternating stack (32,42) in the contact region 300. First backward stepped dielectric material portions (which may be the same as the backward stepped dielectric material portions 65 of the first and second embodiments) may be formed over the stepped surfaces of the first alternating stack (32, 42). The first alternating stack (32,42) and the embedded structures therein are collectively referred to as a first tier (tier) structure.

Referring to fig. 50, the process steps of fig. 46, 47 and 49 may optionally be repeated at least once to form at least another alternating stack (132,142,232,242) and at least one additional set of memory opening fill portions (133, 233). For example, the at least one additional alternating stack (132,142,232,242) may include a second alternating stack (132,142) including the second insulating layer 132 and the second spacer material layer 142, and a third alternating stack (232,242) including the third alternating layer 232 and the third spacer material layer 242. The composition and thickness of the second insulating layer 132 and the third insulating layer 232 may be the same as the first insulating layer 32. The composition and thickness of the second spacer layer 142 and the third spacer layer 242 may be the same as the first spacer layer 42.

After forming the second alternating stack (132,142), a second memory opening may be formed in an area overlying the first memory opening fill portion 33. In one embodiment, the pattern of the second memory opening may be the same as the pattern of the second memory opening filling portion 33 (which is the same as the pattern of the first memory opening 49). In other words, the periphery of the second memory opening in the horizontal cross-sectional view may overlap the periphery of the first memory opening 49 within the tolerance of the overlay variation and Critical Dimension (CD) variation inherent in lithographic alignment. The second memory opening filling part 133 is formed in the second memory opening. The second memory opening filling portion 133 may include any material that may be used for the first memory opening filling portion 33, and may include the same material as the first memory opening filling portion 33 or a different material. Stepped surfaces (not shown) may be formed through the second alternating stack (132,142) in the contact region 300. Second backward stepped dielectric material portions (not shown) may be formed over the stepped surfaces of the second alternating stacks (132, 142). The second alternating stack (132,142) and the embedded structures therein are collectively referred to as a second hierarchy.

A third alternating stack (232,242) may then be formed. If the third alternating stack (232,242) is the topmost alternating stack, an insulating cap layer 70 may be formed on top of the third alternating stack (232, 242). A stepped surface (not shown) may be formed through the third alternating stack (232,242) in the contact region 300. Third backward stepped dielectric material portions (not shown) may be formed over stepped surfaces of the third alternating stacks (232, 242). The third alternating stack (232,242) and the embedded structures therein are collectively referred to as a third hierarchical structure. The third memory opening 249 may be formed in a region covering the second memory opening filling part 133. In one embodiment, the pattern of the third memory openings 249 may be the same as the pattern of the second memory opening filling part 133 (which is the same as the pattern of the first memory openings 49). In other words, the periphery of the third memory opening 249 in the horizontal cross-sectional view may overlap the periphery of the second memory opening within the tolerance of the overlay variation and Critical Dimension (CD) variation inherent in lithographic alignment.

Although the present disclosure is described with an embodiment in which three alternating stacks are formed over substrate 8, a greater or lesser number of alternating stacks may be employed by repeating or not repeating the process sequence of fig. 46, 47, and 49.

Referring to fig. 51, the second memory opening filling portion 133 and the first memory opening filling portion 33 may be removed by at least one etching process selective to the materials of the alternating stack (32,42,132,142,232,242), the insulating cap 70, and the semiconductor oxide liner 31. Subsequently, the semiconductor oxide liner 31 may be removed, for example, by an isotropic etching process. Inter-layer level memory openings 349 may be formed through the third, second, and first layer levels and through source connection layer 146 and sacrificial rail structures 144 and partially through matrix material layer 138. Each inter-level memory opening 349 is a memory opening that extends through a multi-level structure. Where only a single alternating stack is employed, i.e., the first alternating stack (32,42), memory openings extending through the single alternating stack may be formed in place of the inter-level memory openings 349. Each of the inter-layer level memory openings 349 may bridge the interface between the respective sacrificial rail structure 344 and the matrix material layer 138.

In one embodiment, the concave sidewalls of the sacrificial rail structures 144, the concave sidewalls of the matrix material layer 138, and the concave planar surface of the matrix material layer 138 may be physically exposed to a bottom portion of each memory opening (such as each interlayer opening 349) extending between the top surface of the insulating cap layer 70 and the matrix material layer 138. The degree of azimuthal angle of each physically exposed concave sidewall of the sacrificial rail structure 144 (as measured from a vertical edge to another vertical edge) relative to a vertical axis passing through the geometric center of the respective memory opening to which the concave sidewall of the sacrificial rail structure 144 is physically exposed, such as the respective memory opening 349, may be in the range from about 45 degrees to about 270 degrees, although lesser and greater azimuthal angles may also be employed.

Referring to fig. 52, the process steps of fig. 8B-8D may be performed to form a memory stack structure 55, a dielectric core 62, and a drain region 63 within each of the inter-level memory openings 349. Each memory stack structure 55 includes a memory film 50 and a semiconductor channel 60. Each memory film 50 may have the same layer stack as in the first embodiment, or may have the same layer stack as in the second embodiment. Each memory stack structure 55 is formed through the alternating stack (32,42,132,142,232,242), and a portion of the sacrificial rail structure 144.

Optionally, additional structures (similar to element 87 shown in fig. 74, but not shown in fig. 52) and/or additional layers of dielectric material (not shown) such as drain side select gate electrodes may be formed over the insulating cap 70. Alternatively, one or more of the upper sacrificial material layers 42 may be replaced with a conductive layer 46 that serves as a drain-side select gate electrode, as will be described in more detail below. Optionally, a contact level dielectric layer 80 comprising a dielectric material may be formed over the insulating capping layer 70.

Referring to fig. 53, 54A and 54B, a backside trench 79 may be formed through the contact level dielectric layer 80, the insulating cap layer 70, the level structure and the isolation dielectric layer 148. For example, a photoresist layer (not shown) may be formed over the contact level dielectric layer 80 and may be lithographically patterned to form elongated openings, and an anisotropic etch may be performed to form openings through the contact level dielectric layer 80, the insulating capping layer 70, the level structure, and the isolation dielectric layer 148. In one embodiment, the source extension layer 146 may be used as an etch stop layer during the anisotropic etch. The backside trench 79 extends laterally along the direction of the gap between the arrays of memory stack structures 55. The longitudinal horizontal direction of the backside trench 79 is referred to herein as a second horizontal direction (e.g., a word line direction). The angle between the first horizontal direction (which is the longitudinal direction of the sacrificial rail structure 144) and the second horizontal direction may be non-zero and non-orthogonal as shown in fig. 54A, or may be orthogonal as shown in fig. 54B. In other words, the first horizontal direction in the present embodiment may be different from the bit line direction by 10 to 80 degrees (i.e., including the "XY" direction) as shown in fig. 54A, or it may be perpendicular to the word line direction (i.e., may include the "Y" direction perpendicular to the "X" direction) as shown in fig. 54B.

Referring to fig. 55A and 55B, a semiconductor spacer 172 and a dielectric spacer 174 may be sequentially formed at the periphery of each backside trench 79. The semiconductor spacers 172 comprise a semiconductor material such as polysilicon or amorphous silicon and may be formed by depositing a layer of doped semiconductor material in the backside trenches 79 and over the contact level dielectric layer 80, and then anisotropically etching the layer of doped semiconductor material by anisotropic etching to remove horizontal portions of the layer of doped semiconductor material, as shown in fig. 55B. In one embodiment, the thickness of the semiconductor spacers 172 may be in a range from 2nm to 20nm, although lesser and greater thicknesses may also be employed. Dielectric spacers 174 comprise a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride and may be formed by depositing a conformal dielectric material layer over semiconductor spacers 172 and then anisotropically etching the conformal dielectric material layer by anisotropic etching to remove horizontal portions of the conformal dielectric material layer, as shown in fig. 55B. In one embodiment, the thickness of the dielectric spacers 174 may be in the range from 2nm to 20nm, although lesser and greater thicknesses may also be employed. Alternatively, a stack of doped semiconductor material layers and conformal dielectric material layers may be formed sequentially, as shown in fig. 55A, and an anisotropic etch may be performed to remove horizontal portions of the stack of doped semiconductor material layers and conformal dielectric material layers to form a lateral stack of semiconductor spacers 172 and dielectric spacers 174, as shown in fig. 55B. A backside cavity 79' exists within each backside trench 79 within the pair of semiconductor spacers 172 and dielectric spacers 174.

Referring to fig. 56, 57A, and 57B, another anisotropic etch may be performed to etch through source connection layer 146 (where source connection layer 146 is employed) and physically expose a respective portion of the top surface of each sacrificial rail structure 144 under each backside trench 79. In the case where source connecting layer 146 includes a semiconductor material, semiconductor oxide spacers 176 may be formed on each physically exposed sidewall of source connecting layer 146 by oxidation of the physically exposed surface portion of source connecting layer 146. Thermal oxidation or plasma oxidation may be employed to form the semiconductor oxide spacers 176.

Referring to fig. 58, an isotropic etch may be performed to remove the sacrificial rail structures 144 from under the backside trenches 79. For example, if the sacrificial rail structures 144 comprise silicon nitride, a wet etch process using hot phosphoric acid may be used to remove the sacrificial rail structures 144 selective to the contact level dielectric layers 80, the insulating cap layer 70, the dielectric layer spacers 174, the semiconductor oxide spacers 176, the sacrificial liner 154, and the dielectric etch stop layer 145. A laterally extending cavity 143 is formed in the volume of the sacrificial rail structure 144 by removing the sacrificial rail structure 144. The matrix material layer 138 is not removed during the isotropic etch. Accordingly, the plurality of sacrificial rail structures 144 are removed selectively to the layer of matrix material 138 to form a plurality of laterally extending cavities 143.

Referring to fig. 59, portions of memory film 50 and portions of optional dielectric etch stop layer 145 that are physically exposed to laterally extending cavities 143 may be removed, for example, by a series of isotropic etch processes. For example, a series of isotropic etching processes that etch the material of the memory film 50, i.e., the material of the blocking dielectric layer (502, 503 of fig. 8C or 52 of fig. 25), the charge storage element layer (504 of fig. 8C or 54 of fig. 25), and the tunneling dielectric layer (506 of fig. 8C or 56 of fig. 25). During removal of memory film 50, sacrificial liner 154 and dielectric spacer 174 may be removed in parallel. A series of isotropic etch processes removes portions of memory film 50 physically exposed to laterally extending cavities 143 while not removing memory film 50 contacting matrix material layer 138. The sidewalls of the semiconductor channel 60 are exposed in the laterally extending cavity 143.

Subsequently, a source conductive layer may be formed. The source conductive layer (e.g., direct stripe contact type source electrode) may be formed using a non-selective semiconductor deposition process, as in the case of a first process sequence to be described later, or may be formed using a selective semiconductor deposition process, as in the case of a second process sequence to be described later. Fig. 60A, 60B, and 61-66 show a first processing sequence. Fig. 67-73 show a second processing sequence.

Referring to fig. 60A and 60B, steps of forming a layer 166L of doped semiconductor material are shown with a first processing sequence. Fig. 60A shows a third exemplary structure in the configuration shown in fig. 59 (i.e., in a configuration in which the drain select level gate electrode is not formed over the insulating cap layer 70 prior to forming the contact level dielectric layer 80).

Fig. 60B shows an alternative configuration of the third exemplary structure in which the drain select level gate electrode 87 is formed after forming the insulating cap layer 70 and before forming the contact level dielectric layer 80. In this case, drain select level semiconductor pillars 85, drain select level gate dielectric 82, drain select level gate electrode 87 may be formed over drain regions 63. A layer of drain select level dielectric material 802 and an optional layer of via level dielectric material 804 may be formed over the drain select level gate electrode 87. The layer of drain select level dielectric material 802 and the layer of via level dielectric material 804 are collectively referred to as the contact level dielectric material layer 80.

The layer of doped semiconductor material 166L comprises a doped semiconductor material such as doped polysilicon. In one embodiment, the doped semiconductor material layer 166L includes a material having a thickness greater than 1.0 x 10⁵A heavily doped semiconductor material of S/cm conductivity and having the same conductivity type as that of the matrix material layer 138 and the source connecting layer 146. The doped semiconductor material layer 166L may be deposited by a conformal deposition process such as Low Pressure Chemical Vapor Deposition (LPCVD). In one embodiment, the backside trench 79 may have a tapered profile such that a top portion of the backside trench 79 has a greater width than a bottom portion of the backside trench 79.

In one embodiment, the thickness of the doped semiconductor material layer 166L may be selected to be greater than half the width of the backside trench 79 at the bottom portion and less than half the width of the backside trench 79 at the top portion. The layer of doped semiconductor material 166L may be merged at the bottom of the backside trench 79 and not merged at the top of the backside trench 79. In this case, after formation of the doped semiconductor material layer 166L, a wedge-shaped backside cavity may be present within each backside trench 79. Each laterally extending cavity 143 may be at least partially filled by a layer 166L of doped semiconductor material. In one embodiment, package cavities 167 may be formed in the unfilled volume of each laterally extending cavity 143 below backside trench 79. In one embodiment, the layer of doped semiconductor material 166L may be formed directly on the inner surface of each semiconductor spacer 172.

Referring to fig. 61, an isotropic or anisotropic etch may be performed to remove portions of the doped semiconductor material layer 166L that are above a level that includes the bottom surface of the bottom-most spacer material layer (which may be the bottom-most sacrificial material layer 42). A vertical portion of the doped semiconductor material layer 166L may be removed from within each backside trench 79. Each remaining portion of the layer 166L of doped semiconductor material constitutes a source conductive layer 166 that serves as a source for a vertical field effect transistor that includes the semiconductor channel 60 within the memory stack structure 55. During the isotropic etch, semiconductor spacers 172 may be removed from over the top surface of source conductive layer 166. Any remaining portion of semiconductor spacer 172 may be located below the level of the topmost surface including source conductive layer 166.

A source conductive layer 166 is formed in the lower portion of the backside trench 79 and within the plurality of laterally extending cavities 143 and on the sidewalls of the semiconductor channel 60. Source conductive layer 166 may be formed through an opening in source connection layer 146 and may be formed directly on portions of the sidewalls and bottom surface of source connection layer 146.

Each source conductive layer 166 includes a plurality of conductive rail structures 166A extending along the first horizontal direction and laterally spaced apart from each other. A plurality of conductive rail structures 166A are formed in the plurality of laterally extending cavities 143. In other words, in this embodiment, the conductive rail structures 166A extend along a first horizontal direction, which may be 10 to 80 degrees different from the bit line direction and the word line direction (i.e., extend in the "XY" direction), or may be parallel to the bit line direction and perpendicular to the word line direction (i.e., may include the "Y" direction perpendicular to the X direction). Each source conductive layer 166 also includes a conductive strapping structure 166B extending along a second horizontal direction (e.g., in the word line "X" direction) different from the first horizontal direction. A conductive strapping structure 166B is formed in a lower portion of the backside trench 79. Each of the conductive rail structures 166A is adjacent to a conductive crossover structure 166B. A conductive crossover structure 166B is bridged across each of the conductive rail structures 166A. In other words, the conductive bridging structure 166B extends away from the longitudinal sidewall of each conductive track structure 166A extending along the first horizontal direction in both directions, thereby "bridging" the conductive track structures 166A. Each source conductive layer 166 is formed as a unitary structure, i.e., a single continuous structure.

Referring to fig. 62, a third exemplary structure is shown for the first processing sequence. Specifically, the semiconductor oxide portion 175 may be formed by converting a surface portion of the source conductive layer 166 into a semiconductor oxide material. For example, if source conductive layer 166 comprises doped polysilicon, then semiconductor oxide portion 175 may comprise doped silicon oxide. In one embodiment, the semiconductor oxide portion 175 may be formed on top of the conductive strapping structure 166B of the source conductive layer 166 and below the level of the bottommost spacer material layer (i.e., bottommost sacrificial material layer 42) within the alternating stack(s).

Referring to fig. 63, a backside recess 43 is formed by removing the spacer material layer (which may include the first sacrificial material layer 42, the second sacrificial material layer 142, and the third sacrificial material layer 242) selective to the insulating layer (32,132,232), the contact level dielectric layer 80, the insulating cap 70, and the semiconductor oxide portion 175. The same processing steps as those of fig. 14 or fig. 33 may be employed.

Referring to fig. 64, a backside blocking dielectric layer (not shown) may be conformally deposited in the backside recesses and on the sidewalls of the backside trenches 79. The conductive layer 46 and the continuous conductive material layer 46L may be formed by depositing at least one conductive material in the remaining volume of the backside recess 43, at peripheral portions of the backside trench 79, and over the contact level dielectric layer 80. The continuous conductive material layer 46L refers to portions of at least one conductive material deposited outside the backside recesses 43. The conductive layer 46 may be formed using the same process steps as those of fig. 15 or fig. 34.

Referring to fig. 65, the continuous conductive material layer 46L may be removed by recess etching (which may be isotropic etching, anisotropic etching, or a combination thereof). A backside cavity 79' exists over the semiconductor oxide portion 175 within each backside trench 79.

Referring to fig. 66, a dielectric material is deposited in the backside cavity 79' to form the dielectric spacer structure 78. For example, excess portions of the dielectric material deposited above a level including the top surface of the contact level dielectric material layer 80 may be removed by a planarization process that may employ chemical mechanical planarization or recess etching.

Referring to fig. 67, there is shown a first step of a second processing sequence which corresponds to the steps of fig. 67-73 and is employed in place of the first processing sequence corresponding to the steps of fig. 60A, 60B and 61-66. An isotropic etch may be performed on the third exemplary structure shown in fig. 59 to remove the semiconductor spacers 172 from the sidewalls of the backside trenches 79.

Referring to fig. 68, source conductive layer 166 may be formed by selective semiconductor deposition of doped semiconductor material. In this case, host material layer 138 includes a doped semiconductor material, and the doped semiconductor material of source conductive layer 166 has a doping of the same conductivity type as host material layer 138.

During a selective semiconductor deposition process, a semiconductor precursor gas (such as silane, disilane, dichlorosilane, trichlorosilane, germane, etc.), a dopant gas (such as diborane, phosphine, arsine, stibine, etc.), and an etchant gas (such as gaseous hydrogen chloride) may be flowed simultaneously or in a repeating sequence into a process chamber having at least one optional carrier gas (such as hydrogen, nitrogen, and/or argon). The amorphous surfaces, such as the dielectric surfaces of the insulating layer 32, the sacrificial material layers (42, 142, 242), the insulating cap layer 70, and the contact level dielectric layer 80, provide a lower deposition rate for semiconductor material relative to crystalline or semiconductor surfaces, such as the polycrystalline semiconductor surfaces of the matrix material layer 138 and the optional source connection layer 146. By setting the etch rate of the etchant gas (e.g., by selecting a suitable flow rate of the etchant gas) between the deposition rate of the semiconductor material on the amorphous surface and the deposition rate of the semiconductor material on the crystalline semiconductor surface, the doped semiconductor material may grow only from the crystalline semiconductor surfaces of the host material layer 138 and the optional source connection layer 146, and not from the dielectric surfaces of the insulating layer 32, the sacrificial material layer (42, 142, 242), the insulating cap layer 70, and the contact-level dielectric layer 80.

Thus, the selective semiconductor material deposition process deposits doped semiconductor material (e.g., polysilicon) on the semiconductor surface and does not grow from the dielectric surface. Source conductive layer 166 may be formed through an opening in source connection layer 146 and may be formed directly on portions of the sidewalls and bottom surface of source connection layer 146.

Each source conductive layer 166 includes a plurality of conductive rail structures 166A extending along the first horizontal direction and laterally spaced apart from each other. A plurality of conductive rail structures 166A are formed in the plurality of laterally extending cavities 143. Each source conductive layer 166 also includes a conductive strapping structure 166B extending along a second horizontal direction different from the first horizontal direction. As described above, the conductive jumper structure 166B is formed in the lower portion of the backside trench 79. Each source conductive layer 166 is formed as a unitary structure, i.e., a single continuous structure. In one embodiment, package cavity 167 may be formed in an unfilled volume of each laterally extending cavity 143 below backside trench 79.

Referring to fig. 69, the top surface of the conductive strapping structure 166B of the source conductive layer 166 may be optionally recessed to improve the planarity of the top surface of the source conductive layer 166 and to ensure that the top surface of the source conductive layer 166 is provided below the level including the bottom surface of the bottommost spacer material layer (i.e., the bottommost first sacrificial material layer 42).

Referring to fig. 70, the steps of fig. 62 may be performed to form a semiconductor oxide portion 175 by converting the top of source conductive layer 166 (e.g., the top of conductive strapping structure 166B) to a semiconductor oxide material, for example, by thermal oxidation or by plasma oxidation.

Referring to fig. 71, a backside recess 43 is formed by removing the spacer material layer (which may include the first sacrificial material layer 42, the second sacrificial material layer 142, and the third sacrificial material layer 242) selective to the insulating layer (32,132,232), the insulating cap 70, and the semiconductor oxide portion 175. The same processing steps as those of fig. 14 or fig. 33 may be employed.

Referring to fig. 72, a backside blocking dielectric layer (not shown) may be conformally deposited in the backside recesses and on the sidewalls of the backside trenches 79. The conductive layer 46 and the continuous conductive material layer 46L may be formed by depositing at least one conductive material in the remaining volume of the backside recess 43, at the peripheral portion of the backside trench 79, and over the insulating cap 70. The continuous conductive material layer 46L refers to the portion of the at least one conductive material deposited outside the backside recess. The same processing steps as those of fig. 15 or fig. 34 may be employed to form the conductive layer 46.

Referring to fig. 73, the continuous conductive material layer 46L may be removed by a recess etch, which may be an isotropic etch, an anisotropic etch, or a combination thereof. A backside cavity exists over the semiconductor oxide portion 175 within each backside trench 79. A dielectric material is deposited in the backside cavity to form a dielectric spacer structure 78. For example, excess portions of the dielectric material deposited above the level including the top surface of the insulating cap 70 (above the level including the contact level dielectric material layer 80 in the case where the contact level dielectric material layer 80 is employed) may be removed by a planarization process, which may employ chemical mechanical planarization or a recess etch.

Referring to fig. 74, after formation of the dielectric spacer structure 78, a vertical cross-sectional view of an alternate embodiment of the third exemplary structure is shown (including the drain select level gate electrode 87).

FIGS. 75A-75E provide horizontal cross-sectional views of the third exemplary structure in a first configuration (in which the first and second horizontal directions are not orthogonal with respect to each other), along the various horizontal cross-sections A-A ', B-B ', C-C ', D-D ', and E-E ' shown in FIG. 74.

FIGS. 76A-76E provide horizontal cross-sectional views of the third exemplary structure in a second configuration (in which the first and second horizontal directions are orthogonal to each other), along the various horizontal cross-sections A-A ', B-B ', C-C ', D-D ', and E-E ' shown in FIG. 74. The position of the bit line 90 is shown in dashed lines in fig. 74, 75E, and 76E. The bit lines 90 extend in a bit line (e.g., "Y") direction that may be perpendicular to a word line (e.g., "X") direction and extend parallel to a first horizontal direction that is an elongated direction of the conductive rail structures 166A or extend 10 to 80 (such as 30 to 60) degrees different from the first horizontal direction that is an elongated direction of the conductive rail structures 166A. The bit lines 90 are electrically connected to the drain regions through respective drain contact via contact structures 88. In this third embodiment, the matrix material layer 138 serves as a support structure (e.g., support base structure) as described above for the first and second embodiments.

Various example structures of the present disclosure may include a three-dimensional memory device. The three-dimensional memory device may include: an alternating stack of conductive layers 46 and insulating layers (32,132 (if present) 232 (if present)) over the substrate 8; an array of memory stack structures 55, each memory stack structure 55 extending through the alternating stack and comprising a memory film 50 and a semiconductor channel 60 laterally surrounded by the memory film 50; and a source conductive layer (76L, 150, 166) contacting a bottom portion of the sidewalls of each semiconductor channel 60 and located between the alternating stack and the substrate 8. The source conductive layer (76L, 150, 166) may be a layer of doped semiconductor material.

In one embodiment, the source conductive layer 166 includes: a plurality of conductive rail structures 166A extending along a first horizontal direction and laterally spaced apart from one another; and a conductive bridging structure 166B extending along a second horizontal direction different from the first horizontal direction, wherein each of the conductive rail structures 166A is adjacent to the conductive bridging structure 166B. The conductive rail structure 166A may serve as a source region of the memory device or as a source electrode if a doped source region is formed in the bottom of the semiconductor channel 60.

In one embodiment, the three-dimensional memory device may include a support structure including a layer of matrix material 138 laterally surrounding a bottom portion of each of the memory stack structures. A plurality of conductive rail structures 166A are located in a plurality of channels 141 in the matrix material layer 138 extending along the first horizontal direction.

In one embodiment, the convex sidewalls and bottom surface of each memory film 50 contact the layer of matrix material 138. In one embodiment, the convex sidewall of each semiconductor channel 60 contacts the concave sidewall of a respective conductive rail structure 166A, wherein an azimuthal angle between two vertical edges of a contact area between the convex sidewall and the respective conductive rail structure 166A, measured about a vertical axis passing through a geometric center of the memory stack structure 55 including the semiconductor channel, is in a range of 45 degrees to 270 degrees. In one embodiment, the host material layer 138 comprises a first doped semiconductor material and is electrically shorted to the source conductive layer 166. In one embodiment, the entire source conductive layer 166 may be a unitary structure that extends continuously throughout each portion of the source conductive layer 166 and includes a second doped semiconductor material having the same conductivity type as the first doped semiconductor material.

In one embodiment, each sidewall of the plurality of conductive rail structures 166A includes a set of planar vertical sidewall portions that are adjoined to one another by a set of concave vertical sidewall portions, each planar vertical sidewall portion contacting the layer of matrix material 138, and each concave vertical sidewall portion contacting a respective semiconductor channel 60. In one embodiment, the entire bottom surface of the plurality of conductive rail structures 166A contacts the recessed surface of the matrix material layer 138 above a horizontal plane that includes the bottom surface of the matrix material layer 138.

In one embodiment, the conductive bridging structure 166B overlies each of the plurality of conductive rail structures 166A, abuts a top portion of each of the plurality of conductive rail structures 166A, and comprises the same conductive material as the plurality of conductive rail structures 166A.

The plurality of bit lines 90 extend along a bit line direction (i.e., the "Y" direction), and the conductive layer 46 includes word lines extending along a word line direction perpendicular to the bit line direction (i.e., along the "X" direction). The conductive strapping structures 166B also extend in a word line direction parallel to the word line direction and perpendicular to the bit line direction. In one embodiment, the first horizontal direction (i.e., the "XY" direction in which the conductive rail structures 166A extend) is different from both the word line direction and the bit line direction, such as 10 to 80 (e.g., 30 to 60) degrees. In other words, if the first horizontal direction is different from the word line direction by N degrees (e.g., 10 or 30 degrees), the first horizontal direction is different from the bit line direction by 90-N degrees (e.g., 80 or 60 degrees). In another embodiment, the first horizontal direction is parallel to the bit line direction and the conductive rail structures 166A are parallel to the bit lines 90.

Source connection layer 146 may be located between the plurality of conductive rail structures 166A and the alternating stack. The source connection layer 146 may contact sidewalls of the conductive strapping structure 166B and may laterally surround the memory stack structure 55.

Peripheral device 210 may be located beneath memory array region 100 containing memory stack structure 55 or in an adjacent peripheral device region 200 and electrically contacted to source connection layer 146 using additional electrical contacts (not shown).

The dielectric spacer structures 78 comprising the dielectric material may extend vertically through the entire alternating stack and may cover the entire area of the conductive crossover structure 166B. The dielectric material of the dielectric spacer structure 78 produces less mechanical stress from inside the backside trench 79 than a comparable volume of the metal material portion inside the backside trench 79. Thus, by providing the dielectric spacer structure 78 instead of the metal material portion in the backside trench, mechanical stress of the three-dimensional memory device may be mitigated.

In one embodiment, the three-dimensional memory device comprises a vertical NAND device located above the substrate 8, the conductive layers 46 comprise or are electrically connected to respective word lines of the NAND device, and the substrate 8 may comprise a silicon substrate. In one embodiment, the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over a silicon substrate, at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings, and the silicon substrate contains an integrated circuit comprising driver circuitry for the memory device located thereon. In one embodiment, the conductive layer 46 includes a plurality of control gate electrodes having a stripe shape extending substantially parallel to the top surface of the substrate (e.g., along a first horizontal direction between pairs of the backside trenches 79), and the plurality of control gate electrodes may include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. In one embodiment, an array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels 60, wherein at least one end of each of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the substrate; and a plurality of charge storage elements (e.g., embodied as portions of the charge storage element layers (504, 54)). Each charge storage element may be located adjacent a respective one of the plurality of semiconductor channels 60.

The source conductive layer (76L, 150, 166) of various embodiments of the present disclosure may serve as a common source for a vertical field effect transistor that includes the semiconductor channel 60 within the memory stack structure 55. By avoiding the formation of metal structures within backside trench 79, the mechanical stress level of the three-dimensional memory device can be significantly reduced. The source conductive layer (76L, 150, 166) may be contacted by a source electrode contact via structure (not shown) that may be provided in the contact region 300.

While specific preferred embodiments have been mentioned above, it will be understood that the invention is not limited thereto. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present invention. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of conductive layers and insulating layers over a substrate;

an array of memory stack structures, each memory stack structure extending through an alternating stack and comprising a memory film and a semiconductor channel laterally surrounded by the memory film;

a support structure located between the stack structures and the substrate, the support structure comprising a layer of matrix material laterally surrounding a bottom portion of each of the memory stack structures;

a source conductive layer located below the stacked structure and above the substrate and contacting the support structure; and

a conductive rail structure extending along a first horizontal direction, contacting a top surface of the source conductive layer, and contacting sidewalls of the semiconductor channel.

2. The three-dimensional memory device of claim 1, wherein the source conductive layer further comprises a conductive strapping structure extending along a second horizontal direction different from the first horizontal direction, wherein each of the conductive rail structures is adjacent to the conductive strapping structure.

3. The three-dimensional memory device of claim 1, wherein:

the plurality of conductive track structures are located in a plurality of channels extending along a first horizontal direction in the layer of matrix material; and

the convex sidewall and bottom surface of each memory film contact the layer of matrix material.

4. The three-dimensional memory device of claim 1, wherein the convex sidewall of each semiconductor channel contacts the concave sidewall of a respective conductive rail structure, wherein an azimuthal angle between two vertical edges of a contact area between the convex sidewall and the respective conductive rail structure as measured around a vertical axis passing through a geometric center of a memory stack structure including the semiconductor channel is in a range of 45 degrees to 270 degrees.

5. The three-dimensional memory device of claim 1, wherein:

the host material layer comprises a first doped semiconductor material and is electrically shorted to the source conductive layer; and is

The entire source conductive layer is a unitary structure that extends continuously throughout each portion of the source conductive layer and includes a second doped semiconductor material having the same conductivity type as the first doped semiconductor material.

6. The three-dimensional memory device of claim 1, wherein:

each sidewall of the plurality of conductive track structures comprises a set of planar vertical sidewall portions adjoined to one another by a set of concave vertical sidewall portions;

each of the planar vertical sidewall portions contacts the layer of matrix material;

each of the concave vertical sidewall portions contacts a respective semiconductor channel; and is

The entire bottom surface of the plurality of conductive rail structures contacts the recessed surface of the matrix material layer above a horizontal plane including the bottom surface of the matrix material layer.

7. The three-dimensional memory device of claim 2, wherein the conductive crossover structure overlies each of the plurality of conductive rail structures, abuts a top portion of each of the plurality of conductive rail structures, and comprises a same conductive material as the plurality of conductive rail structures.

8. The three-dimensional memory device of claim 7, further comprising a plurality of bit lines extending along a bit line direction, wherein the conductive layer comprises word lines extending along a word line direction perpendicular to the bit line direction.

9. The three-dimensional memory device of claim 8, wherein:

the first horizontal direction is different from both the word line direction and the bit line direction; and

the conductive strapping structure extends in the word line direction.

10. The three-dimensional memory device of claim 8, wherein:

a first horizontal direction is parallel to the bit line direction; and

the conductive strapping structure extends in a word line direction.

11. The three-dimensional memory device of claim 2, further comprising:

a source connection layer between the plurality of conductive rail structures and the alternating stack, contacting sidewalls of the conductive strapping structures, and laterally surrounding the memory stack structures; and a dielectric spacer structure comprising a dielectric material, extending vertically through the entire alternating stack, and covering the entire area of the conductive strapping structure.

12. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device located above the substrate;

the conductive layers comprise or are electrically connected to respective word lines of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate includes an integrated circuit including driver circuitry for a memory device located thereon;

the conductive layer comprises a plurality of control gate electrodes having a strip shape extending substantially parallel to a top surface of the substrate, the plurality of control gate electrodes comprising at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level; and is

The array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the top surface of the substrate, an

A plurality of charge storage elements, each charge storage element located adjacent a respective one of the plurality of semiconductor channels.

13. A method of forming a three-dimensional memory device, comprising:

forming a host material layer over a substrate, the host material layer comprising a plurality of channels extending along a first horizontal direction;

forming a plurality of sacrificial rail structures in the plurality of trenches;

forming an alternating stack of insulating layers and spacer material layers over the matrix material layers and the sacrificial rail structures;

forming memory stack structures through portions of the alternating stacks and the sacrificial rail structures, wherein each of the memory stack structures includes a respective memory film and a respective semiconductor channel;

forming a back side trench extending through the alternating stack, wherein a surface of the sacrificial rail structure is physically exposed under the back side trench;

removing the plurality of sacrificial rail structures selective to the layer of matrix material to form a plurality of laterally extending cavities;

removing portions of the memory film physically exposed to the laterally extending cavities without removing portions of the memory film contacting the layer of matrix material; and

a source conductive layer is formed within a lower portion of the backside trench and the plurality of laterally extending cavities, and the source conductive layer contacts sidewalls of the semiconductor channel.

14. The method of claim 13, wherein the source conductive layer comprises:

a plurality of conductive track structures extending along a first horizontal direction and laterally spaced apart from one another and formed in the plurality of laterally extending cavities; and

a conductive strapping structure extending along a second horizontal direction different from the first horizontal direction and formed in a lower portion of the backside trench, wherein each of the conductive rail structures is adjacent to the conductive strapping structure.

15. The method of claim 13, further comprising forming memory openings through the alternating stack and through an upper portion of the layer of matrix material, wherein each of the memory openings bridges an interface between a respective sacrificial rail structure and the layer of matrix material.

16. The method of claim 13, wherein the source conductive layer is formed by:

depositing a layer of doped semiconductor material in the plurality of laterally extending cavities and the backside trench using a conformal deposition process, wherein there is a backside cavity in the backside trench that is not filled with the layer of doped semiconductor material; and

isotropically removing a vertical portion of the layer of doped semiconductor material from within the backside trench, wherein a remaining portion of the layer of doped semiconductor material comprises the source conductive layer.

17. The method of claim 13, wherein:

the matrix material layer comprises a semiconductor material; and is

The source conductive layer is formed by a selective semiconductor material deposition process that deposits semiconductor material on the semiconductor surface and does not grow from the dielectric surface.

18. The method of claim 13, further comprising forming a source connection layer comprising a conductive material over the plurality of sacrificial rail structures and the layer of matrix material, wherein the alternating stack is formed over the source connection layer and the source conductive layer is formed through an opening in the source connection layer.

19. The method of claim 13, further comprising:

forming a semiconductor oxide portion on top of the source conductive layer and below a level of a bottommost spacer material layer within the alternating stack;

forming a backside recess by removing the layer of spacer material selective to the insulating layer; and is

A conductive layer is formed within the backside recess.

20. The method of claim 19, further comprising:

forming a backside cavity over the semiconductor oxide portion after forming the conductive layer; and

a dielectric separator structure is formed by filling the backside cavity with a dielectric material.

21. The method of claim 13, wherein:

the layer of spacer material is formed as or replaced by a conductive layer;

the substrate comprises a silicon substrate;

the conductive layer comprises a plurality of control gate electrodes having a strip shape extending substantially parallel to a top surface of the substrate, the plurality of control gate electrodes comprising at least a first control gate electrode located in the first device level and a second control gate electrode located in a second device level; and is

The array of monolithic three-dimensional NAND strings comprises: