KR20180040446A - Method for forming via contact - Google Patents
Method for forming via contact Download PDFInfo
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- KR20180040446A KR20180040446A KR1020160132402A KR20160132402A KR20180040446A KR 20180040446 A KR20180040446 A KR 20180040446A KR 1020160132402 A KR1020160132402 A KR 1020160132402A KR 20160132402 A KR20160132402 A KR 20160132402A KR 20180040446 A KR20180040446 A KR 20180040446A
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- via hole
- oxide layer
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 48
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000009713 electroplating Methods 0.000 claims abstract description 11
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000007789 sealing Methods 0.000 claims description 8
- 238000007743 anodising Methods 0.000 claims description 7
- 238000007745 plasma electrolytic oxidation reaction Methods 0.000 claims description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 239000008151 electrolyte solution Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000036571 hydration Effects 0.000 description 1
- 238000006703 hydration reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 비아 콘택 형성 방법에 관한 것으로, 보다 상세하게는 알루미늄 기판에 비아 콘택을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a via contact, and more particularly, to a method of forming a via contact in an aluminum substrate.
기판을 적층하여 고집적된 반도체 소자를 제조하는 경우 상부 기판의 배선과 하부 기판의 배선을 전기적으로 연결하는 비아 콘택이 필요하다. 상기 비아 콘택은 비아 홀(via hole)에 예컨대, 구리(Cu)와 같은 도전성 금속이 채워진 것으로, 통상적으로 도금(plating)에 의해 비아 홀에 도전성 금속이 채워진다. When a highly integrated semiconductor device is manufactured by laminating a substrate, a via contact for electrically connecting the wiring of the upper substrate and the wiring of the lower substrate is required. The via contact is filled with a conductive metal such as copper (Cu), for example, in a via hole, and the via hole is filled with a conductive metal by plating.
상기 비아 홀은 관통 비아 홀(through via hole), 블라인드 비아 홀(blind via hole), 및 베리드 비아 홀(buried via hole)로 구분된다. 상기 관통 비아 홀은, 기판을 두께 방향으로 관통하여 기판의 상측면과 하측면에 모두 개구(開口)가 형성된 비아 홀이며, 상기 블라인드 비아 홀은 기판의 상측면과 하측면 중 일 측면에만 개구가 형성되고 다른 일 측면까지는 관통하지 못한 비아 홀이며, 베리드 비아 홀은 기판의 내부에 형성되어 기판의 상측면 및 하측면에 개구가 형성되지 않은 비아 홀을 의미한다. The via hole is divided into a through via hole, a blind via hole, and a buried via hole. The through-via-hole is a via-hole that penetrates the substrate in the thickness direction and has openings on both upper and lower sides of the substrate. The blind via-hole has openings on only one side of the upper and lower sides of the substrate And the via via hole is a via hole formed in the inside of the substrate and having no opening formed on the upper and lower sides of the substrate.
한편, 종래에는 고집적된 반도체 소자의 소재로서 실리콘(Si) 기판이 주로 사용되었다. 그러나, 실리콘 기판은 원가가 높고 방열 특성이 좋지 않다는 문제가 있어서, 실리콘 기판을 다른 종류의 기판으로 대체하여 비아 콘택을 형성할 필요성이 있다.On the other hand, a silicon (Si) substrate has been mainly used as a material of a highly integrated semiconductor device. However, there is a problem in that the silicon substrate has a high cost and poor heat dissipation property, and it is necessary to replace the silicon substrate with another type of substrate to form a via contact.
본 발명은 알루미늄(Al)을 주성분으로 하는 알루미늄 기판에 비아 콘택을 형성하는 방법을 제공한다. The present invention provides a method of forming a via contact on an aluminum substrate (Al) as a main component.
본 발명은, 실리콘(Si) 기판를 사용하는 경우보다 원가가 절감되고, 방열 특성도 우수한 비아 콘택 형성 방법을 제공한다.The present invention provides a via contact forming method which is more economical than the case of using a silicon (Si) substrate and has excellent heat radiation characteristics.
본 발명은, 순수 알루미늄(Al) 및 알루미늄 합금 중의 하나를 재질로 하는 알루미늄 기판의 표면을 산화시켜 산화알루미늄(Al2O3)으로 이루어진 산화물층을 형성하는 산화물층 형성 단계, 상기 산화물층에 그 표면으로부터 두께 방향으로 연장된 비아 홀(via hole)을 생성하는 비아 홀 생성 단계, 상기 비아 홀의 내주면에 금속을 증착하여 전해 도금용 시드층(seed layer)를 형성하는 시드층 형성 단계, 상기 시드층 상에 금속을 전해 도금하여 상기 비아 홀 내부에 금속을 채우는 전해 도금 단계, 및 상기 알루미늄 기판을 연마하여, 상기 비아 홀 내부에 도금된 금속만 남기고 상기 비아 홀 이외의 영역에 도금된 금속을 제거하는 연마 단계를 포함하고, 상기 비아 홀은 상기 산화물층의 경계를 넘어 연장되지 않는 비아 콘택 형성 방법을 제공한다. The present invention relates to an oxide layer forming step of forming an oxide layer made of aluminum oxide (Al 2 O 3 ) by oxidizing a surface of an aluminum substrate made of one of pure aluminum (Al) and aluminum alloy, Forming a seed layer for electroplating by depositing a metal on an inner circumferential surface of the via hole to form a via hole extending in a thickness direction from a surface of the via hole; And plating the aluminum substrate to leave only the plated metal in the via hole and to remove the plated metal in the region other than the via hole, And a via hole, wherein the via hole does not extend beyond the boundary of the oxide layer.
상기 산화물층 형성 단계는, 상기 알루미늄 기판을 양극 산화하여 표면에 미세공(孔)이 형성된 산화물층을 형성하는 양극 산화 단계, 및 상기 미세공을 폐쇄하는 봉공(封孔) 처리 단계를 구비할 수 있다. The oxide layer forming step may include an anodizing step of anodizing the aluminum substrate to form an oxide layer having micropores formed on its surface, and a sealing process step of closing the micropores have.
상기 산화물층 형성 단계는, 플라즈마 전해 산화(PEO: plasma electrolytic oxidation)에 의해 상기 산화물층을 형성하는 단계를 구비할 수 있다. The oxide layer forming step may include a step of forming the oxide layer by plasma electrolytic oxidation (PEO).
상기 산화물층의 두께는 5 내지 200㎛ 일 수 있다. The thickness of the oxide layer may be 5 to 200 mu m.
상기 비아 홀 생성 단계는, 상기 산화물층의 표면에 레이저(laser)를 조사하여 상기 비아 홀을 생성하는 단계를 구비할 수 있다.The via hole forming step may include a step of irradiating a laser on the surface of the oxide layer to generate the via hole.
본 발명에 의해 형성된 비아 콘택은 실리콘 웨이퍼(wafer)보다 저렴한 알루미늄 재질의 기판에 형성된다. 따라서, 실리콘 기판에 비아 콘택을 형성하는 것보다 비용이 절감되고, 공정도 단순하여 생산성도 향상된다. 또한, 실리콘보다 방열 특성이 우수한 알루미늄 재질의 기판에 비아 콘택이 형성되므로, 비아 콘택을 구비한 반도체 소자를 제조한 경우에도 방열 특성이 향상되어 반도체 소자 성능의 신뢰성이 향상된다.The via contact formed by the present invention is formed on a substrate made of aluminum which is less expensive than a silicon wafer. Therefore, the cost is reduced, the process is simplified, and the productivity is improved as compared with the case of forming the via contact in the silicon substrate. In addition, since the via contact is formed on the substrate made of aluminum excellent in heat dissipation property than silicon, even when the semiconductor element having the via contact is manufactured, the heat dissipation property is improved and the reliability of the semiconductor element performance is improved.
도 1 내지 도 4는 본 발명의 실시예에 따른 비아 콘택 형성 방법을 순차적으로 도시한 단면도이다.1 to 4 are sectional views sequentially illustrating a via contact forming method according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 따른 비아 콘택 형성 방법을 상세하게 설명한다. 본 명세서에서 사용되는 용어(terminology)들은 본 발명의 바람직한 실시예를 적절히 표현하기 위해 사용된 용어들로서, 이는 사용자 또는 운용자의 의도 또는 본 발명이 속하는 분야의 관례 등에 따라 달라질 수 있다. 따라서, 본 용어들에 대한 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.Hereinafter, a method of forming a via contact according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The terminology used herein is a term used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of the user or operator or the custom in the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.
도 1 내지 도 4는 본 발명의 실시예에 따른 비아 콘택 형성 방법을 순차적으로 도시한 단면도이다. 본 발명의 실시예에 따른 비아 콘택 형성 방법은, 산화물층 형성 단계, 비아 홀(via hole) 생성 단계, 시드층(seed layer) 형성 단계, 전해 도금 단계, 및 연마 단계를 구비한다. 도 1을 참조하면, 상기 산화물층 형성 단계는, 알루미늄 기판(50)의 표면(51)을 산화시켜 산화알루미늄(Al2O3)으로 이루어진 산화물층(55)을 형성하는 단계이다. 상기 알루미늄 기판(50)은 순수 알루미늄(Al) 재질로 이루어지거나, 알루미늄 합금 재질로 이루어진다. 알루미늄 기판(50)의 두께는 0.1mm 내지 2mm 일 수 있다.1 to 4 are sectional views sequentially illustrating a via contact forming method according to an embodiment of the present invention. A via contact forming method according to an embodiment of the present invention includes an oxide layer forming step, a via hole forming step, a seed layer forming step, an electrolytic plating step, and a polishing step. Referring to FIG. 1, the oxide layer forming step is a step of oxidizing the
상기 산화물층 형성 단계는, 알루미늄 기판(50)을 양극 산화(anodizing)하여 표면에 다수의 미세공(孔)(미도시)이 형성된 산화물층(55)을 형성하는 양극 산화 단계, 및 상기 다수의 미세공을 폐쇄하는 봉공(封孔) 처리 단계를 구비한다. 상기 양극 산화 단계는 알루미늄을 주성분으로 포함하는 소재, 즉 알루미늄 소재의 표면에 산화알루미늄(Al2O3)의 피막을 형성하는 것으로, 상기 알루미늄 소재를 예컨대, 황산, 수산, 크롬산과 같은 전해액 내에서 양극(anode)으로 하고 통전(通電)시켜 알루미늄 소재의 표면을 산화시키는 것이다.The oxide layer forming step includes an anodizing step of anodizing the
양극 산화 단계에 의해 형성된 산화알루미늄(Al2O3) 피막의 표면에는 다수의 미세공(미도시)이 형성된다. 이 미세공에 불순물이 침투하여 표면이 더러워지기 쉽고, 상기 미세공에 상기 전해액의 잔류물이 침투하여 부식을 초래할 수도 있다. 따라서, 상기 산화물층 형성 단계 이후에 상기 봉공 처리 단계가 수행된다. A large number of micropores (not shown) are formed on the surface of the aluminum oxide (Al 2 O 3 ) film formed by the anodic oxidation step. Impurities penetrate into the micropores, and the surface of the micropores tends to be dirty, and the micropores may penetrate the electrolyte solution to cause corrosion. Therefore, the sealing step is performed after the oxide layer forming step.
봉공 처리의 방법 중에서 물(H2O) 이외의 성분을 필요로 하지 않아 비교적 간단하게 수행할 수 있는 수화 봉공 처리(水化 封孔 處理) 방법이 주로 적용된다. 수화 봉공 처리 방법에는 뜨거운 물에 양극 산화된 알루미늄을 침지(浸漬)하여 봉공 처리하는 방법과, 수증기(水蒸氣)로 채워진 챔버(chamber) 내에 양극 산화된 알루미늄을 두어 봉공 처리하는 방법이 있다. A hydration sealing treatment method is mainly applied in which the components other than water (H 2 O) are not required in the method of sealing treatment and can be relatively easily performed. The hydration-sealing method includes a method in which anodized aluminum is immersed in hot water to perform a seam treatment, and a method in which anodized aluminum is disposed in a chamber filled with water vapor to perform a seam treatment.
한편, 상기 산화물층 형성 단계는, 상기 양극 산화 단계와 상기 봉공 처리 단계를 대신하여, 플라즈마 전해 산화(PEO: plasma electrolytic oxidation)에 의해 상기 산화물층을 형성하는 단계를 구비할 수도 있다. 플라즈마 전해 산화는 알루미늄 소재를 전해액에 침잠시키고, 300 내지 600V의 고전압 펄스를 인가하여 알루미늄 소재의 표면을 산화시키는 방법이다. 상기 고전압 펄스의 인가로 알루미늄 소재의 표면에서 플라즈마가 발생하고, 이에 의해 용융된 알루미늄 소재의 표면이 산화되면서 산화알루미늄(Al2O3)으로 된 산화물층(55)이 형성된다.The oxide layer forming step may include a step of forming the oxide layer by plasma electrolytic oxidation (PEO) instead of the anodizing step and the sealing step. Plasma electrolytic oxidation is a method in which an aluminum material is immersed in an electrolytic solution and a high-voltage pulse of 300 to 600 V is applied to oxidize the surface of the aluminum material. Plasma is generated on the surface of the aluminum material by the application of the high voltage pulse, whereby the surface of the molten aluminum material is oxidized to form an
상기 산화물층 형성 단계에서 상기 산화물층(55)의 두께를 5 내지 200㎛ 로 형성할 수 있다. 한편, 도 1에서는 알루미늄 기판(1)의 양 측면에 산화물층(55)이 형성되고, 그 사이에 알루미늄 또는 알루미늄 합금으로 된 알루미늄층(53)이 잔존한 알루미늄 기판(50)이 도시되어 있으나, 본 발명이 이에 한정되는 것은 아니다. 부연하면, 알루미늄 기판의 양 측면 중 일 측면에 전해액이 침투하지 못하도록 마스킹(masking)을 적층한 후에, 알루미늄 기판을 전해액에 침잠시켜 산화물층 형성 단계를 수행하면 알루미늄 기판의 일 측면에만 산화물층이 형성될 수 있다. In the oxide layer forming step, the thickness of the
도 2를 참조하면, 비아 홀 생성 단계는, 산화물층(55)에 그 표면(51)으로부터 두께 방향, 즉 Z축과 평행하게 연장된 비아 홀(57)을 생성하는 단계이다. 알루미늄 기판(50)(도 1 참조)에 형성된 산화물층(55)의 표면(51)에 레이저(laser)를 조사(照射)하여 비아 홀(57)을 생성할 수 있다. 비아 홀(57)은 산화물층(55)의 경계를 넘어 연장되지 않는다. 레이저 조사에 의해 비아 홀(57)을 형성하는 경우에 비아 홀(57)이 산화물층(55)과 알루미늄층(53) 사이의 경계를 넘어 알루미늄층(53)까지 연장되지 않도록 레이저의 출력과 조사 시간을 적절히 조절한다. 만약 비아 홀이 알루미늄층(53)까지 연장되면, 추후 단계에서 비아 홀 내부에 채워지는 금속과 알루미늄층(53) 간에 쇼트(short circuit)가 발생할 수 있다.2, the via hole forming step is a step of creating, in the
도 3을 참조하면, 상기 시드층 형성 단계는 비아 홀(57)의 내주면과, 비아 홀(57)의 입구(59)의 주변부와, 산화물층(55)의 표면(51)(도 2 참조)에 금속을 증착하여 전해 도금용 시드층(62)을 형성하는 단계이다. 상기 전해 도금 단계는 상기 시드층(62) 상에 금속(64)을 전해 도금하여 상기 비아 홀(57)(도 2 참조) 내부에 금속(64)을 채우는 단계이다. 상기 금속(64)은 예컨대, 구리(Cu)일 수 있다. 3, the step of forming the seed layer is performed by forming the inner surface of the
도 3 및 도 4를 함께 참조하면, 상기 연마 단계는 상기 알루미늄 기판(50)(도 1 참조)을 연마하여, 상기 비아 홀(57)(도 2 참조) 내부에 도금된 금속(64)만 남기고 상기 비아 홀(57) 이외의 영역에 도금된 금속(64)을 제거하는 단계이다. 상기 연마 단계는 CMP(chemical mechanical polishing) 방법을 적용하여 수행할 수 있다. 상기 비아 홀(57) 내부에 채워진 금속(64)이 비아 콘택(via contact)이 된다.3 and 4, the polishing step polishes the aluminum substrate 50 (see FIG. 1) to leave only the
이상에서 설명한 본 발명에 의해 형성된 비아 콘택은 실리콘 웨이퍼(wafer)보다 저렴한 알루미늄 기판(50)에 형성된다. 따라서, 실리콘 기판에 비아 콘택을 형성하는 것보다 비용이 절감되고, 공정도 단순하여 생산성도 향상된다. 또한, 실리콘보다 방열 특성이 우수한 알루미늄 기판(1)에 비아 콘택이 형성되므로, 비아 콘택을 구비한 반도체 소자를 제조한 경우에도 방열 특성이 향상되어 반도체 소자 성능의 신뢰성이 향상된다. The via contact formed by the present invention described above is formed on the
본 발명은 도면에 도시된 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 당해 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능함을 이해할 수 있을 것이다. 따라서 본 발명의 진정한 보호범위는 첨부된 특허청구범위에 의해서만 정해져야 할 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.
50: 알루미늄 기판 53: 알루미늄층
55: 산화물층 57: 비아 홀
62: 시드층 64: 금속50: aluminum substrate 53: aluminum layer
55: oxide layer 57: via hole
62: seed layer 64: metal
Claims (5)
상기 산화물층에 그 표면으로부터 두께 방향으로 연장된 비아 홀(via hole)을 생성하는 비아 홀 생성 단계;
상기 비아 홀의 내주면에 금속을 증착하여 전해 도금용 시드층(seed layer)를 형성하는 시드층 형성 단계;
상기 시드층 상에 금속을 전해 도금하여 상기 비아 홀 내부에 금속을 채우는 전해 도금 단계; 및,
상기 알루미늄 기판을 연마하여, 상기 비아 홀 내부에 도금된 금속만 남기고 상기 비아 홀 이외의 영역에 도금된 금속을 제거하는 연마 단계;를 포함하고,
상기 비아 홀은 상기 산화물층의 경계를 넘어 연장되지 않는 것을 특징으로 하는 비아 콘택 형성 방법.An oxide layer forming step of oxidizing a surface of an aluminum substrate made of one of pure aluminum (Al) and aluminum alloy to form an oxide layer made of aluminum oxide (Al 2 O 3 );
A via hole forming step of forming a via hole extending in the thickness direction from the surface of the oxide layer;
Depositing a metal on the inner peripheral surface of the via hole to form a seed layer for electroplating;
An electrolytic plating step of electroplating a metal on the seed layer to fill metal in the via hole; And
And a polishing step of polishing the aluminum substrate to remove only the metal plated in the via hole and to remove the plated metal in a region other than the via hole,
And the via hole does not extend beyond the boundary of the oxide layer.
상기 산화물층 형성 단계는, 상기 알루미늄 기판을 양극 산화하여 표면에 미세공(孔)이 형성된 산화물층을 형성하는 양극 산화 단계, 및 상기 미세공을 폐쇄하는 봉공(封孔) 처리 단계를 구비하는 것을 특징으로 하는 비아 콘택 형성 방법.The method according to claim 1,
The oxide layer forming step includes an anodizing step of anodizing the aluminum substrate to form an oxide layer having micropores formed on its surface, and a sealing step of closing the micropores Wherein the via contact is formed by a via contact.
상기 산화물층 형성 단계는, 플라즈마 전해 산화(PEO: plasma electrolytic oxidation)에 의해 상기 산화물층을 형성하는 단계를 구비하는 것을 특징으로 하는 비아 콘택 형성 방법.The method according to claim 1,
Wherein the forming of the oxide layer comprises forming the oxide layer by plasma electrolytic oxidation (PEO).
상기 산화물층의 두께는 5 내지 200㎛ 인 것을 특징으로 하는 비아 콘택 형성 방법.The method according to claim 1,
Wherein the oxide layer has a thickness of 5 to 200 占 퐉.
상기 비아 홀 생성 단계는, 상기 산화물층의 표면에 레이저(laser)를 조사하여 상기 비아 홀을 생성하는 단계를 구비하는 것을 특징으로 하는 비아 콘택 형성 방법.The method according to claim 1,
Wherein the via hole forming step comprises forming a via hole by irradiating a laser on a surface of the oxide layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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