KR20180022139A - E-fuse and semiconductor device including the same - Google Patents

Abstract

The present invention provides an e-fuse array having improved durability and a semiconductor device including the same. The semiconductor device of the present invention includes an e-fuse array including a first region and a second region; a first control part using first data stored in the first region; and a second control part accessing a second region more frequently than the first region and using second data stored in the second region.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an e-fuse and a semiconductor device including the same.

FIELD OF THE INVENTION The present invention relates to an e-fuse and a semiconductor device including the same, and more particularly, to an e-fuse having a structure for ensuring durability and a semiconductor device including the same.

An array electrical fuse (ARE) stores (programs) data by applying a high electric field to the gate of the transistor to rupture the gate insulating film. Such an E-fuse array is mainly used to set a specific value determined through testing of a semiconductor integrated circuit, and is particularly used to set an initial value when power is applied to a semiconductor device.

In general, a semiconductor device includes a large number of memory cells, and as the process technology develops, the degree of integration increases and the number of semiconductor devices increases. If any one of these memory cells is defective, the semiconductor device malfunctions. Therefore, the semiconductor device including the defective cell can not use the semiconductor device because it can not perform the desired operation.

However, as the process technology of semiconductor devices is developed these days, defects occur only in a small amount of memory cells. Due to such small defects, it is very inefficient to dispose of the entire semiconductor device as a defective product, considering the yield of the product. Therefore, in order to compensate for this, a semiconductor memory device is additionally provided with a redundant memory cell in addition to a normal memory cell.

A redundancy control circuit for switching connection to a cell included in a redundancy memory cell instead of a normal memory cell in which a defect occurs when a request for access to a specific normal memory cell occurs, Is used. That is, the redundancy memory cell is a memory cell provided for repairing a memory cell (hereinafter, referred to as a 'fail cell') in which a failure occurs in a normal memory cell.

Specifically, for example, when a fail cell is accessed in a read / write operation, a normal memory cell is accessed internally, not a fail cell. At this time, the memory cell to be accessed is a redundancy memory cell.

Accordingly, when the address of the fail cell is inputted, the semiconductor device is assured of normal operation by the operation for accessing the redundancy memory cell, which is not the fail cell (hereinafter referred to as "repair operation").

At this time, the e-fuse array is used to store the address of the redundancy memory cell corresponding to the fail cell described above.

The present invention seeks to provide an e-fuse array having improved durability and a semiconductor device including the same.

A semiconductor device according to an embodiment of the present invention includes: an e-fuse array including a first region and a second region; A first controller using first data stored in the first area; And a second controller accessing the second area by using more of the second data stored in the second area than the number of times the first area is accessed.

The e-fuse array according to an embodiment of the present invention includes a first region including a plurality of fuse cells including a first transistor and a second region including a plurality of fuse cells including a second transistor, The sizes of the first transistor and the second transistor are different.

According to an embodiment of the present invention, in an e-fuse array having different access counts for each region, the durability of the e-fuse array can be improved by having transistors having different sizes depending on regions.

1 illustrates a structure of an e-fuse array in accordance with an embodiment of the present invention;
Fig. 2 is a diagram showing a configuration of a semiconductor device including the e-fuse array of Fig. 1; Fig.
3 is a timing chart of a refresh operation performed in the second control unit of Fig. 2; Fig.
4 is an enlarged view of a section in which an additional refresh operation is performed;
FIG. 5A is a graph showing the relationship between the thickness of the gate oxide film of the transistor and the lifetime of the transistor, FIG. 5B is a graph showing the relationship between the gate length and the lifetime of the transistor, .

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

1 is a diagram illustrating the structure of an e-fuse array 100 according to an embodiment of the present invention.

Referring to FIG. 1, the eFuse array 100 includes a first region 110 and a second region 120.

The e-fuse array 100 has a configuration in which fuse cells 130 composed of program transistors and selection transistors are arranged in a matrix form.

A plurality of fuse cells 130 arranged in the row direction (the lateral direction in FIG. 1) are connected to a common word line. That is, the gates (PG) of the program transistors of the plurality of fuse cells 130 arranged in the row direction are commonly connected and the gates (SG) of the selection transistors of the plurality of fuse cells 130 arranged in the row direction are common Lt; / RTI >

A plurality of fuse cells 130 arranged in a column direction (the longitudinal direction in FIG. 1) are connected to a common bit line. That is, the source / drain of the selection transistor of the plurality of fuse cells 130 arranged in the column direction are connected in common.

The first region 110 and the second region 120 of the eFuse array 100 are arranged in the column direction of the eFuse array 100, for example. Thus, the first region 110 and the second region 120 may be word lines different and bit lines common.

In the first area 110, data having a smaller number of accesses than the data stored in the second area 120 is stored. For example, in the first area 110, initial setting values necessary for booting up the semiconductor device including the e-fuse array 100 can be stored. The initial set value may include, for example, an address of a fail cell required in a repair operation.

In the second area 120, data having a larger access frequency than the data stored in the first area 110 is stored. For example, the second region 120 may store the address of a cell that requires additional refresh.

The memory cell is implemented as a capacitor. That is, data is stored by the charge charged in the capacitor. Charges charged in these capacitors are discharged over time and data is lost. Therefore, a refresh operation for restoring the charge within a predetermined time to the memory cell must be performed.

A progressive failure may occur in such a memory cell and the refreshing ability value may become insufficient. In other words, data is lost before the set refresh operation is performed, because data stored in the memory cell is coupled to peripheral cells or the like, unlike a normal failure in which an error occurs in the read / write operation. The generated memory cell is called a wick cell.

The above-described weak cells can be remedied using a normal repair method, that is, a method having redundant memory cells of sufficient size. Specifically, a method may be considered in which a redundancy memory cell is additionally provided, and a weak cell is replaced with a redundancy memory cell (repair).

In this case, however, the size of the redundancy memory cell and the e-fuse array (i.e., the first area 110) for storing the addresses of the weak cell and the redundancy memory cell become large. As a result, the area of the chip becomes large and the number of dies per wafer decreases, and the yield decreases.

Therefore, in this embodiment, the address of the wiccell is stored in the second area 120, and additional refresh is performed on the wiccle.

2 is a diagram showing a configuration of a semiconductor device 10 including the e-fuse array 100 of FIG.

Referring to FIG. 2, the semiconductor device 10 includes a first region 110, a second region 120, a first latch portion 210, a second latch portion 220, a first control portion 310, 2 < / RTI >

The first area 110 and the second area 120 correspond to the first area 110 and the second area 120 of the e-fuse array 100 shown in FIG. Although the first region 110 and the second region 120 are shown as being separated in FIG. 2, they may be physically adjacent to each other.

In the first area 110, data having a smaller number of accesses than the second area 120, for example, a fail address and the address (redundancy address) of the corresponding redundancy memory cell are corrupted.

In the second area 120, data having a larger number of accesses than the first area 110, for example, the address of a wick cell, is corrupted.

The first latch unit 210 stores data (DATA_1) stored in the first area 110. The first latch unit 210 may store all data (DATA_1) stored in the first area 110 at the time of boot-up, for example.

The second latch unit 220 stores data (DATA_2) stored in the second area 120. The second latch unit 220 may store the specific data DATA_2 in the second area 120 based on the address control signal ADDR_CON_2 of the second control unit 320 described later.

The first controller 310 controls the semiconductor device 10 using the data DATA_1 stored in the first area 110. [

For example, the first control unit 310 may be a repair control unit. The data (DATA_1) laid out in the first area 110 may be the address of the fail cell. The address DATA_1 of the fail cell which is struck in the first area 110 may be stored in the first latch unit 210 at the boot-up time of the semiconductor device 10. [

The first control unit 310 performs a repair operation using the address DATA_1 of the fail cell stored in the latch unit 210. [

Specifically, the first control unit 310 transmits the first address control signal ADDR_CON_1 to the first latch unit 210 when an access to the specific memory cell is requested. The first latch unit 210 transmits the address (DATA_1) of the fail cell to the first control unit 310 in response to the first address control signal ADDR_CON_1.

The first control unit 310 generates a repair control signal REP_CON so as to access the redundant memory cell instead of the specific memory cell which is requested internally when the input address ADD matches the address DATA_1 of the fail cell.

The second controller 320 controls the semiconductor device 10 using data stored in the second area 120.

For example, the second control unit 320 may be a refresh control unit. In the second area 120, an address of a week cell may be stored. The second controller 320 controls the entire memory cells to refresh in a predetermined cycle, and further refreshes the weak cells in the memory cells.

Specifically, the second controller 320 transmits the second address control signal ADDR_CON_2 to the second area 120 in response to the refresh command REF. The second area 120 transmits data corresponding to the second address control signal ADDR_CON_2, that is, the address (DATA_2) of the wake cell, to the second latch unit 220.

The second control unit 320 reads the address DATA_2 of the wicule cell from the second latch unit 220 and generates the refresh control signal REF_CON so that additional refresh is performed on the address DATA_2 of the wake cell.

3 is a timing diagram of the refresh operation performed by the second control unit 320 of FIG.

Referring to FIG. 3, the refresh command REF may be input, for example, every 64 ms. The second control unit 320 may cause the refresh operation to be performed on, for example, 8K word lines at a cycle of 64 ms in response to the refresh command REF (Case 1). However, in this embodiment, to improve the characteristics of the memory cell, the refresh is performed twice for 64 ms, that is, for 32 ms (Case 2).

In addition, in the present embodiment, additional refreshes are performed on the week cells every 16 ms to improve the characteristics of the week cells (Case 3).

Specifically, referring to Case 3 of FIG. 3, a refresh operation is performed on 4K word lines which are half of 8K word lines for 16ms. Then, an additional refresh operation is performed on the word line including the wake cell during?

At this time, the address of the wick cell is stored in the second area 120. The second controller 320 accesses the second area 120 and performs an additional refresh operation using the address of the acquired wake cell.

After the completion of the additional refresh operation for the word line including the wake cell, the second controller 320 performs the refresh operation on the remaining 4K word lines for which the refresh operation is not performed among the 8K word lines. Thereafter, the second controller 320 performs an additional refresh operation on the word line including the wikel cell.

That is, in FIG. 3, the refresh period of 8K word lines is 32ms + 2 * ?. The word line including the Week cell is refreshed once while the 8K word lines are being refreshed, and is refreshed once in the [alpha] section. Therefore, the word line including the Week cells is refreshed three times during 32ms + 2 * [alpha].

Fig. 4 is an enlarged view of a section (a section) where the additional refresh operation of Fig. 3 is performed.

4, after the refresh operation for the 4K-th word line WL4k is completed and before the refresh operation for the 4K + 1-th word line WL4k + 1 is started, n An additional refresh operation is performed on the word lines wWL1 to wWLn. (ARE sensing) is sequentially performed for each of the n word lines wWL1 to wWLn including the wake cell to perform refresh (Weak WL Refresh).

In this case, the first area 110 is accessed during boot-up, and unlike the case where the repair data stored in the first area 110 is all stored in the latch part 210, the data stored in the second area 120, The address of the cell is accessed each time an additional refresh operation is performed.

It is conceivable to store the data of the second area 120 in the latch unit 220 and access the latch unit 220 at the time of boot-up as well as the data of the first area 110. [ However, in this case, the area of the latch portion 220 is increased.

Therefore, in this embodiment, the data in the second area 120 is used after being directly accessed to the second area 120 and stored in the latch part 220 whenever necessary.

When the data stored in the e-fuse array 100 are all stored in the latch units 210 and 220 during boot-up, the -fuse array 100 is accessed only once during boot-up. Therefore, the transistor constituting the e-fuse array 100 has a lower degree of reliability than that of a transistor constituting a normal memory cell because the number of accesses is small.

However, the e-fuse array 100 including the first area 110 and the second area 120 according to the present embodiment is different in the number of accesses of the first area 110 and the second area 120 . For example, the address of the fail cell stored in the first area 110 is accessed only at boot-up time. The addresses of the week cells stored in the second area 120 are accessed every refresh operation.

Therefore, the transistors constituting the second region 120 of the e-fuse array 100 must be assured of a degree of reliability higher than the reliability required for the transistors constituting the first region 110. [

FIG. 5A is a graph showing the relationship between the thickness (Tox) of the gate oxide film of the transistor and the lifetime LT of the transistor, FIG. 5B is a graph showing the relationship between the gate length Lg of the transistor and the lifetime LT, 5C is a graph showing the relationship between the gate width W of the transistor and the performance (IDS).

Here, the gate oxide film means an oxide film formed at the bottom of the gate structure to separate the substrate and the gate structure in the vertical direction in the gate structure formed on the substrate. The gate width means the length of the gate between the source and the drain. The gate length means the thickness of the gate oxide film and the length of the gate perpendicular to the gate width.

Referring to FIG. 5A, a solid line indicates a transistor constituting the first region 110, and a dotted line indicates a transistor constituting the second region 120. As shown in FIG. 5A, the thickness (Tox) and the lifetime LT of the gate oxide film of the transistor are proportional to each other.

However, the number of accesses of the transistor of the first region 110 is smaller than that of the transistor of the second region 120. Therefore, for example, the thickness (Tox1) of the gate oxide film of the transistor of the first region 110 required to ensure a lifetime of 10 years is smaller than the thickness Tox2 of the gate oxide film of the transistor of the second region 120 Can be set.

Referring to FIG. 5B, the solid line represents the transistors constituting the first region 110, and the dotted line represents the transistors constituting the second region 120. In FIG. As shown in FIG. 5B, the gate length Lg of the transistor and the lifetime LT are proportional to each other.

However, the number of accesses of the transistor of the first region 110 is smaller than that of the transistor of the second region 120. Therefore, for example, the gate length Lg1 of the transistor of the first region 110 required to ensure a lifetime of 10 years can be set to be smaller than the gate length Lg2 of the transistor of the second region 120 .

5C is a graph showing the relationship between the gate width W and the performance IDS of the transistor, and the dotted line indicates the transistor having the gate oxide film thickness Tox or gate length Lg larger than the solid line.

As shown by the downwardly directed arrows in Fig. 5C, the current (IDS) value between the drain and source of the transistor decreases from IDS1 to IDS2 as the gate oxide film thickness or gate length increases. At this time, the current (IDS) between the drain and the source of the transistor represents the performance of the transistor.

Thus, to increase the lifetime of the second region 120 to the same extent as the lifetime of the first region 110, as shown in FIGS. 5A and / or 5B, the thickness of the gate oxide film of the transistor of the second region 120, Increasing the length reduces the performance of the transistors in the second region 120.

As shown in Fig. 5C, the gate width W of the transistor and the current (IDS) between the drain and the source, that is, the performance, are proportional. Thus, in order to increase the lifetime of the transistor in the second region 120, if the thickness and / or the gate length of the gate oxide film are increased, the gate width W ) Can be increased.

That is, in the transistor of the second region 120 having the gate width W1, when the gate oxide film thickness and / or the gate length are increased to deteriorate the performance (see arrows in FIG. 5C) ) To the gate width W2, it is possible to prevent degradation of performance.

The e-fuse array 100 according to the embodiment of the present invention has a different structure depending on the number of accesses.

Particularly, the size of the transistor is reduced for the area with a small number of accesses (the first area 110) and the size of the transistor is increased for the area with a large number of accesses (the second area 120).

For example, at least one of the thickness of the gate oxide film of the transistor and the length of the gate of the second region 120 may be larger than that of the first region 110. In addition, the gate width of the transistor of the second region 120 may be larger than that of the first region 110.

According to the embodiment of the present invention having such a structure, since the lifetime of the transistor of the second region 120 having a large number of accesses can be extended, the reliability of the entire semiconductor device can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Claims (20)

An e-fuse array including a first region and a second region;
A first controller using first data stored in the first area; And
A second controller accessing the second area by using more of the second data stored in the second area than the number of times the first area is accessed;
. The method according to claim 1,
Wherein a size of a transistor constituting the first region and a size of a transistor constituting the second region are different from each other. 3. The method of claim 2,
Wherein the thickness of the gate oxide film of the transistor constituting the second region is larger than the thickness of the gate oxide film of the transistor constituting the first region. 3. The method of claim 2,
Wherein the gate length of the transistor constituting the second region is larger than the gate length of the transistor constituting the first region. The method of claim 3,
Wherein the gate width of the transistor constituting the second region is larger than the gate width of the transistor constituting the first region. 5. The method of claim 4,
Wherein the gate width of the transistor constituting the second region is larger than the gate width of the transistor constituting the first region. The method according to claim 1,
And a latch unit for storing the first data stored in the first area at boot-
The semiconductor device further comprising: 8. The method of claim 7,
Wherein the first control unit accesses the latch unit and uses the first data. 9. The method of claim 8,
Wherein the first data is an address of a fail cell. 10. The method of claim 9,
Wherein the first control unit performs a repair operation by accessing a redundancy address corresponding to an address of a fail cell instead of an input address when an input address matches an address of a fail cell stored in the latch unit. The method according to claim 1,
And the second data is an address of a week cell. 12. The method of claim 11,
Wherein the second control unit comprises:
A refresh operation is performed on a memory cell including the wick cell at a predetermined cycle,
And further performs a refresh operation on the weak cell using the address of the weak cell obtained by accessing the second region. 12. The method of claim 11,
Wherein the second control unit comprises:
And performs an additional refresh operation with respect to the wick cell at a cycle twice the predetermined period. A first region including a plurality of fuse cells including a first transistor,
A second region including a plurality of fuse cells including the second transistor
/ RTI >
Wherein the size of the first transistor and the size of the second transistor are different. 15. The method of claim 14,
Wherein the thickness of the gate oxide film of the second transistor is greater than the thickness of the gate oxide film of the first transistor. 15. The method of claim 14,
Wherein a gate length of the second transistor is greater than a gate length of the first transistor. 16. The method of claim 15,
Wherein the gate width of the second transistor is greater than the gate width of the first transistor. 17. The method of claim 16,
Wherein the gate width of the second transistor is greater than the gate width of the first transistor. 15. The method of claim 14,
Wherein the second region is accessed more frequently than the first region. 20. The method of claim 19,
Wherein the first area is accessed during boot-up.

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