KR102547107B1 - Memory device and system including the same - Google Patents

Abstract

The present invention relates to a memory device and a system including the same, and is a technology for improving refresh efficiency by selectively performing an additional refresh operation for a weak address and a post package repair operation. According to the present invention, a command control unit for buffering an address in response to a refresh enable signal and a repair enable signal controls a rupture operation of a fuse set corresponding to an address according to a refresh enable signal and a repair enable signal, and a boot-up operation When the refresh control signal is activated, the fuse unit outputs the refresh control signal and the repair control signal, the refresh control unit controls the refresh operation of the bank according to the refresh signal when the refresh control signal is activated, and the repair operation of the bank is controlled according to the redundancy signal when the repair control signal is activated. It includes a repair control unit that does.

Description

Memory device and system including the same {Memory device and system including the same}

The present invention relates to a refresh and repair operation of a memory device.

A memory cell of a memory device is composed of a transistor serving as a switch and a capacitor storing charge (data). Depending on whether there is charge in the capacitor in the memory cell, that is, whether the terminal voltage of the capacitor is high or low, data is classified as 'high' (logic 1) or 'low' (logic 0).

In principle, there is no power consumption because the storage of data is in the form of accumulated charge in the capacitor. However, data may be lost because the initial amount of charge stored in the capacitor disappears due to leakage current caused by the PN coupling of the MOS transistor.

To prevent this, the data in the memory cell must be read before the data is lost, and the normal amount of charge must be recharged according to the read information. Data storage is maintained only when this operation is periodically repeated, and this process of recharging cell charge is referred to as a refresh operation.

A refresh operation is performed whenever a refresh command is input from the memory controller to the memory. The memory controller inputs a refresh command to the memory at regular intervals in consideration of data retention time of the memory.

For example, if the data retention time of the memory is 64 ms and the refresh command must be input 8000 times to refresh all memory cells in the memory, the memory controller sends 8192 refresh commands to the memory during 64 ms. input into the device.

Meanwhile, in the process of testing the memory device, if the data retention time of some memory cells included in the memory does not exceed the prescribed reference time, the memory device is treated as a fail. should be discarded if

If all memory devices including memory cells whose data retention time does not reach the reference time are all failed, the yield may decrease. In addition, even in a memory device that passes the test, an error may occur if a memory cell whose data retention time does not reach the reference time is generated due to ex post factors.

The present invention is characterized in that refresh efficiency can be improved by selectively performing an additional refresh operation for weak addresses and a post package repair operation.

A memory device according to an embodiment of the present invention includes a command controller for buffering an address in response to a refresh enable signal and a repair enable signal; a fuse unit controlling a rupture operation of a fuse set corresponding to an address according to a refresh enable signal and a repair enable signal, and outputting a refresh control signal and a repair control signal during a boot-up operation; a refresh controller controlling a refresh operation of the bank according to the refresh control signal when the refresh control signal is activated; and a repair controller controlling a repair operation of the bank according to a redundancy signal when the repair control signal is activated.

A system according to another embodiment of the present invention includes a controller that generates a refresh enable signal, a repair enable signal, and an address and command signal; and ruptures the fuse set corresponding to the address in response to the refresh enable signal and the repair enable signal, and controls the refresh operation and repair operation of the bank according to the refresh control signal and the repair control signal corresponding to the rupture data during a boot-up operation. It is characterized in that it comprises a memory device to.

The present invention provides an effect of improving refresh efficiency by selectively performing an additional refresh operation for a weak address and a post package repair operation.

In addition, the embodiments of the present invention are for illustrative purposes, and those skilled in the art will be able to make various modifications, changes, substitutions, and additions through the technical spirit and scope of the appended claims, and such modifications and changes fall within the scope of the following claims. should be seen as

1 is a configuration diagram of a system including a memory device according to an embodiment of the present invention;
2 is a detailed configuration diagram of a command control unit of FIG. 1;
3 is another embodiment of the command control unit of FIG. 1;
4 is a detailed configuration diagram of a refresh control unit and a repair control unit of FIG. 1;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a system including a memory device according to an embodiment of the present invention.

An embodiment of the present invention includes a controller 10 and a memory device 100 . Here, the memory device 100 includes a command control unit 110, a fuse unit 120, a refresh control unit 130, a repair control unit 140, and a bank 150. The fuse unit 120 includes a fuse control unit 121 , a refresh cell array 122 , a repair cell array 123 , and an output control unit 124 .

The controller 10 outputs a refresh enable signal IR_EN, a repair enable signal PPR_EN, a command signal CMD, and an address ADD to the memory device 100 . In an embodiment of the present invention, the address ADD can be shared and used in the refresh mode and the repair mode.

Here, the refresh enable signal IR_EN and the repair enable signal PPR_EN may be signals generated by a mode register set (MRS). Also, the refresh enable signal IR_EN and the repair enable signal PPR_EN may operate complementary to each other. That is, only one of the refresh enable signal IR_EN and the repair enable signal PPR_EN can be activated.

Here, the refresh enable signal IR_EN means an enable signal for performing an innovation refresh (IR) operation, and the IR operation represents an operation for performing a refresh on a weak cell having a short data retention time.

That is, IR (Inovation Refresh) operation is performed to compensate for bits that may cause a refresh failure depending on the environment due to a relatively short data retention time. IR operation ruptures the address (weak address) of a bit with a short data retention time to the fuse, and then performs refresh in addition to the number of refreshes specified in the specification.

For example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) adopts a method of recording data according to charge accumulated in a capacitor inside each cell. The charge of the capacitor inside the cell is lost to the outside of the cell in the form of leakage current over time. In order to prevent data loss due to leakage current, an operation of taking out, reading, and writing data to the cell again is required before the data stored in the cell is completely lost.

The above operation is referred to as a refresh operation, and may be performed at regular intervals or at the request of the system. Since there may be a difference in the retention capability of each of the capacitors inside the cell, that is, the data retention time, a weak cell refresh operation considering the difference is required.

And, the repair enable signal PPR_EN means an enable signal for performing a post package repair operation on the fail address.

For example, DRAM (Dynamic Random Access Memory) is composed of a plurality of memory cells arranged in a matrix form. However, if a defect occurs in even one memory cell among many memory cells, the semiconductor memory device does not operate properly and is therefore processed as a defect. Moreover, the probability of occurrence of defective cells increases with the high integration and high speed of semiconductor memory devices.

Therefore, the yield expressed as the ratio of the number of non-defective chips to the total number of chips, which determines the manufacturing cost of DRAM, is low. Accordingly, research is being conducted on a method for efficiently repairing defective cells in order to improve a yield, as well as a method for high integration and high-speed semiconductor memory devices.

As one method of repairing a defective cell, a technique of embedding a repair circuit for replacing the defective cell with another redundancy cell is being used. In general, a repair circuit includes a column composed of redundant memory cells and redundancy columns/rows arranged in a row. Then, a redundancy column/row is selected in place of the defective column/row.

That is, when a row and/or column address signal designating a defective cell is input, a redundancy column/row is selected instead of a defective column/row of a normal memory cell bank.

In order to find an address designating a defective cell, a plurality of disconnectable fuses are generally provided, and by selectively disconnecting them, the address of the defective cell is programmed.

A repair method for a defective cell in a DRAM includes a repair method in a wafer state and a repair method in a package state.

Here, the wafer repair method is a method of replacing defective cells with redundancy cells after performing a test at the wafer level. And, the packaging repair method is a method of replacing a defective cell with a redundant cell in a packaging state after performing a test in a packaging state. The case where repair is performed in the packaging state is referred to as a post package repair (PPR) method.

In addition, the address ADD is an address including information of a corresponding cell when a weak cell refresh operation or a post package repair operation is performed. That is, the address ADD may include weak address and fail address information known to the controller 10 .

The command controller 110 processes the refresh enable signal IR_EN, the repair enable signal PPR_EN, the command signal CMD, and the address ADD applied from the controller 10 to generate a refresh command signal REF_EN and an address INT_ADD. Here, the refresh command signal REF_EN may be a signal generated by the command signal CMD.

In addition, the fuse controller 121 generates a refresh rupture signal IR_RUP for controlling a rupture operation of the fuse and a repair rupture signal PPR_RUP in response to the refresh enable signal IR_EN, the repair enable signal PPR_EN, and the address INT_ADD.

The fuse controller 121 determines whether the mode is for controlling a refresh operation of a weak cell or a mode for controlling a post package repair operation in response to the refresh enable signal IR_EN and the repair enable signal PPR_EN.

That is, the fuse controller 121 decodes the address INT_ADD according to the refresh enable signal IR_EN and the repair enable signal PPR_EN, and activates one of the refresh rupture signal IR_RUP and the repair rupture signal PPR_RUP. That is, the fuse control unit 121 decodes the address INT_ADD applied from the command control unit 110 to correspond to the fuse array and controls one of the refresh rupture signal IR_RUP and the repair rupture signal PPR_RUP.

For example, the fuse control unit 121 may control the rupture operation by determining whether a fuse set is used or not and sequentially allocating unused fuse sets. That is, when one of the refresh rupture signal IR_RUP and the repair rupture signal PPR_RUP is activated, the fuse controller 121 sequentially allocates addresses and controls the refresh rupture or repair rupture operation based on the unused address. can

Then, the refresh cell array 122 ruptures the fuse in response to the refresh rupture signal IR_RUP and outputs data D1 indicating the position of the fuse line. In addition, the repair cell array 123 ruptures the fuse in response to the repair rupture signal PPR_RUP and outputs data D2 indicating the position of the fuse line.

Here, the refresh cell array 122 and the repair cell array 123 are composed of an E-fuse or an array rupture electrical fuse (ARE) to store address information of a defective cell.

As the size of each element constituting the semiconductor integrated circuit device is miniaturized and the number of elements included in one semiconductor chip increases, the level of defect density also increases. This increase in defect density is a direct cause of lowering the yield of semiconductor devices. When the defect density increases significantly, the wafer on which the semiconductor device is formed must be discarded.

In order to lower the defect density, a redundancy circuit in which defective cells are replaced with redundant cells has been proposed. In the case of a semiconductor memory device, redundancy circuits (or fuse circuits) may be provided for each of a row-based wiring (eg, a word line) and a column-based wiring (eg, a bit line).

This redundancy circuit includes a repair cell array 123 that stores address information of a defective cell. The refresh cell array 122 and the repair cell array 123 are composed of a plurality of fuse sets including a plurality of fuse wires. Here, each fuse set may be formed of an electric fuse (E-fuse) for programming information in a manner of melting the fuse with an overcurrent.

The refresh cell array 122 and the repair cell array 123 are memories that store information about each bit of all fail addresses. The refresh cell array 122 and the repair cell array 123 select corresponding row lines according to the refresh rupture signal IR_RUP and the repair rupture signal PPR_RUP, which are fuse selection information.

In addition, information is programmed in each fuse set in such a way that the fuse is melted by an overcurrent. In addition, self-repair (repair or rupture) is performed for the purpose of rescuing the bit failure in the packaged state of the memory.

After the memory test is completed, the refresh cell array 122 and the repair cell array 123 rupture an electrical fuse corresponding to each bit to permanently store fail information. In addition, the refresh cell array 122 and the repair cell array 123 may output row fuse data and column fuse data stored prior to memory operation after power-up as data D1 and D2.

In the embodiment of the present invention, the refresh cell array 122 and the repair cell array 123 are shown as separate configurations. However, the exemplary embodiment of the present invention is not limited thereto, and the refresh cell array 122 and the repair cell array 123 may be arranged separately for each area in one array, and each area may be selected by a decoding signal. For example, one area may represent an area allocated for refresh, and the other area may represent an area allocated for repair. Here, a fuse area allocated to an existing row line may be used as the refresh area.

When the boot-up signal BOOTUP is activated, the output controller 124 starts a boot-up operation to read information of the refresh cell array 122 and the repair cell array 123. That is, the output controller 124 scans a fuse to be used according to data D1 and D2 including fuse information, and outputs a refresh control signal IR and a repair control signal RE in response to a boot-up signal BOOTUP.

Here, the output controller 124 may scan fuse data for a fail address stored in electric fuses of the refresh cell array 122 and the repair cell array 123 before the memory operates after the power-up operation.

The refresh controller 130 outputs a refresh signal REF for performing a refresh operation of a weak cell to the bank 150 in response to the refresh command signal REF_EN and the refresh control signal IR.

Also, the repair control unit 140 outputs a redundancy signal RED for performing a post package repair operation to the bank 150 in response to the repair control signal RE. For example, when a hard failure occurs, the repair control unit 140 may replace a word line with a redundancy word line to rescue it.

FIG. 2 is a detailed configuration diagram of the command controller 110_1 of FIG. 1 .

The command controller 110_1 generates an address INT_ADD by buffering the address ADD in response to the refresh enable signal IR_EN or the repair enable signal PPR_EN applied from the controller 10 . Here, the refresh enable signal IR_EN and the repair enable signal PPR_EN are not activated at the same time, but only one of the two signals is activated.

That is, the command controller 110_1 buffers the address ADD and outputs the internal address INT_ADD when either one of the refresh enable signal IR_EN and the repair enable signal PPR_EN is activated. In an embodiment of the present invention, address ADD can be shared and used during a weak cell refresh operation and a post package repair operation.

The command controller 110_1 includes an address buffer 111, input units 112 and 113, and a selection unit 114.

Here, the address buffer 111 buffers the address ADD and outputs it to the selector 114. Also, the input units 112 and 113 control the selection operation of the selection unit 114 by combining the refresh enable signal IR_EN and the repair enable signal PPR_EN.

The input unit 112 includes a NAND gate ND1 and a plurality of inverters IV1 to IV4. The NAND gate ND1 performs a NAND operation on the refresh enable signal IR_EN and the repair enable signal PPR_EN inverted by the inverter IV1. Inverters IV2 to IV4 invert and delay the output of NAND gate ND1. The input unit 112 having this configuration activates the selection unit 114 when the refresh enable signal IR_EN is activated.

Also, the input unit 113 includes a NAND gate ND2 and a plurality of inverters IV5 to IV8. The NAND gate ND2 performs a NAND operation on the refresh enable signal IR_EN and the repair enable signal PPR_EN inverted by the inverter IV5. Inverters IV6 to IV8 invert and delay the output of NAND gate ND2. The input unit 113 having this configuration activates the selection unit 114 when the repair enable signal PPR_EN is activated.

The selector 114 includes transmission gates T1 and T2. Here, the transfer gate T1 is turned on when the refresh enable signal IR_EN is activated, and transfers the output of the address buffer 111 to the internal address INT_ADD. The transmission gate T2 is turned on when the repair enable signal PPR_EN is activated, and transfers the output of the address buffer 111 to the internal address INT_ADD.

FIG. 3 is another embodiment of the command controller 100_2 of FIG. 1 .

The command controller 100_2 includes an address buffer 115, an input unit 116, and a selection unit 117.

Here, the address buffer 115 buffers the address ADD and outputs it to the selector 117. The input unit 116 controls the selection operation of the selection unit 117 by combining the refresh enable signal IR_EN and the repair enable signal PPR_EN.

The input unit 116 includes a NOR gate NOR1 and an inverter IV9. The NOR gate NOR1 performs a NOR operation on the refresh enable signal IR_EN and the repair enable signal PPR_EN. Inverter IV9 inverts the output of NORgate NOR1.

The input unit 116 having this configuration activates the selection unit 117 when at least one of the refresh enable signal IR_EN and the repair enable signal PPR_EN is activated.

The selector 117 includes a transmission gate T3. Here, the transmission gate T3 turns on when at least one of the refresh enable signal IR_EN and the repair enable signal PPR_EN is activated, and transfers the output of the address buffer 115 to the internal address INT_ADD.

FIG. 4 is a detailed configuration diagram of a refresh control unit and a repair control unit of FIG. 1 .

The refresh controller 130 includes a refresh latch 131 and a counter 132 .

Here, the refresh latch 131 latches the refresh control signal IR in response to the refresh command signal REF_EN. Then, the counter 132 counts the output of the refresh latch 131 and outputs the refresh signal REF to the bank 150. For example, when data is stored in the refresh latch 131, a refresh operation is performed by counting the refresh control signal IR. On the other hand, when data is not stored in the refresh latch 131, the refresh operation is not performed.

The bank 150 performs an additional refresh operation on weak cells by selectively activating the word line WL in response to the refresh signal REF.

And, the repair controller 140 includes a repair latch 141 and a redundancy controller 142 .

Here, the repair latch 141 latches the repair control signal RE. Also, the redundancy controller 142 outputs a redundancy signal RED for performing a post package repair operation to the bank 150 in response to the output of the repair latch 141 . The bank 150 performs a repair operation on a failed cell by selectively activating the redundancy word line RWL in response to the redundancy signal RED.

For example, a post package repair operation may be performed once per bank group. On the other hand, in the refresh operation, it is possible to refresh a multi-bit fail according to the number of refresh latches 131 .

Accordingly, in the embodiment of the present invention, when a hard failure occurs, the repair controller 140 rescues the fail address. It is assumed that more refresh failures than hard failures occur in the memory device. In the embodiment of the present invention, in the case of a refresh failure, additional refresh of weak cells is performed according to the refresh control unit 130 .

That is, the location of the fail bank is determined by determining the command signal CMD and the address ADD applied from the controller 10, and in case of a hard failure, the repair enable signal PPR_EN is activated to perform a repair operation. And, when a number of refresh failures that cannot be handled in the repair mode occur, the refresh enable signal IR_EN is activated to perform a refresh operation.

When a weak address with a relatively short data retention time occurs, it is determined whether to completely recover the weak address through a repair operation or refresh it using an IR operation. That is, it is determined whether to intensify the refresh by storing the weak address in the fuse and performing additional refresh using the stored address.

According to an embodiment of the present invention, a user may change or control an operation mode of the memory device 100 by controlling a mode register set (MRS) in the controller 10 . That is, if a user (eg, a server) desires, the controller 10 may select an IR mode to perform additional refresh of the memory device 100 .

For example, the refresh control device may increase the refresh cycle to reduce current consumption. If a refresh failure occurs even though the refresh cycle is increased, this may be regarded as a refresh failure rather than a hard failure. The user controls the controller 10 by setting the refresh property fail information to the mode register set (MRS). When the mode register set information input from the user indicates refreshability fail, the controller 10 selects the IR mode and controls the additional refresh of the memory device 100 to be performed.

Those skilled in the art to which the present invention pertains should understand that the embodiments described above are illustrative in all respects and not limiting, since the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. only do The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention. .

Claims (20)

a command controller for buffering addresses in response to the refresh enable signal and the repair enable signal;
a fuse unit which controls a rupture operation of the fuse set corresponding to the address according to the refresh enable signal and the repair enable signal, and outputs a refresh control signal and a repair control signal during a boot-up operation;
a refresh control unit controlling a refresh operation of the bank according to the refresh signal when the refresh control signal is activated; and
and a repair controller controlling a repair operation of the bank according to a redundancy signal when the repair control signal is activated. ◈Claim 2 was abandoned when the registration fee was paid.◈ According to claim 1,
The memory device according to claim 1 , wherein the refresh enable signal and the repair enable signal are activated in a complementary manner. ◈Claim 3 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the command control unit
an input unit combining the refresh enable signal and the repair enable signal;
an address buffer buffering the address; and
and a selector configured to selectively transmit an output of the address buffer according to an output signal of the input unit. ◈Claim 4 was abandoned when the registration fee was paid.◈ The method of claim 3, wherein the selection unit
The memory device of claim 1 , wherein the address at which at least one of the refresh enable signal and the repair enable signal is activated is transmitted to the fuse unit. ◈Claim 5 was abandoned when the registration fee was paid.◈ According to claim 1,
The memory device of claim 1 , wherein the address is shared by the refresh enable signal and the repair enable signal. ◈Claim 6 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the fuse unit
a fuse controller outputting a refresh rupture signal and a repair rupture signal for controlling a rupture operation of a fuse set corresponding to the address according to the refresh enable signal and the repair enable signal;
a refresh cell array in which the fuse set is ruptured in response to the refresh rupture signal;
a repair cell array in which the fuse set is ruptured in response to the repair rupture signal; and
and an output controller configured to output the refresh control signal and the repair control signal corresponding to output data of the refresh cell array and the repair cell array during the boot-up operation. ◈Claim 7 was abandoned when the registration fee was paid.◈ According to claim 6,
The memory device of claim 1, wherein the refresh cell array and the repair cell array include e-fuse. ◈Claim 8 was abandoned when the registration fee was paid.◈ According to claim 6,
The memory device of claim 1 , wherein the refresh cell array and the repair cell array include an array rupture electrical fuse (ARE). ◈Claim 9 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the refresh control unit
A memory device characterized by controlling an additional refresh operation for a weak cell. ◈Claim 10 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the repair control unit
A memory device characterized in that for controlling a post package repair operation. ◈Claim 11 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the refresh control unit
a refresh latch latching the refresh control signal when a refresh command signal is activated; and
and a counter configured to output the refresh signal by counting an output of the refresh latch. ◈Claim 12 was abandoned when the registration fee was paid.◈ 12. The method of claim 11, wherein the refresh controller
The memory device of claim 1 , wherein the refresh signal is activated when data is stored in the refresh latch, and the refresh signal is deactivated when data is not stored in the refresh latch. ◈Claim 13 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the repair control unit
a repair latch latching the repair control signal; and
and a redundancy controller configured to output the redundancy signal in response to an output of the repair latch. ◈Claim 14 was abandoned when the registration fee was paid.◈ According to claim 1,
The refresh enable signal and the repair enable signal are generated in a mode register set (MRS), and the refresh enable signal and the repair enable signal are controlled in response to a change in an operation mode of the mode register set. memory device. a controller that generates a refresh enable signal, a repair enable signal, and address and command signals; and
A fuse set corresponding to the address is ruptured in response to the refresh enable signal and the repair enable signal, and during a boot-up operation, a refresh control signal and a repair control signal corresponding to rupture data are used to refresh and repair a bank System characterized in that it comprises a memory device for controlling. ◈Claim 16 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein the controller
and controlling the refresh enable signal and the repair enable signal in response to a change in an operation mode of a mode register set (MRS). ◈Claim 17 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein the controller
The system characterized in that the refresh enable signal and the repair enable signal are activated complementarily. ◈Claim 18 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein the memory device
a command controller configured to buffer the address in response to the refresh enable signal and the repair enable signal;
a fuse unit which controls a rupture operation of the fuse set corresponding to the address according to the refresh enable signal and the repair enable signal, and outputs the refresh control signal and the repair control signal during the boot-up operation;
a refresh control unit controlling a refresh operation of the bank according to a refresh signal when the refresh control signal is activated; and
and a repair controller controlling a repair operation of the bank according to a redundancy signal when the repair control signal is activated. ◈Claim 19 was abandoned when the registration fee was paid.◈ The method of claim 18, wherein the fuse unit
a fuse controller outputting a refresh rupture signal and a repair rupture signal for controlling a rupture operation of a fuse set corresponding to the address according to the refresh enable signal and the repair enable signal;
a refresh cell array in which the fuse set is ruptured in response to the refresh rupture signal;
a repair cell array in which the fuse set is ruptured in response to the repair rupture signal; and
and an output controller configured to output the refresh control signal and the repair control signal corresponding to output data of the refresh cell array and the repair cell array during the boot-up operation. ◈Claim 20 was abandoned when the registration fee was paid.◈ 19. The method of claim 18, wherein the refresh controller
a refresh latch latching the refresh control signal when a refresh command signal is activated; and
and a counter configured to output the refresh signal by counting an output of the refresh latch.

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