KR20180013419A - Circuit for driving data of the Liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a data driving circuit of a liquid crystal display device, and a driving method thereof. According to the present invention, a switching element capable of selecting an HVDD or VSSH level is added to a charge share circuit of a data driving part. As the switching element is controlled, the breakdown voltage of a transistor composing the charge share circuit is improved at the time of power-on, and a problem that a white color is instantaneously displayed can be solved. The data driving circuit of a liquid crystal display device comprises: a shift register; a latch part; a DA conversion part; a switch array; and a charge share part.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof,

The present invention relates to a liquid crystal display device, and more particularly to a data driving circuit and a data driving circuit of a liquid crystal display device for preventing an instantaneous white screen at power-on and improving the breakdown voltage characteristic of a charge- Driving method.

2. Description of the Related Art Flat panel displays that display images using digital data are typically liquid crystal displays (LCDs) using liquid crystals and OLED display devices using organic light emitting diodes (OLEDs) .

Among these, a liquid crystal display comprises a liquid crystal panel having a plurality of gate lines and a plurality of data lines for displaying an image, and a driving unit for driving the liquid crystal panel. The driving unit includes a gate driver for driving the plurality of gate lines, a data driver for driving the plurality of data lines, and a timing controller for supplying image data and various control signals to the gate driver and the data driver.

On the other hand, when a voltage of the same polarity is continuously applied to the liquid crystal cell of the liquid crystal panel, the liquid crystal cell deteriorates. Therefore, a frame inversion method, a line inversion method, a column inversion ) Method and a dot inversion method are used. When the liquid crystal panel is driven by such an inversion method, the polarity of the data signal must be continuously inverted, so that a lot of power consumption is consumed. Therefore, by charging the data line with a voltage having an intermediate level between the positive polarity data signal and the negative polarity data signal while inverting the polarity of the data signal by using a charge share circuit, .

The charge share circuit is composed of a plurality of switching elements.

MOS transistors are used as a plurality of switching elements constituting the charge sharing circuit. In recent years, MV transistors are used instead of HV class MOS transistors due to high integration.

The MV characteristics of the MOS transistor were improved by about 15% compared with the HV MOS transistor but the breakdown voltage was reduced to 1/2.

Therefore, when the liquid crystal display device is powered on, the breakdown voltage of the MV-class MOS transistor constituting the charge-sharing circuit is increased to about 8V. In addition, when the output level is adjusted to the HVDD level (about 4V) to solve the breakdown voltage problem of the MV class MOS transistor, there is a problem that white is instantaneously displayed at the time of power ON.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a data driving circuit in which a switching element capable of selecting HVDD or VSSH level is further added to a charge- And it is an object of the present invention to provide a data driving circuit and a driving method of a liquid crystal display device which can solve the problem that the breakdown voltage of the constituent transistors is improved and the white color is instantaneously displayed.

According to an aspect of the present invention, there is provided a data driving circuit for a liquid crystal display device, including: a plurality of data lines for sharing charges in the adjacent channels, supplying a VSSH voltage during one horizontal period after a garbage display period, And a charge sharing unit for supplying a voltage.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, comprising: sharing charges remaining in data lines of adjacent channels; Applying a VSSH voltage to the shared channel for one horizontal period after a power-on and a garbage display period before a gate-start pulse is applied; Applying an HVDD voltage to the shared channel for a predetermined horizontal period; And applying a positive polarity data voltage or a negative polarity data voltage to the adjacent channels, respectively.

The data driving circuit and the driving method of the liquid crystal display device according to the present invention having the above-described features have the following effects.

Since the HVDD voltage is applied during the 8 horizontal periods before the power is turned on and the image is displayed, the first to fifth switching elements of the switch array 143 and the charge sharing section 145 are constituted by MV class MOS transistors The breakdown voltage of the first to fifth switching elements can be improved.

In addition, since the gate output enable (GOE) masking can be controlled before the first scan pulse is output, the white display is not recognized during the eight horizontal periods in which the HVDD voltage is applied.

1 is a block diagram schematically showing a liquid crystal display device according to the present invention.
Fig. 2 is a circuit diagram schematically showing the subpixel shown in Fig.
3 is a block diagram schematically showing an internal configuration of a data driver according to an embodiment of the present invention.
FIG. 4 is a circuit diagram of a DA converter, a switch array, and a charge sharing section for two adjacent channels according to the present invention
5 is a timing chart for explaining the operation of the data driving circuit of the liquid crystal display according to the present invention

The data driving circuit and the driving method of the liquid crystal display according to the present invention having the above-described characteristics will now be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a liquid crystal display device according to the present invention, and FIG. 2 is a circuit diagram schematically showing a subpixel shown in FIG.

1 and 2, the liquid crystal display according to the present invention includes a timing controller 130, a gate driver 140, a data driver 150, a liquid crystal panel 160, and a backlight unit 170, .

The timing controller 130 outputs a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150 do. The timing controller 130 supplies the data driver 150 with the data signal DATA supplied from the image processor 110 together with the data timing control signal DDC.

The gate driver 140 sequentially outputs scan pulses to the gate lines GL in response to a gate timing control signal GDC supplied from the timing controller 130. The gate driver 140 is formed in the form of an IC (Integrated Circuit) or a GIP (Gate In Panel) method in the liquid crystal panel 160.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 130 and converts the sampled data signal into a gamma reference voltage. The data driver 150 may invert the polarity of the data voltage in one frame period. The data driver 150 supplies a data voltage to the sub-pixels SP included in the liquid crystal panel 160 through each data line DL. The data driver 150 is formed in the form of an integrated circuit (IC).

The liquid crystal panel 160 displays an image corresponding to a scan signal supplied from the gate driver 140 and a data voltage supplied from the data driver 150. The liquid crystal panel 160 includes subpixels SP for controlling light provided through the backlight unit 170. One sub-pixel includes a switching transistor SW, a storage capacitor Cst, and a liquid crystal layer Clc. A gate electrode of the switching transistor SW is connected to each gate line GL1 and a source electrode thereof is connected to each data line DL1. The storage capacitor Cst is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor SW and the common electrode 2 connected to the common voltage line Vcom. That is, the liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor SW and the common electrode 2 connected to the common voltage line Vcom.

The liquid crystal panel 160 may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode Or ECB (Electrically Controlled Birefringence) mode.

The liquid crystal panel 160 may be embodied as red, green, and blue subpixels, or may be implemented as white subpixels in addition to red, green, and blue subpixels to reduce current consumption.

The backlight unit 170 provides light to the liquid crystal panel 160 using a light source or the like that emits light.

Hereinafter, the data driver 150 will be described in more detail.

3 is a block diagram schematically showing an internal configuration of a data driver according to an embodiment of the present invention.

3, a data driver according to an embodiment of the present invention includes a shift register SR, a first latch LAT1 (1'st latch), a second latch LAT2 (2'nd a DAC (PDAC and NDAC), a switch array 143, a charge control unit 141 and a charge share unit 145 are included. The output amplifier located at the rear end of the charge share section 145 is omitted.

The data driver includes the shift register SR, the first and second latches LAT1 and LAT2, the DA conversion unit DAC, the switch array 143, the charge control unit 141 and the charge share unit 145 Converts the digital data signal into an analog data voltage and outputs it through its output channels CH1 to CHN. Hereinafter, the configuration included in the data driver will be schematically described as follows.

The shift register SR outputs a sampling signal in response to the source start pulse and the source sampling clock output from the timing controller 130. The first and second latches LAT1 and LAT2 sequentially sample digital data signals in response to a sampling signal output from the shift register SR and sequentially sample the data signals sampled corresponding to the source output enable signal SOE And simultaneously outputs data signals for one line.

The DA converter DAC converts a data signal for one line into an analog data voltage in response to the first through n-th gamma gradation voltages output from the gamma voltage generator (not shown). The DA converter DAC includes a positive polarity DA converter (PDAC) for converting the gamma gradation voltage into a positive polarity data voltage in response to the polarity control signal output from the timing controller 130, - >) data voltage.

The source start pulse is a signal for controlling the data sampling start timing of the data driver. The source sampling clock is a signal for controlling data sampling timing of the data driver based on the rising or falling edge. The source output enable signal is a signal for controlling the output timing of the data driver. The polarity control signal is a signal for controlling the vertical polarity of the data voltages output to the data driver.

The switch array 143 receives the positive polarity data voltage and negative polarity data voltages output from the positive polarity DA converter (PDAC) and the negative polarity digital converter (NDAC) ) Or the like.

The charge share unit 145 is disposed at the rear end of the switch array 143 and selectively connects the data lines so that charges (or data voltages) remaining in the data lines of the liquid crystal panel 160 are shared Or short). The charge share unit 145 selectively connects (or short-circuits) the data lines in response to the charge control signal CS output from the charge control unit 141.

Here, the DA conversion unit (DAC), the switch array 143, and the charge share unit 145 for two adjacent channels will be described as follows.

4 is a specific circuit configuration diagram of the DA conversion unit DAC, the switch array 143, and the charge share unit 145 for two adjacent channels according to the present invention.

The DA converter (DAC) includes a positive polarity DA converter (PDAC) for converting the gamma gradation voltage into a positive polarity data voltage, a negative polarity converter (PDC) for converting the gamma gradation voltage to a negative polarity And a DA converter (NDAC).

The switch array 143 includes first through fourth switching elements SW1, SW2, SW3, and SW4 and is connected between the positive polarity DA converter PDAC and the negative polarity DA converter NDAC And operates so that the positive polarity data voltage and the negative polarity data voltage are alternately outputted to the adjacent channel (n channel and n + 1 channel).

That is, when the first and fourth switching devices SW1 and SW4 are turned on and the second and third switching devices SW2 and SW3 are turned off, The negative polarity data voltage output from the negative polarity data converter PDAC is supplied to the data line of the (n) th channel, and the negative polarity data voltage output from the negative polarity DA converter NDAC is supplied to the (n + 1) .

When the first and fourth switching devices SW1 and SW4 are turned off and the second and third switching devices SW2 and SW3 are turned on, The negative data voltage output from the negative polarity DA converter PDAC is supplied to the data line of the (n + 1) -th channel, and the negative polarity data voltage output from the negative polarity DA converter NDAC is supplied to the .

(N) -th channel data line (SW1), when the fifth switching device (SW5) is turned on, the charge sharing unit (145) comprises the fifth to seventh switching devices And the charge (or data voltage) remaining in the (n + 1) th data line.

As described above, when the data line of the (n) th channel and the data line of the (n + 1) th share the charge (or the data voltage), during one horizontal period (1H) after the garbage display period The seventh switching device SW7 is turned on to supply the VSSH voltage and the sixth switching device SW6 is turned on to supply the HVDD voltage during eight horizontal periods 8H.

Here, the sixth switching element SW6 is turned on and supplies the HVDD voltage during the 8 horizontal periods 8H. However, the present invention is not limited to this, and the period may be 5 horizontal periods to 10 power periods.

Therefore, even when the first to fifth switching elements of the switch array 143 and the charge sharing section 145 are constituted by MV-class MOS transistors, the first to fifth switching elements The breakdown voltage can be improved.

The operation of the data driving circuit of the liquid crystal display according to the present invention will now be described.

5 is a timing chart for explaining the operation of the data driving circuit of the liquid crystal display device according to the present invention.

The fifth switching element SW5 of the charge sharing section 145 is turned on to share the charge (or data voltage) remaining in the data line of the (n) th channel and the data line of the (n + 1) .

Then, after the garbage display period before the power is turned on and the gate start pulse GSP is present, the seventh switching device SW7 is turned on during one horizontal period (1H) to turn on the VSSH Applies the voltage to the shared channel, and the sixth switching element SW6 is turned on to apply the HVDD voltage to the shared channel during the 8 horizontal lines (8H) period (t2).

(T3), the fifth to seventh switching elements SW5, SW6, and SW7 of the charge sharing section 145 are all turned off, and the first to fourth switching elements SW1 SW2, SW3 and SW4 are selectively switched so that the positive polarity data voltages output from the positive polarity D / A converters (PDAC) to the data lines of the (n) th channel and the (n + The negative polarity data voltage outputted from the negative polarity DA converter NDAC is applied to display an image.

Since the HVDD voltage is applied during the 8 horizontal periods before the power is turned on and the image is displayed, the first to fifth switching elements of the switch array 143 and the charge sharing section 145 are constituted by MV class MOS transistors The breakdown voltage of the first to fifth switching elements can be improved.

Also, since the gate output enable (GOE) masking can be controlled before the first scan pulse output, the white display is not recognized during the eight horizontal periods when the HVDD voltage is applied.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

SR: Shift register LAT1, LAT2: Latch
DAC: DA conversion section 143: switch array
141: charge control section 145: charge share section

Claims (5)

A shift register for outputting a sampling signal in response to a source start pulse and a source sampling clock output from the timing control unit;
A latch unit for sequentially sampling a digital data signal in response to the sampling signal and simultaneously outputting a sampled data signal corresponding to the source output enable signal SOE;
The data signal for one line is converted into an analog data voltage corresponding to the first to n-th gamma gradation voltages, and converted into a positive (+) data voltage and a negative (-) data voltage corresponding to the polarity control signal, A DA converter;
A switch array for alternately outputting the positive polarity data voltage and the negative polarity data to adjacent channels; And
And a charge sharing unit sharing charge to the neighboring channel, supplying a VSSH voltage during one horizontal period after a garbage display period, and supplying an HVDD voltage during a predetermined horizontal period. The method according to claim 1,
Wherein the charge sharing unit comprises: a first switching device for switching the adjacent channels to share charges;
A second switching element for supplying a VSSH voltage to a channel sharing the charge during one horizontal period after the garbage display period,
And a third switching element for supplying the HVDD voltage to the channel sharing the charge during a predetermined horizontal period. The method according to claim 1,
Wherein the predetermined horizontal period is from 5 horizontal periods to 10 horizontal periods. Sharing remaining charge in data lines of adjacent channels;
Applying a VSSH voltage to the shared channel for one horizontal period after a power-on and a garbage display period before a gate-start pulse is applied;
Applying an HVDD voltage to the shared channel for a predetermined horizontal period; And applying a positive polarity data voltage or a negative polarity data voltage to the adjacent channels, respectively. 5. The method of claim 4,
Wherein the predetermined horizontal period is from 5 horizontal periods to 10 horizontal periods.

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