KR20170135896A - EUV tolerant trenches and hole patterning using dual frequency capacitively coupled plasma (CCP) - Google Patents

Abstract

A method for etching an anti-reflective coating (604) on a substrate is disclosed. The substrate 600 includes an organic layer 606, an antireflective coating layer 604 disposed over the organic layer 606, and a photoresist layer 602 disposed over the antireflective coating layer 604. The method includes patterning the photoresist layer 602 to expose a non-masked portion of the antireflective coating layer 604 and patterning the unmasked portions of the antireflective coating layer 604 and the patterned photoresist 604. [ (608) selectively depositing a carbon-containing layer (609) on a non-sidewall portion of the layer (602). The method also includes etching the substrate 600 to remove the carbon-containing layer 609 and remove the partial thickness of the unmasked portion of the anti-reflective coating layer 604 without reducing the thickness of the photoresist layer 602 (610). The method includes repeating 612 the optional deposition 608 and etch 610 until at least the entire thickness of the unmasked portion of the antireflective coating layer 604 is removed to expose the lower organic layer 606, .

Description

EUV tolerant trenches and hole patterning using dual frequency capacitively coupled plasma (CCP)

37 C.F.R. In accordance with § 1.78 (a) (4), this application is a continuation-in-part of U.S. Provisional Application No. 62 / 142,020.

The present invention relates to semiconductor processing techniques and, more particularly, to an apparatus and method for controlling attributes of a processing system for processing substrates.

10 nm and sub-10 nm (sub-10 nm) patterning technology nodes are one of the key challenges in the semiconductor industry. Several patterning techniques are under study to enable the aggressive pitch requirements required by logic technology. Extreme ultraviolet (EUV) lithography-based patterning is considered a major candidate for sub-10 nm nodes. One challenge with EUV technology is that EUV resists tend to have lower etch selectivity and worse line edge roughness (LER) and line width roughness (LWR) than traditional 193 nm resists will be. As a result, the characteristics of the dry etching process play an increasingly important role in defining the results of the patterning process.

Sub-30 nm node semiconductor fabrication suffers from the physical limitations of traditional lithography techniques. There is a need for an alternative patterning strategy involving augmentation of 193i lithography with LELE (Litho-Etch-Litho-Etch), Self Aligned Double Patterning (SADP) and Self Aligned Quadruple Patterning (SAQP). However, a large number of patterning methods have been used in the form of edge placement errors, higher costs due to more passes through lithography and other processing steps, and the introduction of pitch walking at some processing steps Brings up a challenge.

The disclosed method provides greater EUV photoresist etch selectivity and significantly reduced line edge roughness (LER) and line width roughness (LWR) compared to conventional approaches.

According to an embodiment, a method of etching an antireflective coating layer on a substrate is disclosed. The substrate includes an organic layer, an antireflective coating disposed over the organic layer, and a photoresist layer disposed over the antireflective coating. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and patterning the non-masked portions of the antireflective coating layer and the non-sidewall portions of the patterned photoresist layer. And selectively depositing a carbon-containing layer on the portion. The method also includes etching the film stack to remove the carbon-containing layer and to remove the partial thickness of the unmasked portion of the anti-reflective coating layer without reducing the thickness of the photoresist layer. The method further includes repeating selective deposition and etching until at least the entire thickness of the unmasked portion of the anti-reflective coating layer is removed to expose the underlying organic layer.

According to an embodiment, an additional method of etching a patterned substrate is disclosed. The method includes providing a patterned substrate comprising a patterned EUV (extreme ultraviolet) photoresist, a transfer layer (TL), and an organic planarizing layer (OPL). The method further comprises repeatedly performing a deposition / etching process to selectively etch progressively through the TL and to the OPL, wherein the EUV photoresist and the TL act as a mask for transferring the pattern from the EUV photoresist to the OPL do. The deposition / etching process includes the following two sub-processes in order. In a first sub-process (1), the method comprises depositing a fluorocarbon layer on a patterned substrate comprising a film on an exposed portion of an EUV photoresist and a TL or OPL. In the second sub-process (2), the method includes a reactive ion etching step to selectively remove an increased portion of TL or OPL relative to the fluorocarbon layer and the EUV photoresist. The method further comprises repeatedly performing the deposition / etching sub-processes (1) and (2) to etch the larger photoresist etch selections TL and OPL than would be obtained by performing only a reactive ion etch process.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included in and constitute a part of this specification and which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention in conjunction with the following detailed description and the generic description of the invention. In addition, the leftmost digit of the reference numerals indicates the first reference numerals.
FIG. 1A shows line edge roughness (LER), line width roughness (LWR), and contact edge roughness obtained from conventional EUV lithography techniques.
Figure IB shows higher defects due to conventional EUV lithography techniques that can lead to chip failure during electrical testing.
Figure 1C illustrates a reduction in etch resistance and a decrease in resist margin due to conventional EUV lithography techniques that require high selectivity transfer layer etch.
2 is a schematic diagram 1000 of a dual frequency capacitively coupled plasma (CCP) reactor used to etch an EUV patterned substrate according to an embodiment.
Figure 3a shows top-down and cross sectional electron micrograph images of line / space and contact / bar reference structures after and after lithography and etch pattern transfer, in accordance with an embodiment.
3B is a schematic diagram of a typical material layer stack for EUV patterning, in accordance with an embodiment.
3C is a plot of normalized values of critical dimensions, LER and LWR at each step of processing, according to an embodiment.
4A is a schematic diagram of a process of direct current superposition (DCS) obtained by applying a DC potential to an upper electrode of a CCP chamber, in accordance with an embodiment.
Figure 4B shows a top-down and cross-sectional electron micrographic image showing the effect of DCS on organic selectivity during transfer layer etching, according to an embodiment.
Figure 5A schematically shows an incoming stack for EUV patterning.
Figure 5B shows a cross-sectional electron micrograph showing the effect of DCS curing and etching process optimization on resist selectivity in the application of EUV lithography to trench patterning of the stack of Figure 5a, in accordance with an embodiment.
6 is a schematic diagram of a repeat deposition / etching process according to an embodiment.
7 is a table showing process conditions for an exemplary film deposition / etching process, according to an embodiment.
8 shows a cross-sectional electron micrograph showing the effect of the film-forming / etching process in comparison with the conventional etching according to the embodiment.
Figures 9A-9E illustrate the evolution of LER and LWR during trench patterning using EUV lithography to demonstrate improvements in LER and LWR due to the use of a deposition / etching process, in accordance with an embodiment.
Figures 10A-10E illustrate effect aspect ratios for pattern wiggling and distortion.
11A shows the mechanical stability and resulting downstream pattern roughness of the organic flattening agent layer obtained using the prior art.
Figure 11B shows the effect of the DCS curing process on the mechanical stability of the organic planarization layer and the resulting downstream pattern roughness, in comparison to a process without DCS curing as shown in Figure 11A.
Figures 12A and 12B show top-down cross-sectional electron micrograph images of scummed contact holes and bridged contact hole defects, respectively.
Figure 13 shows the results of a conventional approach to reducing defects in a contact hole array based on tuning of PR selectivity.
Figure 14 illustrates the results of an approach to reducing defects in a contact hole array based on a technique involving performing a repetitive deposition / etching process, in accordance with an embodiment.
15 shows a cross-sectional electron micrograph image taken at three stages of TL open etch, according to an embodiment.

The following detailed description refers to the accompanying drawings which show an exemplary embodiment consistent with the present disclosure. It is to be understood that, in the detailed description, "an embodiment", "an embodiment", "an example embodiment", etc. indicates that the illustrative embodiments described may include a particular feature, structure, That an embodiment does not have to include a particular feature, structure, or characteristic. Further, these phrases do not need to show the same embodiment. Also, it should be understood that when a particle feature, structure, or characteristic is disclosed in connection with an embodiment, whether it is specifically disclosed to affect such feature, structure, or characteristic in relation to other exemplary embodiments Within the knowledge of the technician of the machine.

The exemplary embodiments disclosed herein are provided for purposes of illustration and not limitation. Other embodiments are possible, and modifications to the illustrative embodiments are possible within the scope of this disclosure. Accordingly, the detailed description is not meant to limit the present disclosure. Instead, the scope of the present disclosure is defined only by the following claims and their equivalents.

The following detailed description of the exemplary embodiments is provided to enable any person of ordinary skill in the art to make modifications and adaptations to these exemplary embodiments for various applications without undue experimentation without departing from the scope of this disclosure by applying the knowledge of the ordinary artisans, / RTI > and / or < RTI ID = 0.0 > adaptable < / RTI > Accordingly, such adaptations and modifications are intended to be within the meaning of the exemplary embodiments and the plurality of equivalents based on the teachings and guidance herein disclosed. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, in order that the terminology or phraseology of the specification may be understood by those of ordinary skill in the art in view of the teachings herein.

Sub-30 nm node semiconductor fabrication suffers from the physical limitations of traditional lithography techniques. EUV lithography is a promising approach to the challenges of patterning at 10 nm and sub-10 nm technology nodes. However, EUV lithography also suffers from a number of significant challenges, for example, as shown in Figures 1A-1C.

FIG. 1A shows line edge roughness (LER), line width roughness (LWR), and contact edge roughness obtained from conventional EUV lithography techniques. In another embodiment, Figure IB shows a higher defect due to conventional EUV lithography techniques that can lead to chip failure during electrical testing. In yet another embodiment, FIG. 1C illustrates a reduction in etch resistance and a decrease in resist margin due to conventional EUV lithography techniques that require high selectivity transfer layer etch.

The photoresist budget is constantly decreasing for each technology node. The ability to perform lithography at a smaller pitch follows a trade-off of PR thickness. The typical thickness of the PR for the sub-30 nm technology node is 60-20 nm, and there is a smaller technology node with a thinner combustion resist that can be used for dry etching. In addition, the etch resistance of EUV resists is much smaller than the 193 / 193i lithographic resist, and a further need exists for the development of etching processes to provide a higher selectivity process. Efforts to overcome these challenges include optimizing EUV sources and developing new EUV resist materials.

This disclosure presents lithography techniques based on capacitively coupled plasma (CCP) dry etching methodology to meet EUV patterning challenges. The disclosed systems and methods use a dual frequency CCP in a patterning process that involves repeated deposition / etching processes. As described below, the disclosed embodiments show improvements in LER / LWR, resist selectivity, and critical dimension (CD) tunability for hole and line patterns. The results obtained using the disclosed embodiments are compared to those obtained using conventional plasma hardening methods. Data from a systematic stud showing the key patterning metrics, resist selectivity, and the role of various plasma etch parameters affecting the LER / LWR of the CD are presented.

According to an embodiment, one technique for improving LER and LWR involves superimposing a negative DC voltage on a radio-frequency (RF) plasma at one of the electrodes of the plasma reactor. The resulting emission of ballistic electrons with plasma chemistry has been shown to improve LER and LWR as described in more detail below.

2 is a schematic 200 of a dual frequency CCP reactor used to etch an EUV patterned substrate according to an embodiment. The wafer 202 to be patterned is mounted on an electrostatic chuck (ESC) 204. According to an embodiment, a bias RF voltage 206 may be applied to the ESC to fix the voltage on the wafer 202. The reactor may include an upper electrode (EL) 208 to which a high frequency (HF) voltage 210 may be applied. In addition to the HF voltage 210, a negative DC voltage 212 may also be applied to the top El 208. According to an embodiment, a DC anode El (214) may be provided. According to an embodiment, a 1 kV DC bias 216 that may be applied may be applied between the top EL 208 and the DC anode EL 214.

According to an embodiment, an ionized plasma is applied to the reactor of Figure 2 through the introduction of a process gas and application of a bias voltage 206 to the ESC 204, top EL 208, and anode EL 214 . According to an embodiment, the process gas may include Ar, N ₂ H _2, and various flow Oro carbon (CF _x). The application of the DC potential to the top EL 208 produces a plasma having a lower region 216 and an upper region 218. [ The upper region 218 is a sheath having a higher plasma density than the lower region 216 and a more uniform radial distribution of the plasma. The process of generating a plasma using the DC potential is referred to as direct current superposition (DCS) or DCS curing, as described in more detail below (see Figures 4A and 4B and related discussion).

Initial etch feasibility studies using EUV-based photoresists were run on relaxed pitch samples to determine the effects of resist material changes on CD bias control and pattern fidelity. For this task, patterning was performed using the IBM EUV lithography tool set.

Figures 3A-3C illustrate the results of an initial etch feasibility study according to an embodiment. Figure 3a shows top-down and cross sectional electron micrograph images of line / space and contact / bar reference structures after and after lithography and etch pattern transfer, in accordance with an embodiment. 3B is a schematic diagram of a typical material layer stack for EUV patterning, in accordance with an embodiment. A three-layer patterning scheme of a photoresist (PR) 302, a transfer layer (TL) 304, and an organic flatting agent layer (OPL) 306 was used. TL 304 has been selected because of its high level of plasma etch selectivity for both PR 302 and OPL 306 and OPL 306 has the advantage of flattening any existing terrain as its name implies. According to an embodiment, a trilayer stack may be created on top of the dielectric stack 308.

Four reactive ion etch (RIE) process conditions, referred to as RIE1 - RIE4, are used to control the CD bias control of 0 to 50% of the incoming develop CD, Lt; RTI ID = 0.0 > open. ≪ / RTI > In RIE1 - RIE4, changes were made in at least one of time, pressure, electrode frequency, DC potential, gas flow rate, or substrate temperature. In the sparse '0 etch bias' case, some initial concerns about the PR budget turned out to be negligible because no LER degradation or bridging was observed. In addition, all etch cases exhibit a dramatic improvement of LWR of approximately 63% compared to incoming (i.e., with respect to incoming patterned resist) regardless of the etch conditions. The LER is slightly degraded as a function of the CD bias and an indication that the fluorocarbon (CF _x ) passivation used in the transport layer opening is greater than desired and contributes to LER generation, as shown, for example, in Figure 3C . 3C is a plot of normalized values of critical dimensions, LER and LWR at each step of processing, according to an embodiment.

Aggressive pitch scaling for line-space applications leads to high aspect ratios in the photoresist leading to pattern collapse margins. At the same time as EUV resist height scaling, it is desirable to reduce the TL thickness to reduce the etch selectivity requirement. The lower limit of the TL thickness is dictated, in part, by the hermeticity of the resist solvent and developer. One of the challenges associated with EUV resists is the selectivity when transferring a pattern to a TL. Therefore, in order to reduce LER and LWR to enable good pattern transfer, it is preferable to have good resist selectivity. In order to achieve the appropriate pattern transfer fidelity, according to an embodiment, it is assumed that the etch selectivity should be TL: EUV PR > 5: 1.

The above results are typical of conventional EUV lithography techniques. According to the embodiment, as discussed below, improved results can be obtained through the use of the DCS technique.

4A is a schematic diagram of a process of DCS obtained by applying a DC potential to an upper electrode of a CCP chamber, in accordance with an embodiment. In this process, application of the DC potential to the upper EL 402 changes the radial distribution of the plasma relative to the plasma generated without application of a DC bias and increases the plasma density to produce a thicker upper sheath 404.

Further, according to the embodiment, the DC potential accelerates the positive ions 406 toward the upper electrode. The collision of the positive electrode with the upper electrode generates a secondary electron emission 408 accelerated by the DC potential toward the wafer surface 410. The electrons have sufficient energy to penetrate the bottom sheath 412 and to affect the process at the wafer surface 410, including charge erasing and cross-coupling of the organic film comprising the resist 414. [ This electron beam induced cross-linking / curing can improve the etch selectivity for organic photoresists and organic planarizers.

Figure 4B shows a top-down and cross-sectional electron micrographic image showing the effect of DCS on organic selectivity during transfer layer etching, according to an embodiment. Obviously, using a process without DCS as compared to the result (418) obtained using DCS consumes more resist. In addition, the improved CD bias 420 is obtained using DCS rather than the bias 422 obtained when DCS is not used. The comparison results with and without DCS are as follows.

Figure 5a schematically depicts a stack for EUV patterning and Figure 5b illustrates a cross section of the stack showing the effect of DCS curing and etching process optimization on resist selectivity in the application of EUV lithography to trench patterning, Electron microscope photograph image. 5A, a stack for EUV patterning 502 includes an EUV patterned PR 504, a TL 506, and an organic flattening layer 508, which are formed on top of the dielectric stack 510. In this embodiment, (OPL) 508. The PR 504 has been patterned with a feature 512 representing a pitch of less than 40 nm.

The first panel 514 of Figure 5B is a cross-sectional electron micrographic image of the incoming patterned substrate prior to etching. The second panel 516 of Figure 5B shows the result of a conventional transfer layer opening applied to the trenches. This has a low resist selectivity (i.e., 1.3: 1) for the EUV resist and consumes most of the resist during TL opening resulting in poor pattern transfer. In the third panel 518, DC voltage based processing was employed prior to the transfer layer opening process. Ballistic electrons generated by the DC voltage applied to the top electrode can be collected at the wafer level and can lead to hardening and curing of the resist. For this EUV resist, the DC voltage based pretreatment also showed an increase in resist selectivity of 2.2: 1.

The fourth panel 520 of Figure 5B shows an increase in resist selectivity due to a decrease in ion energy. In this example, the reduction of the ion energy in the transfer layer opening step improved the resist selectivity to 3.6: 1. Reduction of the ion energy also improved the EUV resist profile, thereby reducing the "erosion" of the resist edges and maintaining a more linear profile.

According to an embodiment, the results of Figure 5B illustrate that selectivity for EUV resists can be incrementally increased for a conventional TL opening process. To dramatically improve resist selectivity, a repeat deposition / etch process has been developed, as described in more detail below. The results obtained using the repeated deposition / etching process are shown in the fifth panel 522 of FIG. 5B. This result shows a dramatic improvement in resist etch selectivity from 3.6: 1 to 7.8: 1 using the deposition / etching process of an embodiment of the present invention.

6 is a schematic diagram of the repeated deposition / etching process according to an embodiment. This approach is based on a process sequence consisting of a deposition process followed by an etching process. In this embodiment, the incoming substrate 600 includes an organic layer 606 such as PR 602, TL 604, and OPL. According to an embodiment, Pr 602 is an organic photoresist, such as an EUV photoresist. Also, according to an embodiment, the TL 604 may be a silicon anti-reflection coating (SiARC). The PR 602 is patterned such that the Pr 602 masks a portion of the underlying TL 604 while exposing an unmasked portion of the TL 604. [

In the first step or stage, a deposition process 608 is performed. According to an embodiment, a carbon containing layer 609, such as a fluorocarbon (CF _x ) polymer, may be deposited on the substrate during the deposition process 608. Preferably, the CF _x polymer is deposited on the exposed unmasked portion of the TL 604 and on the non-sidewall portion of the PR 602. The flux of the ion flux and the CF _x radical can be controlled by applying a DC voltage to the upper El (e.g., 402 in FIG. 4). According to an embodiment, the ion flux may have a relatively low energy (e.g., < 100 eV). In the deposition step 608, the gas flow of the fluorocarbon gas controls the CF _x radical flux and thus controls the deposition. According to the embodiment, the CF _x polymer is preferentially deposited on the resist pattern. In other words, the CF _x polymer is deposited thicker on the non-sidewall portion of the PR 602 than the unmasked portion of the TL 604.

According to an embodiment, in a second step or stage, a reactive ion etching 610 is performed. In reactive ion etching 610, a portion of the TL 604 may be preferentially etched while the PR 602 remains large. In other words, the partial thickness of the TL 604 is etched without reducing the thickness of the PR 602 to some extent. In one embodiment, DCS is used during etch 610 to cure PR 602 as TL 604 is etched, thereby facilitating preferential etch.

In a further step or stage, the sequential process of deposition 608 followed by etching 610, as indicated by arrow 612, is repeated. As the iterative process proceeds, the TL 604 is etched following the etch of the bottom OPL to transfer the pattern to the OPL 606. According to an embodiment, this repetitive process obtains a structure 614 in which the TL 604 and planarization layer are etched without significantly impairing the PR. The number of times the sequential film deposition 608 / etch 610 process is to be repeated is determined by the initial thickness of the TL 604 and the organic layer 606 and the etched portion thickness in each iteration.

FIG. 7 is a table 700 illustrating process conditions for an exemplary film / etch process, in accordance with an embodiment. In this embodiment, the first film forming process fluorocarbons for _{(702) (CH 3 F)} (704) and CF ₄ (706) is H ₂ (708) at a gas flow rate of 40 sccm, 50 sccm and 330 sccm, respectively, and Together are introduced into the plasma reactor. During the first etch / cure process 710, the flow of fluorocarbons 704 and 706 is stopped and H ₂ 708 and N ₂ 712 are introduced into the plasma reactor at a gas flow rate of 450 sccm, respectively. The alternate film deposition / etching (curing) is repeated with a predetermined number of repetitions.

In this embodiment, the combined deposition / etching (curing) process is repeated three times. In another embodiment, the deposition / etching (curing) process may be repeated as desired at any predetermined number of times. Other process parameters provided in the table 700 may be supplied to the ESC 204 (see FIG. 2) via the gas pressure 714, power 716 supplied to the top E 208 (see FIG. 2) at high frequency HF, And the DC voltage 720 applied to the top EL 208 (see FIG. 2).

FIG. 8 shows a cross-sectional electron micrographic image 800 showing the effect of the deposition / etching process in comparison to a conventional etch, according to an embodiment. The first image 802 illustrates an incoming substrate having a patterned PR 804, SiARC transfer layer 806 and OPL 808. The second image 810 clearly shows that the PR 804 is consumed during the SiARC etch process by conventional processes. The third image 812 shows the results of the deposition / etching (curing) process of an embodiment of the present invention after the SiARC 806 is etched and the OPL 808 is partially etched. In this embodiment, the PR 814 is not damaged and the height of the PR 814 is not reduced.

Figures 9A-9E illustrate the evolution of the LER and LWR during trench patterning using EUV lithography to demonstrate improvements in LER and LWR due to the use of one cycle of the deposition / etching process, in accordance with an embodiment. DC voltage based plasma conditions allow good control of the CF _x radical flux at relatively low ion energies to help maintain the resist budget and resist profile.

9A is a schematic cross-sectional view of an incoming substrate 900. The incoming substrate 900 includes a patterned resist 902, a transfer layer 904, and a leveling agent 906. According to an embodiment, the substrate 900 may also include a hard mask (HM) stack 908. An HM stack 908 may be provided on top of the dielectric stack 910 and used to pattern the dielectric stack 910.

FIG. 9B includes top-down electron micrographic images 912, 914, 916, and 918 showing the features of the etched substrate at different stages of the etching process. Image 912 represents the substrate after EUV lithography. Image 914 represents the substrate after the TL etch ("TL opening") process. Image 916 represents the substrate after the HM stack open process. Image 918 shows the substrate after the trench and dielectric layer etch process. The results for LER evolution are shown in graph 920 of FIG. 9c. The results for LWR deployment are shown in graph 922 of FIG. 9D. These results indicate that good CD uniformity as measured after TL layer opening has been achieved. These results also show a reduction of about 25-30% of the measured LER and LWR, as summarized in table 924 of Figure 9e.

FIGS. 10A-10E illustrate effective aspect ratios for pattern misalignment and distortion using one cycle of the film deposition / etching process, according to an embodiment. Unlike the multiple patterning approach, EUV lithography allows a complete line-space pattern to be exposed in a single pass. As the line-space pitch decreases, the high aspect ratio of the soft mask reduces the relative mechanical stability. This causes pattern distortion and misalignment depending on the aspect ratio.

10A, a top-down electron micrographic image 1002 shows good results for patterning a substrate having an aspect ratio of approximately 4.1. 10B, a similar top-down electron micrographic image 1004 shows good results for patterning a substrate having an aspect ratio of approximately 4.25. However, the distortion in the resulting patterned substrate is observed for a substrate having an aspect ratio greater than about 4.5. For example, in FIG. 10C, a top-down electron micrographic image 1006 shows pattern distortions (i.e., LER and LWR) for patterning a substrate having an aspect ratio of approximately 4.6. In the top down electron microscope photographic image 1008, significant discrepancy distortion is observed for a substrate having an aspect ratio of about 6.1, as shown in Figure 10D. The results of Figures 10a-10d are graphically depicted in Figure 10e where the normalized CD is displayed as a function of aspect ratio.

According to the embodiment, if the aspect ratio of the soft mask is kept below 4.5, good pattern transfer to the hard mask can be achieved even at small pitch sizes, as shown in Figs. 10A, 10B and 10E. At an aspect ratio of 6.0 or higher, the soft mask can no longer maintain the pattern and a shift is induced, as shown in the image 1008 in Figs. 10D and 10E. Between 4.5 and 6.0 aspect ratios, a small amount of pattern distortion is observed, as shown in Figures 10c and 10e.

The aspect ratio of the soft mask is determined by the pitch dimensions required for integrated and planarizing material performance. A thinner planarization layer reduces the aspect ratio, but the process of reliably creating such a layer can be challenging and limits the design of the stack. Also, as a result, a thinner soft mask is generated in subsequent steps, requiring an additional high selectivity process. The onset of pattern distortion may also depend on the etch chemistry used to etch the planarization layer. The use of new etch chemistries and conditions can impart rigidity to the soft mask and enable a process free from high aspect ratios.

For example, top-down inspection through a partition of the etch sequence, as shown in FIGS. 9A-9E, provides some additional insight into the mechanism for inducing line misalignment. Although the edge roughness is obvious after the TL strip, a remarkable decrease in line shift after the mask CD growth and oxide etching is observed. It is possible to induce a compressive stress in which the CF _x film formation or swelling of the soft mask from plasma chemical exposure is relaxed through line displacement. This non-ideal phenomenon can be transferred directly to the dielectric as shown in a post-ash image (discussed further below with reference to FIGS. 11A and 11B). The application of DCS hardening before or during TL opening can eliminate this discrepancy. At an aggressive pitch of 40 nm or less where the discrepancy is most obvious, the effect becomes dramatic and easily apparent by visual inspection as shown in Figs. 11A and 11B, and is described in more detail below.

11A and 11B illustrate the effect of the DCS curing process on the mechanical stability of the organic planarization layer and the resulting downstream pattern roughness, according to an embodiment. Process 1102 of Figure 11A illustrates the results obtained for etching a high aspect ratio substrate without the application of a DCS curing process. Although an aspect ratio of about 5: 1 is used in this embodiment, other aspect ratios are also contemplated. Process 1104 of FIG. 11B illustrates the improved results obtained for etching a high aspect ratio substrate without the application of a DCS curing process. Panel 1106 schematically illustrates an incoming substrate. Panel 1108 schematically illustrates the substrate after the TL opening operation is applied. The third panel 1110 includes a top-down electron micrographic image 1112 showing significant deviations after the organic mask opening / TL strip process. The fourth panel 1114 includes a top-down electron micrographic image 1116 showing the increased offset after the oxide etch process. Panel 1118 includes a top-down electron micrographic image 1120 that represents a significant deviation of the final etched dielectric.

The effect of performing the DCS curing process is illustrated in process 1104 of FIG. 11B. Panel 1122 schematically illustrates a matching substrate that is the same as the incoming substrate in process 1102. Panel 1124 schematically illustrates the substrate after the TL opening operation has been applied, and the TL opening operation includes the application of a DCS curing process. Panel 1128 schematically illustrates the organic mask open / TL strip operation, and panel 1128 schematically illustrates the oxide etch process. Panel 1130 includes a top-down electron micrographic image 1132 of the final etched dielectric. The image 1132 clearly illustrates the improved LER and LWR characteristics obtained from the DCS curing process of the panel 1124, in contrast to the image 1120 obtained by pouring into the etching process performed without the DCS curing process.

Figs. 11A and 11B show the results of two processes by the same post-etch CD and corresponding flattener aspect ratios. Without DCS cure at TL opening, the LWR is improved by 34% from incoming (Fig. 11A). The inclusion of DCS cure prior to TL opening (FIG. 11B) provides an additional improvement of 52% reduction from incoming. Significant improvement in LER and LWR was also observed (results not shown here) for substrates with planarizer aspect ratios that are much lower than previously identified 4.5: 1 threshold values.

The improved results obtained using the DCS curing process shown in FIG. 11B can be attributed to the interaction of the traction electrons with the planarizing agent stack. With scaled resist, TL, and planarizing agent thickness, the traction electrons penetrate well into the planarizing agent stack and provide improved mechanical resistance to previously observed stress-induced deformation during oxide etching. .

Another pattern fidelity task observed for this evaluation is to provide a top-down cross-sectional electron micrograph of each of the " scummed "contact holes and bridged contact hole defects, as shown in FIGS. 12A and 12B, , A missing for a dense 1 x 1 contact hole array, and a tradeoff between bridged contacts. A precise inspection of the incoming pattern can be accomplished by the fact that the resist material is developed partially incompletely from the intended hole and is partially bridged with the resist height between adjacent contacts 1202 that is much smaller than intended Reveals contact 1204.

The conventional etching process can solve two problems independently (i.e., a scummed contact 1202 or a bridged contact 1204), but before the TL is opened (to cure the scum generation defects) - There is a PR budget that is inadequate to insert a de-scum process. There is also an insufficient margin to simply tuning the PR selectivity of the TL opening.

Figure 13 illustrates a conventional approach to reducing defects in a contact hole array based on tuning of PR selectivity. In this embodiment, Fig. 13 shows three arrays 1302, 1304 and 1306, respectively, by application of a low, medium, and high PR selectivity TL opening recipe. The three arrays 1302, 1304 and 1306 were 1x1 contact holes each having 2200 contacts. In each case, the contacts were inspected for missing or bridged contacts. While this sampling rate of the 2200 contacts is very low in the fabrication level yield analysis, it provides adequate resolution to observe the trade-off between competitive defect modes as a function of resist selectivity.

The result in Figure 13 clearly shows that there is a tradeoff between the bridged contact and the scum generating contact as a function of tuning the PR selectivity. For example, in the low PR selectivity in the array 1302, the bridged contacts 1310 are formed preferentially over the scum generating contacts. However, the scum generating contacts 1312 and 1316 are preferentially formed over the bridged contacts as the PR selectivity increases at the intermediate PR selection in the array 1304 and increases at the high PR selection in the array 1306. For example, when a low PR selectivity recipe is used, a scumming contact is not detected in the array of 2200 contact holes 1302, and four bridged contacts 1310 are observed. When the intermediate PR selectivity recipe was used, five scum generating contacts 1312 were observed in an array 1304 of 2200 contact holes, but bridged contacts were not observed. Finally, when a high PR selectivity recipe was used, twenty scum generation cones 1316 were observed in an array 1306 of 2200 contact holes, but bridged contacts were not observed.

FIG. 14 is a flow diagram of a method of fabricating a contact hole array (not shown) based on a technique including performing a repetitive deposition / etching process (described above and shown in FIGS. 5A, 5B, 6, 7, and 8) &Lt; / RTI &gt; shows the result of an approach to reducing defects in the field. Fig. 14 shows that there is no scum occurrence defect for the array of 2200 contact holes 1402, and no bridge contact is observed. This result represents a significant improvement over the prior art approach shown in FIG. A possible explanation for these improved results is as follows.

Further characterization of the high selectivity (7.8: 1 shown in panel 522 of FIG. 5B) deposition / etching process described above provides an understanding of possible explanations for the improved results of FIG. The results of this survey are presented in FIG. 15 as follows.

15 shows a cross-sectional electron micrograph image taken at three stages of TL open etch, according to an embodiment. The application of the standard TL opening recipe results in a trapezoidal mask shape with a monotonic taper, as shown in the image 1502. The application of the DCS-enhanced deposition process deposits CF _x polymer preferentially onto the resist, as shown in image 1504, to produce a more vertical profile. When the film formation time is doubled, a film formation depending on the aspect ratio occurs. As shown in the image 1506, the top of the structure is rounded and polymer overhangs are formed. Preferential deposition of CF _x on a resist with a low aspect ratio structure provides a mechanism by which a weak portion of a partially bridged contact hole can be passivated without significant deposition on scumming / remaining resist at the bottom of a high aspect ratio hole do. As shown in Figure 14, cycling this new deposition process with organic etch / descum is applied prior to TL opening to remove arra- nent elimination or shear for the 2200 sampled contact holes (both) &lt; / RTI &gt; fault mode (i.e., scum occurrence and bridged contact).

The disclosed method, including repetition of deposition / etch sequences, has successfully demonstrated CCP plasma based etching solutions that enable EUV lithography for trench and contact hole patterning applications. The application of EUV reduces the reticle count, cycle time, integration complexity, and internal level overlay changes for sub-40 nm pitch applications. This approach demonstrates the commitment to reducing the incoming organic mask thickness to avoid pattern collapse.

The disclosed methods also show the application of DCS in a deposition / etching sequence to advantage in improving organic stiffness and etch resistance. DCS also helps mitigate pattern distortion that occurs during the flattener layer opening process, thereby reducing the downstream pattern roughness. A plasma etching method has also been disclosed to provide high resist selectivity during trench patterning and to improve defects in contact hole patterning applications by selective passivation to resist patterns.

It is to be appreciated that a detailed description section, rather than a summary section, is intended to be used to interpret the claims. The Summary section may suggest one or more exemplary embodiments that are not exhaustive of the disclosure, and thus are not intended to limit the appended claims and the disclosure in any manner.

While this disclosure has been illustrated by a description of one or more embodiments and while the embodiments have been described in considerable detail, it is not intended that the scope of the appended claims be limited or limited in any way to such details. Additional advantages and modifications will readily appear to those of ordinary skill in the art. Accordingly, the invention in its broader aspects is not limited to the specific details, representative apparatus and method, and illustrative embodiments shown and described. Accordingly, departures may be made from these details without departing from the scope of the general inventive concept.

Claims (20)

A method for etching through an antireflective coating on a substrate,
Forming a film stack on the substrate, the film stack including a lower organic layer, an anti-reflective coating disposed over the lower organic layer, and a photoresist layer disposed over the reflective coating layer;
Patterning the photoresist layer to expose an unmasked portion of the antireflective coating;
Selectively depositing a carbon-containing layer on an unmasked portion of the antireflective coating and on a non-sidewall portion of the patterned photoresist layer;
Etching the film stack to remove the carbon-containing layer and to remove a portion thickness of the unmasked portion of the anti-reflective coating layer without reducing the thickness of the photoresist layer; And
Repeating the selective deposition step and the etching step until at least the entire thickness of the unmasked portion of the anti-reflective coating layer is removed and the lower organic layer is exposed
RTI ID = 0.0 &gt; a &lt; / RTI &gt; substrate comprising an antireflective coating. The method according to claim 1,
Wherein selectively depositing the carbon-containing layer comprises depositing a greater thickness on a non-sidewall portion of the patterned photoresist layer than on an unmasked portion of the antireflective coating layer. / RTI &gt; coating layer. The method according to claim 1,
Further comprising the steps of: generating secondary electron emissions to be accelerated to the substrate to facilitate the etching and to further remove the partial thickness of the unmasked portion of the anti-reflective coating layer without reducing the thickness of the photoresist layer; In order to make the impregnated photoresist layer more resistant to the etching by sputtering silicon atoms impregnated in the photoresist layer upon removal of the carbon-containing layer, a DC potential is applied to the upper silicon electrode during the etching Lt; RTI ID = 0.0 &gt; anti-reflective coating &lt; / RTI &gt; The method according to claim 1,
The etching step is to etch through the anti-reflective coating layer on the substrate by means of reactive ion etching using a plasma generated from N ₂ H ₂ gas. 5. The method of claim 4,
Wherein the lower organic layer is a planarizer layer, the antireflective coating layer is an SiARC layer, the photoresist layer is an extreme ultraviolet (EUV) photoresist layer, and the carbon containing layer is a fluorocarbon A method for etching on a substrate through an antireflective coating. A method of etching a patterned substrate,
Providing a patterned substrate comprising a patterned EUV (extreme ultraviolet) photoresist, a transfer layer (TL), and an organic planarizing layer (OPL); And
Repeatedly performing a film / etch process to selectively and progressively etch through the TL and into the OPL using the EUV photoresist and TL as a mask for transferring the pattern from the EUV photoresist to the OPL
Lt; / RTI &gt;
The film-forming / etching process is performed sequentially,
(1) depositing a fluorocarbon layer on the patterned substrate comprising the EUV photoresist and exposed portions of the TL or OPL; And
(2) selectively etching the reactive ion to remove the increased portion of the TL or OPL relative to the fluorocarbon layer and the EUV photoresist
Lt; / RTI &gt;
By repeatedly performing the above film-forming / etching processes [(1) and (2)], etching of the TL and OPL results in a photoresist etching selectivity greater than that of the photoresist etching selectivity obtained by performing only a reactive ion etching process Gt; a &lt; / RTI &gt; patterned substrate. The method according to claim 6,
The reactive ion etching step (2) comprises generating a dual frequency capacitively coupled plasma while superimposing direct current potentials. 8. The method of claim 7,
Wherein the plasma comprises N ₂ H ₂ . 9. The method of claim 8,
The direct current potential is applied to the silicon electrode to produce a silicon species in the plasma generated by sputtering from the silicon electrode, and the silicon atom acts to increase the etch selectivity of the EUV photoresist &Lt; / RTI &gt; 10. The method of claim 9,
Wherein a film of silicon is formed on the EUV photoresist to act to increase the etch selectivity of the EUV photoresist. The method according to claim 6,
Wherein the EUV photoresist and the OPL comprise a carbon polymer. 12. The method of claim 11,
Wherein the TL and the OPL are preferentially etched in step (2) relative to the EUV photoresist. The method according to claim 6,
Wherein the EUV photoresist etch selectivity obtained by repeatedly performing the film deposition / etching process is at least 7.8: 1. The method according to claim 6,
Wherein the fluorocarbon layer is preferentially deposited on non-sidewall portions of the patterned EUV photoresist relative to the TL. The method according to claim 6,
Repeatedly performing the deposition / etching process [(1) and (2)] may include etching the TL and OPL to improve the line width roughness by at least 52% Width line roughness of the patterned substrate. The method according to claim 6,
The step of repeatedly performing the film forming / etching process [(1) and (2)] is advantageous in that the TL and the OPL are etched to provide scummed defects and bridges Wherein all of the defects are reduced. 17. The method of claim 16,
Wherein the fluorocarbon layer is preferentially deposited to a greater degree in bridging defects than scum generation defects. The method according to claim 6,
Wherein the patterned EUV photoresist has a thickness less than 60 nm and a patterning critical dimension less than 40 nm, the TL comprises a silicon anti-reflective coating having a thickness less than 60 nm, the OPL having a thickness less than 200 nm And etching the patterned substrate. 8. The method of claim 7,
Wherein ballistic electrons generated through application of the direct current potential change and cure the EUV photoresist to enhance photoresist selectivity. The method according to claim 6,
A carbon layer as the fluorinated method for etching of the patterned substrate comprises a CH ₃ F and CF _4.

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