KR20170121773A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display apparatus, which can easily repair disconnection failure of a data line. The liquid crystal display apparatus comprises: a substrate; a data line and a gate line disposed on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a sustain line partially overlapping the pixel electrode, wherein the sustain line has a first hole in a position overlapping with the data line.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a display device, and more particularly, to a display device that improves disconnection of a data line.

2. Description of the Related Art A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPDs), and is composed of two substrates on which electrodes are formed and a liquid crystal layer sandwiched therebetween. A liquid crystal display device is a display device that adjusts the amount of light transmitted by applying voltages to two electrodes to rearrange the liquid crystal molecules in the liquid crystal layer.

A liquid crystal display device transmits a signal to a thin film transistor of each pixel using a data line and a gate line. When the data line is opened due to foreign substances in the process, a separate wiring must be formed for repair. However, this is an additional process, which causes the process efficiency to be lowered. Further, when the data line is opened after the process is completed, there is a problem that it is difficult to repair. Further, when the signal wiring such as the maintenance line or the like which is disposed in advance is used as the repair wiring, the signal wiring is inherently lost in its function.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device capable of easily repairing disconnection of a data line.

According to an aspect of the present invention, A data line and a gate line disposed on the substrate; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; And a sustain line partially overlapping the pixel electrode, wherein the sustain line includes a display device having a first hole at a position overlapping with the data line.

According to an embodiment of the present invention, the sustain line may include a horizontal portion disposed in parallel with the gate line and a vertical portion disposed in parallel to the data line.

According to an embodiment of the present invention, the transverse portion may have the first hole at a position overlapping the data line.

According to an embodiment of the present invention, the vertical portion may have a second hole at a position overlapping with the data line.

According to an embodiment of the present invention, the vertical portion may extend from a portion of the transverse portion overlapping the data line.

According to another aspect of the present invention, there is provided a plasma display panel comprising: a substrate; A data line and a gate line disposed on the substrate; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; And a retention line partially overlapping the pixel electrode, wherein the data line includes a protrusion overlapping a part of the retention line.

According to an embodiment of the present invention, the protrusion may be disposed in parallel with the gate line.

According to an embodiment of the present invention, the protrusion may overlap a part of the pixel electrode.

According to an embodiment of the present invention, the sustain line may include a horizontal portion disposed in parallel with the gate line and a vertical portion disposed in parallel to the data line.

According to an embodiment of the present invention, the vertical portion may be disposed between the pixel electrode and the data line.

According to an embodiment of the present invention, the projecting portion may overlap with a part of the vertical portion.

According to an embodiment of the present invention, the protrusion may overlap a part of the pixel electrode.

According to an embodiment of the present invention, the vertical portion may extend from the lateral portion.

According to an embodiment of the present invention, the holding line may further include a bending portion connecting the transverse portion and the vertical portion.

According to an embodiment of the present invention, the protrusion can overlap the bending portion.

According to an embodiment of the present invention, the protrusion may overlap a part of the pixel electrode.

The display device according to the present invention has an effect of improving the mono line rate of the data line by using the sustain line as a repair line of the data line.

In addition, since the sustain line of the present invention is used only as a repair line of a data line, the sustain line can still be used as a sustain voltage transmission path, unlike the conventional sustain line.

1 is a plan view schematically showing one pixel according to a first embodiment of the present invention.
2 is a sectional view taken along the line I-I 'in FIG.
3 is a cross-sectional view taken along line II-II 'of FIG.
4 is a cross-sectional view taken along lines III-III 'and IV-IV' in FIG.
5 is a diagram illustrating a method of repairing a data line from the pixel of Fig. 1 to a sustaining line.
6 is a plan view schematically showing one pixel according to the second embodiment of the present invention.
FIG. 7 is a diagram illustrating a method of repairing a data line from the pixel of FIG. 6 to a sustaining line.
8 is a plan view schematically showing one pixel according to the third embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures, and well-known techniques are not specifically described to avoid an undesirable interpretation of the present invention. Like reference numerals refer to like elements throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "below " another portion, it includes not only a case where it is" directly underneath "another portion but also another portion in between. Conversely, when a part is "directly underneath" another part, it means that there is no other part in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

In this specification, when a part is connected to another part, it includes not only a direct connection but also a case where the part is electrically connected with another part in between. Further, when a part includes an element, it does not exclude other elements unless specifically stated to the contrary, it may include other elements.

The terms first, second, third, etc. in this specification may be used to describe various components, but such components are not limited by these terms. The terms are used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second or third component, and similarly, the second or third component may be alternately named.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1 is a cross-sectional view taken along the line I-I 'of FIG. 1, and FIG. 3 is a cross-sectional view taken along line II-II' of FIG. 1 And Fig. 4 is a cross-sectional view taken along line III-III 'and line IV-IV' in Fig. 1, respectively.

1 to 4, one pixel includes a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, sustain lines 740 and 750, The first extension electrode 181, the second sub-pixel electrode PE2, the second extension electrode 182, the common electrode 210, and the liquid crystal layer 333 are formed on the first electrode 354, the first sub-pixel electrode PE1, . The maintenance lines 740 and 750 will be described as a first maintenance line 740 and a second maintenance line 750 for convenience of explanation.

The first thin film transistor TFT1 includes a first gate electrode GE1, a first semiconductor layer 311, a first drain electrode DE1 and a first source electrode SE1 as shown in Fig. do.

The second thin film transistor TFT2 includes a second gate electrode GE2, a second semiconductor layer 312, a second drain electrode DE2, and a second source electrode SE2, as shown in Fig. do.

The third thin film transistor TFT3 includes a third gate electrode GE3, a third semiconductor layer 313, a third drain electrode DE3 and a third source electrode SE3 as shown in Fig. do.

As shown in FIG. 1, the gate line GL is located on the first substrate 301. Specifically, the gate line GL is located in the transistor region T of the first substrate 301. The transistor region T is located between the first sub-pixel region P1 and the second sub-pixel region P2.

The gate line GL includes a line portion 411 having a different line width, a first gate electrode GE1, a second gate electrode GE2 and a third gate electrode GE3. For example, the first to third gate electrodes GE1, GE2, and GE3 may have a line width larger than the line portion 411. [ The line portion 411 and the first to third gate electrodes GE1, GE2 and GE3 are integrally formed.

Although not shown, the gate line GL may have a larger area of its connecting portion (for example, an end portion) than other portions thereof for connection with another layer or an external driving circuit.

The gate line GL may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy or a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) Or a molybdenum series metal such as molybdenum (Mo) or molybdenum alloy. Alternatively, the gate line GL can be made of any one of chromium (Cr), tantalum (Ta), and titanium (Ti). On the other hand, the gate line GL may have a multi-film structure including at least two conductive films having different physical properties.

The first holding line 740 is located on the first substrate 301. The first sustain line 740 is positioned around the boundary between the transistor region T and the first sub-pixel region P1 of the first substrate 301 and around the data line DL. The first sustain line 740 is adjacent to one side of the first sub-pixel electrode PE1. For example, the first sustain line 740 may be located on the upper side, the left side, and the right side of the first sub-pixel electrode PE1, as shown in FIG. 1, and may have a line shape. At this time, the first sustain line 740 and the first sub-pixel electrode PE1 may or may not overlap with each other. In the case where the first sustain line 740 and the first sub-pixel electrode PE1 are overlapped, at least one of the first sub-pixel electrode PE1 and a part of the first sustain line 740 may overlap, It can be overlapped with the stem electrode of the sub-pixel electrode PE1.

The first holding line 740 receives a first holding voltage from the outside. The first holding voltage may be a DC voltage.

The first sustaining line 740 may have the same material and structure (multi-film structure) as the above-described gate line GL. In other words, the gate line GL and the first sustaining line 740 can be made simultaneously in the same process.

The second holding line 750 is located on the first substrate 301. The second sustain line 750 is located around the boundary between the transistor region T and the second sub-pixel region P2 of the first substrate 301 and around the data line DL. The second sustain line 750 is adjacent to one side of the second sub-pixel electrode PE2. For example, the second sustain line 750 may have a line shape located on the upper side, the left side, and the right side of the second sub-pixel electrode PE2, as shown in FIG. At this time, the second sustain line 750 and the second sub-pixel electrode PE2 may or may not overlap with each other. In the case where the second sustain line 750 and the second sub-pixel electrode PE2 overlap, at least one side of the second sub-pixel electrode PE2 and a part of the second sustain line 750 may overlap, It can be overlapped with the stem electrode of the pixel electrode PE2.

1, unlike FIG. 1, the second sustain line 750 may not overlap the stem electrode of the second sub-pixel electrode PE2 and may overlap only the edge of the second sub-pixel electrode PE2.

The second holding line 750 and the first holding line 740 are not connected. That is, the second holding line 750 and the first holding line 740 are separated from each other.

The second sustain line 750 receives a second sustain voltage from the outside. The second sustain voltage and the first sustain voltage may have different magnitudes. For example, the second sustaining voltage may be a DC voltage that is greater than or less than the first sustaining voltage.

When the second sustain voltage is set to be smaller than the first sustain voltage, the afterimage removing capability of the display device is improved. When the second sustain voltage is set to be larger than the first sustain voltage, the flicker removing capability of the display device Improvement.

Alternatively, the first sustain line 740 and the second sustain line 750 may be connected to each other and the same common voltage may be applied.

The second sustaining line 750 may have the same material and structure (multi-film structure) as the above-described gate line GL. In other words, the gate line GL and the second sustaining line 750 can be made simultaneously in the same process.

The first maintenance line 740 for repairing the data line DL includes a horizontal portion 741 disposed in parallel with the gate line GL and a vertical portion 742 disposed parallel to the data line DL ). The vertical portion 742 extends from a portion of the horizontal portion 741 overlapping the data line DL. In addition, the first holding line 740 has a first hole 743 at a position overlapping the data line DL. More specifically, the horizontal portion 741 has a first hole 743 at a position overlapping the data line DL and the vertical portion 742 has a second hole 744 at a position overlapping the data line DL. Respectively. As the vertical portion 742 has the second hole 744, the vertical portion 742 is made of double wiring.

The second sustaining line 750 also includes a vertical portion 752 disposed in parallel with the gate line GL and a vertical portion 752 disposed in parallel with the data line DL. The vertical portion 752 extends from a portion of the horizontal portion 751 overlapping the data line DL. Further, the second sustaining line 750 has a first hole 753 at a position overlapping the data line DL. More specifically, the horizontal portion 751 has a first hole 753 at a position overlapping the data line DL and the vertical portion 752 has a second hole 754 at a position overlapping the data line DL. Respectively.

Thus, the data lines DL can be easily repaired by configuring the first and second maintenance lines 740 and 750. The reason for this will be described concretely with reference to FIG.

5 is a diagram illustrating a method of repairing a data line from the pixel of Fig. 1 to a sustaining line.

Referring to FIG. 5, an open defect may occur in a portion F of the data line DL. The connecting portion CUT of the horizontal portion 741 and the vertical portion 742 of the first holding line 740 is opened and the portions C1 and C2 of the data line DL and the vertical portion 742 are opened . The data signal D can be normally sent to the pixel via the vertical portion 742 of the first sustaining line 740 and the voltage signal V is applied to the horizontal portion 741 of the first sustaining line 740 You can send it to the pixel normally. Therefore, the defect of the data line DL can be easily repaired as compared with the conventional method. In addition, unlike the prior art, the first holding line 740 can be used as a repair wiring and can still maintain its original function of sending the voltage signal V. [

The remaining configurations of the present invention will be further described in detail below.

The gate insulating film 310 is located on the gate line GL, the first holding line 740, and the second holding line 750. At this time, the gate insulating layer 310 may be formed on the entire surface of the first substrate 301 including the first holding line 740 and the second holding line 750.

The gate insulating film 310 may be made of silicon nitride (SiNx), silicon oxide (SiOx) or the like. The gate insulating layer 310 may have a multi-layer structure including at least two insulating layers having different physical properties.

The first to third semiconductor layers 311, 312, and 313 are located on the gate insulating film 310. At this time, the first semiconductor layer 311 overlaps with the first gate electrode GE1, the second semiconductor layer 312 overlaps with the second gate electrode GE2, the third semiconductor layer 313 overlaps with the third gate electrode GE2, And overlaps the gate electrode GE3.

The first to third semiconductor layers 311, 312, and 313 may be connected to each other. Referring to FIG. 1, the first semiconductor layer 311 and the second semiconductor layer 312 are connected to each other.

The first to third semiconductor layers 311, 312 and 313 may be made of amorphous silicon or polycrystalline silicon, respectively.

The ohmic contact layer 360 is located on the first to third semiconductor layers 311, 312, and 313. The ohmic contact layer 360 may be made of a material such as n + hydrogenated amorphous silicon, which is heavily doped with an n-type impurity such as phosphorus, or may be made of a silicide.

The first drain electrode DE1 and the first source electrode SE1 included in the first thin film transistor TFT1 and the second drain electrode DE2 and the second source electrode SE2 included in the second thin film transistor TFT2 And the third drain electrode DE3 and the third source electrode SE3 included in the third thin film transistor TFT3 are located on the ohmic contact layer 360. [

The first source electrode SE1 extends from the data line DL to the transistor region T and is located on the first gate electrode GE1 and the first semiconductor layer 311 as shown in Fig. . The first source electrode SE1 overlaps the first gate electrode GE1 and the first semiconductor layer 311. [ The first source electrode SE1 may be in the form of C, inverted C, U, or inverted U. In Fig. 1, for example, a first source electrode SE1 having a U-shape is shown.

The first source electrode SE1 is preferably made of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof, and may have a multi-film structure including a refractory metal film and a low-resistance conductive film . Examples of the multilayer structure include a double layer film of a chromium or molybdenum (or molybdenum alloy) lower film and an aluminum (or aluminum alloy) upper film, a lower film of molybdenum (or molybdenum alloy), an aluminum (or aluminum alloy) interlayer, molybdenum ) Triple layer of the upper layer. On the other hand, the first source electrode SE1 may be made of various other metals or conductors.

The first drain electrode DE1 is located on the first gate electrode GE1 and the first semiconductor layer 311. [ The first drain electrode DE1 overlaps the first gate electrode GE1, the first semiconductor layer 311, and the first extension electrode 181. [ At this time, the first drain electrode DE1 is connected to the first extended electrode 181 through the first contact hole CH1.

The first drain electrode DE1 may have the same material and structure (multi-film structure) as the first source electrode SE1 described above. In other words, the first source electrode SE1 and the first drain electrode DE1 can be formed simultaneously in the same process.

The first gate electrode GE1, the first drain electrode DE1, the first source electrode SE1, the first semiconductor layer 311 and the ohmic contact layer 360 constitute a first thin film transistor TFT1. At this time, a channel of the first thin film transistor TFT1 is located in a portion of the first semiconductor layer 311 between the first drain electrode DE1 and the first source electrode SE1. The portion of the first semiconductor layer 311 corresponding to the channel portion has a lower thickness than the other portion of the first semiconductor layer 311. [ The first thin film transistor TFT1 is located in the transistor region T, as shown in Fig.

And the second source electrode SE2 is electrically connected to the first source electrode SE1. For this, the second source electrode SE2 and the first source electrode SE1 may be integrally formed. That is, the first source electrode SE1 and the second source electrode SE2 are integrally formed and connected to each other. In addition, the first source electrode SE1 and the second source electrode SE2 formed integrally may have a W-shape.

 The second source electrode SE2 is located on the second gate electrode GE2 and the second semiconductor layer 312. [ The second source electrode SE2 overlaps the second gate electrode GE2 and the second semiconductor layer 312. [ The second source electrode SE2 may have the form of a C, an inverted C, a U, or an inverted U. In Fig. 1, for example, a second source electrode SE2 having a U-shape is shown.

The second source electrode SE2 may have the same material and structure (multi-film structure) as the first source electrode SE1 described above. In other words, the second source electrode SE2 and the first source electrode SE1 can be formed simultaneously in the same process.

The second drain electrode DE2 is located on the second gate electrode GE2 and the second semiconductor layer 312. [ The second drain electrode DE2 overlaps the second gate electrode GE2, the second semiconductor layer 312, and the second extension electrode 182. [ At this time, the second drain electrode DE2 is connected to the second extension electrode 182 through the second contact hole CH2.

The second drain electrode DE2 may have the same material and structure (multi-film structure) as the first source electrode SE1 described above. In other words, the second drain electrode DE2 and the first source electrode SE1 can be formed simultaneously in the same process.

On the other hand, the first drain electrode DE1 and the second drain electrode DE2 extend in the same direction. For example, as shown in FIG. 1, the first drain electrode DE1 and the second drain electrode DE2 extend in the direction in which the first source electrode SE1 and the second source electrode SE2 are disposed.

The second gate electrode GE2, the second drain electrode DE2, the second source electrode SE2, the second semiconductor layer 312 and the ohmic contact layer 360 constitute the second thin film transistor TFT2. At this time, the channel of the second thin film transistor TFT2 is located in the portion of the second semiconductor layer 312 between the second drain electrode DE2 and the second source electrode SE2. The portion of the second semiconductor layer 312 corresponding to the channel portion has a lower thickness than the other portion of the second semiconductor layer 312. The second thin film transistor TFT2 is located in the transistor region T, as shown in Fig.

And the third source electrode SE3 is electrically connected to the second drain electrode DE2. For this, the third source electrode SE3 and the second drain electrode DE2 may be integrally formed. The third source electrode SE3 is located on the third gate electrode GE3 and the third semiconductor layer 313. [ The third source electrode SE3 overlaps the third gate electrode GE3, the third semiconductor layer 313, and the second extending electrode 182. [

The third source electrode SE3 may have the same material and structure (multi-film structure) as the first source electrode SE1 described above. In other words, the third source electrode SE3 and the first source electrode SE1 can be formed simultaneously in the same process.

The third drain electrode DE3 is located on the third gate electrode GE3 and the third semiconductor layer 313. [ The third drain electrode DE3 overlaps the third gate electrode GE3 and the third semiconductor layer 313. The third drain electrode DE3 has the same material and structure as the first source electrode SE1 described above Multi-layer structure). In other words, the third drain electrode DE3 and the first source electrode SE1 can be formed simultaneously in the same process.

The third gate electrode GE3, the third drain electrode DE3, the third source electrode SE3, the third semiconductor layer 313 and the ohmic contact layer 360 constitute a third thin film transistor TFT3. At this time, the channel of the third thin film transistor TFT3 is located in the portion of the third semiconductor layer 313 between the third source electrode SE3 and the third drain electrode DE3. The portion of the third semiconductor layer 313 corresponding to the channel portion has a lower thickness than the other portion. The third thin film transistor TFT3 is located in the transistor region T, as shown in Fig.

The data line DL is located on the gate insulating film 310. Although not shown, the data line DL may have a larger area of its connecting portion (e.g., an end portion) than other portions thereof for connection with another layer or an external driving circuit.

The data line DL intersects the gate line GL, the first holding line 740, and the second holding line 750. Although not shown, where the data line DL and the gate line GL intersect, the data line DL may have a line width smaller than other portions thereof. Likewise, where the data line DL and the sustain line 740 or 750 intersect, the data line DL may have a smaller line width than other portions thereof. The parasitic capacitance between the data line DL and the gate line GL and the capacitance between the data line DL and the sustain line 740 or 750 can be reduced. The data line DL may have the same material and structure (multi-film structure) as the first source electrode SE1 described above. In other words, the data line DL and the first source electrode SE1 can be formed simultaneously in the same process.

Although not shown, a semiconductor layer and a resistive contact layer are formed under the data line DL, the first to third drain electrodes DE1, DE2, DE3, the first to third source electrodes SE1, SE2, SE3, May be located further.

The passivation layer 320 is located on the data line DL, the first to third drain electrodes DE1, DE2 and DE3 and the first to third source electrodes SE1, SE2 and SE3. At this time, the passivation layer 320 is formed on the first substrate 310 including the data line DL, the first to third drain electrodes DE1, DE2, and DE3, and the first to third source electrodes SE1, SE2, (Not shown). The passivation layer 320 may be formed of a plurality of components such as the data line DL, the first to third drain electrodes DE1, DE2, and DE3 positioned between the passivation layer 320 and the first substrate 301, And the first to third source electrodes SE1, SE2, and SE3 of the first substrate 301, as shown in FIG. In addition, the protective layer 320 also protects the components of the first substrate 301.

The protective film 320 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). Meanwhile, the protective film 320 may be made of an inorganic insulating material. In this case, the inorganic insulating material may have photosensitivity and a dielectric constant of about 4.0. The protective film 320 may also have a bilayer structure of the lower inorganic film and the upper organic film so as to prevent damage to the exposed semiconductor layers 311, 312, and 313 while utilizing good insulating properties of the organic film. The thickness of the protective layer 320 may be about 5000 ANGSTROM or more, and may be about 6000 ANGSTROM to about 8000 ANGSTROM.

The passivation layer 320 has first and second contact holes CH1 and CH2 penetrating a part of the passivation layer 320. The first and the second contact holes CH1 and CH2 form a first drain electrode DE1, And the second drain electrode DE2 are exposed.

The first sub-pixel electrode PE1 is positioned on the passivation layer 320. Specifically, the first sub-pixel electrode PE1 is located on the passivation layer 320 of the first sub-pixel region P1.

The first sub-pixel electrode PE1 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Here, ITO may be a polycrystalline or single crystal material, and IZO may also be a polycrystalline or single crystal material.

The first sub-pixel electrode PE1 may further include a first extended electrode 181.

The first extended electrode 181 is located on the protective film 320. Specifically, the first extended electrode 181 is located on the protective film 320 of the transistor region T. The first extended electrode 181 extends from the first sub-pixel electrode PE1 to the transistor region T. [ The first extended electrode 181 is formed integrally with the first sub-pixel electrode PE1. The first extended electrode 181 overlaps the first drain electrode DE1. The first extended electrode 181 is connected to the first drain electrode DE1 through the first contact hole CH1.

The first extended electrode 181 may be made of the same material as the first sub-pixel electrode PE1 described above.

The second sub-pixel electrode PE2 is located on the passivation layer 320. [ Specifically, the second sub-pixel electrode PE2 is located on the protective film 320 of the second sub-pixel region P2.

The second sub-pixel electrode PE2 may be made of the same material as the first sub-pixel electrode PE1 described above.

The second sub-pixel electrode PE2 may further include a second extending electrode 182. [

The second extended electrode 182 is located on the protective film 320. Specifically, the second extended electrode 182 is located on the protective film 320 of the transistor region T. [ The second extended electrode 182 extends from the second sub-pixel electrode PE2 to the transistor region T. [ The second extended electrode 182 is formed integrally with the second sub-pixel electrode PE2. And the second extended electrode 182 is connected to the second drain electrode DE2 through the second contact hole CH2.

The second extended electrode 182 may be made of the same material as the first sub-pixel electrode PE1 described above.

Although not shown, a lower alignment layer is formed on the first sub-pixel electrode PE1, the first extended electrode 181, the second sub-pixel electrode PE2, the second extended electrode 182, and the passivation layer 320 can do. The lower alignment layer may be a vertical alignment layer and may be an alignment layer containing a photoreactive material.

The black matrix 376 is located on the second substrate 302. Specifically, the black matrix 376 is located on the second substrate 302 except the portions corresponding to the pixel regions P1 and P2. On the other hand, the black matrix 376 may be located on the first substrate 301 instead of the second substrate 302.

The color filter 354 is located in the pixel regions P1 and P2. The color filter 354 includes a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter 354 may be disposed on the first substrate 301 instead of the second substrate 302.

The overcoat layer 722 is located on the black matrix 376 and the color filter 354. At this time, the overcoat layer 722 may be formed on the entire surface of the second substrate 302 including the black matrix 376 and the color filter 354.

Overcoat layer 722 may be formed on the second substrate 302 such as components located between the overcoat layer 722 and the second substrate 302 such as the black matrix 376 and the color filter 354 described above. And eliminates the difference in height between the components of the antenna 302. In addition, the overcoat layer 722 prevents the dye constituting the color filter 354 from leaking to the outside.

The common electrode 210 is located on the overcoat layer 722. At this time, the common electrode 210 may be positioned on the entire surface of the second substrate 302 including the overcoat layer 722. Alternatively, the common electrode 210 may be located on the overcoat layer 722 corresponding to the first sub-pixel region P1 and the second sub-pixel region P2. A common voltage is applied to the common electrode 210.

On the other hand, although not shown, the upper alignment layer may be located on the common electrode 210 and the overcoat layer 722. [ The upper alignment layer may be a vertical alignment layer and may be a photo alignment layer using a photopolymerizable material.

The liquid crystal layer 333 is located between the first substrate 301 and the second substrate 302. The liquid crystal layer 333 may include a photopolymerizable material, and the photopolymerizable material may be a reactive monomer or a reactive mesogen.

When the opposing surfaces between the first substrate 301 and the second substrate 302 are defined as upper surfaces and the surfaces opposite to the upper surfaces are respectively defined as the lower surface, (Not shown) may be positioned on the lower surface of the second substrate 302, and a lower polarizer (not shown) may be positioned on the lower surface of the second substrate 302.

The transmission axis of the upper polarizer plate and the transmission axis of the lower polarizer plate are orthogonal to each other. One of the transmission axes and the line unit 411 of the gate line GL are arranged in parallel with each other. On the other hand, the display device may include only one of the upper polarizer and the lower polarizer.

A second embodiment of the present invention will now be described with reference to Figs. 6 and 7. Fig. The description of the same configuration as that of the first embodiment is omitted for the convenience of explanation.

6 is a plan view schematically showing one pixel according to the second embodiment of the present invention. FIG. 7 is a diagram illustrating a method of repairing a data line from the pixel of FIG. 6 to a sustaining line.

6, the first holding line 760 for the repair process of the data line DL includes a horizontal portion 761 disposed in parallel with the gate line GL and a vertical portion 761 disposed in parallel with the data line DL And a vertical portion 762. The vertical portion 762 extends at a portion of the horizontal portion 761 overlapping the data line DL. The vertical portion 762 is disposed between the first sub-pixel electrode PE1 and the data line DL.

The second sustaining line 770 includes a horizontal portion 771 disposed in parallel with the gate line GL and a vertical portion 772 disposed in parallel to the data line DL. The vertical portion 772 extends from a portion of the horizontal portion 771 overlapping the data line DL. The vertical portion 772 is disposed between the second sub-pixel electrode PE2 and the data line DL.

The data line DL includes a protruding portion DL1 that overlaps with a portion of the first retaining line 760 and the second retaining line 770. At least one or more protrusions DL1 are arranged as shown in Fig. 6 and overlap with the vertical portions 762 and 772. [ For example, the protruding portion DL1 may be disposed at both ends of the vertical portions 762 and 772 as shown in Fig. Alternatively, the projecting portion DL1 may be further disposed at the center of the vertical portions 762 and 772.

The protruding portion DL1 is disposed in parallel with the gate line GL and overlaps with a portion of the first sub-pixel electrode PE1 and a portion of the second sub-pixel electrode PE2.

Thus, the data line DL, the first retaining line 760, and the second retaining line 770 are configured to easily repair the data line DL. The reason will be described concretely with reference to FIG.

Referring to FIG. 7, an open defect may occur in a portion F of the data line DL. The connecting portion CUT of the horizontal portion 761 and the vertical portion 762 of the first holding line 760 is opened and the protruding portion DL1 of the data line DL and a portion of the vertical portion 762 C1, and C2. Accordingly, the data signal D can be normally sent to the pixel via the protruding portion DL1 and the vertical portion 762 of the first holding line 760, and the voltage signal V can be applied to the horizontal direction of the first holding line 760 Can be normally sent to the pixel via the unit 761. Therefore, the defect of the data line DL can be easily repaired as compared with the conventional method.

A third embodiment of the present invention will be described below with reference to Fig. For the sake of convenience of description, description of the same components as those of the first and second embodiments will be omitted.

8 is a plan view schematically showing one pixel according to the third embodiment of the present invention.

8, the first holding line 780 and the second holding line 790 disclosed in the third embodiment of the present invention have bent portions 781 and 792 connecting the transverse portions 781 and 791 and the vertical portions 782 and 792, respectively, 783, 793). The protruding portion DL1 overlaps with the bent portions 783 and 793. By arranging the bent portions 783 and 793, the process efficiency of the repair process can be increased. 7, when the bent portions 783 and 793 are disposed in the step of opening the transverse portion 761 and the vertical portion 762, the connecting portion of the transverse portion 761 and the vertical portion 762 is connected to the data line (DL) and the second embodiment. Therefore, the damage of the data line DL in the repairing process can be prevented. Other configurations and effects are the same as those of the second embodiment, and the repair method is the same as that of the second embodiment.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

GL: gate line DL: data line
PE1: first sub-pixel electrode PE2: second sub-pixel electrode
CH1: first contact hole CH2: second contact hole
CH3: third contact hole 181: first extended electrode
182: second extension electrode 210: common electrode
740, 760, 780: First holding line 750, 770, 790: Second holding line
TFT1: first thin film transistor
TFT2: second thin film transistor TFT3: third thin film transistor
DE1: first drain electrode DE2: second drain electrode
DE3: third drain electrode SE1: first source electrode
SE2: second source electrode SE3: third source electrode
GE1: first gate electrode GE2: second gate electrode
GE3: third gate electrode 411:
311: first semiconductor layer 312: second semiconductor layer
313: a third semiconductor layer P1: a first sub-pixel region
P2: second sub-pixel region T: transistor region

Claims (16)

Board;
A data line and a gate line disposed on the substrate;
A thin film transistor connected to the gate line and the data line;
A pixel electrode connected to the thin film transistor; And
And a sustain line partially overlapping the pixel electrode,
And the sustain line has a first hole at a position overlapping with the data line. The method according to claim 1,
Wherein the sustain line includes a horizontal portion disposed in parallel with the gate line and a vertical portion disposed in parallel with the data line. 3. The method of claim 2,
And the horizontal portion has the first hole at a position overlapping with the data line. 3. The method of claim 2,
And the vertical portion has a second hole at a position overlapping with the data line. 3. The method of claim 2,
Wherein the vertical portion extends from a portion of the horizontal portion overlapping with the data line. Board;
A data line and a gate line disposed on the substrate;
A thin film transistor connected to the gate line and the data line;
A pixel electrode connected to the thin film transistor; And
And a sustain line partially overlapping the pixel electrode,
Wherein the data line includes a protrusion overlapping a part of the sustain line. The method according to claim 6,
And the protrusion is disposed in parallel with the gate line. The method according to claim 6,
And the protrusion overlaps with a part of the pixel electrode. The method according to claim 6,
Wherein the sustain line includes a horizontal portion disposed in parallel with the gate line and a vertical portion disposed in parallel with the data line. 10. The method of claim 9,
And the vertical portion is disposed between the pixel electrode and the data line. 10. The method of claim 9,
And the projecting portion overlaps with a part of the vertical portion. 12. The method of claim 11,
And the protrusion overlaps with a part of the pixel electrode. 10. The method of claim 9,
And the vertical portion extends from the lateral portion. 10. The method of claim 9,
Wherein the holding line further includes a bent portion connecting the transverse portion and the vertical portion. 15. The method of claim 14,
And the projecting portion overlaps with the bent portion. 16. The method of claim 15,
And the protrusion overlaps with a part of the pixel electrode.

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