KR20170103599A - Display driving device and display device having the same - Google Patents

Abstract

The present invention relates to a display driving device which comprises: a timing controller; a power management integrated circuit; and a column driver. The timing controller generates image data by dividing input data with a line unit, and generates a power saving signal based on a reference size and a size of a plurality of pixel data included in the image data. The power management integrated circuit generates driving voltage having a voltage level varied based on the power saving signal. The column driver receives the image data from the timing controller, and generates a plurality of output voltages corresponding to the plurality of pixel data included in the image data by using the driving voltage. The display driving device can reduce power consumption without increasing a size.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display driving apparatus,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display driving device capable of reducing power consumption and a display device including the same.

As the resolution of the display device increases, the power consumption of the display driving device for driving the display panel is increasing.

Therefore, researches for reducing the power consumption of the display driving apparatus have been actively conducted. Particularly, in the case of a mobile device operating using a battery, as the power consumption is reduced, the continuous use time of the mobile device increases, so that power consumption reduction becomes more important.

However, when an apparatus for reducing power consumption is separately provided in the display driving apparatus, there is a problem that the size of the display apparatus increases.

An object of the present invention is to provide a display driving apparatus capable of reducing power consumption without increasing the size.

Another object of the present invention is to provide a display device including the display driver.

In order to accomplish one aspect of the present invention, a display driving apparatus according to embodiments of the present invention includes a timing controller, a power management integrated circuit, and a column driver. The timing controller generates image data by dividing the input data in units of lines, and generates a power saving signal based on the size and reference size of the plurality of pixel data included in the image data. The power management integrated circuit generates a drive voltage having a varying voltage level based on the power saving signal. The column driver receives the image data from the timing controller and generates a plurality of output voltages corresponding to the plurality of pixel data included in the image data using the driving voltage.

In order to accomplish one aspect of the present invention, a display driving apparatus according to embodiments of the present invention includes a timing controller, a power management integrated circuit, and a column driver. Wherein the timing controller generates image data by dividing input data in units of lines and generates a positive power reduction based on a magnitude and a positive reference magnitude of pixel data of positive polarity among a plurality of pixel data included in the image data, And generates a negative power saving signal based on the size of the negative pixel data and the negative reference size among the plurality of pixel data included in the image data. The power management integrated circuit generates a positive driving voltage having a voltage level that varies based on the positive power saving signal and generates a negative driving voltage having a varying voltage level based on the negative power saving signal do. Wherein the column driver receives the image data from the timing controller and generates a plurality of positive output voltages corresponding to the positive polarity pixel data included in the image data using the positive driving voltage, And generates a plurality of negative output voltages corresponding to pixel data of the negative polarity included in the image data using the negative driving voltage.

The display driving apparatus according to the present invention can effectively reduce the power consumption without including a separate device for reducing power consumption.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a block diagram showing an example of a timing controller included in the display device of FIG.
3 is a block diagram showing another example of a timing controller included in the display device of FIG.
4 is a block diagram showing another example of the timing controller included in the display device of FIG.
5 is a block diagram showing an example of a column driver included in the display device of FIG.
6 and 7 are views for explaining the operation of the display driving apparatus included in the display apparatus of FIG.
8 is a block diagram showing another example of a column driver included in the display device of FIG.
FIG. 9 is a circuit diagram showing an example of a gamma voltage generating circuit included in the column driver of FIG. 8; FIG.
10 is a block diagram illustrating a display device according to an embodiment of the present invention.
11 is a block diagram illustrating a display device according to an embodiment of the present invention.
12A and 12B are diagrams for explaining the inversion driving method of the display device of FIG.
13 is a block diagram showing an example of a timing controller included in the display device of FIG.
14 is a block diagram showing an example of a column driver included in the display device of FIG.
15 is a block diagram showing another example of a column driver included in the display device of FIG.
16 is a block diagram showing a display device according to an embodiment of the present invention.

1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to Fig. 1, a display device 10a includes a display panel 100 and a display driving device 20. Fig.

The display panel 100 may include red pixels, green pixels, and blue pixels connected to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. Here, n and m represent positive integers.

The display driver 20 may include a timing controller (T_CON) 200, a power management integrated circuit (PMIC) 300, a column driver 400, and a gate driver 500.

In one embodiment, the timing controller 200 and the column driver 400 may be included in different integrated circuits.

The timing controller 200 can receive input data IDATA, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a main clock signal MCLK from an external host.

The timing controller 200 can generate the gate control signal GCS and the column control signal CCS based on the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC and the main clock signal MCLK.

The timing controller 200 divides the input data IDATA on a frame basis based on the vertical synchronization signal VSYNC and divides the input data IDATA on a line basis on the basis of the horizontal synchronization signal HSYNC, Data (RGB) can be generated.

Accordingly, the image data (RGB) may include a plurality of pixel data corresponding to a plurality of pixels arranged on the same line. For example, the image data (RGB) may include red pixel data, green pixel data, and blue pixel data respectively corresponding to red pixels, green pixels, and blue pixels arranged on the same line.

Meanwhile, the timing controller 200 may generate a power saving signal (PSS) based on the size and reference size of the plurality of pixel data included in the image data (RGB).

The timing controller 200 may provide a power saving signal (PSS) to the power management integrated circuit 300.

The power management integrated circuit 300 may generate and supply a driving voltage AVDD having a variable voltage level to the column driver 400 based on the power saving signal PSS.

In one embodiment, the timing controller 200 deactivates the power saving signal PSS when the maximum size of the plurality of pixel data included in the image data RGB is greater than or equal to the reference size, The power saving signal PSS can be activated when the maximum size of the plurality of pixel data included in RGB is smaller than the reference size.

In this case, the power management integrated circuit 300 generates the driving voltage AVDD having the first voltage level when the power saving signal PSS is inactivated, and when the power saving signal PSS is activated, (AVDD) having a second voltage level lower than the first voltage level.

In another embodiment, the timing controller 200 compares the maximum size of the plurality of pixel data included in the image data (RGB) with the first to tth reference sizes, Can generate a power saving signal (PSS) having a value of one of the values.

In this case, the power management integrated circuit 300 may generate a driving voltage AVDD having a voltage level proportional to the value of the power saving signal PSS.

The timing controller 200 may provide the gate control signal GCS to the gate driver 500 and provide the column driver 400 with the column control signal CCS and the image data RGB.

The gate driver 500 may be connected to the display panel 100 through a plurality of gate lines GL1 to GLn. The gate driver 500 can sequentially select the plurality of gate lines GL1 to GLn based on the gate control signal GCS.

The column driver 400 may be connected to the display panel 100 through a plurality of data lines DL1 to DLm. The column driver 400 processes the image data RGB using the driving voltage AVDD provided from the power management integrated circuit 300 based on the column control signal CCS and outputs the image data RGB A plurality of output voltages corresponding to the plurality of pixel data may be generated and the plurality of output voltages may be provided to the display panel 100 through the plurality of data lines DL1 to DLm.

For example, the column driver 400 generates a red output voltage corresponding to the red pixel data, a green output voltage corresponding to the green pixel data, and a blue output voltage corresponding to the blue pixel data, The red output voltage, the green output voltage, and the blue output voltage may be provided to the red pixel, the green pixel, and the blue pixel included in the display panel 100, respectively, through the lines DL1 to DLm have.

In one embodiment, the display panel 100 may be driven by the display driver 20 in a non-inverting manner. For example, the display panel 100 may be an organic light emitting diode (OLED) display device. In this case, the plurality of output voltages provided to the display panel 100 by the display driving apparatus 20 may always have a positive polarity.

As described above, when the maximum size of the plurality of pixel data included in the image data RGB is relatively large, the column driver 400 generates the output voltage having a relatively high voltage level, The column driver 400 may generate the output voltage having a relatively low voltage level when the maximum size of the plurality of pixel data included in the RGB data is relatively small.

Therefore, the power management integrated circuit 300 included in the display driving circuit 20 according to the present invention can reduce the power consumption of the image data RGB when the maximum size of the plurality of pixel data included in the image data RGB is relatively large. The driving voltage AVDD having a relatively high voltage level during the horizontal period provided to the display panel 100 is provided to the column driver 400 while the corresponding plurality of output voltages are supplied to the column driver 400, When the maximum size of the plurality of pixel data is relatively small, the plurality of output voltages corresponding to the image data RGB are supplied to the display panel 100 at a voltage level of the driving voltage AVDD during the horizontal period The driving voltage AVDD having a relatively low voltage level can be generated and provided to the column driver 400.

As the voltage level of the driving voltage AVDD is lower, the power consumption of the display driving circuit 20 is reduced. Therefore, the display driving circuit 20 according to the present invention can effectively reduce power consumption Can be reduced.

2 is a block diagram showing an example of a timing controller included in the display device of FIG.

Referring to FIG. 2, the timing controller 200a may include a control circuit 210, a line buffer 220, and a comparator 230a.

The control circuit 210 can receive input data IDATA, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a main clock signal MCLK from an external host. The control circuit 210 can generate the gate control signal GCS and the column control signal CCS based on the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC and the main clock signal MCLK. The control circuit 210 divides input data IDATA on a frame basis based on the vertical synchronization signal VSYNC and divides the input data IDATA on a line basis on the basis of the horizontal synchronization signal HSYNC, Data (RGB) can be generated.

The control circuit 210 may store image data (RGB) including the plurality of pixel data corresponding to one line in the line buffer 220.

The image data (RGB) stored in the line buffer 220 may be provided to the column driver 400.

Meanwhile, the control circuit 210 may provide the maximum size MAX_M of the plurality of pixel data stored in the line buffer 220 to the comparator 230a.

The comparator 230a may generate the power saving signal PSS by comparing the maximum size MAX_M with the reference size REF_M.

In one embodiment, the comparator 230a generates a deactivated power saving signal PSS when the maximum magnitude MAX_M is greater than or equal to the reference magnitude REF_M and the maximum magnitude MAX_M is greater than the reference magnitude REF_M ), It is possible to generate the activated power saving signal PSS.

In this case, the power management integrated circuit 300 generates a driving voltage AVDD having the first voltage level when the power saving signal PSS is inactivated, and when the power saving signal PSS is activated, (AVDD) having the second voltage level lower than the first voltage level.

In one embodiment, the reference magnitude REF_M may be stored within the timing controller 200a. In another embodiment, a reference size REF_M may be provided from the host.

3 is a block diagram showing another example of a timing controller included in the display device of FIG.

Referring to FIG. 3, the timing controller 200b may include a control circuit 210, a line buffer 220, and a comparator 230b.

The control circuit 210 and the line buffer 220 included in the timing controller 200b of FIG. 3 are the same as the control circuit 210 and the line buffer 220 included in the timing controller 200a of FIG. Therefore, the description of the control circuit 210 and the line buffer 220 included in the timing controller 200b of FIG. 3 will be omitted.

The comparator 230b may compare the maximum magnitude MAX_M with the first to tth reference magnitudes REF_M1 to REF_Mt, respectively. The comparator 230b compares the power saving signal having one of the first to the (t + 1) values based on the comparison result of the maximum magnitude MAX_M and the first to tth reference magnitudes REF_M1 to REF_Mt, (PSS [1: (t + 1)]).

For example, the comparator 230b may generate a power saving signal PSS [1: (t + 1)] having a larger value as the maximum size MAX_M is larger.

In this case, the power management integrated circuit 300 may generate a driving voltage AVDD having a voltage level proportional to the value of the power saving signal PSS [1: (t + 1)].

In one embodiment, the first through tth reference sizes REF_M1 through REF_Mt may be stored within the timing controller 200a. In another embodiment, first through tth reference sizes REF_M1 through REF_Mt may be provided from the host.

4 is a block diagram showing another example of the timing controller included in the display device of FIG.

4, the timing controller 200c includes a control circuit 210, first through third line buffers 220-1, 220-2 and 220-3, a comparator 230c, 240).

The control circuit 210 can receive input data IDATA, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a main clock signal MCLK from an external host. The control circuit 210 can generate the gate control signal GCS and the column control signal CCS based on the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC and the main clock signal MCLK. The control circuit 210 divides input data IDATA on a frame basis based on the vertical synchronization signal VSYNC and divides the input data IDATA on a line basis on the basis of the horizontal synchronization signal HSYNC, Data (RGB) can be generated.

The control circuit 210 sequentially supplies the image data RGB including the plurality of pixel data corresponding to one line to the first through third line buffers 220-1, 220-2, and 220-3 Can be stored. Accordingly, the plurality of pixel data corresponding to the first through third consecutive lines may be stored in the first through third line buffers 220-1, 220-2 and 220-3, respectively.

The image data RGB stored in the first through third line buffers 220-1, 220-2 and 220-3 may be sequentially provided to the column driver 400. [

4, the timing controller 200c is shown as including three line buffers 220-1, 220-2, and 220-3, but the present invention is not limited thereto. The timing controller 200c may be any Number of line buffers.

The control circuit 210 receives the first through third maximum sizes MAX_M1 and MAX_M2 of the plurality of pixel data stored in the first through third line buffers 220-1, 220-2 and 220-3, , MAX_M3) to the comparator 230c.

The comparator 230c can generate the first to third power saving signals PSS1, PSS2, and PSS3 by comparing the first to third maximum magnitudes MAX_M1, MAX_M2, and MAX_M3 with the reference magnitude REF_M have.

In one embodiment, the comparator 230c generates the deactivated first power saving signal PSS1 when the first maximum magnitude MAX_M1 is greater than or equal to the reference magnitude REF_M and the first maximum magnitude MAX_M1 ) Is smaller than the reference size REF_M, it is possible to generate the activated first power saving signal PSS1.

Similarly, the comparator 230c generates the deactivated second power saving signal PSS2 when the second maximum magnitude MAX_M2 is greater than or equal to the reference magnitude REF_M, and the second maximum magnitude MAX_M2 Is smaller than the reference size REF_M, it is possible to generate the activated second power saving signal PSS2.

Similarly, the comparator 230c generates a deactivated third power saving signal PSS3 when the third maximum magnitude MAX_M3 is greater than or equal to the reference magnitude REF_M, and the third maximum magnitude MAX_M3 is equal to Is smaller than the reference size REF_M, it is possible to generate the activated third power saving signal PSS3.

The AND gate 240 can perform a logical AND operation on the first to the s power saving signals PSS1, PSS2, and PSS3 to generate the power saving signal PSS.

For example, the AND gate 240 activates the power saving signal PSS when all of the first to s < th > power saving signals PSS1, PSS2 and PSS3 are activated, If at least one of the signals PSS1, PSS2, PSS3 is deactivated, the power saving signal PSS can be deactivated.

In this case, the power management integrated circuit 300 generates a driving voltage AVDD having the first voltage level when the power saving signal PSS is inactivated, and when the power saving signal PSS is activated, It is possible to generate a driving voltage AVDD having a second voltage level lower than the first voltage level.

The power management integrated circuit 300 determines the voltage level of the driving voltage AVDD using the charge pump so that the power consumption of the display driving apparatus 20 increases when the voltage level of the driving voltage AVDD is frequently changed .

As described above with reference to FIG. 4, the timing controller 200c included in the display driving apparatus 20 according to the present invention is configured such that the maximum size of all pixel data included in a plurality of consecutive lines is larger than a reference size (PSS) can be generated only when it is smaller than the power saving signal REF_M.

The number of line buffers included in the timing controller 200c can be determined based on the power consumption increase due to the voltage level change of the drive voltage AVDD and the power consumption decrease due to the decrease of the voltage level of the drive voltage AVDD have.

5 is a block diagram showing an example of a column driver included in the display device of FIG.

Referring to FIG. 5, the column driver 400a includes a plurality of data latches 410-1, 410-2, ..., and 410-m, a plurality of level shifters 420-1, 420-2,. ..., 420-m, a plurality of decoders 430-1, 430-2, ..., 430-m, a plurality of output buffers 440-1, 440-2, m, and a gamma voltage generating circuit 450a.

The plurality of data latches 410-1, 410-2, ..., and 410-m receive image data RGB including the plurality of pixel data corresponding to one line from the timing controller 200 And may provide the plurality of level shifters 420-1, 420-2, ..., and 420-m with the plurality of pixel data every horizontal period.

The plurality of level shifters 420-1, 420-2, ..., and 420-m may output a voltage level of the plurality of pixel data.

The gamma voltage generating circuit 450a may generate a plurality of gamma voltages VG [0: 255].

Although the gamma voltage generating circuit 450a is illustratively illustrated as generating a plurality of gamma voltages VG [0: 255] having 256 gradation levels in FIG. 5, the present invention is not limited thereto, The gamma voltage generating circuit 450a may generate an arbitrary number of gamma voltages.

 The plurality of decoders 430-1, 430-2, ..., and 430-m receive a plurality of gamma voltages VG [0: 255] from the gamma voltage generating circuit 450a, It is possible to receive a plurality of pixel data PD from the shifters 420-1, 420-2, ..., and 420-m.

 Each of the plurality of decoders 430-1, 430-2, ..., and 430-m selects one of the plurality of gamma voltages VG [0: 255] based on the corresponding pixel data PD. And output it as an input voltage VIN.

Each of the plurality of output buffers 440-1, 440-2, ..., 440-m may be coupled between a drive voltage AVDD and a ground voltage AVSS provided from the power management integrated circuit 300 .

Further, each of the plurality of output buffers 440-1, 440-2, ..., 440-m generates an output voltage VOUT corresponding to the input voltage VIN using the driving voltage AVDD . Therefore, the maximum voltage level of the output voltage VOUT output from each of the plurality of output buffers 440-1, 440-2, ..., 440-m corresponds to the voltage level of the received driving voltage AVDD .

The plurality of output buffers 440-1, 440-2, ..., and 440-m can provide the display voltage VOUT to the display panel 100 through the plurality of data lines DL1 to DLm have.

6 and 7 are views for explaining the operation of the display driving apparatus included in the display apparatus of FIG.

Fig. 6 shows the operation of the display driving apparatus 20 when the display driving apparatus 20 includes the timing controller 200a shown in Fig.

The maximum size MAX_M of the plurality of pixel data corresponding to one line may be changed as shown in FIG.

6, the power management integrated circuit 300 includes a driving voltage (VL2) having a second voltage level VL2 during a horizontal interval 1H that is smaller than the reference size REF_M AVDD to the column driver 400 and drives the column driver 400 having the first voltage level VL1 higher than the second voltage level VL2 during the horizontal interval 1H which is greater than the reference size REF_M. The column driver 400 can supply the voltage AVDD.

7 shows the operation of the display driving apparatus 20 when the display driving apparatus 20 includes the timing controller 200b shown in Fig.

The maximum size MAX_M of the plurality of pixel data corresponding to one line may be changed as shown in FIG.

7, the power management integrated circuit 300 may be driven by a driving circuit having a third voltage level VL3 for a horizontal interval 1H which is smaller than the first reference size REF_M1, And provides the voltage AVDD to the column driver 400 and supplies the third voltage level VL3 during the horizontal interval 1H which is greater than the first reference magnitude REF_M1 and smaller than the second reference magnitude REF_M2, To the column driver 400 and supplies the driving voltage AVDD having the second voltage level VL2 higher than the second reference level REF_M2 to the column driver 400 during the second horizontal period 1H, It is possible to provide the column driver 400 with the driving voltage AVDD having the first voltage level VL1 higher than the voltage level VL2.

5, each of the plurality of output buffers 440-1, 440-2, ..., and 440-m is connected between a driving voltage AVDD and a ground voltage AVSS, The power consumption of each of the output buffers 440-1, 440-2, ..., and 440-m is proportional to the difference between the driving voltage AVDD and the ground voltage AVSS can do.

As described above with reference to FIGS. 1 to 7, the display driving apparatus 20 according to the present invention is configured such that when the maximum size of the pixel data included in the image data RGB is relatively large, the voltage level of the driving voltage AVDD And the voltage level of the driving voltage AVDD can be reduced when the maximum size of the pixel data included in the image data RGB is relatively small.

Therefore, the display driving apparatus 20 according to the present invention is configured such that when the voltage level of the output voltage VOUT output from the plurality of output buffers 440-1, 440-2, ..., and 440-m is relatively low And the voltage level of the output voltage VOUT output from the plurality of output buffers 440-1, 440-2, ..., and 440-m is relatively high , By increasing the voltage level of the driving voltage AVDD, the power consumption of the display driving apparatus 20 can be effectively reduced while the performance of the display driving apparatus 20 is maintained.

8 is a block diagram showing another example of a column driver included in the display device of FIG.

Referring to FIG. 8, the column driver 400b includes a plurality of data latches 410-1, 410-2, ..., and 410-m, a plurality of level shifters 420-1, 420-2,. ..., 420-m, a plurality of decoders 430-1, 430-2, ..., 430-m, a plurality of output buffers 440-1, 440-2, m, and a gamma voltage generating circuit 450b.

The column driver 400b of FIG. 8 is the same as the column driver 400a of FIG. 5 except for the operation of the gamma voltage generating circuit 450b. Therefore, redundant description will be omitted.

The gamma voltage generating circuit 450b may generate a plurality of gamma voltages VG [0: 255].

In one embodiment, the gamma voltage generation circuit 450b may receive the power saving signal PSS from the timing controller 200. [

In this case, the gamma voltage generation circuit 450b selectively stops generation of at least one gamma voltage having a high voltage level among the plurality of gamma voltages VG [0: 255] based on the power saving signal PSS can do.

For example, when the display driving apparatus 20 includes the timing controller 200a shown in FIG. 2, the gamma voltage generating circuit 450b generates a plurality of gamma voltages (Vs) while the power saving signal PSS is inactivated (VG [0: 255]) having a relatively high voltage level among the plurality of gamma voltages VG [0: 255] while the power saving signal PSS is activated, +1: 255]) and generate only gamma voltages VG [0: k] having a relatively low voltage level. Here, k represents a positive integer less than 255.

FIG. 9 is a circuit diagram showing an example of a gamma voltage generating circuit included in the column driver of FIG. 8; FIG.

Referring to FIG. 9, the gamma voltage generating circuit 450b may include a plurality of amplifiers 451-1 through 451-7 and a resistor circuit 452. In FIG.

As shown in FIG. 9, each of the plurality of amplifiers 451-1 through 451-7 can amplify and output a plurality of reference gamma voltages VGMA1 through VGMA7, respectively.

In one embodiment, the plurality of reference gamma voltages VGMA1 to VGMA7 may have a voltage level that is sequentially lowered. For example, the voltage level of the first reference gamma voltage VGMA1 may be the highest, and the voltage level of the seventh reference gamma voltage VGMA7 may be the lowest.

Although the gamma voltage generating circuit 450b is shown as including seven amplifiers 451-1 through 451-7 in Fig. 9, the present invention is not limited thereto, and according to the embodiment, the gamma voltage generating circuit 450b 450b may include any number of amplifiers.

The resistor circuit 452 can connect the output terminals of the plurality of amplifiers 451-1 through 451-7 through a resistor. Therefore, as shown in FIG. 9, the resistance circuit 452 can output a plurality of gamma voltages VG [0: 255] through different nodes.

On the other hand, the gamma voltage generating circuit 450b can generate a plurality of enable signals EN1 to EN7 internally based on the power saving signal PSS received from the timing controller 200. [ Each of the plurality of enable signals EN1 to EN7 may be provided to the plurality of amplifiers 451-1 to 451-7.

Each of the plurality of amplifiers 451-1 to 451-7 may be turned on to amplify and output a corresponding reference gamma voltage when each of the plurality of enable signals EN1 to EN7 is activated.

On the other hand, each of the plurality of amplifiers 451-1 through 451-7 may be turned off when each of the plurality of enable signals EN1 through EN7 is inactivated.

In one embodiment, the gamma voltage generation circuit 450b includes a plurality of amplifiers 451-1 to 451-EN7 by activating all of the plurality of enable signals EN1 to EN7 when the power saving signal PSS is inactivated, 7) can be turned on.

On the other hand, the gamma voltage generating circuit 450b generates a reference gamma voltage of a relatively high voltage level among the plurality of enable signals EN1 to EN7 when the power saving signal PSS is activated, One of the enable signals EN1 to ENq may be inactivated and only the remaining enable signals EN (q + 1) to EN7 may be activated. For example, the gamma voltage generating circuit 450b deactivates the first enable signal EN1 and the second enable signal EN2 when the power saving signal PSS is activated, and the third to seventh enable The signals EN3 to EN7 can be activated.

In this case, the gamma voltage generating circuit 450b stops the generation of the gamma voltages VG [k + 1: 255] having the relatively high voltage levels and outputs the gamma voltages VG [ : k]).

When the power saving signal PSS is activated, at least one of the plurality of amplifiers 451-1 to 451-7 is turned off, so that the power consumption of the gamma voltage generating circuit 450b can be reduced.

The power saving signal PSS is inactivated when the maximum size MAX_M of the plurality of pixel data included in the image data RGB is smaller than the reference size REF_M, During the deactivation, each of the plurality of decoders 430-1, 430-2, ..., 430-m has a gamma voltage having a high voltage level among a plurality of gamma voltages VG [0: 255] (VIN).

Therefore, even if the gamma voltage generating circuit 450b stops generating at least one gamma voltage having a high voltage level among the plurality of gamma voltages VG [0: 255] while the power saving signal PSS is inactivated, The power consumption can be effectively reduced without affecting the operation of the device 20. [

10 is a block diagram illustrating a display device according to an embodiment of the present invention.

The timing controller 200 and the column driver 400 included in the display device 10b of FIG. 10 are included in the same integrated circuit 30 while the timing controller 200 included in the display device 10a of FIG. The display device 10b of FIG. 10 and the display device 10a of FIG. 1 are the same except that the column driver 400 and the column driver 400 are included in different integrated circuits.

1 and 10, according to the embodiment, the timing controller 200 and the column driver 400 may be implemented in the same integrated circuit 30, or may be implemented in different integrated circuits.

11 is a block diagram illustrating a display device according to an embodiment of the present invention.

Referring to Fig. 11, the display device 40a includes a display panel 100 and a display driving device 50. Fig.

The display panel 100 may include red pixels, green pixels, and blue pixels connected to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. Here, n and m represent positive integers.

The display driver 50 may include a timing controller T_CON 600, a power management integrated circuit (PMIC) 700, a column driver 800, and a gate driver 900.

In one embodiment, the timing controller 600 and the column driver 800 may be included in different integrated circuits.

The timing controller 600 can receive input data IDATA, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a main clock signal MCLK from an external host.

The timing controller 600 may generate the gate control signal GCS and the column control signal CCS based on the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC and the main clock signal MCLK.

The timing controller 600 divides the input data IDATA in units of frames based on the vertical synchronization signal VSYNC and divides the input data IDATA in units of lines on the basis of the horizontal synchronization signal HSYNC, Data (RGB) can be generated.

Accordingly, the image data (RGB) may include a plurality of pixel data corresponding to a plurality of pixels arranged on the same line.

Meanwhile, the timing controller 600 generates a positive power saving signal PSSP based on the magnitude and the positive reference magnitude of pixel data of positive polarity among the plurality of pixel data included in the image data RGB , A negative power saving signal (PSSN) can be generated based on the magnitude of the negative polarity pixel data and the negative reference magnitude among the plurality of pixel data included in the image data (RGB).

Timing controller 600 may provide a positive power saving signal (PSSP) and a negative power saving signal (PSSN) to power management integrated circuit (700).

The power management integrated circuit 700 generates a positive drive voltage AVDDP having a voltage level that varies based on the positive power save signal PSSP and generates a variable voltage VSS based on the negative power save signal PSSN, (AVDDN) having a high level can be generated. The power management integrated circuit 700 may provide the column driver 800 with a positive driving voltage AVDDP and a negative driving voltage AVDDN.

In one embodiment, the timing controller 600 generates a positive power saving signal PSSP when the maximum magnitude of the pixel data of positive polarity included in the image data RGB is equal to or greater than the positive reference magnitude, And may activate the positive power saving signal PSSP when the maximum size of the pixel data of the positive polarity included in the image data RGB is smaller than the reference size. Similarly, the timing controller 600 deactivates the negative power saving signal PSSN when the maximum size of the pixel data of the negative polarity included in the image data RGB is equal to or greater than the negative reference size, And the negative power saving signal PSSN can be activated when the maximum size of the pixel data of the negative polarity included in the image data RGB is smaller than the reference size.

In this case, the power management integrated circuit 700 generates a positive drive voltage AVDDP having a first voltage level when the positive power save signal PSSP is inactive, and the positive power save signal PSSP When activated, a positive drive voltage (AVDDP) having a second voltage level lower than the first voltage level may be generated. Similarly, the power management integrated circuit 700 generates a negative drive voltage AVDDN having a third voltage level when the negative power save signal PSSN is inactive, A negative driving voltage AVDDN having a fourth voltage level lower than the third voltage level may be generated.

In another embodiment, the timing controller 600 compares the maximum magnitudes of the pixel data of positive polarity included in the image data (RGB) with the reference magnitudes of the first to the t-th magnitudes, respectively, t + 1) < / RTI > values. < RTI ID = 0.0 > Similarly, the timing controller 600 compares the maximum magnitudes of the pixel data of the negative polarity included in the image data (RGB) with the first to tth negative reference magnitudes, respectively, and outputs the first to (t + 1) < / RTI > values.

In this case, the power management integrated circuit 700 generates a positive driving voltage AVDDP having a voltage level proportional to the value of the positive power saving signal PSSP, It is possible to generate a negative driving voltage AVDDN having a proportional voltage level.

The timing controller 600 may provide the gate control signal GCS to the gate driver 900 and provide the column driver 800 with the column control signal CCS and the image data RGB.

The gate driver 900 may be connected to the display panel 100 through a plurality of gate lines GL1 to GLn. The gate driver 900 can sequentially select the plurality of gate lines GL1 to GLn based on the gate control signal GCS.

The column driver 800 may be connected to the display panel 100 through a plurality of data lines DL1 to DLm. The column driver 800 uses the positive driving voltage AVDDP provided from the power management integrated circuit 700 based on the column control signal CCS to generate the positive polarity pixel data And processes the negative polarity pixel data included in the image data RGB by using the negative driving voltage AVDDN provided from the power management integrated circuit 700 Thereby generating a plurality of negative output voltages. The column driver 800 may provide the plurality of positive output voltages and the plurality of negative output voltages to the display panel 100 through the plurality of data lines DL1 to DLm.

In one embodiment, the display panel 100 may be driven in an inverting manner by the display driver 20. [ For example, the display panel 100 may be a liquid crystal display (LCD) device. In this case, the display driving device 50 may alternately provide the positive output voltage and the negative output voltage to each of the plurality of pixels included in the display panel 100. [

12A and 12B are views for explaining the inversion driving method of the display device shown in FIG.

12A and 12B illustrate operation of the display panel 100 when the display panel 100 is driven by the column inversion method.

As shown in FIG. 12A, the display driving apparatus 50 provides the positive output voltage to each of a plurality of pixels arranged in even-numbered columns in the P-th frame, and a plurality of Each of the pixels may be provided with the negative output voltage.

On the other hand, the display driver 50 provides the negative output voltage to each of the plurality of pixels arranged in the even-numbered columns in the (P + 1) -th frame, Each of which may provide the positive output voltage.

12A and 12B, the display panel 100 is driven by a column inversion method. However, the present invention is not limited to this, and the display panel 100 may be driven by various inversion methods.

As described above, when the maximum size of the pixel data of the positive polarity included in the image data RGB is relatively large, the column driver 800 generates the positive output voltage having a relatively high voltage level , The column driver 800 can generate the positive output voltage having a relatively low voltage level when the maximum size of the positive polarity pixel data included in the image data RGB is relatively small.

Similarly, when the maximum size of the negative polarity pixel data included in the image data RGB is relatively large, the column driver 800 generates the negative output voltage having a relatively high voltage level, If the maximum size of the negative polarity pixel data included in the image data RGB is relatively small, the column driver 800 may generate the negative output voltage having a relatively low voltage level.

Therefore, in the power management integrated circuit 700 included in the display driving circuit 50 according to the present invention, when the maximum size of the pixel data of the positive polarity included in the image data RGB is relatively large, And generates a positive driving voltage AVDDP having a relatively high voltage level during a horizontal period in which the positive output voltages corresponding to the pixel data of the display panel 100 are supplied to the display panel 100 and supplies the positive driving voltage AVDDP to the column driver 800, When the maximum size of the pixel data of the negative polarity included in the image data RGB is relatively large, the negative output voltages corresponding to the pixel data of the negative polarity are supplied to the display panel 100 A negative driving voltage AVDDN having a relatively high voltage level can be generated and provided to the column driver 800 during the period. On the other hand, when the maximum size of the pixel data of the positive polarity included in the image data RGB is relatively small, the positive output voltages corresponding to the pixel data of the positive polarity are applied to the display panel 100 A positive driving voltage AVDDP having a relatively low voltage level is generated by reducing the voltage level of the positive driving voltage AVDDP during the provided horizontal period and provided to the column driver 800, The negative output voltages corresponding to the pixel data of the negative polarity are supplied to the display panel 100 during the horizontal period when the maximum size of the pixel data of the negative polarity included therein is relatively small, A negative driving voltage AVDDN having a relatively low voltage level can be generated and provided to the column driver 800 by reducing the voltage level of the AVDDN.

As the voltage level of the positive driving voltage AVDDP and the voltage level of the negative driving voltage AVDDN are lower, the power consumption of the display driving circuit 50 is reduced. Therefore, the display driving circuit 50 according to the present invention can reduce the power consumption It is possible to effectively reduce the power consumption without including a separate device for reduction.

13 is a block diagram showing an example of a timing controller included in the display device of FIG.

13, the timing controller 600 may include a control circuit 610, a line buffer 620, a first comparator 630-1, and a second comparator 630-2.

The control circuit 610 can receive input data IDATA, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a main clock signal MCLK from an external host. The control circuit 610 can generate the gate control signal GCS and the column control signal CCS based on the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC and the main clock signal MCLK. The control circuit 610 divides the input data IDATA on a frame basis based on the vertical synchronization signal VSYNC and divides the input data IDATA on a line basis on the basis of the horizontal synchronization signal HSYNC, Data (RGB) can be generated. The control circuit 610 may store the image data RGB including the plurality of pixel data corresponding to one line in the line buffer 620. [

The image data (RGB) stored in the line buffer 620 may be provided to the column driver 800.

On the other hand, the control circuit 610 provides the first comparator 630-1 with the maximum magnitude (MAX_MP) of the amount of pixel data of positive polarity among the plurality of pixel data stored in the line buffer 620, (MAX_MN) of the negative polarity pixel data among the plurality of pixel data stored in the buffer 620 to the second comparator 630-2.

The first comparator 630-1 may compare the positive maximum magnitude MAX_MP with the positive reference magnitude REF_MP to generate a positive power saving signal PSSP.

The second comparator 630-2 may compare the negative maximum magnitude MAX_MN with the negative reference magnitude REF_MN to generate a negative power saving signal PSSN.

In one embodiment, the first comparator 630-1 generates an inactive positive power saving signal PSSP if the positive maximum magnitude MAX_MP is greater than or equal to the positive reference magnitude REF_MP, If the maximum amount of the quantity MAX_MP is less than the positive reference size REF_MP, an activated positive power saving signal PSSP can be generated.

Similarly, the second comparator 630-2 may generate a deactivated negative power saving signal PSSN if the negative maximum magnitude MAX_MN is greater than or equal to the negative reference magnitude REF_MN, If the maximum size MAX_MN is smaller than the negative reference size REF_MN, the activated negative power saving signal PSSN can be generated.

In this case, the power management integrated circuit 700 generates a positive drive voltage AVDDP having the first voltage level when the positive power save signal PSSP is inactive, A positive driving voltage AVDDP having the second voltage level lower than the first voltage level may be generated. The power management integrated circuit 700 also generates a negative drive voltage AVDDN having the third voltage level when the negative power save signal PSSN is inactive and the negative power save signal PSSN When activated, a negative drive voltage (AVDDN) having the fourth voltage level lower than the third voltage level may be generated.

In one embodiment, a positive reference magnitude REF_MP and a negative reference magnitude REF_MN may be stored within the timing controller 600.

In another embodiment, a positive reference size REF_MP and a negative reference size REF_MN may be provided from the host.

In one embodiment, similar to the timing controller 200b shown in FIG. 3, the first comparator 630-1 compares the positive maximum magnitude MAX_MP with the first through t positive reference magnitudes, respectively The second comparator 630-2 generates a positive power saving signal PSSP having one of the first to t-th values and the second comparator 630-2 generates the positive maximum power level signal MAX_MN and the first to tth A negative power saving signal PSSN having one of the first through the (t + 1) values can be generated by comparing each of the negative reference magnitudes.

In this case, the power management integrated circuit 700 generates a positive driving voltage AVDDP having a voltage level proportional to the value of the positive power saving signal PSSP, It is possible to generate a negative driving voltage AVDDN having a proportional voltage level.

In one embodiment, similar to the timing controller 200c shown in FIG. 4, the timing controller 600 controls the maximum size MAX_MP of the amount of pixel data of all positive polarity included in a plurality of consecutive lines, The power saving signal PSSP of the active amount is generated and only the negative maximum magnitude of the pixel data of the negative polarity included in the successive plurality of lines MAX_MN) is smaller than the negative reference magnitude (REF_MN), it may generate the activated negative power saving signal (PSSN).

14 is a block diagram showing an example of a column driver included in the display device of FIG.

14, the column driver 800a includes a plurality of data latches 810-1, 810-2, ..., 810- (m-1), 810-m, a plurality of level shifters 820 820-2, ..., 820- (m-1), 820-m), a plurality of decoders 830-1, 830-2, a plurality of output buffers 840-1, 840-2, ..., 840- (m-1) and 840-m, a gamma voltage generating circuit 850a, first multiplexers MUX1, A first multiplexer 851, and a second multiplexer MUX2 852.

The plurality of data latches 810-1, 810-2, ..., 810- (m-1), 810-m include the plurality of pixel data corresponding to one line from the timing controller 600 820-2, ..., 820- (m-1), 820-2, ..., 820-2, ..., 820- m. < / RTI >

The plurality of level shifters 820-1, 820-2, ..., and 820- (m-1) and 820-m may output the voltage levels of the plurality of pixel data.

The gamma voltage generation circuit 850a may generate a plurality of positive gamma voltages VGP [0: 255] and a plurality of negative gamma voltages VGN [0: 255].

The plurality of decoders 830-1, 830-2, ..., 830- (m-1), 830-m are connected to a plurality of level shifters 420-1, 420-2, m from the plurality of pixel data PD. Positive decoders disposed in the even-numbered columns of the plurality of decoders 830-1, 830-2, ..., 830- (m-1), 830-m are connected to the gamma voltage generating circuit 850a, 830- (m-1), 830-m) from a plurality of decoders 830-1, 830-2, ..., 830- Negative decoders disposed in odd-numbered columns may receive a plurality of negative gamma voltages VGN [0: 255] from gamma voltage generation circuit 850a.

Each of the positive decoders selects one of a plurality of positive gamma voltages VGP [0: 255] based on the received pixel data PD and outputs it as an input voltage VIN, Each may select one of a plurality of negative gamma voltages VGN [0: 255] based on the corresponding pixel data PD and output it as an input voltage VIN.

The plurality of output buffers 840-1, 840-2, ..., 840- (m-1), 840-m are arranged in positive output buffers and odd-numbered columns disposed in even-numbered columns Lt; / RTI > output buffers.

Each of the positive output buffers is coupled between a positive drive voltage AVDDP and a ground voltage AVSS provided from the power management integrated circuit 700 and each of the negative output buffers is coupled to a power management integrated circuit 700 (AVDDN) and the ground voltage (AVSS) provided from the negative voltage supply source (not shown).

Each of the positive output buffers generates an output voltage VOUT corresponding to an input voltage VIN using a positive drive voltage AVDDP and each of the negative output buffers has a negative drive voltage AVDDN, May be used to generate the output voltage VOUT corresponding to the input voltage VIN. Therefore, the maximum voltage level of the output voltage VOUT output from each of the positive output buffers corresponds to the voltage level of the received positive driving voltage AVDDP, and the output voltage VOUT output from each of the negative output buffers VOUT) may correspond to the voltage level of the received negative driving voltage AVDDN.

On the other hand, as shown in Fig. 14, the first multiplexers 851 are connected to the plurality of level shifters 820-1, 820-2, ..., 820- (m- 1) and 820-m may be provided to the decoder located in the same column or may be provided to the decoders located in adjacent columns.

Similarly, as shown in Figure 14, the second multiplexers 852 are coupled to a plurality of output buffers 840-1, 840-2, ..., 840- (m- 1) and 840-m may output the output voltage VOUT through the data lines located in the same column or may cross the data lines located in the adjacent columns.

The path control signal MS may be a signal whose logic level is inverted every frame. Therefore, the column driver 800a shown in FIG. 14 can drive the display panel 100 in a column inversion manner.

In one embodiment, the path control signal MS may be provided from the timing controller 600. [

14, each of the positive output buffers is connected between a positive drive voltage AVDDP and a ground voltage AVSS and operates using a positive drive voltage AVDDP, and the negative output Each of the buffers is connected between the negative drive voltage AVDDN and the ground voltage AVSS and operates using the negative drive voltage AVDDN so that the plurality of output buffers 840-1, 840-2, ..., , 840- (m-1), 840-m may be proportional to the difference between the positive driving voltage AVDDP and the negative driving voltage AVDDN.

As described above with reference to Figs. 11 to 14, the display driving apparatus 50 according to the present invention is characterized in that when the maximum size of the pixel data of the positive polarity included in the image data RGB is relatively large, The voltage level of the positive driving voltage AVDDP can be increased and the voltage level of the positive driving voltage AVDDP can be reduced when the maximum size of the positive polarity pixel data included in the image data RGB is relatively small. Similarly, the display driving apparatus 50 according to the present invention increases the voltage level of the negative driving voltage AVDDN when the maximum size of the pixel data of the negative polarity included in the image data RGB is relatively large, The voltage level of the negative driving voltage AVDDN can be reduced when the maximum size of the pixel data of the negative polarity included in the image data RGB is relatively small. Therefore, the display driving apparatus 50 according to the present invention can effectively reduce the power consumption while maintaining the performance as it is.

15 is a block diagram showing another example of a column driver included in the display device of FIG.

15, the column driver 800b includes a plurality of data latches 810-1, 810-2, ..., 810- (m-1), 810-m, a plurality of level shifters 820 820-2, ..., 820- (m-1), 820-m), a plurality of decoders 830-1, 830-2, a plurality of output buffers 840-1, 840-2, ..., 840- (m-1) and 840-m, a gamma voltage generating circuit 850b, first multiplexers MUX1, A first multiplexer 851, and a second multiplexer MUX2 852.

The column driver 800b of FIG. 15 is the same as the column driver 800a of FIG. 14 except for the operation of the gamma voltage generating circuit 850b. Therefore, redundant description will be omitted.

Gamma voltage generation circuit 850b may generate a plurality of positive gamma voltages VGP [0: 255] and a plurality of negative gamma voltages VGN [0: 255].

In one embodiment, the gamma voltage generation circuit 850b may receive a positive power saving signal PSSP and a negative power saving signal PSSN from the timing controller 600. [

In this case, the gamma voltage generating circuit 850b generates at least one positive gamma voltage having a high voltage level among the plurality of positive gamma voltages VGP [0: 255] based on the positive power saving signal PSSP And generating at least one negative gamma voltage having a high voltage level among a plurality of negative gamma voltages VGN [0: 255] based on the negative power saving signal PSSN, Can be selectively stopped.

For example, when the display driver 50 includes the timing controller 600 shown in FIG. 13, the gamma voltage generation circuit 850b may generate a plurality of positive All of the gamma voltages VGP [0: 255] are generated and a relatively high voltage level of the plurality of positive gamma voltages VGP [0: 255] is generated while the positive power saving signal PSSP is activated It is possible to stop generating positive positive gamma voltages VGP [k + 1: 255] and to generate only positive gamma voltages VGP [0: k] having a relatively low voltage level. Similarly, the gamma voltage generation circuit 850b generates all of the plurality of negative gamma voltages VGN [0: 255] while the negative power saving signal PSSN is inactive, and outputs the negative power saving signal PSSN, (K + 1: 255) having a relatively high voltage level among a plurality of negative gamma voltages VGN [0: 255] during the activation of the negative gamma voltages VGN [ Only negative gamma voltages VGN [0: k] having a voltage level can be generated. Here, k represents a positive integer less than 255.

As described above, while the positive power saving signal PSSP is deactivated, each of the positive decoders has a positive gamma voltage having a high voltage level among the plurality of positive gamma voltages VGP [0: 255] Each of the negative decoders has a high voltage level among the plurality of negative gamma voltages VGN [0: 255], while the negative power saving signal PSSN is inactive while not selecting it as the input voltage VIN The negative gamma voltage may not be selected as the input voltage VIN.

Thus, the gamma voltage generation circuit 850b may be configured to generate at least one positive gamma voltage having a high voltage level among the plurality of positive gamma voltages VGP [0: 255] while the positive power saving signal PSSP is deactivated Even if the generation of at least one negative gamma voltage having a high voltage level among the plurality of negative gamma voltages VGN [0: 255] is stopped while the negative power saving signal PSSN is inactivated The power consumption can be effectively reduced without affecting the operation of the display drive device 50. [

16 is a block diagram showing a display device according to an embodiment of the present invention.

The timing controller 600 and the column driver 800 included in the display device 40b of FIG. 16 are included in the same integrated circuit 60, while the timing controller 600 included in the display device 40a of FIG. The display device 40b of FIG. 16 and the display device 40a of FIG. 11 are identical to each other, except that the column driver 800 and the column driver 800 are included in different integrated circuits.

As shown in Figs. 11 and 16, according to the embodiment, the timing controller 600 and the column driver 800 may be implemented in the same integrated circuit 60, or may be implemented in different integrated circuits.

The present invention can be usefully used in any electronic device including a user's display device. For example, the present invention can be applied to mobile phones, smart phones, personal digital assistants, portable multimedia players, digital cameras, notebook computers, and the like.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

Claims (10)

A timing controller for generating image data by dividing input data in units of lines and generating a power saving signal based on a size and a reference size of a plurality of pixel data included in the image data;
A power management integrated circuit for generating a drive voltage having a varying voltage level based on the power saving signal; And
And a column driver that receives the image data from the timing controller and generates a plurality of output voltages corresponding to the plurality of pixel data included in the image data using the driving voltage. The apparatus according to claim 1,
When the maximum size of the plurality of pixel data included in the image data is greater than or equal to the reference size, the power saving signal is deactivated,
And activates the power saving signal when the maximum size of the plurality of pixel data included in the image data is smaller than the reference size. The power management integrated circuit according to claim 2,
Generating the drive voltage having a first voltage level when the power saving signal is inactive and generating the drive voltage having a second voltage level lower than the first voltage level when the power saving signal is activated Display driver. 2. The apparatus of claim 1, wherein the reference magnitude includes first through t-th reference magnitudes (t is a positive integer greater than or equal to 2)
Wherein the timing controller compares the maximum size of the plurality of pixel data included in the image data with the first to tth reference magnitudes, respectively, and outputs the first to the (t + 1) A display drive device for generating a power saving signal. 5. The power management integrated circuit of claim 4,
And generates the drive voltage having a voltage level proportional to the value of the power saving signal. The apparatus according to claim 1,
Line buffers;
A control circuit for dividing the input data in units of lines and storing the plurality of pixel data corresponding to one line in the line buffer; And
And a comparator for comparing the maximum size of the plurality of pixel data stored in the line buffer with the reference size to generate the power saving signal. The apparatus according to claim 1,
First through s (s is a positive integer equal to or greater than two) line buffers;
A control circuit for dividing the input data in units of lines and storing the plurality of pixel data corresponding to the first to s-th lines successively in the first to s-th line buffers, respectively;
A comparator that compares each of the first through s maximum sizes of the plurality of pixel data stored in each of the first through s line buffers with the reference size to generate first through s th power saving signals; And
And a logical product gate for performing an AND operation on the first to the < RTI ID = 0.0 > s < / RTI > power saving signals to generate the power saving signal. The apparatus of claim 1, wherein the column driver comprises:
A gamma voltage generating circuit for generating a plurality of gamma voltages;
A decoder for selecting one of the plurality of gamma voltages based on the pixel data included in the image data and outputting the selected one as an input voltage; And
And an output buffer connected between the driving voltage and the ground voltage and using the driving voltage to generate the output voltage corresponding to the input voltage. 9. The apparatus of claim 8, wherein the timing controller provides the power saving signal to the gamma voltage generation circuit,
Wherein the gamma voltage generating circuit selectively stops generation of at least one gamma voltage having a relatively high voltage level among the plurality of gamma voltages based on the power saving signal. Generates a positive power saving signal based on a magnitude and a positive reference magnitude of pixel data of positive polarity among a plurality of pixel data included in the image data by dividing the input data into line units, A timing controller for generating a negative power saving signal based on the size of the negative pixel data and the negative reference size among the plurality of pixel data included in the image data;
A power management integrated circuit for generating a positive driving voltage having a varying voltage level based on the positive power saving signal and generating a negative driving voltage having a varying voltage level based on the negative power saving signal; And
And generates a plurality of positive output voltages corresponding to the positive polarity pixel data included in the image data using the positive driving voltage, And a column driver for generating a plurality of negative output voltages corresponding to pixel data of the negative polarity included in the image data using a voltage.

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