KR20170094744A - 집적 회로 및 상기 집적 회로의 제조를 위한 컴퓨터 구현 방법 - Google Patents

집적 회로 및 상기 집적 회로의 제조를 위한 컴퓨터 구현 방법 Download PDF

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Publication number
KR20170094744A
KR20170094744A KR1020160100122A KR20160100122A KR20170094744A KR 20170094744 A KR20170094744 A KR 20170094744A KR 1020160100122 A KR1020160100122 A KR 1020160100122A KR 20160100122 A KR20160100122 A KR 20160100122A KR 20170094744 A KR20170094744 A KR 20170094744A
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KR
South Korea
Prior art keywords
air gap
integrated circuit
timing
conductive pattern
routing
Prior art date
Application number
KR1020160100122A
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English (en)
Korean (ko)
Inventor
류성민
원효식
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US15/420,514 priority Critical patent/US9991249B2/en
Priority to TW106104007A priority patent/TWI718245B/zh
Priority to CN201710070632.9A priority patent/CN107066681B/zh
Publication of KR20170094744A publication Critical patent/KR20170094744A/ko
Priority to US15/981,408 priority patent/US10418354B2/en

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    • G06F17/5068
    • G06F17/5072
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • G06F2217/40

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020160100122A 2016-02-11 2016-08-05 집적 회로 및 상기 집적 회로의 제조를 위한 컴퓨터 구현 방법 KR20170094744A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/420,514 US9991249B2 (en) 2016-02-11 2017-01-31 Integrated circuit and computer-implemented method of manufacturing the same
TW106104007A TWI718245B (zh) 2016-02-11 2017-02-08 積體電路、製造其的電腦實施方法以及定義其的標準元件
CN201710070632.9A CN107066681B (zh) 2016-02-11 2017-02-09 集成电路和制造集成电路的计算机实现方法
US15/981,408 US10418354B2 (en) 2016-02-11 2018-05-16 Integrated circuit and computer-implemented method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20160015820 2016-02-11
KR1020160015820 2016-02-11

Publications (1)

Publication Number Publication Date
KR20170094744A true KR20170094744A (ko) 2017-08-21

Family

ID=59757519

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160100122A KR20170094744A (ko) 2016-02-11 2016-08-05 집적 회로 및 상기 집적 회로의 제조를 위한 컴퓨터 구현 방법

Country Status (2)

Country Link
KR (1) KR20170094744A (zh)
TW (1) TWI718245B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200057297A (ko) * 2018-11-16 2020-05-26 삼성전자주식회사 반도체 장치의 제조 방법 및 레이아웃 디자인 시스템

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714039B (zh) * 2019-03-27 2020-12-21 創意電子股份有限公司 時序模型、時序模型建立方法、與相關的頂層分析方法
US11069695B2 (en) * 2019-05-31 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Floating gate test structure for embedded memory device
DE102020100001B4 (de) 2019-05-31 2022-05-25 Taiwan Semiconductor Manufacturing Co. Ltd. Integrierter Schaltkreis mit einer Mehrzahl von Speicherprüfstrukturen und Verfahren zu dessen Herstellung sowie Speicherprüfstruktur einer eingebetteten Speichervorrichtung

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008103610A (ja) * 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体集積回路の配線構造およびその設計方法と設計装置
US8375347B2 (en) * 2009-05-12 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Driven metal critical dimension (CD) biasing
US8765595B2 (en) * 2012-01-06 2014-07-01 International Business Machines Corporation Thick on-chip high-performance wiring structures
US8603889B2 (en) * 2012-03-30 2013-12-10 International Business Machines Corporation Integrated circuit structure having air-gap trench isolation and related design structure
KR102033496B1 (ko) * 2013-07-12 2019-10-17 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US9231074B2 (en) * 2013-07-19 2016-01-05 Globalfoundries Inc. Bipolar junction transistors with an air gap in the shallow trench isolation
KR102143501B1 (ko) * 2013-12-05 2020-08-11 삼성전자 주식회사 레이아웃 디자인 시스템 및 이를 이용하여 제조한 반도체 장치
KR102247918B1 (ko) * 2014-04-07 2021-05-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200057297A (ko) * 2018-11-16 2020-05-26 삼성전자주식회사 반도체 장치의 제조 방법 및 레이아웃 디자인 시스템

Also Published As

Publication number Publication date
TWI718245B (zh) 2021-02-11
TW201826155A (zh) 2018-07-16

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