KR20170092006A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to an electronic device. More specifically, the present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device having improved reliability according to the present invention comprises: a memory cell array including a plurality of strings connected between a bit line and a source line, wherein the plurality of strings include selective transistors respectively connected to selective lines and a plurality of memory cells respectively connected to a plurality of word lines; and a peripheral circuit performing a reading operation with respect to the selected memory cells among the plurality of memory cells. The peripheral circuit can discharge the selective lines prior to the plurality of word lines in the reading operation.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and an operation method thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM , RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

An embodiment of the present invention is to provide a semiconductor memory device with improved reliability and a method of operation thereof.

A plurality of strings coupled between a bit line and a source line in accordance with an embodiment of the present invention, wherein the plurality of strings comprise select transistors coupled to select lines and a plurality of memory cells The method comprising the steps of applying a read voltage to a selected word line to which selected memory cells of the plurality of memory cells are connected and applying a pass voltage to unselected word lines to which unselected memory cells are connected Reading data stored in the selected memory cells based on the output of the bit line, and discharging the select lines prior to the selected word line and unselected word lines.

A plurality of strings coupled between a bit line and a source line in accordance with an embodiment of the present invention, wherein the plurality of strings comprise select transistors coupled to select lines and a plurality of memory cells The method comprising the steps of applying a pass voltage to unselected word lines to which selected memory cells of the plurality of memory cells are connected and unselected memory cells to which the selected memory cells are connected, And discharging the selected lines when a first reference time elapses after applying a pass voltage to the selected word line and the non-selected word lines when a second reference time elapses after dispensing the selected lines. And discharging.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of strings connected between a bit line and a source line, the plurality of strings being connected to select transistors and a plurality of word lines, A memory cell array including a plurality of connected memory cells and a peripheral circuit for performing a read operation on selected ones of the plurality of memory cells, Lt; RTI ID = 0.0 > wordlines < / RTI >

According to an embodiment of the present invention, a semiconductor memory device and an operation method thereof having improved reliability are provided.

1 is a block diagram showing a configuration of a memory system.
2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
3 is a view showing the memory cell array structure of FIG.
4 shows another embodiment of the memory cell array of FIG.
5 is a graph showing voltages applied to the respective lines during a read operation.
FIG. 6 is a view for explaining a phenomenon occurring when the voltage of FIG. 5 is applied.
7 is a diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.
8 is a flowchart for explaining the operation of the semiconductor memory device according to the embodiment of the present invention.
Fig. 9 is a flowchart showing the discharge operation of Fig. 8. Fig.
10 is a block diagram showing a memory system including the semiconductor memory device of FIG.
11 is a block diagram illustrating an application example of the memory system of FIG.
12 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first and / or second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having", etc., are used to specify that there are described features, numbers, steps, operations, elements, parts or combinations thereof, and that one or more other features, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as ideal or overly formal in the sense of the art unless explicitly defined herein Do not.

In the following description of the embodiments of the present invention, descriptions of techniques which are well known in the technical field of the present invention and are not directly related to the present invention will be omitted. This is for the sake of clarity of the present invention without omitting the unnecessary explanation.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a memory system.

The memory system 50 includes a semiconductor memory device 100 and a controller 200.

The semiconductor memory device 100 may include a memory device such as a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM) such as phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer random access memory (STT-RAM) . In addition, the semiconductor memory device 100 of the present invention can be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory device in which the charge storage layer is made of a conductive floating gate (FG) but also to a charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

The semiconductor memory device 100 includes a memory cell array 110 and peripheral circuits 120 for driving the memory cell array 110. The memory cell array 110 includes a plurality of nonvolatile memory cells.

The memory cell array 110 includes a plurality of memory blocks, and the plurality of memory blocks may be divided into a system block, a user block, and the like depending on the use thereof.

In an embodiment, the memory cell array 110 includes a content addressable memory (CAM) region 111. The cam region 111 may include a plurality of memory cells included in at least one memory block. The memory block corresponding to the cam area 111 may be a cam block. The cam block and the memory block may have the same structure. The setting information of the semiconductor memory device 100 may be stored in the cam area 111. [

Specifically, the cam area 111 may store conditions or other information set in connection with data input / output operations. In the embodiment, the number of read / write cycles (P / E cycle), the defective column address, and the defective block address information may be stored in the cam area 111. In the embodiment, optional information necessary for the operation of the semiconductor memory device 100, for example, program voltage information, read voltage information, erase voltage information or cell gate oxide film thickness information, etc., is stored in the cam area 111 . In an embodiment, the repair information may be stored in the cam area 111. [ When power is supplied to the semiconductor memory device 100, the information stored in the cam area 111 is read by the peripheral circuit 120, and the peripheral circuit 120 reads the data input / output To control the memory cell array 110 to perform operations.

According to the embodiment of the present invention, the information on the first reference time (tref1) and the second reference time (tref2) necessary for the semiconductor memory device to discharge a plurality of lines in the reading operation is stored in the cam area 111 .

The first reference time tref1 may be the time at which the voltage of the selected word line of the semiconductor memory device reaches the pass voltage Vpass.

The second reference time tref2 may be the time at which the select lines DSL and SSL of the memory cell array of the semiconductor memory device are discharged. It may be a time at which the voltage of the select lines DSL and SSL reaches the ground voltage GND.

The peripheral circuit (120) operates in response to the control of the controller (200). The peripheral circuit 120 may program the data in the memory cell array 110 in response to the control of the controller 200. [ The peripheral circuit 120 may be operable to read data from the memory cell array 110 and to erase the data in the memory cell array 110.

In various embodiments, the read operation and the program operation of semiconductor memory device 100 may be performed page by page. The erase operation of the semiconductor memory device 100 may be performed on a memory block basis.

In the program operation, the peripheral circuit 120 can receive a command indicating a program operation, a physical block address (PBA) (physical address, PA), and write data from the controller 200. [ The peripheral circuit 120 can program the write data to the selected page when one memory block and one page included in the memory block are selected by the physical block address (PBA).

In a read operation, the peripheral circuit 120 can receive a command (hereinafter referred to as a read command) and a physical block address (PBA) indicating a read operation from the controller 200. The peripheral circuit 120 can read data from one memory block selected by the physical block address (PBA) and one page included therein, and output the read data (hereinafter, page data) to the controller 200 .

In the erase operation, the peripheral circuit 120 can receive the command indicating the erase operation and the physical block address (PBA) from the controller 200. [ The physical block address (PBA) will specify one memory block. The peripheral circuit 120 will erase the data of the memory block corresponding to the physical block address (PBA).

The controller 200 controls the overall operation of the semiconductor memory device 100. The controller 200 can access the semiconductor memory device 100 in response to a request from an external host. The controller 200 commands the semiconductor memory device 100 in response to a request from an external host.

As an embodiment, the controller 200 may control the semiconductor memory device 100 to perform a program operation, a read operation, or an erase operation. In operation of the program, the controller 200 will provide the program command, address, and data to the semiconductor memory device 100 via the channel. In a read operation, the controller 200 will provide a read command and address to the semiconductor memory device 100 via the channel. In the erase operation, the controller 200 will provide the erase command and address to the semiconductor memory device 100 via the channel.

The controller 200 may include a RAM 210, a memory controller 220, and an error correction circuit 230.

A random access memory (RAM) 210 operates under the control of the memory controller 220 and can be used as a work memory, a buffer memory, a cache memory, and the like. When the RAM 210 is used as a work memory, the data processed by the memory control unit 220 can be temporarily stored. When the RAM 210 is used as a buffer memory, it can be used to buffer data to be transferred from the host (not shown) to the semiconductor memory device 100 or from the semiconductor memory device 100 to the host (not shown).

The memory control unit 220 is configured to control a read operation, a program operation, an erase operation, and a background operation of the semiconductor memory device 100. The memory controller 220 is configured to drive firmware for controlling the semiconductor memory device 100.

The memory controller 220 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through a flash translation layer (FTL). Specifically, the flash translation layer (FTL) receives the logical block address (LBA) using the mapping table and can convert it into the physical block address (PBA). The physical block address may be a page number referring to a specific word line of the memory cell array 110. [ There are various mapping methods for the address in the flash conversion layer, depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

The error correction code circuit 230 generates a parity which is an error correction code (ECC) for the data to be programmed. In addition, during a read operation, the error correction code circuit 230 can correct an error using parity for the read page data. The error correction code circuit 230 includes a low density parity check (LDPC) code, a Bose (Chaudhri) code, a turbo code, a Reed- , Coded modulation such as trellis-coded modulation (TCM), block coded modulation (BCM), and hamming code can be used to correct errors.

In a read operation, the error correction code circuit 230 can correct errors in the read page data. Decode may fail if the read page data contains error bits that exceed the correctable number of bits. If the page data contains error bits equal to or less than the number of correctable bits, the decoding may succeed.

The success of the decode indicates that the read command has been passed. Failure of decode indicates that the read command failed. When the decode is successful, the controller 200 outputs the error-corrected page data to the host.

Although not shown in the figure, the controller 200 may further include a memory interface for communicating with the semiconductor memory device 100. The memory interface includes a protocol for communicating with the semiconductor memory device 100. For example, the memory interface may include at least one of flash interfaces such as a NAND interface, a NOR interface, and the like.

In addition, the controller 200 may further include a host interface for performing data exchange between the host and the controller 200. The host interface includes a protocol for communicating between the host and the controller 200. Illustratively, the controller 200 may be implemented using a variety of communication protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- (Host) through at least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, Respectively.

2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

3 is a view showing a structure of the memory cell array 110 of FIG.

Referring to FIG. 2, a semiconductor memory device 100 includes a memory cell array 110 and a peripheral circuit 120.

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 via the row lines RL and to the read and write circuit 123 via the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells.

The plurality of memory cells included in the memory cell array 110 can be used as a plurality of blocks according to the use thereof.

In an embodiment, the memory cell array 110 may include a content addressable memory (CAM) region 111 of FIG. The cam region 111 may include a plurality of memory cells included in at least one memory block. The memory block corresponding to the cam area 111 may be a cam block. The cam block may be at least one of the memory blocks BLK1 to BLKz. The cam block may have the same structure as the memory blocks. The setting information of the semiconductor memory device 100 may be stored in the cam area 111. [ Specifically, the cam area 111 may store conditions or other information set in connection with data input / output operations. In the embodiment, the number of read / write cycles (P / E cycle), the defective column address, and the defective block address information may be stored in the cam area 111. In the embodiment, optional information necessary for the operation of the semiconductor memory device 100, for example, program voltage information, read voltage information, erase voltage information or cell gate oxide film thickness information, etc., is stored in the cam area 111 . In an embodiment, the repair information may be stored in the cam area 111. [

According to the embodiment of the present invention, the information on the first reference time (tref1) and the second reference time (tref2) necessary for the semiconductor memory device to discharge a plurality of lines in the reading operation is stored in the cam area 111 .

The first reference time tref1 may be the time at which the voltage of the selected word line of the semiconductor memory device reaches the pass voltage Vpass.

The second reference time tref2 may be the time at which the selection lines DSL and SSL of the memory cell array of the semiconductor memory device are discharged. That is, it may be a time at which the voltage of the selection lines DSL and SSL reaches the ground voltage GND.

The first to z-th memory blocks BLK1 to BLKz are commonly connected to the first to m-th bit lines BL1 to BLm. The first to z-th memory blocks BLK1 to BLKz include a plurality of cell strings. The plurality of cell strings are connected to the first to m-th bit lines BL1 to BLm, respectively.

In FIG. 3, elements included in the first memory block BLK1 of the plurality of memory blocks BLK1 to BLKz are shown for convenience of description, and elements included in each of the remaining memory blocks BLK2 to BLKz Is omitted. It will be understood that each of the remaining memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

The memory block BLK1 includes a plurality of cell strings CS11 to CS1m, CS21 to CS2m. The first to m-th cell strings CS11 to CS1m are connected to the first to m-th bit lines BL1 to BLm, respectively.

Each of the first through m-th cell strings CS11 through CS1m includes a drain select transistor DST, a plurality of memory cells MC1 through MCn connected in series, and a source select transistor SST. The drain select transistor DST is connected to the drain select line DSL1. The first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively. The source select transistor SST is connected to the source select line SSL1. And the drain side of the drain select transistor DST is connected to the corresponding bit line. The drain select transistors of the first to m-th cell strings CS11 to CS1m are connected to the first to m-th bit lines BL1 to BLm, respectively. The source side of the source select transistor SST is connected to the common source line CSL. As an embodiment, the common source line CSL may be connected in common to the first to z-th memory blocks BLK1 to BLKz.

The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 are included in the row lines RL in Fig. The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 are controlled by the address decoder 121. [ The common source line (CSL) is controlled by the control logic (125). The first to m-th bit lines BL1 to BLm are controlled by the read and write circuit 123.

2, the peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a control logic 125. The address decoder 121 is connected to the memory cell array 110 via the row lines RL. The address decoder 121 is configured to operate in response to control of the control logic 125. The address decoder 121 receives the address ADDR via the control logic 125.

As an embodiment, the program operation and the read operation of the semiconductor memory device 100 are performed page by page. In a program operation and a read operation, the address ADDR will include a block address and a row address.

The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects one of the memory blocks BLK1 to BLKz according to the decoded block address.

The address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 applies the voltages supplied from the voltage generator 122 to the row lines RL according to the decoded row address to select one word line of the selected memory block.

In program operation, the address decoder 121 will apply a program voltage to the selected word line and a pass voltage lower than the program voltage to the unselected word lines. During a program verify operation, the address decoder 121 will apply a verify voltage to the selected word line and a verify pass voltage higher than the verify voltage to unselected word lines.

In a read operation, the address decoder 121 will apply a read voltage to the selected word line and a pass voltage higher than the read voltage to the unselected word lines.

As an embodiment, the erase operation of semiconductor memory device 100 is performed on a memory block basis. In the erase operation, the address ADDR includes a block address. The address decoder 121 decodes the block address and selects one memory block according to the decoded block address.

As an example, the address decoder 121 may include a block decoder, a word line decoder, an address buffer, and the like.

The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the semiconductor memory device 100. Voltage generator 122 operates in response to control of control logic 125.

In an embodiment, the voltage generator 122 may regulate the external supply voltage to generate the internal supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the semiconductor memory device 100.

In an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors to receive an internal supply voltage, and may selectively generate a plurality of voltages by selectively activating a plurality of pumping capacitors in response to control of the control logic 125 . The generated plurality of voltages are applied to the word lines selected by the address decoder 121.

The read and write circuit 123 includes first through m-th page buffers PB1 through PBm. The first through m-th page buffers PB1 through PBm are connected to the memory cell array 110 through first through m-th bit lines BL1 through BLm, respectively. The first through m-th page buffers PB1 through PBm operate in response to control of the control logic 125. [

The first to m < th > page buffers PB1 to PBm communicate data with the data input / output circuit 124. [ The first to m-th page buffers PB1 to PBm receive data (DATA) to be stored via the data input / output circuit 124 and the data lines DL.

The first to m-th page buffers PB1 to PBm transmit data (DATA) to be stored to the data (DATA) received through the data input / output circuit 124 when a program pulse is applied to the selected word line, To the selected memory cells via bit lines BLl through BLm. The memory cells of the selected page are programmed according to the transferred data (DATA). A memory cell coupled to a bit line to which a program allowable voltage (e.g., ground voltage) is applied will have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which the program inhibit voltage (e.g., power supply voltage) is applied will be maintained. During the program verify operation, the first through m-th page buffers PB1 through PBm read page data from the selected memory cells via the bit lines BL1 through BLm.

In a read operation, the read and write circuit 123 reads data (DATA) from the memory cells of the selected page through the bit lines (BL) and outputs the read data (DATA) to the input / output circuit 124.

In the erase operation, the read and write circuit 123 may float the bit lines BL.

The data input / output circuit 124 is connected to the first through m-th page buffers PB1 through PBm through the data lines DL. The data input / output circuit 124 operates in response to control of the control logic 125. At the time of programming, the data input / output circuit 124 receives data (DATA) to be stored from an external controller (not shown).

The data input / output circuit 124 outputs data transferred from the first through m-th page buffers PB1 through PBm included in the read / write circuit 123 to the external controller during a read operation.

The control logic 125 is connected to an address decoder 121, a voltage generator 122, a read and write circuit 123 and a data input / output circuit 124. The control logic 125 may control the overall operation of the semiconductor memory device 100. The control logic 125 receives the command CMD and the address ADDR from the external controller. The control logic 125 is configured to control the address decoder 121, the voltage generator 122, the read and write circuit 123 and the data input / output circuit 124 in response to the command CMD. The control logic 125 transfers the address ADDR to the address decoder 121. [

According to an embodiment of the present invention, the control logic 125 can read the information stored in the cam area 111 when the semiconductor memory device 100 is powered on.

In an embodiment of the present invention, the control logic 125 may control the read and write operations of the word lines and select lines in accordance with a first reference time tref1 and a second reference time tref2, can do.

The control logic 125 controls the voltage generator 122 and the address decoder 121 to apply the pass voltage (Vpass) to the selected word line in the discharge period during a read operation.

The control logic 125 may discharge the selection lines DSL and SSL after the first reference time tref1 elapses after applying the pass voltage Vpass to the selected word line. The control logic 125 may control the voltage generator 122 and the address decoder 121 to apply a ground voltage to the selection lines DSL and SSL when the first reference time tref1 elapses.

The control logic 125 may discharge the word lines of the memory cell array 110 after the second reference time tref2 elapses after applying the ground voltage to the select lines DSL and SSL. The control logic 125 may control the voltage generator 122 and the address decoder 121 to apply a ground voltage to the word lines to discharge the word lines when the second reference time tref2 has elapsed .

The control logic 125 may include at least one counter circuit for determining whether the first reference time tref1 and the second reference time tref2 have elapsed.

Referring again to FIG. 3, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. 3, the internal structure of the first memory block BLK1 is shown for the convenience of recognition, and the internal structure of the remaining memory blocks BLK2 to BLKz is omitted. It will be understood that the second to z-th memory blocks BLK2 to BLKz are configured similarly to the first memory block BLK1.

Referring to FIG. 3, the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a U shape. In the first memory block BLK1, m cell strings are arranged in the row direction (i.e., the + X direction). In Figure 3, two cell strings are shown arranged in the column direction (i.e., the + Y direction). However, it will be understood that three or more cell strings may be arranged in the column direction for convenience of explanation.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, And a selection transistor DST.

Each of the select transistors SST and DST and each of the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an example, a pillar for providing a channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. In Fig. 3, the source select transistors of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to the second source select line SSL2.

In another embodiment, the source select transistors of the cell strings CS11 to CS1m, CS21 to CS2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p + 1 to nth memory cells MCp + 1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the direction opposite to the + Z direction, and are connected in series between the source selection transistor SST and the pipe transistor PT. The p + 1 th to nth memory cells MCp + 1 to MCn are sequentially arranged in the + Z direction, and are serially connected between the pipe transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the p + 1 to nth memory cells MCp + 1 to MCn are connected through a pipe transistor PT. The gates of the first to n < th > memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n < th > memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the cell string can be stably controlled. Thus, the reliability of the data stored in the memory block BLK1 is improved.

The gates of the pipe transistors PT of each cell string are connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp + 1 to MCn. The cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

The cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 4, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

Memory cells connected to the same word line within the cell strings arranged in the row direction constitute one page. For example, the memory cells connected to the first word line WL1 of the cell strings CS11 to CS1m in the first row constitute one page. The memory cells connected to the first word line WL1 of the cell strings CS21 to CS2m of the second row constitute another page. The cell strings to be arranged in one row direction will be selected by selecting any one of the drain select lines DSL1 and DSL2. One of the selected cell strings will be selected by selecting any one of the word lines WL1 to WLn.

4 is a view showing another embodiment of the memory cell array 110 of FIG.

Referring to FIG. 4, the memory cell array 110 includes a plurality of memory blocks BLK1 'to BLKz'. In FIG. 4, the internal structure of the first memory block BLK1 'is shown for the convenience of recognition, and the internal structure of the remaining memory blocks BLK2' to BLKz 'is omitted. It will be understood that the second to z-th memory blocks BLK2 'to BLKz' are configured similarly to the first memory block BLK1 '.

The first memory block BLK1 'includes a plurality of cell strings CS11' to CS1m ', CS21' to CS2m '. Each of the plurality of cell strings CS11 'to CS1m', CS21 'to CS2m' extend along the + Z direction. Within the first memory block BLK1 ', m cell strings in the + X direction are arranged. In Figure 4, two cell strings are shown arranged in the + Y direction. However, it will be understood that three or more cell strings may be arranged in the column direction for convenience of explanation.

Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection And a transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11 'to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21 'to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11 'to CS1m', CS21 'to CS2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are connected to the first to the nth word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n < th > memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the cell string can be stably controlled. Accordingly, the reliability of the data stored in the memory block BLK1 'is improved.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' of the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 'to CS2m' of the second row are connected to the second drain select line DSL2.

As a result, the memory block BLK1 'of FIG. 4 has an equivalent circuit similar to the memory block BLK1 of FIG. 3, except that the pipe transistor PT is excluded in each cell string.

5 is a graph showing voltages applied to the respective lines during a read operation.

FIG. 6 is a view for explaining a phenomenon occurring when the voltage of FIG. 5 is applied.

A read operation of the semiconductor memory device is an operation of sensing the status of a memory cell after accessing an address of the memory cell. The read operation is an operation for sensing whether a memory cell is programmed or erased, or a program state at a certain level in a program state. Both program verification and erase verification accompanying program operation and erase operations are a type of read operation. Therefore, it should be noted that the verify operation according to the embodiment of the present invention can also be applied to the program verify operation and the erase verify operation, respectively.

Referring to FIG. 5, the read operation of the semiconductor memory device may be divided into a precharge period P1, a read period P2, and a discharge period P3.

In the precharge period P1, the semiconductor memory device applies predetermined voltages to perform read operations on the respective lines connected to the memory cell array.

The source selection voltage Vssl and the drain selection voltage Vdsl are applied to the source selection line SSLsel and the selected drain selection line DSLsel in the precharge period P1 respectively. The source selection voltage Vssl and the drain selection voltage Vdsl turn on the source selection transistor and the drain selection transistor included in the selected memory string, respectively.

The selected word line SELWL may be supplied with the word line set voltage Vset. Here, the word line setting voltage Vset may be the same voltage level as the pass voltage Vpass applied to the unselected word lines UNSELWL. In various embodiments, the word line set voltage Vset may cause the selected word line SELWL to float. The word line set voltage Vset is a voltage for setting the selected word line SELWL to a state required for a read operation. According to the operation of the semiconductor memory device according to the present invention, various word line set voltages can be applied.

A pass voltage Vpass is applied to the unselected word lines UNSELWL. The pass voltage Vpass is a voltage capable of turning on the memory cells connected to the unselected word line UNSELWL.

A bit line voltage VBL may be applied to the bit lines BL. The bit line voltage VBL may precharge the bit lines BL for a read operation.

The description of the operation of sensing the voltage level or current of the bit line through the page buffer PB after the precharge operation of the bit line BL or the valence operation of the memory cell corresponds to a portion deviating from the core features of the present invention Therefore, detailed description is omitted.

In the read period P2, the semiconductor memory device applies the read voltage Vread to the selected word line SELWL to read the data stored in the plurality of memory cells connected to the selected word line SELWL.

During the read period P2, the voltages applied to the source select line SSLsel, the drain select line DSLsel, and the unselected word lines UNSELWL are maintained in the precharge period P1.

A read voltage Vread is applied to the selected word line SELWL.

The potential of the bit line BL may have a value of a high, low, or floating state depending on the program state of the memory cells connected to the selected word line SELWL.

In the discharge period P3, the semiconductor memory device discharges each line connected to the memory cell array.

Referring to FIG. 5, a semiconductor memory device may apply a pass voltage Vpass to a selected word line SELWL to equalize the voltage levels of all the word lines. In an embodiment, the voltage levels of the word lines may be set to have different values.

At time tl, the semiconductor memory device discharges the word lines.

Referring to FIG. 6, one memory string includes source select transistors connected to a source select line (SSL), dummy memory cells connected in series with a source select transistor, and dummy memory cells are connected to a dummy word line DWL . Each of the plurality of memory cells connected to the dummy memory cell may be connected to the 0th to xx word lines WL00 to WLXX. 6, the memory cell connected to the 0th word line WL00 is in an erased state (PV0), and the memory cell connected to the first word line WL01 is programmed in the seventh program state PV7 . The memory cells connected to the second to the XXth word lines WL02 to WLXX may each be programmed in an arbitrary program state.

The word lines are discharged at the time t1 of the discharge period P3. At this time, since the source selection line is in a state in which the source selection voltage is being applied, the source selection transistor may be turned on. Since the drain select voltage is being applied to the drain select line, the drain select transistor may be in a turned-on state. A ground voltage is applied to the common source line, the drain select line, and the bit line during the discharge interval P3. When discharge is started for all the word lines, the voltage of the word lines decreases from the pass voltage (Vpass) to the ground voltage (GND).

The on / off state of the channel can be changed for each word line according to the difference of the threshold voltages of the memory cells connected to the word lines in the discharge period P3.

That is, when the threshold voltage of the memory cell connected to the 0th word line WL00 is lower than the threshold voltage of the memory cell connected to the first word line WL01, the channel of the memory cell connected to the first word line WL01 is first And an OFF state is reached. Since the channel of the memory cells having a high threshold voltage reaches the OFF state before the channel of the memory cells having the low threshold voltage, the threshold voltage of the memory cells having the low threshold voltage existing in the boundary of the memory cells having the high threshold voltage The channel may be in a floating state in the discharge operation. Therefore, a local boosting phenomenon may occur between channels that are in an OFF state.

When a local boosting state occurs, a potential difference between the source line or the bit line in the channel of the second word line WL02 toward the channel of the zeroth word line WL0 in accordance with the potential difference from the ground voltage GND of the hot line Injection (HCI) phenomenon may occur. Therefore, the threshold voltage may increase even though the memory cell connected to the 0th word line WL0 is in the erase state (PV0). This causes a read disturbance, which can not guarantee the reliability of the semiconductor memory device.

In FIG. 6, a memory string including a source selection transistor, a drain selection transistor (not shown) and a dummy memory cell is shown, but in the embodiment, the source selection transistor, the dummy memory cell and the drain selection transistor And may include a plurality of.

7 is a diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.

In the embodiment of FIG. 7, the operation of the semiconductor memory device in the precharge interval P1 and the read interval P2 is the same as that in FIG.

According to the embodiment of the present invention, the semiconductor memory device discharges select lines (SSL, DSL) before the word lines and discharges the word lines in the discharge period P3.

In the discharge period P3, the semiconductor memory device applies the pass voltage Vpass to the selected word line SELWL to equalize the voltage levels of all the word lines. In various embodiments, the semiconductor memory device may be configured such that the voltages of the word lines are different from each other.

After the pass voltage Vpass is applied to the selected word line SELWL and the first reference time tref1 elapses (t3), the semiconductor memory device discharges the selection lines SSLsel, DSLsel. The semiconductor memory device may apply a ground voltage to the selection lines (SSLsel, DSLsel) to discharge the selection lines (SSLsel, DSLsel).

The first reference time tref1 may be the time required for the voltage of the selected word line SELWL to reach the pass voltage Vpass.

In various embodiments, either the source select line (SSL) or the drain select line (DSL) can be discharged first without simultaneously discharging the select lines (SSLsel, DSLsel). Alternatively, the semiconductor memory device can discharge the selection lines SSLsel, DSLsel directly in the discharge interval P3 without performing the equalizing operation of changing the voltage of the selected word line SELWL to the pass voltage Vpass have.

The semiconductor memory device may discharge the word lines after the second reference time tref2 has elapsed (t4) after the discharge for select lines has begun. The semiconductor memory device may apply a ground voltage to the selected word line (SELWL) and unselected word lines (UNSELWL) to discharge the word lines.

The second reference time tref2 may be the time at which the selection lines SSLsel, DSLsel are discharged. That is, the time required for the selection transistors SST and DST to turn off.

In various embodiments, the discharge of the word lines may not be started at the same time, but may be sequentially discharged from a farther positioned word line relative to either the source line or the bit line. Alternatively, the plurality of word lines may be divided into at least one or more word line groups, and sequentially discharged from the word line group adjacent to either the source line or the bit line.

Information about the first reference time tref1 and the second reference time tref2 may be stored in the CAM region of the memory cell array. When power is supplied to the semiconductor memory device, information about the first reference time (tref1) and the second reference time (tref2) can be read from the cam area to perform a discharge operation according to the embodiment of FIG.

8 is a flowchart for explaining the operation of the semiconductor memory device according to the embodiment of the present invention.

Referring to FIG. 8, in operation S810, the semiconductor memory device may apply a read voltage Vread to a selected word line and apply a pass voltage Vpass to a non-selected word line. In operation S810, the semiconductor memory device performs a read operation on a plurality of memory cells connected to the selected word line.

In step S820, the semiconductor memory device performs a discharge operation with respect to the word lines and the selection lines. The discharge operation in step S820 will be described in more detail with reference to FIG.

9 is a flowchart showing the discharge operation of FIG.

Referring to FIG. 9, in step S910, the semiconductor memory device may apply the pass voltage Vpass to the selected word line. In step S910, the semiconductor memory device adjusts the voltage level of all the word lines to the pass voltage (Vpass). In various embodiments, the equalizing step of S910 may be omitted. If step S910 is omitted, step S920 may not be performed, and the process may proceed directly to step S930.

In step S920, the semiconductor memory device can determine whether the first reference time has elapsed. The first reference time may be the time at which the voltage of the selected word line of the semiconductor memory device reaches the pass voltage (Vpass).

If it is determined in step S920 that the first reference time has elapsed, the flow advances to step S930.

In step S930, the semiconductor memory device discharges the selection lines. The select lines may be a source select line (SSL) and a drain select line (DSL). The semiconductor memory device may apply a ground voltage to the select lines to discharge the select lines. In various embodiments, one of the source select line (SSL) or the drain select line (DSL) may be discharged first without simultaneously discharging the select lines.

In step S940, the semiconductor memory device can determine whether or not the second reference time has elapsed. The second reference time may be the time at which the selection lines (DSL, SSL) of the memory cell array of the semiconductor memory device are discharged. It may be a time at which the voltage of the selection lines DSL and SSL reaches the ground voltage GND.

If it is determined in step S940 that the second reference time has elapsed, the flow advances to step S950.

In step S950, the semiconductor memory device disposes selected word lines and non-selected word lines.

In various embodiments, the discharging of the word lines in step S950 may not be started at the same time, but may be sequentially discharged from a farther positioned word line based on either the source line or the bit line. Alternatively, the plurality of word lines may be divided into at least one or more word line groups, and sequentially discharged from the word line group adjacent to either the source line or the bit line.

According to an embodiment of the present invention, the select lines may be discharged prior to the word lines during a discharge operation of a read operation or a verify operation. According to an embodiment of the present invention, partial local boosting due to the different program states of the memory cells is prevented, thereby preventing read disturb.

10 is a block diagram showing a memory system including the semiconductor memory device of FIG.

10, memory system 1000 includes a semiconductor memory device 1300 and a controller 1200.

The semiconductor memory device 1300 can be constructed and operated in the same manner as the semiconductor memory device 100 described with reference to FIG. Hereinafter, a duplicate description will be omitted.

The controller 1200 is connected to the host (Host) and the semiconductor memory device 1300. In response to a request from the host (Host), the controller 1200 is configured to access the semiconductor memory device 1300. For example, the controller 1200 is configured to control the read, program, erase, and background operations of the semiconductor memory device 1300. The controller 1200 is configured to provide an interface between the semiconductor memory device 1300 and the host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory device 1300.

The controller 1200 includes a random access memory (RAM) 1210, a processing unit 1220, a host interface 1230, a memory interface 1240, and an error correction block 1250 .

The RAM 1210 is connected to at least one of an operation memory of the processing unit 1220, a cache memory between the semiconductor memory device 1300 and the host and a buffer memory between the semiconductor memory device 1300 and the host .

The processing unit 1220 controls all operations of the controller 1200.

The processing unit 1220 is configured to render data received from a host. For example, the processing unit 1220 may randomize data received from a host using a randomizing seed. The rendered data is provided to the semiconductor memory device 1300 as data to be stored (DATA, see FIG. 1) and is programmed into the memory cell array 110 (see FIG. 1).

The processing unit 1220 is configured to derandomize the data received from the semiconductor memory device 1300 during a read operation. For example, processing unit 1220 will derandomize data received from semiconductor memory device 1300 using a derandomizing seed. The de-randomized data will be output to the host.

As an example, the processing unit 1220 may perform the randomization and de-randomization by driving software or firmware.

The host interface 1230 includes a protocol for performing data exchange between the host (Host) and the controller 1200. As an exemplary embodiment, the controller 1200 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- Various interface protocols such as protocol, Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, IDE (Integrated Drive Electronics) protocol, (Host) via at least one of the following:

The memory interface 1240 interfaces with the semiconductor memory device 1300. For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 1250 is configured to detect and correct errors in data received from the semiconductor memory device 1300 using an error correcting code (ECC).

The controller 1200 and the semiconductor memory device 1300 may be integrated into one semiconductor device. In an exemplary embodiment, the controller 1200 and the semiconductor memory device 1300 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the semiconductor memory device 1300 may be integrated in a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1200 and the semiconductor memory device 1300 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is dramatically improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital image player a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

As an exemplary embodiment, semiconductor memory device 1300 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 1300 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package ), A Wafer-Level Processed Stack Package (WSP), or the like.

FIG. 11 is a block diagram illustrating an example application 2000 of the memory system 1000 of FIG.

11, the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. [ Semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A plurality of semiconductor memory chips are divided into a plurality of groups.

In Fig. 11, the plurality of groups are shown as communicating with the controller 2200 through the first through k-th channels CH1 through CHk, respectively. Each semiconductor memory chip will be configured and operated similarly to one of the semiconductor memory devices 100 described with reference to FIG.

Each group is configured to communicate with the controller 2200 via one common channel. The controller 2200 is configured similarly to the controller 1200 described with reference to Fig. 10 and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

In Fig. 11, it has been described that a plurality of semiconductor memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one semiconductor memory chip is connected to one channel.

12 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG.

12, a computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, (2000).

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 12, the semiconductor memory device 2100 is shown connected to the system bus 3500 through a controller 2200. However, the semiconductor memory device 2100 may be configured to be connected directly to the system bus 3500. [ At this time, the functions of the controller 2200 will be performed by the central processing unit 3100 and the RAM 3200.

In Fig. 12, it is shown that the memory system 2000 described with reference to Fig. 11 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to FIG. As an example, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to Figures 10 and 11. [

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

In the embodiments described above, all of the steps may optionally be performed or omitted. Also, the steps in each embodiment need not occur in order, but may be reversed. It should be understood, however, that the embodiments herein disclosed and illustrated herein are illustrative of specific examples and are not intended to limit the scope of the present disclosure. That is, it will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are feasible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, And is not intended to limit the scope of the invention. It is to be understood by those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: semiconductor memory device
110: memory cell array
120: peripheral circuit
121:
122: voltage generator
123: Read and Write Circuit
124: Data input / output circuit
125: control logic

Claims (20)

A plurality of strings coupled between a bit line and a source line, said plurality of strings including a plurality of memory cells each connected to select transistors and a plurality of word lines, each connected to select lines In an operating method,
Applying a read voltage to a selected word line to which selected memory cells of the plurality of memory cells are connected and applying a pass voltage to unselected word lines to which unselected memory cells are connected;
Reading data stored in the selected memory cells; And
And disabling the select lines prior to the selected word line and unselected word lines. 2. The method of claim 1,
Applying ground voltages to the select lines; And
And applying a ground voltage to the selected word line and the unselected word lines after discharge for the selected lines is completed. 3. The method of claim 2, wherein prior to applying the ground voltages to the select lines,
And applying a pass voltage to the selected word line. 3. The method of claim 2,
A source select line and a drain select line,
Wherein applying the ground voltages to the select lines comprises:
Wherein a ground voltage is first applied to either the source select line or the drain select line. 3. The method of claim 2, wherein applying a ground voltage to the selected word line and the non-
Wherein a ground voltage is sequentially applied from a word line located away from the source line or the bit line. 3. The method of claim 2, wherein applying a ground voltage to the selected word line and the non-
Dividing the plurality of word lines into at least one word line group and sequentially applying a ground voltage from a word line group adjacent to either the source line or the bit line. A plurality of strings coupled between a bit line and a source line, said plurality of strings including a plurality of memory cells each connected to select transistors and a plurality of word lines, each connected to select lines In an operating method,
Applying a pass voltage to selected word lines to which selected memory cells of the plurality of memory cells are connected and unselected word lines to which unselected memory cells are connected;
Discharging the selection lines when a first reference time elapses after applying a pass voltage to the selected word line; And
And discharging the selected word line and the unselected word lines after a second reference time elapses after discharging the selected lines. 8. The method of claim 7,
Wherein the voltage on the selected word line is the time it takes for the voltage on the selected word line to reach the pass voltage. 8. The method of claim 7,
And the voltage of the selection lines is the time required for reaching the ground voltage. 8. The method of claim 7,
A source select line and a drain select line,
The step of discharging the selection lines comprises:
Wherein either the source select line or the drain select line is first discharged. 8. The method of claim 7, wherein discharging the selected word line and unselected word lines comprises:
And sequentially discharging a word line located at a distance from either the source line or the bit line. 8. The method of claim 7, wherein discharging the selected word line and unselected word lines comprises:
Dividing the plurality of word lines into at least one word line group and sequentially discharging the word line group adjacent to either the source line or the bit line. 8. The method of claim 7, wherein the first reference time and the second reference time are time-
(CAM) among the plurality of memory cells. A memory cell array including a plurality of strings coupled between a bit line and a source line, the plurality of strings including a plurality of memory cells each connected to select transistors and a plurality of word lines, each connected to select lines; And
And a peripheral circuit for performing a read operation on selected ones of the plurality of memory cells,
Wherein the peripheral circuit comprises:
And said select lines are discharged earlier than said plurality of word lines in said read operation. 15. The semiconductor memory device according to claim 14,
An address decoder for selecting any one of the plurality of word lines in response to an address received from an external controller;
A voltage generator for generating voltages to be applied to the select lines and the plurality of word lines during the read operation; And
And control logic for controlling the address decoder and the voltage generator in the read operation. 16. The apparatus of claim 15,
A semiconductor device which applies the ground voltages to the selection lines and controls the address decoder and the voltage generator to apply a ground voltage to the selected word line and the unselected word lines after discharge of the selected lines is completed, Memory device. 17. The method of claim 16,
And controls the address decoder and the voltage generator to apply a pass voltage to the plurality of word lines before applying ground voltages to the select lines. 17. The method of claim 16,
A source select line and a drain select line,
The control logic comprises:
And controls the address decoder and the voltage generator to apply a ground voltage first to any one of the source select line and the drain select line. 17. The method of claim 16,
And controls the address decoder and the voltage generator to sequentially apply a ground voltage from a word line located away from the source line or the bit line. 17. The method of claim 16,
The address decoder and the voltage generator are controlled so as to divide the plurality of word lines into at least one word line group and successively apply a ground voltage from a word line group adjacent to either the source line or the bit line Semiconductor memory device.

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