KR20170052029A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to an electronic device, and more specifically, relates to a semiconductor memory device with improved reliability and an operation method thereof. According to the present invention, the semiconductor memory device comprises: a plurality of memory cells connected to a plurality of word lines; and a peripheral circuit applying verification voltage to a word line selected from the plurality of word lines to verify a program state of the plurality of memory cells, and applying a first pass voltage to the unselected word lines while the verification voltage is applied to the selected word line. When a first program state of first to N^th program states divided based on a threshold voltage of the plurality of memory cells is successfully verified, the peripheral circuit applies a second pass voltage to the unselected word lines while the verification voltage is applied to the selected word line.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and an operation method thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM , RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

An embodiment of the present invention is to provide a semiconductor memory device with improved reliability and a method of operation thereof.

As an embodiment of the present invention, an operation method of a semiconductor memory device for programming a plurality of memory cells connected to a selected word line includes the steps of: verifying the program state of the plurality of memory cells by applying a verify voltage to the selected word line Applying a first pass voltage to unselected word lines while a verify voltage is applied to the selected word line, and if the verify is successful, applying a first pass voltage applied to the unselected word lines To a second pass voltage having a level higher than the first pass voltage.

As an embodiment, a method of operating a semiconductor memory device including a plurality of memory cells programmed to have any one of first through N-th program states classified based on a threshold voltage of a memory cell, Applying a program voltage to a selected word line to which cells are connected and verifying a program state of the plurality of memory cells by applying a verify voltage to the selected word line, The first pass voltage is applied to the non-selected word lines while the verify voltage is applied to the non-selected word lines, and when the verification of the first program state is successful, Voltage.

As an embodiment, a semiconductor memory device of the present invention includes a plurality of memory cells connected to a plurality of word lines and a plurality of memory cells connected to a plurality of word lines by applying a verify voltage to a selected one of the plurality of word lines, And applying a first pass voltage to unselected word lines while a verify voltage is applied to the selected word line and applying a first pass voltage to unselected word lines while applying a verify voltage to the selected word line, And a peripheral circuit that applies a second pass voltage to the unselected word lines while the verify voltage is applied to the selected word line if the verify of the first of the states is successful.

As an embodiment, the semiconductor memory device of the present invention is a semiconductor memory device which applies a program voltage to a selected one of a plurality of memory cells and a plurality of word lines coupled to a plurality of word lines, applies a verify voltage to the selected word line And a peripheral circuit for verifying a program state of the plurality of memory cells, wherein the peripheral circuit applies a first pass voltage to unselected word lines while applying a verify voltage to the selected word line, The first pass voltage applied to the unselected word lines is changed to the second pass voltage when the verification of the first one of the first through the N-th program states classified based on the threshold voltages of the non-selected word lines is successful.

According to an embodiment of the present invention, a semiconductor memory device and an operation method thereof having improved reliability are provided.

1 is a block diagram showing a configuration of a memory system.
2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
3 is a view showing the memory cell array structure of FIG.
4 shows another embodiment of the memory cell array of FIG.
5 is a diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.
6 is a flowchart for explaining the operation of the semiconductor memory device according to the embodiment of the present invention.
FIG. 7 is a block diagram showing a memory system including the semiconductor memory device of FIG. 2. FIG.
8 is a block diagram illustrating an application example of the memory system of FIG.
FIG. 9 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 8. FIG.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first and / or second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having", etc., are used to specify that there are described features, numbers, steps, operations, elements, parts or combinations thereof, and that one or more other features, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as ideal or overly formal in the sense of the art unless explicitly defined herein Do not.

In the following description of the embodiments of the present invention, descriptions of techniques which are well known in the technical field of the present invention and are not directly related to the present invention will be omitted. This is for the sake of clarity of the present invention without omitting the unnecessary explanation.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a memory system.

The memory system 50 includes a semiconductor memory device 100 and a controller 200.

The semiconductor memory device 100 may include a memory device such as a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM) such as phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer random access memory (STT-RAM) . In addition, the semiconductor memory device 100 of the present invention can be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory device in which the charge storage layer is made of a conductive floating gate (FG) but also to a charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

The semiconductor memory device 100 includes a memory cell array 110 and peripheral circuits 120 for driving the memory cell array 110. The memory cell array 110 includes a plurality of nonvolatile memory cells.

The memory cell array 110 includes a plurality of memory blocks, and the plurality of memory blocks may be divided into a system block, a user block, and the like depending on the use thereof.

The peripheral circuit (120) operates in response to the control of the controller (200). The peripheral circuit 120 may program the data in the memory cell array 110 in response to the control of the controller 200. [ The peripheral circuit 120 may be operable to read data from the memory cell array 110 and to erase the data in the memory cell array 110.

In various embodiments, the read operation and the program operation of semiconductor memory device 100 may be performed page by page. The erase operation of the semiconductor memory device 100 may be performed on a memory block basis.

In the program operation, the peripheral circuit 120 can receive a command indicating a program operation, a physical block address (PBA) (physical address, PA), and write data from the controller 200. [ The peripheral circuit 120 can program the write data to the selected page when one memory block and one page included in the memory block are selected by the physical block address (PBA).

In a read operation, the peripheral circuit 120 can receive a command (hereinafter referred to as a read command) and a physical block address (PBA) indicating a read operation from the controller 200. The peripheral circuit 120 can read data from one memory block selected by the physical block address (PBA) and one page included therein, and output the read data (hereinafter, page data) to the controller 200 .

In the erase operation, the peripheral circuit 120 can receive the command indicating the erase operation and the physical block address (PBA) from the controller 200. [ The physical block address (PBA) will specify one memory block. The peripheral circuit 120 will erase the data of the memory block corresponding to the physical block address (PBA).

The controller 200 controls the overall operation of the semiconductor memory device 100. The controller 200 can access the semiconductor memory device 100 in response to a request from an external host. The controller 200 commands the semiconductor memory device 100 in response to a request from an external host.

As an embodiment, the controller 200 may control the semiconductor memory device 100 to perform a program operation, a read operation, or an erase operation. In operation of the program, the controller 200 will provide the program command, address, and data to the semiconductor memory device 100 via the channel. In a read operation, the controller 200 will provide a read command and address to the semiconductor memory device 100 via the channel. In the erase operation, the controller 200 will provide the erase command and address to the semiconductor memory device 100 via the channel.

The host interface will include a protocol for performing data exchange between the external host and the controller 200. As an embodiment, the controller 200 may be implemented as a USB (Universal Serial Bus) protocol, an MMC (multimedia card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI- At least one of various interface protocols such as a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, And is configured to communicate with an external host via one.

The controller 200 may include a RAM 210, a memory controller 220, and an error correction circuit 230.

A random access memory (RAM) 210 operates under the control of the memory controller 220 and can be used as a work memory, a buffer memory, a cache memory, and the like. When the RAM 210 is used as a work memory, the data processed by the memory control unit 220 can be temporarily stored. When the RAM 210 is used as a buffer memory, it can be used to buffer data to be transferred from the host (not shown) to the semiconductor memory device 100 or from the semiconductor memory device 100 to the host (not shown).

The memory control unit 220 is configured to control a read operation, a program operation, an erase operation, and a background operation of the semiconductor memory device 100. The memory controller 220 is configured to drive firmware for controlling the semiconductor memory device 100.

The memory controller 220 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through a flash translation layer (FTL). Specifically, the flash translation layer (FTL) receives the logical block address (LBA) using the mapping table and can convert it into the physical block address (PBA). The physical block address may be a page number referring to a specific word line of the memory cell array 110. [ There are various mapping methods for the address in the flash conversion layer, depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

The error correction code circuit 230 generates a parity which is an error correction code (ECC) for the data to be programmed. In addition, during a read operation, the error correction code circuit 230 can correct an error using parity for the read page data. The error correction code circuit 230 includes a low density parity check (LDPC) code, a Bose (Chaudhri) code, a turbo code, a Reed- , Coded modulation such as trellis-coded modulation (TCM), block coded modulation (BCM), and hamming code can be used to correct errors.

In a read operation, the error correction code circuit 230 can correct errors in the read page data. Decode may fail if the read page data contains error bits that exceed the correctable number of bits. If the page data contains error bits equal to or less than the number of correctable bits, the decoding may succeed.

The success of the decode indicates that the read command has been passed. Failure of decode indicates that the read command failed. When the decode is successful, the controller 200 outputs the error-corrected page data to the host.

2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, a semiconductor memory device 100 includes a memory cell array 110 and a peripheral circuit 120.

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 via the row lines RL and to the read and write circuit 123 via the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells.

The plurality of memory cells included in the memory cell array 110 can be used as a plurality of blocks according to the use thereof. Here, the plurality of blocks may be divided into a main block and an extra block, and the other blocks may store various setting information related to the operation of the memory cells.

The first to z-th memory blocks BLK1 to BLKz are commonly connected to the first to m-th bit lines BL1 to BLm. The first to z-th memory blocks BLK1 to BLKz include a plurality of cell strings. The plurality of cell strings are connected to the first to m-th bit lines BL1 to BLm, respectively.

Each of the plurality of cell strings may include a drain select transistor, a plurality of memory cells connected in series, and a source select transistor. The drain select transistor is connected to the drain select line. A plurality of memory cells are connected to a plurality of word lines. The source select transistor is connected to the source select line. And the drain side of the drain select transistor is connected to the corresponding bit line. The drain select transistors of the plurality of cell strings are connected to the first to m-th bit lines BL1 to BLm, respectively. The source side of the source select transistor is connected to a common source line. In an embodiment, the common source lines may be connected in common to the first to z-th memory blocks BLK1 to BLKz.

The drain select line, the plurality of word lines, and the source select line are included in the row lines RL. The drain select line, the plurality of word lines, and the source select line are controlled by the address decoder 121. The common source line is controlled by the control logic 125. The first to m-th bit lines BL1 to BLm are controlled by the read and write circuit 123.

The peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124 and a control logic 125. The address decoder 121 is connected to the memory cell array 110 via the row lines RL. The address decoder 121 is configured to operate in response to control of the control logic 125. The address decoder 121 receives the address ADDR via the control logic 125.

As an embodiment, the program operation and the read operation of the semiconductor memory device 100 are performed page by page. At the time of programming, the address ADDR will include the block address and the row address.

The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects one of the memory blocks BLK1 to BLKz according to the decoded block address.

The address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 applies the voltages supplied from the voltage generator 122 to the row lines RL according to the decoded row address to select one word line of the selected memory block.

In program operation, the address decoder 121 will apply a program pulse to the selected word line and a lower pass pulse to the unselected word lines than the program pulse. During a program verify operation, the address decoder 121 will apply a verify voltage to the selected word line and a verify pass voltage higher than the verify voltage to unselected word lines.

In an embodiment of the present invention, the semiconductor memory device may be operable to change the level of the verify pass voltage according to the verify state of the program. This will be described in more detail in the description of FIGS. 5 and 6 to be described later.

As an embodiment, the erase operation of semiconductor memory device 100 is performed on a memory block basis. In the erase operation, the address ADDR includes a block address. The address decoder 121 decodes the block address and selects one memory block according to the decoded block address.

As an example, the address decoder 121 may include a block decoder, a word line decoder, an address buffer, and the like.

The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the semiconductor memory device 100. Voltage generator 122 operates in response to control of control logic 125.

In an embodiment, the voltage generator 122 may regulate the external supply voltage to generate the internal supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the semiconductor memory device 100.

In an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors to receive an internal supply voltage, and may selectively generate a plurality of voltages by selectively activating a plurality of pumping capacitors in response to control of the control logic 125 . The generated plurality of voltages are applied to the word lines selected by the address decoder 121.

During program operation, the voltage generator 122 will generate a high pass program pulse and a lower pass pulse than the program pulse. In a program verify operation, the voltage generator 130 will generate a verify pass voltage that is higher than the verify voltage and verify voltage.

The read and write circuit 123 includes first through m-th page buffers PB1 through PBm. The first through m-th page buffers PB1 through PBm are connected to the memory cell array 110 through first through m-th bit lines BL1 through BLm, respectively. The first through m-th page buffers PB1 through PBm operate in response to control of the control logic 125. [

The first to m < th > page buffers PB1 to PBm communicate data with the data input / output circuit 124. [ The first to m-th page buffers PB1 to PBm receive data (DATA) to be stored via the data input / output circuit 124 and the data lines DL.

The first to m-th page buffers PB1 to PBm transmit data (DATA) to be stored to the data (DATA) received through the data input / output circuit 124 when a program pulse is applied to the selected word line, To the selected memory cells via bit lines BLl through BLm. The memory cells of the selected page are programmed according to the transferred data (DATA). A memory cell coupled to a bit line to which a program allowable voltage (e.g., ground voltage) is applied will have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which the program inhibit voltage (e.g., power supply voltage) is applied will be maintained. During the program verify operation, the first through m-th page buffers PB1 through PBm read page data from the selected memory cells via the bit lines BL1 through BLm.

In a read operation, the read and write circuit 123 reads data (DATA) from the memory cells of the selected page through the bit lines (BL) and outputs the read data (DATA) to the input / output circuit 124. In the erase operation, the read and write circuit 123 may float the bit lines BL.

As an example, the read and write circuit 123 may include a column select circuit.

The data input / output circuit 124 is connected to the first through m-th page buffers PB1 through PBm through the data lines DL. The data input / output circuit 124 operates in response to control of the control logic 125. At the time of programming, the data input / output circuit 124 receives data (DATA) to be stored from an external controller (not shown).

The control logic 125 is connected to an address decoder 121, a voltage generator 122, a read and write circuit 123 and a data input / output circuit 124. The control logic 125 may control the overall operation of the semiconductor memory device 100. The control logic 125 receives the command CMD and the address ADDR from the external controller. The control logic 125 is configured to control the address decoder 121, the voltage generator 122, the read and write circuit 123 and the data input / output circuit 124 in response to the command CMD. The control logic 125 transfers the address ADDR to the address decoder 121. [

According to the embodiment of the present invention, the peripheral circuit 120 can perform at least one program operation on selected memory cells when a command (CMD) for instructing a program is received. A program voltage (pulse) may be applied to the selected word line during program operation. When the program voltage is applied, the control logic 125 performs at least one verify operation and outputs a state fail signal to the controller or a state pass signal according to the result of the verify operation.

The page data read from the selected memory cells during the verify operation will be temporarily stored in the first to m page buffers PB1 to PBm. The first through m page buffers PB1 through PBm may communicate control results to the control logic 125 in response to control of the control logic 125. [

The semiconductor memory device 100 according to the present invention programs a plurality of memory cells connected to a selected word line. The plurality of memory cells may be programmed into any one of the first to Nth program states PV1 to PVN. Since the program voltage and the verify voltage itself used in the program operation are not characteristic of the present invention, a detailed description thereof will be omitted here. Semiconductor memory device 100 may apply a program voltage and a program verify voltage to the selected word line. At this time, the program pass voltage and the read pass voltage may be applied to the non-selected verify lines, respectively.

In the present invention, the semiconductor memory device 100 can determine the level of the read pass voltage according to the result of the verify operation.

3 is a view showing a structure of the memory cell array 110 of FIG.

Referring to FIG. 3, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. 3, the internal structure of the first memory block BLK1 is shown for the convenience of recognition, and the internal structure of the remaining memory blocks BLK2 to BLKz is omitted. It will be understood that the second to z-th memory blocks BLK2 to BLKz are configured similarly to the first memory block BLK1.

Referring to FIG. 3, the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a U shape. In the first memory block BLK1, m cell strings are arranged in the row direction (i.e., the + X direction). In Figure 3, two cell strings are shown arranged in the column direction (i.e., the + Y direction). However, it will be understood that three or more cell strings may be arranged in the column direction for convenience of explanation.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, And a selection transistor DST.

Each of the select transistors SST and DST and each of the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an example, a pillar for providing a channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. In Fig. 3, the source select transistors of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to the second source select line SSL2.

In another embodiment, the source select transistors of the cell strings CS11 to CS1m, CS21 to CS2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p + 1 to nth memory cells MCp + 1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the direction opposite to the + Z direction, and are connected in series between the source selection transistor SST and the pipe transistor PT. The p + 1 th to nth memory cells MCp + 1 to MCn are sequentially arranged in the + Z direction, and are serially connected between the pipe transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the p + 1 to nth memory cells MCp + 1 to MCn are connected through a pipe transistor PT. The gates of the first to n < th > memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n < th > memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the cell string can be stably controlled. Thus, the reliability of the data stored in the memory block BLK1 is improved.

The gates of the pipe transistors PT of each cell string are connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp + 1 to MCn. The cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

The cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 4, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

Memory cells connected to the same word line within the cell strings arranged in the row direction constitute one page. For example, the memory cells connected to the first word line WL1 of the cell strings CS11 to CS1m in the first row constitute one page. The memory cells connected to the first word line WL1 of the cell strings CS21 to CS2m of the second row constitute another page. The cell strings to be arranged in one row direction will be selected by selecting any one of the drain select lines DSL1 and DSL2. One of the selected cell strings will be selected by selecting any one of the word lines WL1 to WLn.

4 is a view showing another embodiment of the memory cell array 110 of FIG.

Referring to FIG. 4, the memory cell array 110 includes a plurality of memory blocks BLK1 'to BLKz'. In FIG. 4, the internal structure of the first memory block BLK1 'is shown for the convenience of recognition, and the internal structure of the remaining memory blocks BLK2' to BLKz 'is omitted. It will be understood that the second to z-th memory blocks BLK2 'to BLKz' are configured similarly to the first memory block BLK1 '.

The first memory block BLK1 'includes a plurality of cell strings CS11' to CS1m ', CS21' to CS2m '. Each of the plurality of cell strings CS11 'to CS1m', CS21 'to CS2m' extend along the + Z direction. Within the first memory block BLK1 ', m cell strings in the + X direction are arranged. In Figure 4, two cell strings are shown arranged in the + Y direction. However, it will be understood that three or more cell strings may be arranged in the column direction for convenience of explanation.

Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection And a transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11 'to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21 'to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11 'to CS1m', CS21 'to CS2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are connected to the first to the nth word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to n < th > memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the cell string can be stably controlled. Accordingly, the reliability of the data stored in the memory block BLK1 'is improved.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' of the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 'to CS2m' of the second row are connected to the second drain select line DSL2.

As a result, the memory block BLK1 'of FIG. 4 has an equivalent circuit similar to the memory block BLK1 of FIG. 3, except that the pipe transistor PT is excluded in each cell string.

5 is a diagram for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.

During a program operation, the semiconductor memory device repeatedly applies a program voltage and a verify voltage to a selected word line. At this time, the semiconductor memory device can apply the pass voltages to prevent the memory cells connected to the unselected word lines from being programmed. The pass voltages applied by the semiconductor memory device can be divided into a program pass voltage and a read pass voltage. The program pass voltage is the voltage applied to unselected word lines when a program voltage is applied to the selected word line. The read pass voltage is a voltage applied to unselected word lines when a verify voltage is applied to the selected word line.

The program operation of the semiconductor memory device can be performed with an operation in which the program voltage pulse is applied and a verify operation in which the program state is verified. During the program operation, the program pass voltage and the read pass voltage are applied to the unselected word lines. Accordingly, the plurality of memory cells connected to the unselected word lines are continuously supplied with the pass voltages during the program operation. This may cause a pass disturb where the threshold voltage of the memory cells changes.

The memory cells connected to the selected word line may be programmed by the Incremental Step Pulse Programming (ISSP) scheme. The ISPP scheme applies a pulse incremented by a constant step voltage to each repeated program loop. The memory cells connected to the selected word line may have the first program state PV1 to the Nth program state PVN in the target program state, respectively.

While the program operation is being performed, the semiconductor memory device performs verification of each program state, gradually increasing the level of the program voltage applied to the selected word line.

In the present invention, a pass voltage having a relatively low voltage level is applied until the verification of the first program state PV1 is succeeded in order to minimize the stress due to the pass voltage in the verification step of the first program state PV1 And if the verification of the first program state PV1 is successful, the level of the pass voltage is restored to the original state to minimize pass disturbance.

5 shows waveforms of voltage pulses applied to a selected word line (selected) and unselected word lines (unselected).

Referring to FIG. 5, the program operation may be performed through a plurality of program loops (program loops 1 to N). In one program loop, the semiconductor memory device applies the program voltage pulses Vpgm1 to Vpgm (n) to the selected word line (selected), and then applies the respective verify voltages Vvfy1 to Vvfyn ). At the same time, the semiconductor memory device applies the program pass voltage Vpp and the read pass voltage to unselected word lines unselected.

5, it is assumed that the verification of the first program state PV1 in the (N-1) -th program loop (program loop N-1) is successful. The semiconductor memory device can apply the first pass voltage VRP1 to the unselected word lines during the program loop 1 to the program loop N-1 until the verification of the first program state PV1 is successful have.

Specifically, the peripheral circuit of the semiconductor memory device applies the first pass voltage (VRP1) to the unselected word lines while applying the program verify voltages (Vvfy1 to Vvfy (n)) to the selected word line.

If verification of the first program state PV1 is successful in the program loop N-1, the semiconductor memory device supplies the second pass voltage VRP2, which is the read pass voltage applied to the unselected word line in the subsequent program loop, . The second pass voltage VRP2 has a voltage level higher than the first pass voltage VRP1. In various embodiments, the second pass voltage VRP2 has a voltage level that is higher than the first pass voltage VRP1 by the reference voltage Vref. The first pass voltage VRP1 is higher than the threshold voltage of the highest programmed state and is lower than the second pass voltage VRP2 and the reference voltage Vref is higher than the second pass voltage VRP2 and the first pass voltage VRP2, (VRP1).

Specifically, the peripheral circuit of the semiconductor memory device applies the second pass voltage VRP2 to the unselected word lines while applying the program verify voltages Vvfy1 to Vvfy (n) to the selected word line.

When the first pass voltage VRP1 having a voltage level relatively lower than the second pass voltage VRP2 is used, the threshold voltage of the memory cells can be relatively higher because the cell current is lowered. However, if the level of the pass voltage is increased to the second pass voltage after a successful verification operation for the first program state PV1, the threshold voltage of the memory cells which have been read high can be normally read low. Therefore, the program operation can be performed without reducing the threshold voltage distribution while reducing the pass disturbance.

In an embodiment, when the second pass voltage VRP2 and the threshold voltage of the memory cell are in a constant correlation, the verification operation for the subsequent first program state may be omitted.

6 is a flowchart for explaining the operation of the semiconductor memory device according to the embodiment of the present invention.

In step 601, the semiconductor memory device sets the read pass voltage applied to the unselected word lines to the first pass voltage. Specifically, the peripheral circuit of the semiconductor memory device applies the verify voltages to the selected word line and applies the read pass voltage to the unselected word lines. The read path voltage applied here may be the first path voltage.

In step 603, the semiconductor memory device performs a program operation. The program operation can be performed through a plurality of program loops. The program loop includes applying a program voltage to the selected word line and verifying the program state of the memory cells. In the operation of verifying the program state, the verify voltage is applied to the selected word line, the page data is read from the selected page, and the completion of the program is determined with respect to the read data. The program operation is repeated until the verification of both the first program state PV1 to the Nth program state PVN is successful. In operation 603, the semiconductor memory device determines in operation 605 whether the verification of the first program state PV1 is successful. The semiconductor memory device can determine whether verification of the first program state PV1 is successful in the verify operation of each program loop while each program loop is repeated.

As a result of the determination in step 605, if the verification of the first program state PV1 is successful, the semiconductor memory device sets the read pass voltage applied to the unselected word lines to the second pass voltage. The semiconductor memory device applies a second pass voltage to the unselected word lines while applying the verify voltages to the selected word line in subsequent program loops.

FIG. 7 is a block diagram showing a memory system including the semiconductor memory device of FIG. 2. FIG.

7, memory system 1000 includes a semiconductor memory device 1300 and a controller 1200.

The semiconductor memory device 1300 can be constructed and operated in the same manner as the semiconductor memory device 100 described with reference to FIG. Hereinafter, a duplicate description will be omitted.

The controller 1200 is connected to the host (Host) and the semiconductor memory device 1300. In response to a request from the host (Host), the controller 1200 is configured to access the semiconductor memory device 1300. For example, the controller 1200 is configured to control the read, program, erase, and background operations of the semiconductor memory device 1300. The controller 1200 is configured to provide an interface between the semiconductor memory device 1300 and the host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory device 1300.

The controller 1200 includes a random access memory (RAM) 1210, a processing unit 1220, a host interface 1230, a memory interface 1240, and an error correction block 1250 .

The RAM 1210 is connected to at least one of an operation memory of the processing unit 1220, a cache memory between the semiconductor memory device 1300 and the host and a buffer memory between the semiconductor memory device 1300 and the host .

The processing unit 1220 controls all operations of the controller 1200.

The processing unit 1220 is configured to render data received from a host. For example, the processing unit 1220 may randomize data received from a host using a randomizing seed. The rendered data is provided to the semiconductor memory device 1300 as data to be stored (DATA, see FIG. 1) and is programmed into the memory cell array 110 (see FIG. 1).

The processing unit 1220 is configured to derandomize the data received from the semiconductor memory device 1300 during a read operation. For example, processing unit 1220 will derandomize data received from semiconductor memory device 1300 using a derandomizing seed. The de-randomized data will be output to the host.

As an example, the processing unit 1220 may perform the randomization and de-randomization by driving software or firmware.

The host interface 1230 includes a protocol for performing data exchange between the host (Host) and the controller 1200. As an exemplary embodiment, the controller 1200 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- Various interface protocols such as protocol, Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, IDE (Integrated Drive Electronics) protocol, (Host) via at least one of the following:

The memory interface 1240 interfaces with the semiconductor memory device 1300. For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 1250 is configured to detect and correct errors in data received from the semiconductor memory device 1300 using an error correcting code (ECC).

The controller 1200 and the semiconductor memory device 1300 may be integrated into one semiconductor device. In an exemplary embodiment, the controller 1200 and the semiconductor memory device 1300 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the semiconductor memory device 1300 may be integrated in a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1200 and the semiconductor memory device 1300 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is dramatically improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital image player a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

As an exemplary embodiment, semiconductor memory device 1300 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 1300 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package ), A Wafer-Level Processed Stack Package (WSP), or the like.

8 is a block diagram illustrating an example application 2000 of the memory system 1000 of FIG.

8, the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. [ Semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A plurality of semiconductor memory chips are divided into a plurality of groups.

In Fig. 8, the plurality of groups are shown as communicating with the controller 2200 through the first through k-th channels CH1-CHk, respectively. Each semiconductor memory chip will be configured and operated similarly to one of the semiconductor memory devices 100 described with reference to FIG.

Each group is configured to communicate with the controller 2200 via one common channel. The controller 2200 is configured similarly to the controller 1200 described with reference to Fig. 7 and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

In FIG. 8, it has been described that a plurality of semiconductor memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one semiconductor memory chip is connected to one channel.

FIG. 9 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG.

9, a computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, (2000).

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 9, the semiconductor memory device 2100 is shown connected to the system bus 3500 through a controller 2200. However, the semiconductor memory device 2100 may be configured to be connected directly to the system bus 3500. [ At this time, the functions of the controller 2200 will be performed by the central processing unit 3100 and the RAM 3200.

In FIG. 9, it is shown that the memory system 2000 described with reference to FIG. 8 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to Fig. As an example, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to Figs.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

In the embodiments described above, all of the steps may optionally be performed or omitted. Also, the steps in each embodiment need not occur in order, but may be reversed. It should be understood, however, that the embodiments herein disclosed and illustrated herein are illustrative of specific examples and are not intended to limit the scope of the present disclosure. That is, it will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are feasible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, And is not intended to limit the scope of the invention. It is to be understood by those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: semiconductor memory device
110: memory cell array
120: peripheral circuit
121:
122: voltage generator
123: Read and Write Circuit
124: Data input / output circuit
125: control logic

Claims (21)

A method of operating a semiconductor memory device for programming a plurality of memory cells connected to a selected word line,
Applying a verify voltage to the selected word line to verify a program state of the plurality of memory cells;
Applying a first pass voltage to unselected word lines while a verify voltage is applied to the selected word line; And
Changing the first pass voltage applied to the unselected word lines to a second pass voltage having a level higher than the first pass voltage when the verification is successful; Wherein the semiconductor memory device is a semiconductor memory device. 2. The method of claim 1, wherein the step of changing to the second pass voltage comprises:
Wherein when the verification of the first one of the first to Nth program states that is a target program state having a sequentially higher threshold voltage distribution of the plurality of memory cells is successful, And applying a second pass voltage to the unselected word lines. 3. The method of claim 2,
And a voltage level higher than a threshold voltage of the N-th programmed state. The method of claim 1,
And a voltage level higher than the first pass voltage by a reference voltage. 5. The method of claim 4,
Wherein the threshold voltage of the plurality of memory cells is determined based on a threshold voltage of the plurality of memory cells. 3. The method of claim 2, wherein performing the verification comprises:
Determines that the verify is successful if the threshold voltages of the plurality of memory cells exceed the threshold voltage of the target program state among the first to Nth program states and if the threshold voltage of the nth program state is not exceeded And determines that the verification has failed. 1. A method of operating a semiconductor memory device comprising a plurality of memory cells programmed to have any one of a first to an Nth program state, the first to Nth program states being based on a threshold voltage of a memory cell,
Applying a program voltage to a selected word line to which the plurality of memory cells are connected; And
And verifying the program state of the plurality of memory cells by applying a verify voltage to the selected word line,
Wherein the verifying step comprises:
Applying a first pass voltage to unselected word lines while applying a verify voltage to the selected word line,
And changing a first pass voltage applied to the unselected word lines to a second pass voltage when the verification of the first program state is successful. 8. The method of claim 7, wherein the first through N < th >
Sequentially have a high threshold voltage distribution,
The first pass voltage may be a voltage,
And a voltage level higher than a threshold voltage of the N-th programmed state. 8. The method of claim 7,
And a voltage level higher than the first pass voltage by a reference voltage. 10. The method of claim 9,
Wherein the threshold voltage of the plurality of memory cells is determined based on a threshold voltage of the plurality of memory cells. 8. The method of claim 7, wherein performing the verification comprises:
Judges that the threshold voltage of the plurality of memory cells exceeds the threshold voltage of the nth program state among the first to Nth program states, And determines that the verification has failed. A plurality of memory cells coupled to a plurality of word lines; And
A verify voltage is applied to a selected one of the plurality of word lines to verify a program state of the plurality of memory cells and a verify voltage is applied to unselected word lines while a verify voltage is applied to the selected word line When a verify operation of the first one of the first to N-th program states, which are distinguished based on the threshold voltages of the plurality of memory cells, is successful, a verify voltage is applied to the selected word line And a peripheral circuit for applying a second pass voltage to the unselected word lines. 13. The method of claim 12, wherein the first through the N-
Sequentially have a high threshold voltage distribution,
The first pass voltage may be a voltage,
And a voltage level higher than a threshold voltage of the N-th programmed state. 13. The method of claim 12,
And has a voltage level higher than the first pass voltage by a reference voltage. 15. The method of claim 14,
Wherein the threshold voltage is determined based on a threshold voltage of the plurality of memory cells. 13. The semiconductor memory device according to claim 12,
Judges that the threshold voltage of the plurality of memory cells exceeds the threshold voltage of the n < th > program state among the first to N < th > program states, And judges that the verification has failed. A plurality of memory cells coupled to a plurality of word lines; And
And a peripheral circuit that applies a program voltage to a selected one of the plurality of word lines and verifies a program state of the plurality of memory cells by applying a verify voltage to the selected word line,
Wherein the peripheral circuit comprises:
And applies a first pass voltage to unselected word lines while applying a verify voltage to the selected word line and applies a first pass voltage to the first program state among the first to Nth program states The first pass voltage applied to the unselected word lines is changed to the second pass voltage. 18. The method of claim 17, wherein the first through N < th >
Sequentially have a high threshold voltage distribution,
The first pass voltage may be a voltage,
And a voltage level higher than a threshold voltage of the N-th programmed state. 18. The method of claim 17,
And has a voltage level higher than the first pass voltage by a reference voltage. 20. The method of claim 19,
Wherein the threshold voltage is determined based on a threshold voltage of the plurality of memory cells. 20. The method of claim 19,
Judges that the threshold voltage of the plurality of memory cells exceeds the threshold voltage of the n < th > program state among the first to N < th > program states, And judges that the verification has failed.

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