KR20170091983A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device with an improved operating characteristic. The semiconductor device comprises: a substrate including a first and a second region; a first and a second fin-type pattern protruding more than the substrate in the first and the second region; a first and a second gate electrode extended side by side on the first fin-type pattern in a direction crossing the first fin-type pattern, and separated from each other by a first gap; a third and a fourth gate electrode extended side by side on the second fin-type pattern in a direction crossing the second fin-type pattern, and separated from each other by the first gap; a first recess formed on the substrate between the first and the second gate electrode; a second recess which is formed on the substrate between the third and the fourth gate electrode, is shallower than the first recess, and is narrower than the first recess; a first source/drain filling the first recess; and a second source/drain filling the second recess.

Description

[0001]

The present invention relates to a semiconductor device.

As one of scaling techniques for increasing the density of semiconductor devices, there is a scaling technique for forming a fin body or a nanowire-shaped silicon body on a substrate and forming a gate on the surface of the silicon body (multi gate transistors have been proposed.

Since such a multi-gate transistor uses a three-dimensional channel, scaling is easy. Further, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

A problem to be solved by the present invention is to provide a semiconductor device with improved operational characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including first and second regions, first and second fin-shaped patterns protruding from the substrate in the first and second regions, respectively, First and second gate electrodes extending in parallel to each other in a direction crossing the first fin-shaped pattern and spaced apart from each other by a first distance on the first fin-shaped pattern, first and second gate electrodes extending on the second fin- Third and fourth gate electrodes extending parallel to each other in a direction intersecting the pattern and spaced apart from each other by a first distance, a first recess formed in the substrate between the first and second gate electrodes, A second recess formed in the substrate between the fourth gate electrode and the fourth gate electrode, the second recess being shallower than the first recess and narrower than the first recess, a first source / drain filling the first recess, Second cattle to Seth It includes a gas / drain.

The height of the upper surface of the first source / drain and the height of the upper surface of the second source / drain may be different from each other.

The height of the top surface of the first source / drain may be higher than the height of the top surface of the source / drain.

The height of the upper surface of the first source / drain may be lower than the height of the upper surface of the source / drain.

The width of the first and second recesses may become narrower.

The ratio of the width narrowing to the depth of the first recess may be smaller than the ratio of the width narrowing to the depth of the second recess.

The height of the upper surface of the second source / drain may be different from the height of the upper surface of the second fin-shaped pattern.

The upper surface of the second source / drain may include a convex portion.

The upper surface of the second source / drain may include a concave portion.

The lowermost portion of the upper surface of the concave portion may be lower than the upper surface of the second fin-shaped pattern.

The upper surface of the first source / drain may be flush with the upper surface of the first fin-shaped pattern.

The first region may be a PMOS region, and the second region may be an NMOS region.

The first source / drain may include SiGe, and the second source / drain may include Si.

And the second source / drain may include P.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including first and second regions, first and second regions extending in parallel with each other on the first region, Third and fourth gate electrodes extending in parallel to each other on the first region and extending parallel to each other and spaced apart from each other by a first distance, Wherein a width of the first recess is reduced in a depth direction, a second recess formed in the substrate between the third and fourth gate electrodes, and a second recess formed in the substrate, The lower surface of the second recess has a second recess which is gradually reduced in the depth direction, a first source / drain that fills the first recess, a second source / drain that fills the second recess, a second source / drain that fills the first source / The first Wherein a height of a lowermost portion of the first silicide is a first silicide having a first level and a second silicide formed on the second source / drain, and a height of a lowermost portion of the second silicide is different from a height of the second silicide Lt; RTI ID = 0.0 > silicide < / RTI >

A first fin-shaped pattern protruding from the substrate in the first region; and a second fin-shaped pattern protruding from the substrate in the second region, wherein the first and second gate electrodes are formed on the first fin- And the third and fourth gate electrodes may intersect the second fin-shaped pattern on the second fin-shaped pattern.

The first level may be higher than the second level.

The second silicide may include a silicide recess and a step on both sides of the recess.

The first level may be lower than the second level.

The second silicide may include a silicide recess and protrusions on both sides of the recess.

The semiconductor device may further include a first contact formed on the first silicide and a second contact formed on the second silicide.

A first barrier layer surrounding the first contact and in contact with the first silicide, and a second barrier layer surrounding the second contact and in contact with the second silicide.

The first recess may be deeper than the second recess.

The width of the first recess may be wider than the width of the second recess.

Here, a first spacer formed on both sides of the first gate electrode, and a second spacer formed on both sides of the second gate electrode may be further included.

The first source / drain may include a first overlap region overlapping the first spacer.

The second source / drain may not overlap the second spacer.

The second source / drain may include a second overlap region overlapping the second spacer, and the width of the first overlap region may be greater than the width of the second overlap region.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including first and second regions, first and second fin-shaped patterns protruding from the substrate in first and second regions, A first gate electrode crossing the first fin-shaped pattern on the first fin-shaped pattern, a second gate electrode crossing the second fin-shaped pattern on the second fin-shaped pattern, and a second gate electrode crossing the first fin- One source / drains and second source / drains formed on both sides of the second gate electrode, wherein an interval between the first source / drains is smaller than an interval between the second sources / drains.

The first source / drain may be narrower in the depth direction.

And the width of the second source / drain may be reduced toward the depth direction.

The ratio of the width of the first source / drain to the depth of the second source / drain may be different from the ratio of the width of the second source / drain to the depth of the second source / drain.

The ratio of the width of the first source / drain to the depth of the second source / drain may be smaller than the ratio of the width of the second source / drain to the depth of the second source / drain.

A third gate electrode formed in parallel with the first gate electrode in the first region, the first source / drain includes a third gate electrode positioned between the first and third gate electrodes, In the second region, a fourth gate electrode formed in parallel with the second gate electrode, and the second source / drain may further include a fourth gate electrode positioned between the second and fourth gate electrodes .

The spacing between the first and third gate electrodes may be the same as the spacing between the second and fourth gate electrodes.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including first and second regions, first and second fin-shaped patterns protruding from the substrate in first and second regions, A first gate structure crossing the first fin-shaped pattern on a first fin-shaped pattern, the first gate structure comprising a first gate electrode and a first spacer formed on both sides of the first gate electrode, A gate structure, a second gate structure crossing the second fin-shaped pattern on the second fin-shaped pattern, the second gate structure comprising a second gate electrode and a second spacer formed on both sides of the second gate electrode A first overlap region formed on both sides of the first gate structure and overlapping the first spacer, and a second overlapping region formed on both sides of the first overlapping region overlapping the first spacer, And a second non-overlap region formed on both sides of the second gate electrode and overlapping with the second spacer, and a second non-overlap region non-overlapping with the second spacer, And a second source / drain, wherein a width of the first overlap region is different from a width of the second overlap region.

The width of the first overlap region may be greater than the width of the second overlap region.

Wherein the first gate structure comprises a first work function metal and a first fill metal formed on the first work function metal, the second gate structure comprises a second work function metal, And a second fill metal formed on the second metal layer.

The first fill metal and the second fill metal may comprise the same material.

Wherein the first work function metal comprises an N-type work function metal and a P-type work function metal, the second work function metal comprises the N-type work function metal, .

The width of the first source / drain may be greater than the width of the second source / drain.

The depth of the first source / drain may be deeper than the depth of the second source / drain.

The heights of the upper surface of the first source / drain and the upper surface of the second source / drain may be different from each other.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention.
2 is a cross-sectional view taken along line A-A 'and B-B' in Fig.
3 is an enlarged cross-sectional view for explaining the portion J1 in FIG. 2 in detail.
3 is an enlarged cross-sectional view for explaining the portion J2 of FIG. 2 in detail.
5 is a sectional view taken along line C-C 'in Fig.
6 is a cross-sectional view taken along line D-D 'in FIG.
7 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
8 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
9 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
10 is an enlarged cross-sectional view for explaining the portion J3 in Fig. 9 in detail.
11 is an enlarged cross-sectional view for explaining the portion J4 in Fig. 9 in detail.
12 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
13 is an enlarged cross-sectional view showing an enlarged portion J5 in Fig.
Fig. 14 is an enlarged cross-sectional view of the portion J6 in Fig. 12 enlarged.
15 is an enlarged cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
16 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
17 is an enlarged cross-sectional view for explaining the silicide portion of the second region of FIG.
18 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
19 is an enlarged cross-sectional view for explaining the silicide portion of the second region of FIG.
20 is a block diagram of a SoC system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.
21 is a block diagram of an electronic system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle.

Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above" indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, with reference to Figs. 1 to 6, a semiconductor device according to some embodiments of the present invention will be described.

FIG. 1 is a layout view for explaining a semiconductor device according to some embodiments of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A 'and B-B' in FIG. FIG. 3 is an enlarged cross-sectional view for explaining the portion J1 of FIG. 2 in detail, and FIG. 3 is an enlarged cross-sectional view for explaining the portion J2 of FIG. 2 in detail. FIG. 5 is a cross-sectional view taken along line C-C 'of FIG. 1, and FIG. 6 is a cross-sectional view taken along line D-D' of FIG.

1 to 6, a semiconductor device according to some embodiments of the present invention includes a substrate 10, a first fin pattern F1, a second fin pattern F2, first through sixth shallow trenches ST1 The first to third trenches T1 to T3, the first interlayer insulating film 20, the second interlayer insulating film 30, the first gate electrode 200, the second gate electrode 300, And may include a gate electrode 201, a fourth gate electrode 301, gate insulating films 130 and 140, a gate spacer 160, a first source / drain E1, a second source / drain E2, have.

The substrate 10 may be, for example, bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide . Alternatively, the substrate 10 may have an epilayer formed on the base substrate.

The substrate 10 may include a first region I and a second region II. The first region I and the second region II may be adjacent to each other or may be spaced apart from each other. Therefore, the first fin type pattern F1 of the first region I and the second fin type pattern F2 of the second region II may extend in different directions. However, for convenience of explanation, it is assumed that the first fin type pattern F1 of the first region I and the second fin type pattern F2 of the second region II extend in the same direction.

Transistors of different conductivity types may be formed in the first region I and the second region II. For example, the first region I may be a region where a PMOS is formed, and the second region II may be a region where an NMOS is formed, but the present invention is not limited thereto.

The first region I and the second region II may be defined by a first trench T1, a second trench T2 and a third trench T3. The first trenches T1 may have first and second sides facing each other. The first trench T1 may be in contact with the first region I on the first side and the second region II on the second side.

The first region I may comprise a first active region ACT1 and the second region II may comprise a second active region ACT2. The first active area ACT1 and the second active area ACT2 may be adjacent to each other or may be spaced apart from each other.

The second trench T2 can be in contact with the first region I. That is, the first region I may be located between the first trench T1 and the second trench T2. The third trench T3 may be in contact with the second region II. That is, the second region II may be located between the first trench T1 and the second trench T2.

Referring to FIG. 1, the first fin type pattern F1 and the second fin type pattern F2 may be elongated in the first direction X. Although the first pin-type pattern F1 and the second pin-type pattern F2 are shown in a rectangular shape in Fig. 1, the present invention is not limited thereto. If the first and second pinned patterns F1 and F2 are rectangular, the first pinned pattern F1 and the second pinned pattern F2 are parallel to the long side extending in the first direction X, And may include short sides extending in two directions (Y). At this time, the second direction Y may be a direction that is not parallel to the first direction X but intersects with the first direction X.

The first fin type pattern F1 may be plural and the first fin type patterns F1 may be arranged to be spaced apart from each other in the second direction Y. [ The second fin-shaped patterns F2 may be plural and the second fin-shaped patterns F2 may be disposed apart from each other in the second direction Y. [

The plurality of first fin-shaped patterns F1 may be defined by the first to third shallow trenches ST1 to ST3. Further, the plurality of second fin-shaped patterns F2 may be defined by the fourth to sixth shallow trenches ST4 to ST6. That is, in the first region I, the first fin type pattern F1 is defined by the first trench T1, the second trench T2 and the first to third shallow trenches ST1 to ST3, In the region II, the second fin type pattern F2 is defined by the first trench T1, the third trench T3 and the fourth to sixth shallow trenches ST4 to ST6.

The depths of the first to sixth shallow trenches ST1 to ST6 may be shallower than the depths of the first to third trenches T1 to T3. However, the widths of the first to sixth shallow trenches ST1 to ST6 may be narrower than the widths of the first to third trenches T1 to T3. The volume of the first interlayer insulating film 20 formed in the first to third trenches T1 to T3 is equal to the volume of the first interlayer insulating film 20 formed in the first to sixth shallow trenches ST1 to ST6 May be greater than the volume.

The first fin type pattern F1 and the second fin type pattern F2 may be formed by etching a part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. [ The first fin type pattern F1 and the second fin type pattern F2 may include, for example, silicon or germanium, which is an element semiconductor material. In addition, the first fin type pattern F1 and the second fin type pattern F2 may include a compound semiconductor, for example, a IV-IV group compound semiconductor or a III-V group compound semiconductor.

For example, in the case of the IV-IV group compound semiconductor, the first and second fin patterns F1 and F2 may be formed of carbon (C), silicon (Si), germanium (Ge) A binary compound containing at least two or more ternary compounds, or a compound doped with a Group IV element thereon.

The first fin type pattern F1 and the second fin type pattern F2 are group III elements and include at least one of aluminum (Al), gallium (Ga), and indium (In) A ternary compound, a ternary compound or a siliceous compound in which one of phosphorus (P), arsenic (As) and antimony (Sb) is combined and formed.

In the semiconductor device according to the embodiments of the present invention, the first fin type pattern F1 and the second fin type pattern F2 are described as including silicon.

The first interlayer insulating film 20 may fill part of the first through sixth shallow trenches ST1 through ST6 and the first through third trenches T1 through T3. The first interlayer insulating film 20 may surround a part of the side surfaces of the first to eighth fin patterns F1 to F8.

The first interlayer insulating film 20 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material having a lower dielectric constant than silicon oxide. Low dielectric constant materials include, for example, FOX (Flowable Oxide), TONZ Silicon (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), Borophosphosilicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate, Fluoride Silicate Glass, CDO, Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG, Parylene, Bis-benzocyclobutenes, material, or a combination thereof.

The first interlayer insulating film 20 may have a specific stress characteristic. That is, after the first interlayer insulating film 20 is deposited, its volume may be shrunk by heat treatment to have tensile stress characteristics. The inclination of the first to eighth fin-shaped patterns F1 to F8 depending on the volume of the first interlayer insulating film 20 can be determined by the tensile stress characteristic of the first interlayer insulating film 20. [ That is, when the volumes of the first interlayer insulating films 20 located on both sides are different from each other, the larger the difference in the volume, the larger the slope of the fin pattern. This is because the shrinking rate of the large-volume first interlayer insulating film 20 is smaller than the shrinkage rate of the first interlayer insulating film 20 having a small volume.

Specifically, the first fin-shaped pattern F1 directly contacting the first trench T1 and the second trench T2 among the first fin-shaped patterns F1 extends in the direction of the first trench T1 and the second trench T2 . ≪ / RTI >

That is, the first trench T1 of the first fin-shaped pattern F1 and the uprising of the second trench T2 in the direction of the second trench T2, which are in direct contact with the first trench T1 and the second trench T2, The angles are the first angle? 1 and the second angle? 2, respectively.

The second fin type pattern F2 directly contacting the second trench T2 and the third trench T3 of the second fin pattern F2 is tilted in the direction of the second trench T2 and the third trench T3 .

That is, the second trench T2 of the second fin-shaped pattern F2 and the upstanding trench T2 of the third trench T3, which are in direct contact with the second trench T2 and the third trench T3, The angles are the third angle [theta] 3 and the fourth angle [theta] 4, respectively.

The first to fourth angles? 1 to? 4 may be acute angles. That is, the first fin-shaped pattern F1 and the second fin-shaped pattern F2 can be inclined at an acute angle in the direction of the larger trench among the trenches that are in contact with each other.

The first gate electrode 200 and the second gate electrode 300 may extend in parallel with each other. The first gate electrode 200 and the second gate electrode 300 may extend in the second direction Y. The first gate electrode 200 and the second gate electrode 300 may be spaced apart from each other in the first direction X. [ The first gate electrode 200 may be separated from the second gate electrode 300 by a first distance D1.

The third gate electrode 201 and the fourth gate electrode 301 may extend in parallel with each other. The third gate electrode 201 and the fourth gate electrode 301 may extend in the second direction Y. [ The third gate electrode 201 and the fourth gate electrode 301 may be spaced apart from each other in the second direction Y. [ The third gate electrode 201 may be spaced apart from the fourth gate electrode 301 by a first distance D1. That is, the distance in which the two gate electrodes are spaced apart from each other in the first region I and the second region II may be the same.

The first gate electrode 200 and the third gate electrode 201 may extend in the second direction Y. The first gate electrode 200 may intersect each of the first fin-shaped patterns F1. That is, the first gate electrode 200 may include a plurality of first pin-shaped patterns F1 spaced from each other and overlapping each other. The first fin-shaped pattern F1 may include a portion overlapping the first gate electrode 200 and a portion overlapping the first gate electrode 200, respectively.

And the third gate electrode 201 may cross the second fin-shaped pattern F2, respectively. That is, the third gate electrode 201 may include a portion overlapping each of the plurality of second fin-shaped patterns F2 spaced from each other. The second fin pattern F2 may include a portion overlapping the third gate electrode 201 and a portion not overlapping the third gate electrode 201, respectively.

The second gate electrode 300 and the fourth gate electrode 301 may extend in the second direction. The second gate electrode 300 may intersect each of the first fin-shaped patterns F1. That is, the second gate electrode 300 may include a portion overlapping with the plurality of first fin-shaped patterns F1 spaced from each other. The first fin pattern F1 may include a portion overlapping the second gate electrode 300 and a portion not overlapping the second gate electrode 300, respectively.

And the fourth gate electrode 301 may intersect each of the second fin-shaped patterns F2. That is, the fourth gate electrode 301 may include a portion overlapping each of the plurality of second fin-shaped patterns F2 spaced from each other. The second fin-shaped pattern F2 may include a portion overlapping the fourth gate electrode 301 and a portion not overlapping the fourth gate electrode 301, respectively.

The first gate electrode 200 and the third gate electrode 201 may or may not be connected to each other. Similarly, the second gate electrode 300 and the fourth gate electrode 301 may or may not be connected to each other.

Referring to FIGS. 2 and 5, the first gate electrode 200 may include a first work function metal 210 and a first fill metal 220. The first work function metal 210 functions to adjust the work function and the first fill metal 220 functions to fill a space formed by the first work function metal 210. The first work function metal 210 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

The third gate electrode 201 may include a third work function metal 210 and a third fill metal 320. The third work function metal 310 functions to adjust the work function and the third fill metal 320 functions to fill a space formed by the third work function metal 310. The third work function metal 310 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

In some embodiments of the present invention, the first region I may be a PMOS region, so that the first work function metal 210 and the third work function metal 310 may be an N-type work function metal and a P- Lt; / RTI > For example, the first work function metal 210 and the third work function metal 310 may be at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, But is not limited thereto. The first fill metal 220 and the third fill metal 320 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, , But is not limited thereto.

The second gate electrode 201 may include a second work function metal 211 and a second fill metal 221. The second work function metal 211 functions to adjust the work function and the second fill metal 221 functions to fill a space formed by the second work function metal 211. The second work function metal 211 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

The fourth gate electrode 301 may include a fourth work function metal 311 and a fourth fill metal 321. The fourth work function metal 311 controls the work function and the fourth fill metal 321 functions to fill a space formed by the fourth work function metal 311. The fourth work function metal 311 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

In some embodiments of the present invention, the second region II may be an NMOS region, so that the second work function metal 211 and the fourth work function metal 311 may be N-type work function metals. The second work function metal 211 and the fourth work function metal 311 may comprise at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, However, the present invention is not limited thereto. The second fill metal 221 and the fourth fill metal 321 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, , But is not limited thereto.

The first gate electrode 200, the second gate electrode 201, the third gate electrode 201 and the fourth gate electrode 301 may be formed by, for example, a replacement process or a gate last process gate last process, but the present invention is not limited thereto.

The gate insulating films 130 and 140 are formed between the first and second fin patterns F1 and F2 and the first and second gate electrodes 200 and 201 and between the first and second interlayer insulating films 20 and 20, 2 gate electrodes 200 and 201, respectively.

The gate insulating films 130 and 140 are formed between the first fin type pattern F1 and the second fin type pattern F2 and between the third and fourth gate electrodes 300 and 301 and between the first interlayer insulating film 20 and the third And fourth gate electrodes 300 and 301, respectively.

The gate insulating layers 130 and 140 may include an interfacial layer 130 and a high-permittivity layer 140.

The interface film 130 may be formed by oxidizing a part of the first fin type pattern F1 and the second fin type pattern F2. The interface film 130 may be formed along the profile of the first to third pinned patterns F1 to F2 protruding above the upper surface of the first interlayer insulating film 20. [ In the case of the silicon fin type pattern in which the first to third pin patterns F1 to F2 include silicon, the interface film 130 may include a silicon oxide film.

5, the interface film 130 is not formed along the upper surface of the first interlayer insulating film 20. However, the present invention is not limited thereto. Depending on the method of forming the interface film 130, the interface film 130 may be formed along the upper surface of the first interlayer insulating film 20. [

Alternatively, even if the first interlayer insulating film 20 contains silicon oxide, if the physical properties of the silicon oxide included in the first interlayer insulating film 20 and the physical properties of the silicon oxide film included in the interface film 130 are different, The film 130 may be formed along the upper surface of the first interlayer insulating film 20.

The high permittivity film 140 may be formed between the interface film 130 and the first and second gate electrodes 200 and 201 and between the third and fourth gate electrodes 300 and 301. Can be formed along the profile of the first fin type pattern F1 and the second fin type pattern F2 protruding above the upper surface of the first interlayer insulating film 20. [ The high dielectric constant film 140 is formed between the first and second gate electrodes 200 and 201 and the first interlayer insulating film 20 and between the third and fourth gate electrodes 300 and 301 and the first interlayer insulating film 20 As shown in Fig.

The high-permittivity film 140 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. The high-permittivity film 140 may be formed of, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, Zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, And may include at least one of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate But is not limited thereto.

The gate spacers 160 may be disposed on the sidewalls of the first to fourth gate electrodes 200, 201, 300, and 301 extending in the second direction Y. [ Gate spacers 160 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon nitride pellets (SiOCN) and at least one of a combination of the two.

Although the gate spacer 160 is illustratively shown as a single film in the drawing, it may be a multiple spacer in which a plurality of films are stacked. The shape of gate spacer 160 and the shape of each of the multiple spacers forming gate spacer 160 may be I or L or a combination thereof depending on the manufacturing process or application.

2 to 4 and 6, the first source / drain E1 is formed on both sides of the first gate electrode 200 and the second gate electrode 300 in the first direction X, Can be formed on the pattern F1, respectively. The first source / drain E1 may be the source / drain region of each transistor on the first fin pattern F1.

Fig. 2 is a sectional view in the first direction X, and Fig. 6 is a sectional view in the second direction Y. Fig.

Referring to FIG. 2, the first source / drain E1 in the first region I may be formed to fill the first recess F1r formed on the upper surface of the first fin-shaped pattern F1. At this time, since the first gate electrode 200 and the second gate electrode 300 are formed in a portion where the first recess Flr is not formed on the upper surface of the first fin-shaped pattern F1, (E1) may be formed between the first gate electrode 200 and the second gate electrode 300.

The first source / drain E1 may have the same top surface as the first fin-shaped pattern F1. That is, the height of the upper surface of the first source / drain E1 and the height of the upper surface of the first fin-shaped pattern F1 may be the same. The upper surface of the first source / drain E1 may be flat. A part of the upper surface of the first source / drain E1 may overlap with a part of the lower surface of the gate spacer 160.

In the second region II, the second source / drain E2 may be formed to fill the second recess F2r formed on the upper surface of the second fin-shaped pattern F2. At this time, since the third gate electrode 201 and the fourth gate electrode 301 are formed on the upper surface of the second fin pattern F2 where the second recess F2r is not formed, the second source / The second gate electrode E2 may be formed between the third gate electrode 201 and the fourth gate electrode 301.

And the second source / drain E2 may have a top surface higher than the second fin-shaped pattern F2. That is, the height of the upper surface of the second source / drain E2 may be higher than the height of the upper surface of the second fin-shaped pattern F2. The upper surface of the second source / drain E2 may have a convex portion CV.

The convex portion CV of the upper surface of the second source / drain E2 may be formed to be convex from the upper surface of the second fin type pattern F2. The upper surface of the second source / drain E2 may be formed higher than the upper surface of the first source / drain E1.

The second source / drain E2 may be formed on the second fin-shaped pattern F2 on both sides of the third gate electrode 201 and the fourth gate electrode 301 in the first direction X, respectively. And the second source / drain E2 may be the source / drain region of each transistor on the second fin-shaped pattern F2.

The first source / drain E1 and the second source / drain E2 may comprise an epi layer formed by an epitaxial process. Also, the first source / drain E1 and the second source / drain E2 may be an elevated source / drain. The first region I may be a PMOS region and the second region II may be an NMOS region so that the first source / drain E1 may be a SiGe epitaxial layer, for example. The second source / drain E2 may be, for example, an Si epitaxial layer. At this time, the second source / drain E2 may include Si: P doped with P at a high concentration.

The first source / drain E1 may fill the first recess F1r of the first fin-shaped pattern F1. Similarly, the second source / drain E2 may fill the second recess F2r of the second fin-shaped pattern F2. Accordingly, the first source / drain E1 and the second source / drain E2 may have a U-shaped bottom portion along the bottom surface of the recesses Flr and F2r. In some embodiments of the present invention, the first source / drain E1 and the second source / drain E2 are formed in a W-shaped or U-shaped continuous "UU" -type bottom according to the formation of recesses F1r, F2r Lt; / RTI >

The first recess F1r and the second recess F2r may have a U-shaped bottom surface, and accordingly, the width may become narrower toward the depth direction. At this time, the degree of narrowing width depending on the depths of the first recess Flr and the second recess F2r may be different from each other. Specifically, the degree of the width narrowing depending on the depth of the first recess F1r may be smaller than the degree of the width narrowing depending on the depth of the second recess F2r. Thus, the curved surface of the lower surface of the first recess F1r is gentler than the curved surface of the lower surface of the second recess F2r, and the curved surface of the lower surface of the second recess F2r is the curved surface of the lower surface of the first recess F1r It can be steeper than the curved surface of the lower surface.

Likewise, the first source / drain E1 and the second source / drain E2 have a U-shaped bottom along the bottom surface of the recesses F1r and F2r, and the first source / drain E1 and the second source / The width of the second source / drain E2 may become narrower toward the depth direction. In addition, the degree of the width narrowing depending on the depth of the first source / drain E1 may be smaller than the degree of the width narrowing depending on the depth of the second source / drain E2. Thus, the curved surface of the lower surface of the first source / drain E1 is gentler than the curved surface of the lower surface of the second source / drain E2, and the curved surface of the lower surface of the second source / Can be steeper than the curved surface of the lower surface of the base E1.

The first source / drain E1 is formed on both sides of the first gate electrode 200 and the second gate electrode 300, and a region between the first source / drain E1 on both sides of the gate electrode May be used as the first channel region. The length D2 of the first channel region, that is, the distance D2 between the first source / drain E1 may be the same in the first region I. However, since the lower surface of the first source / drain E1 is formed in a U-shape, the gap between the first source / drain E1 can be widened toward the depth direction. That is, the interval D2 between the first source / drain E1 can be a wider interval D2 'at the deeper level.

The second source / drain E2 is formed on both sides of the third gate electrode 201 and the fourth gate electrode 301, and a region between the second source / drain E2 on both sides of the gate electrode Can be used as the second channel region. The length D3 of the second channel region, that is, the distance D3 between the second source / drain E2, may be the same in the second region II. However, since the lower surface of the second source / drain E2 is formed in a U-shape, the distance between the second source / drain E2 can be widened toward the depth direction. That is, the interval D3 between the second source / drain E2 can be a wider interval D3 'at the deeper level.

The width of the first recess F1r may be greater than the width of the second recess F2r. In this case, the "width" may mean the width of the first direction X. That is, the width of the first recessed portion F1r in the first direction X may be greater than the width of the second recessed portion F2r in the first direction X. Therefore, the first recess Flr may be deeper than the second recess F2r, and the first recess Flr may be wider in the first direction X than the second recess F2r. Accordingly, the first source / drain E1 may have a larger volume than the second source / drain E2. The lowermost portion of the lower surface of the first source / drain E1 may be lower than the lowermost portion of the lower surface of the second source / drain E2. The width of the first source / drain E1 in the first direction X may be greater than the width of the second source / drain E2 in the first direction X. [

The distance between the source / drain in the first region I and the second region II, that is, the distance D2 between the first source / drain E1 and the second source / drain E2 D3 may be different from each other. That is, the distance D2 between the first source / drain E1 may be larger than the distance D3 between the second source / drain E2. This is because the distance D1 between the first gate electrode 200 and the second gate electrode 300 in the first direction X and the distance D1 between the third gate electrode 201 and the fourth gate electrode 301 The widths of the first recesses F1r and the second recesses F2r in the first direction X may be different from each other. That is, since the first direction X of the first recess Fl is larger than the width of the second recess F2r in the first direction X, the first region I and the second region II The spacing between the source and the drain may be different from each other.

Referring to FIG. 3, the first source / drain E1 may overlap the gate spacer 160. Specifically, the first source / drain E1 may include an overlap region OR overlapping the gate spacer 160 and a nonoverlap region OR overlapping the gate spacer 160.

The overlap region OR includes a region overlapping the gate spacer 160 formed on the side surface of the first gate electrode 200 and a region overlapping the gate spacer 160 formed on the side surface of the second gate electrode 300 can do. That is, the overlap region OR can be divided into two regions. However, the present invention is not limited thereto. The overlap region OR may exist only in at least one of the two regions.

The non-overlap region OR may be located between the two overlap regions OR. The non-overlap region OR can be formed deeper than the overlap region OR. This may be because the lower surface of the first source / drain E1 is U-shaped.

Referring to FIG. 4, the second source / drain E2 may not overlap the gate spacer 160. Specifically, the second source / drain E2 may not be overlapped with the gate spacer 160, but may be formed to contact the side surface of the gate spacer 160. Accordingly, the gate spacer 160 and the second source / drain E2 may not overlap each other vertically.

The first source / drain E1 of the first region I may overlap the gate spacer 160 while the second source / drain E2 of the second region II may overlap the gate spacer 160. [ As shown in FIG.

Referring to FIG. 6, the outer circumferential surfaces of the first source / drain E1 and the second source / drain E2 may have various shapes. For example, the outer circumferential surfaces of the first source / drain E1 and the second source / drain E2 may be at least one of a diamond shape, a circular shape, and a rectangular shape. In Fig. 6, a diamond shape (or a pentagonal shape or a hexagonal shape) is exemplarily shown.

In the first region I, since the semiconductor device according to the embodiment of the present invention is a PMOS transistor, the first source / drain E1 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. For example, the compressive stress material can increase the mobility of carriers in the channel region by applying compressive stress to the first pinned pattern F1.

In the second region II, when the semiconductor device according to the embodiment of the present invention is an NMOS transistor, the second source / drain E2 may include a tensile stress material. For example, when the second fin type pattern F2 is silicon, the second source / drain E2 may comprise a material having a smaller lattice constant than silicon (e.g., SiC). For example, the tensile stress material may apply tensile stress to the second fin-shaped pattern F2 to improve the mobility of carriers in the channel region.

The first source / drain E1 and the second source / drain E2 of the first region I may have a convex polygonal shape. As shown in FIG. 6, the convex polygon may be pentagonal.

The first source / drain E1 may each have a convex polygonal shape. At this time, the plurality of first source / drain E1 may have the same shape. In this case, "identical" does not mean only completely identical shapes but includes concepts in which the internal angles of the convex polygons are the same.

Also, the first source / drain E1 may be symmetrical with respect to each other. Also, the first source / drain E1 includes a lower region and an upper region formed on the lower region, the width of the lower region being increased as the height is increased, and the width of the upper region Can be narrowed.

The upper region may include a first outer surface and a second outer surface that are symmetrical to each other, and a normal direction of the first and second outer surfaces may be the same in the first source / drain E1.

The plurality of first source / drain E1 may be identical to each other in the inner angle. In some embodiments of the present invention, the interior angle may refer to only three interior angles that do not touch the first pinned pattern F1. That is, the three internal angles of the first source / drain E1 have a constant value depending on the crystal direction.

Since the first region I is a PMOS region, the first source / drain E1 may include SiGe, and the epitaxial growth thereof may be performed in a straight direction in the crystal direction. Therefore, the first source / drain E1 may have the same shape.

Referring to FIG. 6, the second source / drain E2 of the second region II may have a convex polygonal shape. The convex polygon may be pentagonal. At this time, the "convex polygon" does not necessarily mean only a figure having a flat surface other than the cabinet but has a plurality of internal angles which are greatly characterized, and includes a shape connecting the plural internal angles to a curved surface. That is, as shown in Fig. 6, the "convex polygon" in the present specification is characterized by a large angle of the interior, other interior angles, and the plane connecting each interior angle may not be plane.

The second source / drain E2 may have a different shape. Specifically, the internal angles of the second source / drain E2 may be different from each other.

Since the second region II is an NMOS region, the second source / drain E2 may include Si or Si: P, and the epitaxial growth thereof may be performed in a crystal direction unlike the first region I . Accordingly, the plurality of second source / drain E2 may have different shapes.

The second source / drain E2 includes a lower region and an upper region formed on the lower region, and the width of the lower region increases as the height increases, and the width of the upper region increases as the height increases. Can be.

In the second source / drain (E2), the upper region includes a third outer surface and a fourth outer surface that are symmetrical with respect to each other, and the normal direction of the third and fourth outer surfaces includes a third outer surface and a fourth outer surface, can be different.

2 to 4 and 6, the height of the interface at which the first source / drain E1 and the first fin-shaped pattern F1 meet in the first region I is the height of the interface in the second region II 2 can be lower than the height of the interface where the source / drain E2 and the second fin-shaped pattern F2 meet. That is, the lower surface of the first source / drain E1 may be lower than the lower surface of the second source / drain E2.

This is because the recessed depth of the first fin-shaped pattern F1 in the first region I is deeper. Since the first source / drain E1 is formed regularly in the first region I according to the degree of the first recess F1r of the first fin type pattern F1, the first source / (E1) can be determined. That is, the distance from the substrate 10 in the pin-shaped pattern can be narrowed. Accordingly, the deeper the first recess Flr, the wider the width of the upper surface of the recessed pin-shaped pattern. That is, since the entire volume of the first source / drain E1 is formed along the crystal direction, it can be determined according to the width of the upper surface of the exposed fin-shaped pattern.

On the contrary, in the second region II, the shape of the second source / drain E2 is irregular, so that the width of the upper surface of the exposed fin pattern does not affect the volume of the second source / drain E2 . However, the volume of the second source / drain E2 can be determined by how much the second source / drain E2 has grown for as long as the second source / drain E2 has grown. Therefore, unlike the first region (I), it is not necessary to deeply form the recess of the pin-shaped pattern in the second region (II). Therefore, the height of the interface between the fin-shaped pattern and the epitaxial pattern of the first region I may be lower than the height of the interface between the fin-shaped pattern of the second region II and the epitaxial pattern.

The upper surface of the second fin-shaped pattern F2 of the second region II may be higher than the upper surface of the first fin-shaped pattern F1 of the first region I. The width of the upper surface of the second fin type pattern F2 of the second region II may be narrower than the width of the upper surface of the first fin type pattern F1 of the first region I.

Some of the second source / drain E2 of the second region II may be in contact with each other. That is, some of the second source / drain E2 may be merged with each other.

The first source / drain E1 of the first region I may not be in contact with each other and may be spaced apart from each other. On the other hand, at least one of the second source / drain E2 may be in contact with each other. This is because the width of the second source / drain E2 of the second region II is larger than that of the first source / drain E1 of the first region I.

The semiconductor device according to some embodiments of the present invention may be formed with an air gap G as portions of the second source / drain E2 contact with each other in the second region II.

The air gap G may be formed between the two second sources / drains E2 that are in contact with each other. The air gap G may be formed on the first interlayer insulating film 20. The air gap G can be covered with two second source / drain E2 that are in contact with each other.

The semiconductor device according to some embodiments of the present invention may be applied to a nano-sheet, a multi-bridged channel (MBC), and a 3-5 group semiconductor device other than the above- Drain may be applied.

Hereinafter, a semiconductor device according to some embodiments of the present invention will be described with reference to FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

7 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. 7 is a cross-sectional view corresponding to a cross-sectional view taken along line A-A 'and B-B' in FIG.

Referring to FIG. 7, the upper surface of the second source / drain E2 of the second region II may be flat. That is, the distance between the gate electrodes of the first region I and the second region II, that is, the distance between the first gate electrode 200 and the second gate electrode 300, The shape of the top surface of the second source / drain E2 of the second region II may be changed according to the distance between the first gate electrode 301 and the fourth gate electrode 301.

At this time, the distance between the gate electrodes of the first region I and the second region II, that is, the distance D1 'between the first gate electrode 200 and the second gate electrode 300, The intervals D1 'between the gate electrode 201 and the fourth gate electrode 301 may be equal to each other. The distance between the gate electrodes of the first region I and the second region II, that is, the distance D1 'between the first gate electrode 200 and the second gate electrode 300, 201 and the fourth gate electrode 301 may be larger than the interval (D1 in FIG. 2) of FIG. 2 described above.

Hereinafter, with reference to FIG. 8, another region of the semiconductor device according to some embodiments of the present invention will be described. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

8 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. 8 is a cross-sectional view corresponding to a cross-sectional view taken along line A-A 'and B-B' in FIG.

Referring to FIG. 8, the upper surface of the second source / drain E2 of the second region II may include a recessed portion. That is, the distance between the gate electrodes of the first region I and the second region II, that is, the distance between the first gate electrode 200 and the second gate electrode 300, The shape of the top surface of the second source / drain E2 of the second region II may be changed according to the distance between the first gate electrode 301 and the fourth gate electrode 301.

At this time, the distance between the gate electrodes of the first region I and the second region II, that is, the distance D1 '' between the first gate electrode 200 and the second gate electrode 300, The intervals D1 '' between the third gate electrode 201 and the fourth gate electrode 301 may be equal to each other. The distance between the gate electrodes of the first region I and the second region II, that is, the distance D1 '' between the first gate electrode 200 and the second gate electrode 300, The interval D1 '' between the first gate electrode 201 and the fourth gate electrode 301 may be larger than the interval (D1 in FIG. 2) and the interval in FIG. 7 (D1 'in FIG.

That is, the shape of the upper surface of the second source / drain E2 gradually changes from the shape including the convex portion to the shape including the concave portion through the flat shape while the distance between the gates gradually increases. However, the present invention is not limited thereto.

In addition, as the spacing D1 '' between the gates increases, the shape of the bottom surface of the first recess Flr and the second recess F2r may also vary. That is, the lower surfaces of the first recesses F1r and the second recesses F2r may have a U shape instead of a U shape, or a U shape or a U shape.

Hereinafter, other regions of the semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 9 to 11. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

FIG. 9 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention, and FIG. 10 is an enlarged cross-sectional view for explaining the portion J3 of FIG. 9 in detail. 11 is an enlarged cross-sectional view for explaining the portion J4 in Fig. 9 in detail.

9-11, the second source / drain E2 of the second region II of the semiconductor device according to some embodiments of the present invention may overlap the gate spacer 160. Referring to FIG.

10, the first source / drain E1 includes a first overlap region OR1 that overlaps with the gate spacer 160 and a second overlap region OR1 that overlaps with the gate spacer 160 in the first non- NOR1).

The first overlap region OR1 has a region overlapping with the gate spacer 160 formed on the side surface of the first gate electrode 200 and a region overlapping with the gate spacer 160 formed on the side surface of the second gate electrode 300. [ . ≪ / RTI > That is, the first overlap region OR1 can be divided into two regions. However, the present invention is not limited thereto. The first overlap region OR1 may include only at least one of the two regions.

The first non-overlap region NOR1 may be located between the two first overlap regions OR1. The first non-overlap region NOR1 may be formed deeper than the overlap region OR. This may be because the lower surface of the first source / drain E1 is U-shaped.

11, the second source / drain E2 includes a second overlap region OR2 that overlaps with the gate spacer 160 and a second overlapping region OR2 that does not overlap with the gate spacer 160. In other words, NOR2).

The second overlap region OR2 has a region overlapping with the gate spacer 160 formed on the side surface of the first gate electrode 200 and a region overlapping with the gate spacer 160 formed on the side surface of the second gate electrode 300. [ . ≪ / RTI > That is, the second overlap region OR2 can be divided into two regions. However, the present invention is not limited thereto. The second overlap region OR2 may include at least one of the two regions.

The second non-overlap region NOR2 may be located between the two second overlap regions OR2. The second nonoverlap region NOR2 can be formed deeper than the second overlap region OR2. This may be because the lower surface of the first source / drain E1 is U-shaped.

The width D4 of the first direction X of the first overlap region OR1 of the first region I is greater than the width D2 of the first overlap region OR2 of the second region II (D5). That is, since the width of the first recess F1r in which the first source / drain E1 is formed is larger than the width of the second recess F2r in which the second source / drain E2 is formed, / Drain E1 overlap with gate spacer 160 may be greater than the thickness of second source / drain E2 overlap with gate spacer 160. [

Hereinafter, other regions of the semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 12 to 14. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

FIG. 12 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention, and FIG. 13 is an enlarged cross-sectional view of an enlarged portion J5 in FIG. Fig. 14 is an enlarged cross-sectional view of the portion J6 in Fig. 12 enlarged. FIG. 14 is an enlarged view of the second silicide S2 of FIG. 12, and for simplicity, the second contact C2 and the second barrier layer L2 are omitted.

12 to 14, a semiconductor device according to some embodiments of the present invention includes a capping layer 150, a first silicide layer 160 formed on a first source / drain E1 and a second source / (S1) and a second silicide (S2).

The capping layer 150 may be formed on the high-permittivity layer 140 and the first gate electrode 200. The capping layer 150 may comprise, for example, SiN. The capping layer 150 may contact the inner wall of the gate spacer 160. The top surface of the capping layer 150 may be at the same level as the top surface of the gate spacer 160, but is not limited thereto. The upper surface of the capping layer 150 may be higher than the upper surface of the gate spacer 160.

The first and second silicides S1 and S2 may be formed on the first source / drain E1 and the second source / drain E2. The silicide may be formed by partially deforming the first source / drain E1 and the second source / drain E2. The silicide may comprise a metal. The metal may include at least one of Ni, Co, Pt, Ti, W, Hf, Yb, Tb, Dy, Er, Pd and their alloys.

The contact holes ch1 and ch2 penetrate the second interlayer insulating film 30 and the third interlayer insulating film 40 and expose at least a part of the first and second silicides S1 and S2. The barrier layers L1 and L2 are conformally formed along the side surfaces and the bottom surfaces of the contact holes ch1 and ch2 and the contacts C1 and C2 are formed on the barrier layers L1 and L2 with the contact holes ch1 and ch2 As shown in Fig.

The first source / drain E1 and the second source / drain E2 protrude from the surface of the substrate 10, that is, the surfaces of the first fin type pattern F1 and the second fin type pattern F2, And may include protrusions surrounding both sides of the second silicide (S1, S2).

As shown, the protrusions may be of a shape that becomes narrower as the distance from the surface of the substrate 10 becomes smaller.

In addition, the protrusions may have a shape that covers at least 1/2 of the vertical length of the first and second silicides S1 and S2. In the figure, protrusions are shown in the form of wrapping the entire side surfaces of the first and second silicides S1 and S2, but are not limited thereto.

The first and second silicides S1 and S2 may not be formed on at least a part of the surfaces of the first source / drain E1 and the second source / drain E2. 12, in the region between the first and second silicides S1 and S2 and the first to fourth gate electrodes 200, 201, 300, and 301, / Drain E1 and the surface of the second source / drain E2.

The first and second silicides S1 and S2 may be a reversed cone type, as shown. Therefore, the narrow tip region can be located downward (toward the substrate 10), and the bottom surface can be positioned upward (opposite to the substrate 10). Further, since the first and second silicides S1 and S2 are narrow in the lower part and widened in the upward direction, the side faces can be inclined at a predetermined angle?. The predetermined angle may be, for example, 30 DEG to 70 DEG, but is not limited thereto. More specifically, the predetermined angle may be 40 ° or more and 60 °, but is not limited thereto.

In addition, the tip regions of the first and second silicides S1 and S2 may be positioned higher than the surface of the substrate 10. [ By doing so, the channel length of the transistor can be sufficiently secured, and the operation characteristics of the transistor can be enhanced.

The first silicide S1 may be formed on the first source / drain E1. Accordingly, the upper surface of the first silicide S1 can be flat. However, a recess may be formed by the portion where the first contact C1 and the first barrier layer L1 are formed in the first silicide S1. That is, the upper surface of the first silicide S1 can be flattened by the first source / drain E1, except for the portion where the first contact C1 and the first barrier layer L1 are formed.

The first contact hole ch1 may be formed in a part of the upper portion of the first silicide S1. That is, a recess may be formed in a part of the upper portion of the first silicide S1. The recess may be semicircular as shown. However, the present invention is not limited to this, and may be a square or another shape.

And the second silicide S2 may be formed on the second source / drain E2. Thus, the upper surface of the second silicide S2 can be convex upward. However, a recess may be formed by the portion where the second contact C2 and the second barrier layer L2 are formed in the second silicide S2. That is, the upper surface of the second silicide S2 except the portion where the second contact C2 and the second barrier layer L2 are formed can be convexed upward by the second source / drain E2.

And the second contact hole ch2 may be formed in a part of the upper portion of the second silicide S2. That is, a recess may be formed in a part of the upper portion of the second silicide S2. The recess may be semicircular in shape as shown. However, the present invention is not limited thereto.

Referring to FIG. 14, the second silicide S2 in the second region II may include a first silicide recess R1, a third convex portion CV3, and a fourth convex portion CV4 . Since the upper surface of the second source / drain E2 is convex upward, the upper surface of the second silicide S2, except for the first silicide recess R1, may be convex upward.

The first silicide recess R1 may be a portion where the second contact hole ch2 is formed. That is, the first silicide recess R1 may be a position where the second barrier layer L2 and the second contact C2 are formed.

That is, the third convex portion CV3 and the fourth convex portion CV4 may be formed on both sides of the first silicide recess R1. The third convex portion CV3 and the fourth convex portion CV4 can be formed by forming the first silicide recess R1 as the upper surface of the second source / drain E2 is convex.

Hereinafter, other regions of the semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 12 and 15. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

15 is an enlarged cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention. FIG. 15 is an enlarged view for explaining another embodiment only at J5 in FIG.

Referring to FIGS. 12 and 15, the first silicide S1-2 may be formed on the first source / drain E1. The first silicide S1-2 may be formed by converting the upper portion of the first source / drain E1. The lower portion of the first silicide S1-2 may be U-shaped. However, the present invention is not limited thereto, and may be various shapes depending on the process of silicidation. A first contact hole ch1-2 may be formed on the first silicide S1-2. The first contact holes ch1-2 may pass through the second interlayer insulating film 30 and may expose the upper surface of the first silicide S1-2.

The upper surface of the first silicide S1-2 may not be recessed by the first contact holes ch1-2. Therefore, the upper surface of the first silicide S1-2 may be formed flat. The first barrier layer L1-2 and the first contact C1-2 are electrically connected to the first silicide S1-2 and the second contact layer C1-2 by contacting the first contact hole ch1-2 with the first silicide S1-2. . Thus, the upper surface of the first silicide S1-2 can maintain a flat shape.

Hereinafter, another region of the semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 16 and 17. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

FIG. 16 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and FIG. 17 is an enlarged cross-sectional view illustrating a silicide portion of the second region of FIG. FIG. 17 is an enlarged view of the second silicide S2 of FIG. 16, and for convenience of illustration, the second contact C2 and the second barrier layer L2 are omitted.

16 and 17, the second source / drain E2 of the semiconductor device according to some embodiments of the present invention overlaps with the gate spacer 160 and may include a flat top surface.

That is, the second silicide S2 in the second region II may include the second silicide recess R2. Since the upper surface of the second source / drain E2 is formed flat, the upper surface of the second silicide S2, except for the second silicide recess R2, may be flat.

The second silicide recess R2 may be a portion where the second contact hole ch2 is formed. That is, the second silicide recess R2 may be a position where the second barrier layer L2 and the second contact C2 are formed.

Hereinafter, other regions of the semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 18 and 19. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted. FIG. 19 is an enlarged view of the second silicide S2 of FIG. 18, and for convenience, the second contact C2 and the second barrier layer L2 are omitted.

FIG. 18 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and FIG. 19 is an enlarged cross-sectional view illustrating a silicide portion of the second region of FIG.

18 and 19, the second silicide S2 in the second region II may include a third silicide recess R3 and two steps ST. Since the upper surface of the second source / drain E2 is convex downward, the upper surface of the second silicide S2 including the third silicide recess R3 may be convex downward.

The third silicide recess R3 may be a portion where the second contact hole ch2 is formed. That is, the third silicide recess R3 may be a position where the second barrier layer L2 and the second contact C2 are formed.

That is, the step ST may be formed on both sides of the third silicide recess R3. The step ST may be a part where the inclination is changed abruptly by the third chamber side recess R3. That is, the upper surface of the second source / drain E2 may be convex downward, but the step ST of the third silicide recess R3 may be formed so that the slope of the third silicide recess R3 becomes more sharply downward. However, the present invention is not limited thereto, and the second contact C2 and the second barrier layer L2 may be formed without any recesses.

20 is a block diagram of a SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 20, the SoC system 1000 includes an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC system 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a bus 1030 may have a multi-layer structure. For example, the bus 1030 may be a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI). However, the present invention is not limited thereto.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the elements of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

21 is a block diagram of an electronic system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.

21, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver.

Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an SRAM.

The semiconductor device according to the embodiments of the present invention described above may be provided in the storage device 1130 or may be provided as a part of the controller 1110, the input / output device 1120, the I / O, and the like.

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: substrate F1: first pinned pattern
F2: first fin type pattern 200: first gate electrode
201: third gate electrode 300: second gate electrode
301: fourth gate electrode E1: first source / drain
E2: Second source / drain

Claims (20)

A substrate comprising first and second regions;
First and second fin-shaped patterns protruding from the substrate in the first and second regions, respectively;
First and second gate electrodes extending parallel to each other in a direction crossing the first fin-shaped pattern and spaced apart from each other by a first distance;
Third and fourth gate electrodes extending on the second fin-shaped pattern in parallel with each other in a direction crossing the second fin-shaped pattern and spaced apart from each other by a first distance;
A first recess formed in the substrate between the first and second gate electrodes;
A second recess formed in the substrate between the third and fourth gate electrodes, the second recess being shallower than the first recess and narrower than the first recess;
A first source / drain to fill the first recess; And
And a second source / drain that fills the second recess. The method according to claim 1,
Wherein a height of an upper surface of the first source / drain and a height of an upper surface of the second source / drain are different from each other. The method according to claim 1,
And the width of the first and second recesses becomes narrower as they are deepened. The method of claim 3,
Wherein the ratio of the width narrowing to the depth of the first recess is smaller than the ratio of the width narrowing to the depth of the second recess. The method according to claim 1,
And the height of the upper surface of the second source / drain is different from the height of the upper surface of the second fin-shaped pattern. 6. The method of claim 5,
And an upper surface of the second source / drain includes a convex portion. 6. The method of claim 5,
And the upper surface of the first source / drain is flush with the upper surface of the first fin-shaped pattern. The method according to claim 1,
Wherein the first region is a PMOS region and the second region is an NMOS region. A substrate comprising first and second regions;
First and second gate electrodes extending parallel to each other on the first region and spaced apart from each other by a first distance;
Third and fourth gate electrodes extending parallel to each other on the first region and extending in parallel to each other and spaced apart from each other by a first distance;
A first recess formed in the substrate between the first and second gate electrodes, the width of the first recess decreasing in the depth direction;
A second recess formed in the substrate between the third and fourth gate electrodes, the lower surface of the second recess being reduced in depth direction;
A first source / drain to fill the first recess;
A second source / drain to fill the second recess;
A first silicide formed on the first source / drain, the lowermost height of the first silicide being a first level; And
And a second silicide formed on the second source / drain, wherein a height of a lowermost portion of the second silicide is a second level different from the first level. 10. The method of claim 9,
A first fin-shaped pattern protruding from the substrate in the first region;
And a second fin-shaped pattern protruding from the substrate in the second region,
The first and second gate electrodes crossing the first fin-shaped pattern on the first fin-shaped pattern,
And the third and fourth gate electrodes cross the second fin-shaped pattern on the second fin-shaped pattern. 10. The method of claim 9,
Wherein the first level is higher than the second level. 12. The method of claim 11,
Wherein the second silicide includes a silicide recess and a step on both sides of the recess. 10. The method of claim 9,
Wherein the first level is lower than the second level. 14. The method of claim 13,
Wherein the second silicide includes a silicide recess and protrusions on both sides of the recess. 10. The method of claim 9,
A first contact formed on the first silicide,
And a second contact formed on the second silicide. 16. The method of claim 15,
A first barrier layer surrounding the first contact and in contact with the first silicide,
And a second barrier layer surrounding the second contact and in contact with the second silicide. 10. The method of claim 9,
Wherein the first recess is deeper than the second recess. 10. The method of claim 9,
A first spacer formed on both sides of the first gate electrode,
And a second spacer formed on both sides of the second gate electrode. 19. The method of claim 18,
And the first source / drain includes a first overlap region overlapping with the first spacer. A substrate comprising first and second regions;
First and second fin-shaped patterns protruding from the substrate in the first and second regions, respectively;
A first gate electrode crossing the first fin-shaped pattern on the first fin-shaped pattern;
A second gate electrode crossing the second fin-shaped pattern on the second fin-shaped pattern;
First source / drains formed on both sides of the first gate electrode; And
And second source / drains formed on both sides of the second gate electrode,
And an interval between the first source / drains is smaller than an interval between the second sources / drains.

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