KR20170089742A - LDO regulator including dual loop circuit, and application processor and user device including the same - Google Patents

Abstract

According to an embodiment of the present invention, an LDO regulator comprises: a course loop block, a fine loop block, and a digital control block. The course loop block generates a course code by receiving input voltage from an output terminal; and controls course current to be provided to the output terminal depending on the course code. The fine loop block generates a fine code by receiving the input voltage from the output terminal; and controls fine current to be provided to the output terminal depending on the fine code. The digital control block receives the course code from the course loop block; and generates a control signal for controlling the fine loop block. The LDO regulator according to an embodiment of the present invention controls output voltage (Vout) within a large voltage range by using the course loop circuit; and finely controls the output voltage (Vout) by using the fine loop circuit. The LDO regulator according to an embodiment of the present invention rapidly and accurately controls the output voltage (Vout).

Description

[0001] The present invention relates to an LDO regulator including a dual-loop circuit and an application processor including the LDO regulator and a user equipment (including an LDO regulator including a dual loop circuit,

The present invention relates to a voltage regulator, and more particularly, to an LDO regulator including a coarse loop circuit and a fine loop circuit.

A voltage regulator is used to provide a constant voltage to the circuit. Voltage regulators can be roughly divided into linear regulators and switching regulators, depending on how the voltage is regulated. The switching regulator has a drawback in that the efficiency is good, but the noise characteristic is poor. On the other hand, linear regulators have the advantage of lowering the efficiency but having better noise characteristics. Since the linear regulator has good noise characteristics, it can supply precise and stable voltage.

The LDO regulator (low drop-out regulator) is a kind of linear regulator. LDO regulators are used to reliably power various electronic devices. For example, LDO regulators can be used in power management integrated circuits (PMICs) in mobile devices such as smart phones and tablet PCs.

On the other hand, a power management integrated circuit (PMIC) of a mobile device can provide various power supply voltages to a semiconductor circuit such as an application processor (AP) or a memory by using an LDO regulator. Conventional power management integrated circuits (PMICs) provide various power supply voltages through various power supply lines. When multiple power lines are used between a power management integrated circuit (PMIC) and a semiconductor circuit, there is a problem that the required voltage can not be stably provided due to parasitic resistance or parasitic inductance.

It is an object of the present invention to provide an LDO regulator capable of stably supplying a voltage to a semiconductor circuit, and an application processor and a user apparatus including the LDO regulator.

It is another object of the present invention to provide an LDO regulator capable of quickly and finely adjusting an output voltage, and an application processor and a user apparatus including the LDO regulator.

An LDO regulator according to an embodiment of the present invention includes a coarse block, a fine loop block, and a digital control block. The course loop block adjusts the course current provided to the output terminal in accordance with the course code, which is supplied with an input voltage from an output terminal and generates a course code. The fine loop block receives an input voltage from the output terminal, generates a fine code, and adjusts the fine current provided to the output terminal according to the fine code. The digital control block receives the course code from the cosine loop block and generates a control signal for controlling the fine loop block.

In one embodiment, the course loop block includes a reference voltage converter for receiving the course code and changing a course reference voltage, an analog digital converter (ADC) for receiving the input voltage and the course reference voltage and generating the course code, And a course current driver for receiving the course code from the ADC and providing the course current.

As an example, the ADC may be a current mirror flash analog-to-digital converter (CMF ADC). Wherein the CMF ADC receives the input voltage and forms a second current path, the sum of the currents in the first and second current paths being a current source A first current mirror circuit for forming a third current path by current mirroring the first current path, and a second current mirror circuit for current mirroring the second current path, And a second current mirror circuit that forms N (N is a natural number of 5 or more) current path.

As an embodiment, the fine loop block may include a comparator that compares the input voltage with a reference voltage and outputs a selection signal as a comparison result, and a comparator that operates in response to a control signal of the digital control block, A shift register for outputting a fine code by performing a shift operation to the left or right, and a fine current driver for receiving the fine code and providing the fine current.

In one embodiment, the digital control block includes a fine loop controller for receiving the course code and outputting an enable signal for operating the shift register and a reset signal for resetting the shift register, and a shift register And an initial fine current selector for outputting an initial signal for adjusting the initial fine current.

An application processor according to an embodiment of the present invention includes an LDO regulator for controlling a course current according to a course code, controlling a fine code using the course code, and controlling a fine current according to the fine code, And a load circuit supplied with the course current and the fine current.

As an embodiment, the LDO regulator includes: a course loop circuit that adjusts a course current provided to the output terminal in accordance with the course code, the input circuit receiving an input voltage from the output terminal and generating the course code; A fine loop circuit for adjusting the fine current provided to the output terminal in accordance with the fine code and for receiving the course code from the course loop circuit and for controlling the fine loop circuit, And a digital controller for generating a control signal for the control signal.

A user equipment according to an embodiment of the present invention includes an application processor including a power management integrated circuit that provides a power source voltage through a power source line and an LDO regulator that receives a power source voltage through the power source line and generates an internal power source . The LDO regulator includes: a coarse loop circuit that receives an input voltage from an output terminal and generates a course code; a course loop circuit that adjusts a course current provided to the output terminal according to the course code; A fine loop circuit for generating a code for adjusting the fine current to be provided to the output terminal in accordance with the fine code and a control circuit for receiving the course code from the course loop circuit and generating a control signal for controlling the fine loop circuit do.

The LDO regulator according to the embodiment of the present invention can adjust the output voltage Vout in a large voltage range using a coarse loop circuit and finely adjust the output voltage Vout in a small voltage range using a fine loop circuit . According to the LDO regulator according to the embodiment of the present invention, the output voltage Vout can be adjusted quickly and accurately.

1 is a block diagram illustrating a typical user device.
2 is a block diagram illustrating a user device in accordance with an embodiment of the present invention.
3 is a block diagram illustrating an exemplary first LDO regulator shown in FIG.
4 is a block diagram showing another embodiment of the first LDO regulator shown in FIG.
FIG. 5 is a circuit diagram illustrating an exemplary analog-to-digital converter (ADC) shown in FIG.
FIG. 6 is a circuit diagram showing another embodiment of the analog-to-digital converter (ADC) shown in FIG.
FIG. 7 is a circuit diagram showing another embodiment of the analog-to-digital converter (ADC) shown in FIG.
FIG. 8 is a diagram for illustrating the CMF ADC shown in FIG. 7 by way of example.
FIG. 9 is a diagram for explaining an operation method of the shift register shown in FIG. 4 as an example.
FIG. 10 is a block diagram illustrating an exemplary digital controller shown in FIG.
11 is a block diagram exemplarily showing the fifth control unit shown in FIG.
12 is a timing chart for explaining the operation of the loop controller which is the enable waveform shown in Fig.
13 is a timing chart for explaining the operation of the initial fine current selector shown in FIG.
FIG. 14 is a block diagram and timing diagram for explaining an operation method of the first LDO regulator shown in FIG. 2. FIG.
15 is a flowchart illustrating an exemplary operation of the LDO regulator according to the embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

1 is a block diagram illustrating a typical user device. Referring to FIG. 1, a user device 10 includes a power management integrated circuit (PMIC) 11 and an application processor 12. User device 10 includes high-end mobile devices such as smart phones, tablet PCs, and the like. The performance of the advanced mobile device may depend on the application processor 12. Accordingly, the application processor 12 used in the mobile device is rapidly developing. In order to achieve better performance in a smaller area, the process of the application processor 12 becomes finer and the design becomes complicated.

The application processor 12 requires several levels of power supply voltage to drive various internal circuits. These power supply voltages can be supplied by the power management integrated circuit (PMIC) 11. 1, the power management integrated circuit 11 may provide various power supply voltages such as 0.8V, 0.9V, 1.1V and 1.8V to the application processor 12 through various power supply lines .

Referring to FIG. 1, the application processor 12 is connected to the power management integrated circuit 11 through a power supply line. The current I flows through the power supply line and the parasitic resistances Rp1 to Rp4 and the parasitic inductances Lp1 to Lp4 may exist. The DC value of the power supply voltage can be changed by the parasitic resistances Rp1 to Rp4. For example, assume that the power management integrated circuit 11 provides a supply voltage of 0.8V to the application processor 12. When the current (I) flows through the power supply line, a voltage drop corresponding to IxRp1 may occur. When the current I flowing in the power supply line changes suddenly, the recovery of the power supply voltage may be slowed due to the parasitic inductance Lp1.

The user device 10 shown in Fig. 1 connects capacitors Ce1 to Ce4 to respective power supply lines in order to reduce the influence of parasitic components present in the power supply lines. The capacitors Ce1 to Ce4 connected to the power supply line can speed up the recovery speed of the power supply voltage when the current I is abruptly changed. The user device 10 shown in FIG. 1 simply connects the capacitor to the power supply line, thereby effectively reducing the influence of the parasitic component of the power supply line.

2 is a block diagram illustrating a user device in accordance with an embodiment of the present invention. Referring to FIG. 2, the user device 100 includes a power management integrated circuit (PMIC) 110 and an application processor 120. Here, the application processor 120 may be used in a mobile device. The power management integrated circuit 110 may provide the power supply voltage to the application processor 120 through the power supply line.

In Fig. 2, by way of example, a power supply voltage of 1.8 V is provided through a power supply line. The application processor 120 is supplied with a power supply voltage of 1.8 V from the power management integrated circuit 110 and internally generates a power supply voltage of 0.8 V, 0.9 V, and 1.1 V. [ To this end, the application processor 120 includes a plurality of LDO regulators (low drop-out regulators). A plurality of LDO regulators may be integrated within the application processor 120. The application processor 120 may generate a plurality of power supply voltages through the integrated LDO regulator.

Referring to FIG. 2, the application processor 120 includes first to fourth LDO regulators 121 to 124. The first to fourth LDO regulators 121 to 124 may have the same internal configuration and operation principle. The first LDO regulator 121 receives an external voltage of 1.8V and can generate an internal voltage of 0.9V. And the second LDO regulator 122 can generate an internal voltage of 0.8V. The internal voltages of the first and second LDO regulators 121 and 122 may be provided to a central processing unit (CPU) 125. The third LDO regulator 123 generates an internal voltage of 1.1 V and provides the generated internal voltage to the display controller 126. The fourth LDO regulator 124 generates an internal voltage of 0.8 V and provides the generated internal voltage to the memory controller 127.

The user device 100 shown in FIG. 2 may reduce the number of power lines or the number of capacitors connected to the power line. According to the user apparatus 100 shown in Fig. 2, the routing effect of the printed circuit board (PCB) is reduced. In addition, the user device 100 can reduce the area and cost, as well as the effect of parasitic components effectively.

3 is a block diagram illustrating an exemplary LDO regulator shown in FIG. The LDO regulator 121a shown in FIG. 3 is a digital LDO regulator and may have the same configuration and operation principle as the first to fourth LDO regulators 121 to 124 shown in FIG.

3, the LDO regulator 121a includes a voltage divider 201, a coarse loop block 210, a fine loop block 220, and a digital control block 230 . The LDO regulator 121a can provide the output voltage Vout to the load circuit 202. [ The voltage divider 201 receives the output voltage Vout and can provide the divided input voltage Vin to the cosine loop block 210 and the fine loop block 220. [

The cosine loop block 210 may adjust the output voltage Vout to a large voltage range. The cosine loop block 210 receives the input voltage Vin and can output a coarse code (C_LPT). The course loop block 210 provides the course code C_LPT to the digital control block 230. The course loop block 210 can adjust the course current I_LPT provided to the output terminal in accordance with the course code C_LPT.

The coarse loop block 210 can adjust the course current I_LPT using a large power transistor (LPT). Here, the large power transistor (LPT) means a transistor having a large size. The large power transistor (LPT) has a large current supply amount and can control the output voltage (Vout) to a large voltage range.

The fine loop block 220 can finely adjust the output voltage Vout with a small voltage range. The fine loop block 220 is provided with an input voltage Vin and can internally generate a fine code C_SPT in response to the fine loop control signal F_CTRL. The fine loop control signal F_CTRL is provided from the digital control block 230. The fine loop block 220 may provide a fine current (I_SPT) to the output terminal after the course current I_LPT is provided.

The fine loop block 220 may adjust the fine current I_SPT using a small power transistor (SPT). Here, the small power transistor (SPT) means a transistor having a small size. The small power transistor (SPT) has a small current supply and can finely adjust the output voltage (Vout) in a small range.

The digital control block 230 may control the operation of the fine loop block 220. The digital control block 230 receives the course code C_LPT from the course loop block 210 and provides the fine loop control signal F_CTRL to the fine loop block 220. The digital control block 230 may control to cause the fine loop block 220 to operate immediately after the operation of the cosine loop block 210. [ The digital control block 230 quickly controls the loop operation switching, thereby reducing the transition effect.

4 is a block diagram showing another embodiment of the LDO regulator shown in FIG. Referring to Fig. 4, the LDO regulator 121b includes a voltage divider circuit 301, a load driving circuit 302, and a load capacitor 303. Fig.

The voltage divider circuit 301 is connected between the output terminal and the ground terminal, distributes the output voltage Vout, and generates the distribution voltage Vdid. For example, assume that a first resistor (e.g., R) is connected between the output terminal and the distribution node and a second resistor (e.g., 4R) is connected between the distribution node and the ground terminal. If the output voltage Vout is 0.9V, then the divided voltage Vdid is 0.72V. Load current IL flows in the load driving circuit 302. The load capacitor 303 has a load capacitance CL.

The LDO regulator 121b further includes a coarse loop circuit 310, a fine loop circuit 320, and a digital controller 330. [ The LDO regulator 121b receives the power supply voltage VDD and can adjust the output voltage Vout. The coarse loop circuit 310 adjusts the output voltage Vout to a large voltage range and the fine loop circuit 320 adjusts the output voltage Vout to a small voltage range .

4, the course loop circuit 310 includes a reference voltage converter Vrefc changer 311, an analog-to-digital converter (ADC) 312, and a coarse current driver 313. The reference voltage converter 311 receives the course code C_LPT from the ADC 312 and can change the course reference voltage Vrefc. The reference voltage converter 311 provides the changed course reference voltage Vrefc to the ADC 312. [

[Table 1] is a diagram for illustrating the operation principle of the reference voltage converter 311 by way of example.

C_LPT [5: 1] Vrefc 11111 648mv 11110 684mV 11100 720mV 11000 756mV 10000 792 mV 00000 828mV

Referring to Table 1, the reference voltage converter 311 receives a 5-bit course code C_LPT [5: 1] and can change it to a course reference voltage Vrefc corresponding to each course code . For example, when the course code C_LPT [5: 1] is 11111, the course reference voltage Vrefc can be changed to 648 mV. In the case where the course code C_LPT [5: 1] is 11110, it is changed to 684 mV. In the case of 11100, it is changed to 720 mV. When the course code C_LPT [5: 1] is changed to 1150, 756 mV, 10000 is changed to 792 mV. Can be changed to 828 mV. As the load current increases, the course voltage increases. When the load current decreases, the course voltage decreases.

The reference voltage converter 311 can increase the course reference voltage Vrefc when the load current IL increases. Conversely, the reference voltage converter 311 can lower the course reference voltage Vrefc when the load current IL decreases. The reference voltage converter 311 changes the course reference voltage Vrefc so that the output voltage Vout can be more easily adjusted during the course loop operation.

The ADC 312 receives the input voltage Vin and the course reference voltage Vrefc and can generate a coarse code C_LPT. For example, the ADC 312 may generate the first to fifth course codes C_LPT [5: 1]. The first to fifth course codes C_LPT [5: 1] are provided to the reference voltage converter 311 and the course current driver 313.

The course current driver 313 receives the course code C_LPT from the ADC 312 and supplies a coarse current I_LPT to the output terminal. For example, the course current driver 313 may include first through fifth PMOS transistors M_LP1 through M_LP5. The first to fifth PMOS transistors M_LP1 to MLP5 may be connected between a power supply terminal and an output terminal. Here, the power supply terminal receives the power supply voltage VDD, and the output terminal provides the output voltage Vout.

The first through fifth PMOS transistors M_LP1 through M_LP5 may be controlled by the first through fifth course codes C_LPT [5: 1]. For example, the first PMOS transistor M_LP1 may be controlled by the first course code C_LPT [1]. The code current driver 313 can adjust the course current I_LPT provided to the output terminal in accordance with the course code of the ADC 312. [ When the first to fifth PMOS transistors M_LP1 to M_LP5 are all turned on, the largest course current I_LPT is provided. As the first to fifth PMOS transistors M_LP1 to M_LP5 are turned off, the course current I_LPT is reduced.

4, the fine loop circuit 320 includes a comparator 321, a shift register 322, and a fine current driver 323. The fine loop circuit 320 can precisely adjust the output voltage Vout. The fine loop circuit 320 may provide a fine current I_SPT to the output terminal.

The comparator 321 compares the input voltage Vin with the reference voltage Vref and provides the comparison result to the shift register 322. [ The comparator 321 receives the reference voltage Vref through the (+) input terminal and the input voltage Vin through the (-) input terminal. The comparator 321 can operate in synchronization with the clock signal CLK. The comparator 321 can provide the comparison result to the selection terminal SEL of the shift register 322 through the output terminal. A selection signal SEL of 1 is provided when the reference voltage Vref is higher than the input voltage Vin and a selection signal SEL of 0 when the reference voltage Vref is lower than the input voltage Vin.

 The shift register 322 operates in response to the enable signal EN. The enable signal EN is provided from the digital controller 330. The enable signal EN may be provided to the shift register 322 after operation of the course loop circuit 310. The shift register 322 can operate in synchronization with the clock signal CLK. The shift register 322 receives the selection signal SEL from the comparator 321 and can output a fine code (C_SPT). By way of example, the shift register 322 can output a 20-bit fine code (C_SPT [20: 1]), assuming a 20-bit shift register.

The fine current driver 323 receives the fine code C_SPT from the shift register 322 and can supply a fine current I_SPT to the output terminal. For example, the fine current driver 323 may include first through twentieth PMOS transistors M_SP1 through M_SP20. The first to twentieth PMOS transistors M_SP1 to M_SP20 may be connected between a power terminal and an output terminal. The first through twentieth PMOS transistors M_SP1 through M_SP20 may be controlled by first through twentieth fine codes C_SPT [20: 1].

For example, the first PMOS transistor M_SP1 may be controlled by the first fine code C_SPT [1]. The fine current driver 323 can adjust the fine current I_SPT provided to the output terminal in accordance with the fine code of the shift register 322. When the first to twentieth PMOS transistors M_SP1 to M_SP20 are all turned on, the largest fine current I_SPT is provided. As the first to twentieth PMOS transistors M_SP1 to M_SP20 are turned off, the fine current I_SPT is reduced.

The fine current driver 323 may have the same operation principle as the course current driver 313. [ However, the size of each PMOS transistor of the fine current driver 323 may be smaller than the PMOS transistor of the course current driver 313. The fine current driver 323 uses a transistor having a small current supply amount, so that the output voltage Vout can be finely adjusted to a small voltage range.

4, the digital controller 330 can control the operation of the fine loop circuit 320. [ The digital controller 330 receives the course code C_LPT and can output a control signal. The control signal includes an enable signal EN, a reset signal RST, and an initial signal INIT. The enable signal EN is a signal for operating the shift register 322. The reset signal RST is a signal for resetting the fine code C_SPT of the shift register 322. The initial signal INIT is a signal for determining the initial fine current.

The digital controller 330 may use a simple counter to cause a fine loop operation to begin immediately following the course loop operation. The digital controller 330 can quickly control the switching of the loop operation, thereby reducing the transition effect. The internal configuration and operation principle of the digital controller 330 will be described later.

FIG. 5 is a circuit diagram illustrating an exemplary analog-to-digital converter (ADC) shown in FIG. The ADC 312a shown in FIG. 5 is a flash ADC (flash ADC), which includes a voltage divider circuit 410 and a comparison circuit 420. FIG. In the example of FIG. 5, the flash ADC 312 may generate a five digit binary code.

The voltage divider circuit 410 may include first to sixth resistors R1 to R6. The first to sixth resistors R1 to R6 may all have the same resistance value or different resistance values. The voltage distribution circuit 410 receives the course reference voltage Vrefc and can generate five distribution voltages Vd1 to Vd5. The first to fifth distribution voltages Vd1 to Vd5 are provided to the comparison circuit 420. [

The comparison circuit 420 includes first to fifth comparators 421 to 425. The first to fifth comparators 421 to 425 receive the input voltage Vin in common. Here, the input voltage Vin is equal to the divided voltage Vdid of the voltage divider circuit 301 shown in Fig. The input voltage Vin may be provided to the (+) input terminals of the first to fifth comparators 421 to 425. The first comparator 421 receives the input voltage Vin through the positive input terminal and receives the first divided voltage Vd1 through the negative input terminal. The first comparator 421 can compare the input voltage Vin with the first divided voltage Vd1 and generate the first course code C_LPT [1] of 1 or 0 according to the comparison result.

For example, if the input voltage Vin is higher than the first distribution voltage Vd1, the course code 1 is generated. If the input voltage Vin is lower than the first distribution voltage Vd1, the course code 0 can be generated. Likewise, the second to fifth comparators 422 to 425 may generate the second to fifth course codes C_LPT [5: 2]. The comparison circuit 420 provides the course code C_LPT [5: 1] to the course current driver (see FIG. 4) 313.

FIG. 6 is a circuit diagram showing another embodiment of the analog-to-digital converter (ADC) shown in FIG. The digital ADC 312b shown in FIG. 6 includes a comparator (COM) 510 and a code generator 520.

The comparator 510 compares the course reference voltage Vrefc with the input voltage Vin. The comparator 510 may be provided with the input voltage Vin through the (+) input terminal and the course reference voltage Vrefc through the (-) input terminal. The comparator 510 may compare the input voltage Vin with the course reference voltage Vrefc and provide an error voltage Verr to the code generator 520. [

The code generator 520 may generate a coarse code according to the error voltage Verr. For example, if the error voltage Verr is + b or more, the course code (C_LPT [5: 1]) becomes 11111. If the error voltage Verr is + a to + b, the course code (C_LPT [5: 1]) becomes 11110. If the error voltage Verr is 0 to + a, the course code (C_LPT [5: 1]) becomes 11100. If the error voltage Verr is -a to 0, the course code (C_LPT [5: 1]) becomes 11000. If the error voltage Verr is -b to -a, the course code C_LPT [5: 1] is 10000. Finally, if the error voltage Verr is smaller than -b, the course code C_LPT [5: 1] becomes 00000. The code generator 520 provides the course code C_LPT [5: 1] to the course current driver (see FIG. 4, 313).

FIG. 7 is a circuit diagram showing another embodiment of the analog-to-digital converter (ADC) shown in FIG. The ADC 312c shown in FIG. 7 includes a comparison circuit 610, a first current mirror circuit 620, and a second current mirror circuit 630 as a current mirror flash ADC (CMF ADC) .

The comparison circuit 610 includes first and second PMOS transistors PM1 and PM2, first and second NMOS transistors NM1 and NM2 and a current source 611. [ Here, it is assumed that the sizes of the first and second PMOS transistors PM1 and PM2 are one. In Fig. 7, x1 is indicated.

The first PMOS transistor PM1 is connected between the power supply terminal and the first node ND1. The gate of the first PMOS transistor PM1 is connected to the first node ND1. The first PMOS transistor PM1 has a diode connection structure. The second PMOS transistor PM2 is connected between the power supply terminal and the second node ND2. And the gate of the second PMOS transistor PM2 is connected to the second node ND2. The second PMOS transistor PM2 has a diode connection structure.

The first NMOS transistor NM1 is connected between the first node ND1 and the third node ND3. The first NMOS transistor NM1 receives the course reference voltage Vrefc through the gate thereof. The second NMOS transistor NM2 is connected between the second and third nodes ND2 and ND3. The second NMOS transistor NM2 receives the input voltage Vin through the gate thereof.

The current source 611 is connected between the third node ND3 and the ground terminal. The current flowing through the current source 611 is fixed. For example, the current source 611 may be fixed at 2xIb. The current source 611 may be composed of an NMOS transistor (not shown).

The comparison circuit 610 forms first and second current paths. The first current path I1 passes through the first PMOS transistor PM1 and the first NMOS transistor NM1. The second current path I2 passes through the second PMOS transistor PM2 and the second NMOS transistor NM2. The comparison circuit 610 compares the course reference voltage Vrefc with the input voltage Vin. The amount of current flowing in the first current path I1 and the second current path I2 may vary depending on the course reference voltage Vrefc and the input voltage Vin.

The sum of the currents flowing in the first and second current paths I1 and I2 can be fixed to 2xIb by the current source 611. [ When the input voltage Vin is higher than the course reference voltage Vrefc, the current flowing through the second current path I2 is increased by Ierr and the current flowing through the first current path I1 is decreased by Ierr . Conversely, when the input voltage Vin is lower than the course reference voltage Vrefc, the current flowing in the second current path I2 decreases and the current flowing in the first current path I1 can increase relatively .

The first current mirror circuit 620 includes a third PMOS transistor PM3 and a third NMOS transistor NM3. The third PMOS transistor PM3 is connected between the power supply terminal and the fourth node ND4. The gate of the third PMOS transistor PM3 is connected to the first node ND1. That is, the gate of the third PMOS transistor PM3 is commonly connected to the gate of the first PMOS transistor PM1. The size of the third PMOS transistor PM3 is equal to the size of the first PMOS transistor PM1. That is, the size of the third PMOS transistor PM3 is x1.

The first current mirror circuit 620 forms the third current path I3. The third current path I3 passes through the third PMOS transistor PM3 and the third NMOS transistor NM3. By the current mirroring, the amount of current flowing in the third current path I3 becomes equal to the amount of current flowing in the first current path I1. When the amount of current flowing in the third current path I3 increases, the voltage level of the fourth node ND4 rises. Conversely, when the amount of current flowing in the third current path I3 decreases, the voltage level of the fourth node ND4 decreases.

As the input voltage Vin increases, the amount of current in the second current path I2 increases. At this time, the amount of current in the first and third current paths I1 and I3 decreases relatively and the voltage level of the fourth node ND4 decreases. That is, when the input voltage Vin increases with the course reference voltage Vrefc being fixed, the voltage level of the fourth node ND4 decreases. Conversely, when the input voltage Vin decreases, the voltage level of the fourth node ND4 increases.

The second current mirror circuit 630 includes the fourth to eighth PMOS transistors PM4 to PM8 and the fourth to eighth NMOS transistors NM4 to NM8. The fourth PMOS transistor PM4 is connected between the power supply terminal and the first output node OD1. The gate of the fourth PMOS transistor PM4 is connected to the second node ND2. The size of the fourth PMOS transistor PM4 may be different from that of the second PMOS transistor PM2. For example, assuming that the size of the second PMOS transistor PM2 is 1, the fourth PMOS transistor PM4 may have a size six times larger than that of the second PMOS transistor PM4. In FIG. 7, it is indicated by x6. Hereinafter, the fourth PMOS transistor has a size of x6.

The fourth NMOS transistor NM4 is connected between the first output node OD1 and the ground terminal. The gate of the fourth NMOS transistor NM4 is connected to the fourth node ND4. Assuming that the size of the third NMOS transistor NM3 is 1, the fourth NMOS transistor NM4 has a size of x14. The fourth PMOS transistor PM4 and the fourth NMOS transistor NM4 form a fourth current path I4. The first output node OD1 outputs the first course code C_LPT [1].

Likewise, the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 form a fifth current path I5. The fifth PMOS transistor PM5 has a size of x8, and the fifth NMOS transistor NM5 has a size of x12. And the second output node OD2 outputs the second course code C_LPT [2].

The sixth PMOS transistor PM6 and the sixth NMOS transistor NM6 form a sixth current path I6. The sixth PMOS transistor PM6 has a size of x10, and the sixth NMOS transistor NM6 has a size of x10. And the third output node OD3 outputs the third course code C_LPT [3]. The seventh PMOS transistor PM7 and the seventh NMOS transistor NM7 form a seventh current path I7. The seventh PMOS transistor PM7 has a size of x12, and the seventh NMOS transistor NM7 has a size of x8. And the fourth output node OD4 outputs the fourth course code C_LPT [4]. The eighth PMOS transistor PM8 and the eighth NMOS transistor NM8 form an eighth current path I8. The eighth PMOS transistor PM8 has a magnitude of x14, and the eighth NMOS transistor NM8 has a magnitude of x6. The fifth output node OD5 outputs the fifth course code C_LPT [5].

The fourth current path I4 is constituted by the fourth PMOS transistor PM4 having the smallest magnitude x6 and the fourth NMOS transistor NM4 having the largest magnitude x14. The fourth current path I4 can be switched to the low level most quickly. For example, when the input voltage Vin is lowered, the voltage levels of the second and fourth nodes ND2 and ND4 become high. When the fourth node ND4 rises, the first output node OD1 is discharged most rapidly through the fourth NMOS transistor NM4. At this time, the first course code C_LPT [1] outputs 0 first.

Conversely, the eighth current path I8 is composed of the eighth PMOS transistor PM8 of the largest magnitude x14 and the eighth NMOS transistor NM8 of the smallest magnitude x6. The eighth current path I8 can be switched to the highest level as fast as possible. For example, when the input voltage Vin becomes high, the voltage levels of the second and fourth nodes ND2 and ND4 become low. When the second node ND2 is lowered, the fifth output node OD5 is charged fastest through the eighth PMOS transistor PM8. At this time, the fifth course code C_LPT [5] outputs 1 first.

FIG. 8 is a diagram for illustrating the CMF ADC shown in FIG. 7 by way of example. Referring to FIGS. 7 and 8, the CMF ADC 312 obtains the error voltage Verr using the difference between the input voltage Vin and the course reference voltage Vrefc. The error voltage (Verr) can be obtained by the following equation.

When the input voltage Vin is much higher than the course reference voltage Vrefc (for example, 72 mV or more), the second and fourth nodes ND2 and ND4 of FIG. 7 have a very low voltage level in proportion thereto. At this time, the fourth to eighth PMOS transistors PM4 to PM8 are all turned on, and the fourth to eighth NMOS transistors NM4 to NM8 are all turned off. Due to this operating principle, C_LPT [5: 1] becomes 11111 when the error voltage Verr is 72 mV or more.

When the input voltage Vin becomes low, the voltage levels of the second and fourth nodes ND2 and ND4 become high. When the fourth node ND4 rises, the first output node OD1 is discharged most rapidly through the fourth NMOS transistor NM4. That is, when Verr is 36 mV to 72 mV, C_LPT [5: 1] becomes 11110. In this way, when Verr is 0 to 36 mV or more, C_LPT [5: 1] becomes 11100. When Verr is from -36mV to 0, C_LPT [5: 1] becomes 11000. When Verr is from -72 mV to -36 mV, C_LPT [5: 1] becomes 10000.

When the input voltage Vin is lower than the course reference voltage Vrefc by 72 mV or more, the second and fourth nodes ND2 and ND4 in Fig. 7 have the highest voltage level. At this time, the fourth to eighth PMOS transistors PM4 to PM8 are all turned off, and the fourth to eighth NMOS transistors NM4 to NM8 are all turned on. That is, when Verr is smaller than -72 mV, C_LPT [5: 1] becomes 00000.

The CMF ADC 312 shown in FIG. 7 can generate a course code (C_LPT) by using a size difference between the NMOS transistor and the PMOS transistor. According to the CMF ADC 312 shown in Fig. 7, power consumption can be reduced because a simple current mirror circuit is used. Since the CMF ADC 312 is implemented by a PMOS transistor and an NMOS transistor, the area can be reduced.

FIG. 9 is a diagram for explaining an operation method of the shift register shown in FIG. 4 as an example. Referring to Fig. 9, the shift register 322 outputs a 20-bit fine code (C_SPT [20: 1]). The shift register 322 shifts left or shift right by one bit in synchronization with the clock signal CLK. The shift register 322 can move left or right depending on the selection signal SEL.

For example, when the selection signal is 0 (SEL = 0), the shift register 322 moves one bit to the left. And C_SPT [20] becomes one. For example, assuming that the shift register 322 outputs a fine code (C_SPT [20: 1] = 000 ... 001) at t, the shift register 322 at t + : 1] = 000 ... 011). When the selection signal is 1 (SEL = 1), the shift register 322 moves one bit to the right. And C_SPT [1] becomes zero. For example, assuming that the shift register 322 outputs a fine code (C_SPT [20: 1] = 011..111) at t, the shift register 322 shifts the fine code C_SPT [20: 1] = 001 ... 111). The shift register 322 provides a fine code (C_SPT [20: 1]) to the fine current driver 323.

FIG. 10 is a block diagram illustrating an exemplary digital controller shown in FIG. The digital controller 330 shown in Fig. 10 receives the course code C_LPT [5: 1] and generates the control signals EN, RST, and INIT [3: 1]. Referring to FIG. 10, the digital controller 330 includes first to fifth control units 331 to 335 and a logic gate 336.

The first control unit 331 receives the first course code C_LPT [1] and generates the first control signals EN [1], RST [1], and INIT1 [3: 1]. Likewise, the fifth control unit 335 receives the fifth course code C_LPT [5] and generates the fifth control signals EN [5], RST [5], and INIT5 [3: 1] . The logic gate 336 receives the first to fifth control signals and performs a logical operation.

For example, the logic gate 336 receives the first to fifth enable signals EN [5: 1], performs an OR operation, and outputs an enable signal EN. The logic gate 336 receives the first to fifth reset signals RST [5: 1] and can output the reset signal RST as a result of the OR operation. The logic gate 336 receives the first to fifth initial signals INIT1 [3: 1] to INIT5 [3: 1] and outputs the initial signal INIT [3: 1] can do.

The digital controller 330 can determine the initial fine current of the fine loop circuit 320 using the initial signal INIT [3: 1] when changing from the course loop operation to the fine loop operation. The digital controller 330 determines the initial fine current of the fine loop circuit 320, thereby reducing the transition effect due to the loop change.

11 is a block diagram exemplarily showing the fifth control unit shown in FIG. 11, the fifth control unit 335 receives the fifth course code C_LPT [5] and outputs the fifth control signals EN [5], RST [5], INIT5 [3: 1] . The fifth control unit 335 includes an enable fine loop controller (EFLC) 341 and an initial fine loop selector 344.

The enable fine loop controller 341 includes a 4-bit counter 342 and a rising edge detector 343. The 4-bit counter 342 provides the first output value Q [1] to the rising edge detector 343 and provides the third output value Q [3] to the initial fine current selector 344. The fourth output value Q [4] of the 4-bit counter 342 is used as the fifth enable signal EN [5]. The rising edge detector 343 detects the rising edge of the first output value Q [1] and outputs the fifth reset signal RST [5] as a detection result. The enable fine loop controller 341 receives the fifth course code C_LPT [5] and outputs the fifth enable signal EN [5] and the fifth reset signal RST [5].

12 is a timing chart for explaining the operation of the loop controller which is the enable waveform shown in Fig. 11 and 12, the 4-bit counter 342 generates the 4-bit output value Q [4: 1] in synchronization with the fifth course code C_LPT [5].

Bit counter 342 generates 0000 during the first period of the fifth course code C_LPT [5], 0001 during the second period, and 0010 during the third period. In this manner, the 4-bit counter 342 generates 0110 during the seventh period and 0111 during the eighth period. The fifth enable signal EN [5] may be obtained through the fourth output value Q [4] of the 4-bit counter 342. [ The fifth reset signal RST [5] can be obtained by detecting the rising edge of the first output value Q [1] of the 4-bit counter 342. [

Referring again to FIG. 11, the initial fine current selector 344 includes a 3-bit counter 345 and a logic circuit 346. Bit counter 345 receives the third output value Q [3] of the 4-bit counter 342 via the enable terminal En. Bit counter 345 operates in response to the third output value Q [3] and generates a 3-bit output value C [3: 1] in synchronization with the clock signal CLK. The 3-bit counter 345 provides the 3-bit output value C [3: 1] to the logic circuit 346. The logic circuit 346 receives the 3-bit output value C [3: 1] and outputs the fifth initial signal INIT5 [3: 1].

FIG. 13 is a timing diagram for illustratively illustrating the operation of the initial fine current selector shown in FIG. 11; FIG. 13 is a timing chart showing an enlarged view of the fifth period (the fourth and fifth rising edge sections) in Fig.

11 and 13, the 3-bit counter 345 generates a 3-bit output value C [3: 1] in synchronization with the clock signal CLK. Bit counter 345 is generating 000 during the first period of the clock signal CLK. Bit counter 345 can generate 001 in synchronization with the first rising edge of the clock signal CLK. Bit counter 345 may generate 010 in synchronization with the second rising edge and during the third period. Likewise, the 3-bit counter 345 may generate 101 during the sixth period and 110 during the seventh period. Bit counter 345 can generate 111 in synchronization with the seventh rising edge.

The logic circuit 346 receives the output value C [3: 1] of the 3-bit counter 345 and can generate 000 during the first to seventh periods of the clock signal CLK. The logic circuit 346 may generate 111 in synchronization with the seventh rising edge of the clock signal CLK. The logic circuit 346 may provide the initial signal INIT [3: 1] to the shift register 322 of the fine loop circuit 320.

The initial fine current selector 344 may calculate the low level interval of the fifth course code C_LPT [5] using the 3-bit counter 345. [ The initial fine current selector 344 calculates the low level interval of the fifth course code C_LPT [5] and provides the initial signal INIT [3: 1] to the shift register 322. The initial fine current selector 344 may set the initial fine current to the initial signal INIT [3: 1].

The digital controller 330 uses a simple counter so that the design can be simplified. The digital controller 330 can adjust the fine fine current because it can set the initial fine current at the time of the loop operation change. In addition, the digital controller 330 can reduce the transition effect due to the loop change.

FIG. 14 is a block diagram and timing diagram for explaining an operation method of the LDO regulator shown in FIG. 2. FIG. The LDO regulator 121d shown in Fig. 14 includes a voltage divider circuit 301, a load driving circuit 302, a load capacitor 303, a coarse loop circuit 310, a fine loop circuit 320, 330).

The course loop circuit 310 includes the CMF ADC 312 shown in FIG. The course current driver 313 of the course loop circuit 310 includes first through fifth PMOS transistors M_LP1 through M_LP5. Each PMOS transistor can supply 40mA of current. The fine current driver 323 of the fine loop circuit 320 includes first to twentieth PMOS transistors M_SP1 to M_SP20. Each PMOS transistor can supply 2mA of current.

The LDO regulator 121d receives the power supply voltage VDD and can adjust the output voltage Vout. The LDO regulator 121 can stably provide the output voltage Vout irrespective of changes in the load current IL. That is, even if the load current IL changes from 20 mA to 200 mA, the output voltage Vout can be stably maintained at 0.9 V. [

In the T1 period, the load current IL is 20 mA and the LDO regulator 121d maintains the output voltage Vout of 0.9V. All of the first to fifth course codes C_LPT [5: 1] of the course loop circuit 310 are in the high level state and the first to fifth PMOS transistors M_LP1 to M_LP5 of the course current driver 313 are all Off state. The initial signal INIT [3: 1] provided from the digital controller 330 has a previous value, and the enable signal EN is at a high level. The fine loop circuit 320 operates in response to the enable signal EN and nine to ten PMOS transistors among the first to twentieth PMOS transistors M_SP1 to M_SP20 of the fine current driver 323 are turned on have. The fine loop circuit 320 supplies a fine current I_SPT of 20 mA.

In the T2 period, the load current IL becomes as high as 200 mA. The output voltage Vout of the LDO regulator 121d becomes lower than 0.9V. The fine loop circuit 320 is turned off, and the coslop circuit 310 is turned on. When the output voltage Vout is lowered, the input voltage Vin provided to the cos Loop circuit 310 and the fine loop circuit 320 is lowered. When the input voltage Vin is lowered, the first to fifth course codes C_LPT [5: 1] of the CMF ADC 312 are changed as described in FIGS. 7 and 8.

First, the first course code C_LPT [1] becomes zero. As the output voltage Vout continues to decrease, the second to fourth course codes C_LPT [4: 2] also become 0 in order. When the first course code C_LPT [1] becomes 0, the first PMOS transistor M_LP1 is turned on and a course current I_LPT of 40 mA is supplied. Next, when the second course code C_LPT [2] becomes 0, the second PMOS transistor M_LP2 is turned on. At this time, a course current (I_LPT) of 40 mA is further supplied. In this way, when the third and fourth course codes C_LPT [3] and C_LPT [4] are 0, the third and fourth PMOS transistors M_LP3 and M_LP4 are sequentially turned on. The course current I_LPT continues to increase additionally.

On the other hand, in response to the first course code C_LPT [1], the initial signal INIT [3: 1] provided from the digital controller 330 is 000 and the enable signal EN transits to the low level . When the enable signal EN transitions to the low level, the fine loop circuit 320 is turned off.

The first to fourth course codes C_LPT [4: 1] of the course loop circuit 310 maintain the low level state and the fifth course code C_LPT [5] is toggled . As the fifth course code C_LPT [5] is toggled, the course current I_LPT varies between 160 mA and 200 mA. As the course current I_LPT changes, the output voltage Vout changes to a large voltage range. On the other hand, in the period T3, the digital controller 330 generates a control signal for operating the fine loop circuit 320.

For example, the digital controller 330 may generate a reset signal RST to be provided to the shift register 322 of the fine loop circuit 320. The reset signal RST is a signal for setting all the fine codes C_SPT [20: 1] of the shift register 322 to 1. When the reset signal RST is input to the shift register 322, the fine current I_SPT will be 0 mA.

The fifth course code C_LPT [5] continues to be toggled, and the digital controller 330 generates a control signal for operating the fine loop circuit 320 in the T4 section. For example, the digital controller 330 may generate an initial signal INIT [3: 1] to be provided to the shift register 322 of the fine loop circuit 320. The initial signal INIT [3: 1] is a signal for setting a part of the fine codes C_SPT [20: 1] of the shift register 322 to 0. For example, the first to tenth fine codes C_SPT [ (INIT [3: 1] = 111) is set to 0, the fine current I_SPT will be 20 mA.

In the T5 section, the digital controller 330 generates the enable signal EN using the output value of the fifth course code C_LPT [5]. When the enable signal EN becomes a high level, the coarse loop circuit 310 maintains the same state, and the fine loop circuit 320 starts to operate. For example, the course loop circuit 310 can supply the course current I_LPT of 160 mA because the first to fourth course codes C_LPT [4: 1] are held at zero. The fine loop circuit 320 operates in response to the enable signal EN. The fine loop circuit 320 can supply a fine current I_SPT of 40 mA by setting all of the first through twentieth fine codes C_SPT [20: 1] to zero.

The LDO regulator 121d according to the embodiment of the present invention adjusts the output voltage Vout in a large voltage range using the course loop circuit 310 and delicately outputs the output voltage Vout using the fine loop circuit 320. [ Can be adjusted. According to the LDO regulator 121d according to the embodiment of the present invention, the output voltage Vout can be adjusted quickly and accurately.

FIG. 15 is a flowchart for illustrating an exemplary operation method of the LDO regulator shown in FIG. Referring to Figs. 14 and 15, the LDO regulator 121d includes a coarse loop circuit 310, a fine loop circuit 320, and a digital controller 330. Fig.

The course current driver 313 of the course loop circuit 310 includes first through fifth PMOS transistors M_LP1 through M_LP5. Each PMOS transistor can supply 40mA of current. The fine current driver 323 of the fine loop circuit 320 includes first to twentieth PMOS transistors M_SP1 to M_SP20. Each PMOS transistor can supply 2mA of current. The LDO regulator 121d can stably provide the output voltage Vout regardless of the change in the load current IL.

Step S110 is a steady state. In step S110, the fine loop circuit 320 provides a load current IL of 20 mA. The LDO regulator 121 maintains the output voltage Vout of 0.9V. Ten PMOS transistors among the first through twentieth PMOS transistors M_SP1 through M_SP20 of the fine current driver 323 are in a turned-on state.

The step S120 is a load transient state in which the load current IL temporarily rises. In step S120, the fine loop circuit 320 turns off. The course loop circuit 310 maintains the turn-on state. When the load current IL increases to 200 mA, the output voltage Vout of the LDO regulator 121d becomes lower than 0.9V. When the output voltage Vout is lowered, the input voltage Vin provided to the cos Loop circuit 310 is lowered. When the input voltage Vin becomes lower, the first to fifth course codes C_LPT [5: 1] become 0 in order. The course current I_LPT increases toward 200 mA.

Step S130 is a load settling state. In step S 130, the digital controller 330 changes control signals for starting the fine loop circuit 320. The digital controller 330 may generate a reset signal RST to be provided to the shift register 322 of the fine loop circuit 320. [ When the reset signal RST is input to the shift register 322, the fine current I_SPT will be 0 mA. In step S130, as the fifth course code C_LPT [5] is toggled, the course current I_LPT varies between 160 mA and 200 mA. As the course current I_LPT changes, the output voltage Vout changes to a large voltage range.

Step S140 is a state in which the output voltage is delicately adjusted (load settling state). In step S140, the digital controller 330 generates the enable signal EN using the output value of the fifth course code C_LPT [5]. When the enable signal EN becomes a high level, the coarse loop circuit 310 maintains the same state, and the fine loop circuit 320 starts to operate. The course loop circuit 310 can supply the course current I_LPT of 160 mA. The fine loop circuit 320 may supply a fine current I_SPT of 40 mA in response to the enable signal EN.

As described above, the LDO regulator according to the embodiment of the present invention can receive the power supply voltage VDD and adjust the output voltage Vout. The LDO regulator according to the embodiment of the present invention can stably provide the output voltage Vout regardless of the change in the load current IL.

The above-described contents of the present invention are only specific examples for carrying out the invention. The present invention will include not only concrete and practical means themselves, but also technical ideas which are abstract and conceptual ideas that can be utilized as future technologies.

100: user equipment 110: power management integrated circuit
120: Application processors 121 to 124: LDO regulators
125: central processing unit 126: display
127: memory 210: coarse loop block
220: Fine Loop Block 230: Digital Control Block
310: Coslop circuit 311: Reference voltage converter
312: analog-to-digital converter 313: course current driver
320: Fine loop circuit 321: Comparator
322: shift register 323: fine current driver
330: Digital controller

Claims (25)

A course loop block for adjusting a course current provided to the output terminal in accordance with the course code, the input signal being supplied from an output terminal and generating a course code;
A fine loop block for adjusting a fine current provided to the output terminal according to the fine code, the fine loop being provided with an input voltage from the output terminal and generating a fine code; And
And a digital control block that receives the course code from the COUR LOBS block and generates a control signal for controlling the fine loop block. The method according to claim 1,
And a voltage divider that divides the output voltage of the output terminal and outputs the input voltage. The method according to claim 1,
Wherein the coarse-
A reference voltage converter for receiving the course code and changing a course reference voltage;
An analog-to-digital converter (ADC) receiving the input voltage and the course reference voltage and generating the course code; And
And a course current driver for receiving the course code from the ADC and providing the course current. The method of claim 3,
The reference voltage converter raises the course reference voltage when the load current increases, and reduces the course reference voltage when the load current decreases. The method of claim 3,
A comparator for comparing the input voltage with the course reference voltage and generating an error voltage; And
And a code generator for generating the course code according to the level of the error voltage and providing the course code to the reference voltage generator, the course current driver, and the digital control block. The method of claim 3,
The ADC is a current mirrored flash analog-to-digital converter (CMF ADC). The method according to claim 6,
The CMF ADC includes:
The input of the input voltage and forming a second current path, wherein the sum of the currents in the first and second current paths is maintained constant by the current source / RTI >
A first current mirror circuit forming a third current path by current mirroring the first current path; And
And a second current mirror circuit that forms a fourth to an Nth (N is a natural number of 5 or more) current path by current mirroring the second current path. 8. The method of claim 7,
The first current path includes a first PMOS transistor coupled between a power terminal and a first node, and a first NMOS transistor coupled between the first node and the current source;
The second current path includes a second PMOS transistor coupled between the power supply terminal and a second node, and a second NMOS transistor coupled between the second node and the current source;
Wherein a gate of the first PMOS transistor is connected to the first node, a gate of the second PMOS transistor is connected to the second node, a gate of the first NMOS transistor receives the course reference voltage, And a gate of the second NMOS transistor receives the input voltage. 9. The method of claim 8,
The current source being connected between a third node and a ground terminal,
The third current path includes a third PMOS transistor connected between the power supply terminal and a fourth node, and a third NMOS transistor coupled between the fourth node and the ground terminal;
Wherein a gate of the third PMOS transistor is coupled to the first node and a gate of the third NMOS transistor is coupled to the fourth node. 10. The method of claim 9,
The fourth current path includes a fourth PMOS transistor coupled between the power supply terminal and a first output node and a fourth NMOS transistor coupled between the first output node and the ground terminal;
The Nth current path includes an Nth PMOS transistor connected between the power supply terminal and the (N-3) th output node; and an Nth NMOS transistor connected between the (N-3) th output node and the ground terminal;
The gates of the fourth to Nth PMOS transistors are connected to the second node, and the gates of the fourth to Nth NMOS transistors are connected to the fourth node. 11. The method of claim 10,
The size of the fourth to N-th PMOS transistors is different, and the sizes of the fourth to N-th NMOS transistors are different. The method of claim 3,
Wherein the path current driver includes a plurality of PMOS transistors connected between a power supply terminal and an output terminal, and a gate of each PMOS transistor receives a course code from the ADC and provides the path current. The method according to claim 1,
The fine loop block includes:
A comparator for comparing the input voltage with a reference voltage and outputting a selection signal as a comparison result;
A shift register which operates in response to a control signal of the digital control block and shifts left or right according to a selection signal of the comparator to output a fine code; And
And a fine current driver receiving the fine code and providing the fine current. 14. The method of claim 13,
Wherein the shift register shifts left or right by one bit in synchronization with a clock signal. 14. The method of claim 13,
The digital control block includes:
A fine loop controller for receiving the course code and outputting an enable signal for operating the shift register and a reset signal for resetting the shift register; And
And an initial fine current selector for outputting an initial signal for controlling the initial fine current by controlling the shift register. 16. The method of claim 15,
Wherein the enable-
An N-bit counter for receiving the course code and generating an N-bit output value and providing the enable signal using a first output value Q [4] of the N-bit output value; And
And a rising edge detector for outputting the reset signal using a second output value Q [1] of the N-bit output values. 17. The method of claim 16,
Wherein the initial fine current selector comprises:
An M-bit counter that operates in response to a third output value Q [3] of the N-bit output value and generates an M-bit output value in response to the clock signal; And
And a logic circuit receiving the output value of the M-bit counter and outputting the initial signal. An LDO regulator which adjusts the course current according to the course code, controls the fine code using the course code, and adjusts the fine current according to the fine code; And
And a load circuit for receiving the course current and the fine current from the LDO regulator. 19. The method of claim 18,
The LDO regulator includes:
A course loop circuit for adjusting a course current provided to the output terminal in accordance with the course code, the input circuit receiving an input voltage from an output terminal and generating the course code;
A fine loop circuit for adjusting a fine current provided to the output terminal according to the fine code, the fine loop circuit being provided with an input voltage from the output terminal and generating the fine code; And
And a digital controller that receives the course code from the course loop circuit and generates a control signal for controlling the fine loop circuit. 20. The method of claim 19,
Wherein the course loop circuit comprises:
A reference voltage converter for receiving the course code and changing a course reference voltage;
An analog-to-digital converter (ADC) receiving the input voltage and the course reference voltage and generating the course code; And
And a course current driver for receiving the course code from the ADC and providing the course current. 21. The method of claim 20,
The ADC includes:
The input of the input voltage and forming a second current path, wherein the sum of the currents in the first and second current paths is maintained constant by the current source / RTI >
A first current mirror circuit forming a third current path by current mirroring the first current path; And
And a second current mirror circuit that forms a fourth to an Nth (N is a natural number greater than or equal to 5) current path by current mirroring the second current path. 22. The method of claim 21,
Wherein the fourth through Nth (N is a natural number of 5 or more) current paths are constituted by PMOS transistors of different sizes and NMOS transistors of different sizes. 20. The method of claim 19,
The fine loop circuit comprises:
A comparator for comparing the input voltage with a reference voltage and outputting a selection signal as a comparison result;
A shift register which operates in response to a control signal of the digital controller and shifts left or right according to a selection signal of the comparator to output a fine code; And
And a fine current driver receiving the fine code and providing the fine current. 24. The method of claim 23,
The digital controller includes:
A fine loop controller for receiving the course code and outputting an enable signal for operating the shift register and a reset signal for resetting the shift register; And
And an initial fine current selector for outputting an initial signal for controlling an initial fine current by controlling the shift register. A power management integrated circuit that provides a power supply voltage through a power supply line; And
And an application processor including an LDO regulator provided with a power supply voltage through the power supply line and generating an internal power supply,
The LDO regulator includes: a coarse loop circuit that adjusts a course current to be provided to the output terminal in accordance with the course code, the input being supplied with an input voltage from an output terminal and generating a course code;
A fine loop circuit for adjusting a fine current provided to the output terminal according to the fine code, the fine loop circuit being provided with an input voltage from the output terminal and generating the fine code; And
Wherein the course code is received from the course loop circuit and generates a control signal for controlling the fine loop circuit.

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