KR20170080775A - Organic light emitting diode display and driving method thereby - Google Patents

Abstract

The present invention relates to a non-inverting input terminal (+) of an amplifier, an initializing period for initializing a gate-source voltage of a driving transistor and a current integrator for sensing a current flowing through the driving transistor, ) Based on a second reference voltage to which an offset voltage is added to a first reference voltage applied to the inverting input terminal (-) And an offset voltage control unit for applying the third reference voltage, from which the offset voltage of the amplifier is removed, to the non-inverting input terminal (+) of the amplifier at the first reference voltage.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an organic light emitting display and a driving method thereof.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode (OLED) includes an anode electrode, a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, And generates visible light.

The OLED display arranges pixels each including an OLED in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data. Each of the pixels includes a driving TFT (Thin Film Transistor) that controls a driving current flowing in the OLED according to a voltage (Vgs) applied between the gate electrode and the source electrode of the pixel. The electrical characteristics of the driving TFT, such as threshold voltage, mobility, etc., deteriorate as the driving time elapses, and a deviation may occur for each pixel. If the electrical characteristics of the driving TFT are different for each pixel, the luminance between the pixels for the same video data is different, so that the desired image is difficult to implement.

An internal compensation method and an external compensation method are known in order to compensate an electric characteristic deviation of a driving TFT. The internal compensation scheme automatically compensates the threshold voltage deviation between the driving TFTs within the pixel circuit. In order to perform the internal compensation, the driving current flowing through the OLED must be determined regardless of the threshold voltage of the driving TFT, so that the configuration of the pixel circuit is very complicated. Moreover, the internal compensation scheme is unsuitable for compensating the mobility deviation between the driving TFTs.

The external compensation method measures the sensing voltage and current corresponding to the electrical characteristics (threshold voltage, mobility) of the driving TFTs and compensates the electrical characteristic deviation by modulating the video data in the external circuit connected to the display panel based on the sensing voltage do. In recent years, research on such external compensation schemes has been actively conducted.

In the conventional external compensation method, the data driving circuit directly receives a sensing voltage from each pixel through a sensing line, converts the sensed voltage to a digital sensing value, and transmits the sensed voltage to a timing controller. The timing controller modulates the digital video data based on the digital sensing value to compensate for the electrical characteristic deviation of the driving TFT. Since the driving TFT is a current device, its electrical characteristics are represented by the magnitude of the current Ids flowing between the drain and the source in accordance with the constant gate-source voltage Vgs.

As shown in Fig. 1, the data driving circuit of the external compensation method includes a sensing block for sensing the electrical characteristics of the driving TFT. The sensing block includes an integrator (CI) composed of an amplifier (AMP), an integrating capacitor (Cfb) and a switch (SW). The integrator includes an inverting input terminal (-) for receiving the source-to-drain current Ids of the driving TFT, a non-inverting input terminal (+) for receiving the reference voltage Vref, and an amplifier An integrated capacitor Cfb connected between the inverting input terminal (-) and the output terminal of the amplifier AMP and a switch SW connected to both ends of the integrating capacitor Cfb. The amplifier AMP operates as a unit gain buffer having a gain of 1 due to the turn-on of the switch SW in the initialization period. In the initialization period Tinit, the non-inverting input terminal (+) and the inverting input terminal (-) of the amplifier AMP are initialized to the reference voltage Vref + Vos including the offset value Vos. The offset value Vos is different for each amplifier AMP.

In the initialization period, a reference voltage (Vref + Vos) including an offset value is applied to the source electrode of the driving TFT, and a data voltage is applied to the gate electrode of the driving TFT through the data driving circuit. Thus, the source-drain current Ids corresponding to the potential difference (Vgs) between the gate electrode and the source electrode flows in the drive TFT. The same data voltage is applied to the gate electrode of the driving TFT for each pixel but a reference voltage Vref + Vos including different offsets is applied to the source node of the driving TFT, A deviation is generated in the potential difference (Vgs) between the source electrodes, and a deviation of the current flowing between the source electrode and the drain electrode by a different offset value is generated.

In this way, when compensating for deviating currents, deviations of different offset values are continuously generated even in the compensated data. Therefore, a line noise is generated between the lines arranged in the longitudinal direction due to the deviation of the current during the sensing period.

It is an object of the present invention to provide an organic light emitting diode display device capable of compensating a deviation of an offset value between current integrators to sense an accurate sensing value and compensating a panel with accurate sensing values to improve reliability of sensing and compensation And to provide a driving method thereof.

In order to achieve the above object, according to the present invention, there is provided an organic light emitting display device including a pixel having a driving transistor, an amplifier, a current integrator for sensing a current flowing through the driving transistor, The first reference voltage is applied to the non-inverting input terminal (+) of the inverting input terminal (-) and the second reference voltage applied to the inverting input terminal And an offset voltage control unit for applying the third reference voltage, from which the offset voltage of the amplifier is removed, to the non-inverting input terminal (+) of the amplifier at the first reference voltage.

The offset voltage control unit includes an offset capacitor connected between the third node and the fourth node, a first reference voltage input for inputting a first reference voltage, a first offset switch connected between the third node and the third node, A second offset switch connected between the four nodes, and a third offset switch connected between the inverting input terminal (-) of the amplifier and the fourth node.

The current integrator is configured such that the current received from the pixels is input to the inverting input terminal (-) connected to each pixel, and the first path and the first reference voltage or the third reference voltage are supplied to the non- And swaps the second path applied and applied to the input terminal (+).

A first sample & holder for sampling a first output voltage of the current integrator; and a second sample & holder for sampling a second output voltage of the current integrator output subsequent to the first output voltage, &Amp; & holders, a sampling unit for simultaneously outputting the sampled voltages through a single output channel, and an analog to digital converter (ADC) for converting voltages received from a single output channel of the sampling unit into digital sensing values and outputting the digital sensing values. .

The amplifier further includes a first external input terminal connected to the non-inverting input terminal (+) and directly connected to the sensing line, and a second external input terminal connected to the inverting input terminal (-) and directly connected to the offset voltage controlling unit , And a swapping unit connected between the first external input terminal and the non-inverted input terminal (+) and between the second external input terminal and the inverted input terminal (-) to swap the first path and the second path.

The swapping section includes a first swap switch operable to output a first output voltage obtained by adding an offset voltage to an output voltage output from the amplifier, and a second swap switch operative to output a second output voltage obtained by subtracting an offset voltage from the output voltage .

The first swap switch includes a first external input terminal, an eleventh swap switch and a second external input terminal connected to the inverting input terminal (-), and a twelfth swap switch connected to the non-inverting input terminal (+) , The second swap switch includes a second external input terminal, a twenty-second swap switch connected to the inverted input terminal (-), and a twenty-first swap switch connected to the first external input terminal and the non-inverted input terminal (+) , One end of the twelfth swap switch and one end of the twenty-second swap switch are connected, and one end of the twelfth swap switch and one end of the twenty-one swap switch are connected.

The first sample & holder is coupled between a first average capacitor storing a first output voltage output from the current integrator, a current integrator and a first averaging capacitor to control a first output voltage to be stored in a first averaging capacitor, A sample switch and a first holding switch connected between the first averaging capacitor and the analog-to-digital converter for controlling the first output voltage stored in the first averaging capacitor to be output through a single output channel, the second sample & A second sample switch connected between a second average capacitor for storing the second output voltage outputted from the integrator, the current integrator and the second average capacitor to control the second output voltage to be stored in the second average capacitor, A second output voltage, connected between the capacitor and the analog to digital converter, And a second holding switch for controlling the output through the channel.

The driving method of the present invention includes the steps of applying a first reference voltage to a non-inverting input terminal (+) of an amplifier during an initialization period for initializing a gate-source voltage of the driving transistor, applying a first reference voltage to the non- Applying a second reference voltage to the inverting input terminal (-) of the amplifier and, based on the second reference voltage, applying a third reference voltage from which the offset voltage of the amplifier is removed at the first reference voltage to the non- ). ≪ / RTI >

The initialization period includes a first initialization period and a second initialization period that is a period after the first initialization period. During the first initialization period, the first reference voltage is applied to the non-inverting input terminal (+) of the amplifier through the first offset switch, And a second reference voltage is stored in the offset capacitor through the third offset switch.

During the second initialization period, the second reference voltage applied to the fourth node through the third offset switch is lowered by the first reference voltage applied to the fourth node through the second offset switch to an offset voltage, The first reference voltage applied to the third node through the switch changes from the second reference voltage applied to the fourth node to the third reference voltage by the changed potential difference and the third reference voltage is applied to the non- +). ≪ / RTI >

When a third reference voltage is applied to the non-inverting input terminal (+) of the amplifier, a first reference voltage from which the offset voltage of the amplifier is removed may be applied to the source electrode of the driving transistor.

The first path and the first reference voltage or the third reference voltage, to which the current received from the pixels is input to the inverting input terminal (-) connected to each pixel, flows through the non-inverting input terminal (+) And swapping the second path.

The present invention compensates for the deviation of the offset value between the current integrators, thereby sensing a more accurate sensing value and compensating the panel with accurate sensing values, thereby greatly increasing the reliability of sensing and compensation.

In addition, the present invention realizes a low current and a high-speed sensing through a current sensing method using an electric current integrator in sensing electric characteristic deviations of a driving element, thereby greatly reducing sensing time.

Figure 1 shows a conventional current integrator applying a reference voltage to a pixel with an offset value during an initialization period.
2 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
3 is a view showing a pixel array formed on the display panel of Fig.
4 and 5 are views showing a connection structure and a sensing principle of a sensing block having an offset voltage control unit according to the present invention.
Figures 6 and 7 illustrate the operation of the offset voltage control of the present invention.
8 and 9 are views showing a connection structure and a sensing principle of a sensing block including an offset voltage control unit and a current integrator according to the present invention.
Figures 10A-11B illustrate the operation of the offset voltage control and current integrator of the present invention.
Figures 12 and 13 show offset voltage compensated according to the invention.
Fig. 14 is a diagram showing that line-like noise is removed between lines arranged in the longitudinal direction according to the present invention; Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 12. FIG.

FIG. 2 shows an organic light emitting display according to an embodiment of the present invention, and FIG. 3 shows a pixel array formed on the display panel of FIG.

2 and 3, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, 16).

A plurality of data lines and sensing lines 14A and 14B and a plurality of gate lines 15 are intersected with each other in the display panel 10 and pixels are arranged in a matrix do.

Each pixel P is connected to any one of the data lines 14A, to one of the sensing lines 14B and 14B, and to one of the gate lines 15. [ Each pixel P is electrically connected to the data line 14A in response to the gate pulse input through the gate line 15 to receive the data voltage from the data line 14A and to receive the data voltage via the sensing line 14B And outputs a sensing signal.

Each of the pixels P is supplied with a high potential drive voltage EVDD and a low potential drive voltage EVSS from a power supply not shown. The pixel P of the present invention may include an OLED, a driving TFT (Thin Film Transistor), a first and a second switching TFT (Thin Film Transistor), and a storage capacitor for external compensation. The thin film transistors (TFT) constituting the pixel P may be implemented as a p-type or an n-type. In addition, the semiconductor layer of the thin film transistors (TFT) constituting the pixel P may include amorphous silicon, polysilicon, or an oxide.

Each of the pixels P may operate differently at the time of normal driving for image implementation and at the time of sensing for sensing value acquisition. The sensing driving may be performed for a predetermined time prior to the normal driving, or may be performed during verticality blank periods during the normal driving.

The normal driving can be performed by the normal operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11. [ The sensing operation may be performed by the sensing operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11. [ The operation of deriving the compensation data for the deviation compensation based on the sensing result and the operation of modulating the digital video data using the compensation data are performed in the timing controller 11. [

The data driving circuit 12 includes at least one data driver IC (Integrated Circuit, SDIC). The data driver IC (SDIC) includes a plurality of digital-to-analog converters (DACs) connected to the respective data lines 14A, a plurality of sensing blocks connected to the sensing lines 14B, And a commonly connected analog-to-digital converter (hereinafter referred to as an ADC).

The DAC of the data driver IC (SDIC) converts digital video data (RGB) into image data voltage for data conversion in accordance with the data timing control signal (DDC) applied from the timing controller 11 during normal driving, . On the other hand, the DAC of the data driver IC (SDIC) generates the data voltage in accordance with the data timing control signal (DDC) applied from the timing controller 11 during the sensing operation.

Each sensing block of the data driver IC (SDIC) includes a current integrator (17, CI) for integrating the sensing signal of the pixel (P) inputted through the sensing line (14B), that is, the current between the source and the drain of the driving TFT, And a sampling unit (SH) for sampling and holding the output of the integrator (17, CI). The ADC of the data driver IC (SDIC) sequentially digitally processes the outputs of the sampling units (SH) and transmits them to the timing controller (11).

The gate drive circuit 13 generates an image display gate pulse on the basis of the gate control signal GDC during normal driving and then outputs the image display gate pulse to the gate lines (L # 1, L # 2, 15). The gate driving circuit 13 generates sensing gate pulses based on the gate control signal GDC during the sensing operation and then outputs the gate lines 15 (L # 1, L # 2, ...) ). The sensing gate pulse may have a longer on-pulse interval than the gate pulse for image display. One or more on-pulse sections of the sensing gate pulse may be included in one line sensing on-time. Here, the 1-line sensing on time means a scan time allocated to simultaneously sensing the pixels of the 1-row pixel line (L # 1, L # 2, ...).

The timing controller 11 controls the operation of the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE A data control signal DDC for controlling the timing and a gate control signal GDC for controlling the operation timing of the gate drive circuit 13 are generated. The timing controller 11 divides the normal driving and the sensing driving based on a predetermined reference signal (driving power enable signal, vertical synchronizing signal, data enable signal, etc.), and outputs the data control signal DDC and the gate And generates the control signal GDC. In addition, the timing controller 11 can generate additional control signals (RST, SAM, HOLD, and the like in Fig. 4) necessary for sensing driving.

The timing controller 11 can transmit the digital data corresponding to the sensing data voltage to the data driving circuit 12 during sensing driving. The timing controller 11 applies a digital sensing value SD transmitted from the data driving circuit 12 at the time of sensing driving to a previously stored compensation algorithm to derive a threshold voltage deviation Vth and a mobility deviation K And stores the compensation data in the memory 16 that can compensate for the deviations.

The timing controller 11 modulates the digital video data RGB for image implementation with reference to the compensation data and the offset value (or the offset voltage Vos) stored in the memory 16 during the normal driving, .

4 and 5 show the connection structure and sensing principle of the sensing block provided with the offset voltage control unit 18 of the present invention, and FIGS. 6 and 7 illustrate the operation of the offset voltage control unit 18 of the present invention Show. 4 and 5 are merely examples for helping to understand the driving of the current sensing method. The pixel structure to which the current sensing of the present invention is applied and the driving timing thereof can be variously modified, so that the technical idea of the present invention is not limited to this embodiment.

4, the pixel P of the present invention includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2 .

The OLED includes an anode electrode connected to the second node N2, a cathode electrode connected to the input terminal of the low potential driving voltage (EVSS), and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT DT controls the amount of current input to the OLED according to the gate-source voltage Vgs.

The driving TFT DT has a gate electrode connected to the first node N1, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the second node N2.

The storage capacitor Cst is connected between the first node N1 and the second node N2.

The first switch TFT (ST1) applies the data voltage (Vdata) on the data line (14A) to the first node (N1) in response to the gate pulse (SCAN). The first switch TFT ST1 has a gate electrode connected to the gate line 15, a drain electrode connected to the data line 14A, and a source electrode connected to the first node N1.

The second switch TFT (ST2) switches the current flow between the second node (N2) and the sensing line (14B) in response to the gate pulse (SCAN). Or the second switch TFT (ST2) switches to apply the first reference voltage to the second node (N2) in response to the gate pulse (SCAN). The second switch TFT ST2 has a gate electrode connected to the second gate line 15, a drain electrode connected to the sensing line 14B, and a source electrode connected to the second node N2.

The offset voltage controller 18 included in the sensing block of the present invention applies a first reference voltage to the non-inverting input terminal (+) of the amplifier (AMP) included in the current integrator 17, And the second reference voltage Vref + The third reference voltage Vref-Vos is applied again to the non-inverting input terminal (-) of the current integrator 17. [ Here, the second reference voltage Vref + Vos is a reference voltage to which the offset voltage Vos is added to the first reference voltage, and the third reference voltage Vref-Vos is the offset voltage of the amplifier AMP at the first reference voltage Vos).

The offset voltage control unit 18 includes an offset capacitor CAZ connected between the third node N3 and the fourth node N4, a first reference voltage input terminal receiving the first reference voltage, A second offset switch Q2 connected between the first reference voltage input terminal and the second node N2, and an inverting input terminal (-) of the amplifier AMP and a second offset switch Q2 connected between the first node Q1 and the second node N2, And a third offset switch (Q3) connected between the second switch (N2).

The offset voltage controller 18 detects the offset voltage Vos of the amplifier AMP using the first reference voltage input from the first reference voltage input terminal and outputs the detected offset voltage Vos to the first offset switch Q1 ) To the amplifier AMP through the switching operation of the third offset switch Q3 to cancel the detected offset voltage Vos. Accordingly, the offset voltage controller 18 can apply the first reference voltage obtained by removing the offset voltage Vos of the amplifier AMP to the source electrode of the driving TFT provided in the pixel.

The current integrator 17, CI included in the sensing block of the present invention is connected to the sensing line 14B and is connected to the inverting input terminal (-) receiving the current Ids between the source and the drain of the driving TFT from the sensing line 14B. An amplifier AMP including a non-inverting input terminal (+) receiving a first reference voltage Vref or a third reference voltage Vref-Vos and an output terminal Vout outputting an integral value Vsen, An integrating capacitor Cfb connected between the inverting input terminal (-) and the output terminal of the amplifier AMP and a first switch SW1 connected to both ends of the integrating capacitor Cfb.

The sampling section SH belonging to the sensing block of the present invention includes a sample switch SW2 switched in accordance with the sampling signal SAM, a holding switch SW3 switched in accordance with the holding signal HOLD, and a sample switch SW2 And a holding capacitor Ch having one end connected between the holding switch SW3 and the other end connected to the ground voltage source GND.

5 to 7 show one sensing waveform for each of the pixels in a one-line sensing on-time defined by the on-pulse interval of the sensing gate pulse SCAN for sensing pixels arranged in the same row have. Referring to FIG. 5, the sensing operation includes an initialization period (Tinit), a sensing period (Tsen), and a sampling period (Tsam).

The amplifier AMP operates as a unit gain buffer having a gain of 1 due to the turn-on of the first switch SW1 in the initialization period Tinit. The noninverting input terminal (+), the inverting input terminal (-), the sensing line 14B, and the second node N2 of the amplifier AMP in the initialization period Tinit are at the second reference voltage Vref + Vos And is initialized to the first reference voltage Vref. The initialization period Tinit includes a first initialization period Ti1 and a second initialization period Ti2 that is a period after the first initialization period Ti1.

Referring to FIG. 6, during the first setup period Ti1, the offset voltage controller 18 receives the first reference voltage from the first reference voltage input terminal. The first offset switch Q1 and the third offset switch Q3 provided in the offset voltage control unit 18 are simultaneously turned on and the second offset switch Q2 is turned off. The first reference voltage is applied to the non-inverting input terminal (+) of the amplifier AMP through the first offset switch Q1. A second reference voltage Vref + Vos, to which the offset voltage Vos of the amplifier AMP is added, is applied to the first reference voltage input through the non-inverting input terminal (+), . The second reference voltage Vref + Vos is stored in the offset capacitor CAZ via the third offset switch Q3 connected to the inverting input terminal (-) of the amplifier AMP. Accordingly, a first reference voltage is applied to the third node N3, and a second reference voltage Vref + Vos is applied to the fourth node N4. Therefore, a potential difference of the offset voltage Vos is generated between the third node N3 and the fourth node N4.

Referring to FIG. 7, during the second initialization period Ti2, the offset voltage controller 18 continuously receives the first reference voltage from the first reference voltage input terminal. The second offset switch Q2 provided in the offset voltage control unit 18 is turned on and the first offset switch Q1 and the third offset switch Q3 are simultaneously turned off. The first reference voltage is applied to the fourth node N4 through the second offset switch Q2. The second reference voltage Vref + Vos applied to the fourth node N4 is lowered by the offset voltage Vos by the first reference voltage applied through the second offset switch Q2. Thus, the fourth node N4 is lowered from the second reference voltage Vref + Vos to the first reference voltage.

At the same time, the third node N3 is coupled to the fourth node N4. The third node N3 changes by the potential difference of the fourth node N4. The first reference voltage applied to the third node N3 is lowered by the offset voltage Vos. Accordingly, a third reference voltage Vref-Vos obtained by subtracting the offset voltage Vos from the first reference voltage is applied to the third node N3. The third reference voltage Vref-Vos is applied to the non-inverting input terminal (+) of the amplifier AMP connected to the third node N3. The inverting input terminal (-) of the amplifier AMP is connected to the third reference voltage Vref-Vos inputted through the non-inverting input terminal (+), and the first reference voltage Vref-Vos added with the offset voltage Vos of the amplifier AMP . The first reference voltage is applied to the second node N2 through the sensing line 14B connected to the inverting input terminal (-) of the amplifier AMP. And the second node N2 is connected to the source electrode of the driving TFT provided in the pixel.

The data voltage is applied to the first node N1 while the first reference voltage is applied to the second node N2. The source-drain current Ids corresponding to the potential difference (Vdata-Vref) between the first node N1 and the second node N2 flows and is stabilized in the driving TFT DT.

The amplifier AMP operates as the current integrator 17 and CI to turn off the source-drain current Ids (Ids) flowing in the driving TFT DT due to the turn-off of the first switch SW1 in the sensing period Tsen ). The potential difference between the two ends of the integrating capacitor Cfb due to the current Ids flowing into the inverting input terminal (-) of the amplifier AMP in the sensing period Tsen becomes smaller as the sensing time elapses, that is, The larger it increases. Since the inverting input terminal (-) and the non-inverting input terminal (+) of the amplifier (AMP) are short-circuited through the virtual ground and the potential difference between them is zero, the inverting input terminal -) is maintained at the reference voltage Vref irrespective of the increase in the potential difference of the integrating capacitor Cfb. Instead, the output terminal potential of the amplifier AMP is lowered corresponding to the potential difference across the integrating capacitor Cfb. Under this principle, the current Ids flowing through the sensing line 14B in the sensing period Tsen is generated as an integral value Vsen which is a voltage value through the integrating capacitor Cfb. The lowering slope of the output value Vout of the current integrator 17 increases as the amount of current Ids flowing through the sensing line 14B increases, so that the magnitude of the integral value Vsen becomes smaller as the amount of current Ids becomes larger. In the sensing period Tsen, the integration value Vsen is stored in the holding capacitor Ch via the sample switch SW2.

When the holding switch SW3 is turned on in the sampling period Tsam, the integral value Vsen stored in the holding capacitor Ch is input to the ADC via the holding switch SW3. The integral value Vsen is converted from the ADC to the digital sensing value SD and then transmitted to the timing controller 11. [ The digital sensing value SD is used by the timing controller 11 to derive the threshold voltage deviation (Vth) and the mobility deviation (K) of the driving TFT. In the timing controller 11, the capacitance of the integral capacitor Cfb, the reference voltage Vref, and the sensing time Tsen are stored in advance in a digital code. Therefore, the timing controller 11 compares the source-drain current (Ids = Cfb * Vv / tt) flowing from the digital sensing value SD, which is a digital code for the integral value Vsen to the driving TFT DT, ㅿ V = Vref-Vsen, ㅿ t = Tsen) can be calculated.

The timing controller 11 applies the source-to-drain current Ids flowing in the driving TFT DT to the compensation algorithm to calculate deviation values (threshold voltage deviation (Vth) and mobility deviation (K)) and deviation compensation (Vth + [Delta] Vth, K + [Delta] K). The compensation algorithm may be implemented as a look-up table or computational logic. The capacitance of the integral capacitor Cfb included in the current integrator 17 or CI of the present invention is as small as one hundredth of the parasitic capacitance existing in the sensing line 14B, The time required for drawing the current Ids to the integrated value (Vsen) level is drastically shortened as compared with the conventional voltage sensing method. Further, in the conventional voltage sensing method, since the source voltage of the driving TFT is sampled at the sensing voltage after the source voltage of the driving TFT is sampled at the threshold voltage sensing, the sensing time becomes very long. In the current sensing method of the present invention, The source-drain current of the driving TFT can be integrated within a short time through the current sensing during the sensing, and the integrated value can be sampled, so that the sensing time can be greatly shortened.

Unlike the parasitic capacitors of the sensing line 14B, the integrated capacitor Cfb included in the current integrator 17, CI of the present invention does not change the stored value according to the display load, Acquisition is possible.

As described above, the current sensing method of the present invention is advantageous in that low current sensing is possible and high-speed sensing is possible as compared with the conventional voltage sensing method. The current sensing method of the present invention is also capable of sensing a plurality of times for each of the pixels within one line sensing on time in order to enhance the sensing performance.

The offset voltage control unit 18 is connected to the non-inverting input terminal (+) of the current integrator 17 to eliminate the offset voltage Vos of the amplifier AMP itself have. Accordingly, it is possible to uniformly output the panel driven through the current integrator 17 by eliminating the deviation between the channels.

FIGS. 8 and 9 show the connection structure and sensing principle of the sensing block with the offset voltage control unit and the current integrator of the present invention, FIGS. 10a to 11b show the operation of the offset voltage control unit and the current integrator of the present invention Show. 8 and 9 are merely examples for helping to understand the driving of the current sensing method. The pixel structure to which the current sensing of the present invention is applied and the driving timing thereof can be variously modified, so that the technical idea of the present invention is not limited to this embodiment.

In FIGS. 8 and 9, the contents overlapping with those described in FIGS. 4 and 5 will be omitted.

8, the pixel P of the present invention includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2 . A detailed description of the offset voltage control unit 18 provided in the sensing block has already been described with reference to FIG. 4, and will not be described here.

The amplifier AMP provided in the current integrator 17 (17, CI) is configured such that the current received from the pixels P is input to the inverting input terminal (-) connected to each pixel P, The path and the first reference voltage or the third reference voltage Vref-Vos are applied to the non-inverting input terminal (+) connected to the offset voltage control unit 18 to swap the second path. The amplifier AMP is connected to the first external input terminal IP1 and the inverting input terminal (-) which are connected to the non-inverting input terminal (+) and directly connected to the sensing line 14B, And a first path connected between the first external input terminal IP1 and the inverted input terminal (-) and a second path connected between the second external input terminal IP1 and the non-inverted input terminal (+), And a swapping unit 17a for swapping a second path connected between the swapping units 17a and 17b. The first path is connected between the first external input terminal IP1 and the inverted input terminal (-) under the control of the swapping portion 17a or connected between the first external input terminal IP1 and the non-inverted input terminal + do. Accordingly, the current received from the pixels can be applied to the inverting input terminal (-) through the first path or applied to the non-inverting input terminal (+).

The second path is connected between the second external input terminal IP2 and the non-inverted input terminal + under the control of the swapping portion 17a or connected between the second external input terminal IP2 and the inverted input terminal - do. Accordingly, the first reference voltage or the second reference voltage Vref + Vos may be applied to the non-inverting input terminal (+) or the inverting input terminal (-) through the first path.

The swapping unit 17a includes first swap switches S11 and S12 that are operated to output a first output voltage obtained by adding an offset voltage Vos to an output voltage output from the amplifier AMP, And second swap switches S21 and S22 that are operated to output a second output voltage obtained by subtracting the second output voltage.

The first swallowing switches S11 and S12 include an eleventh swirl switch S11 and a twelfth swage switch S12. The eleventh swap switch S11 is connected to the first external input terminal IP1 and the inverted input terminal (-) to form a first path. The twelfth swage switch S12 is connected to the second external input terminal IP2 and the non-inverted input terminal (+) to form a second path.

The second swap switches S21 and S22 include a twenty-first swap switch S21 and a twenty-second swap switch S22. The twenty-first swap switch S21 is connected to the first external input terminal IP1 and the non-inverted input terminal (+) to form a first path. The twenty-second swap switch S22 is connected to the second external input terminal S22 and the inverted input terminal (-) to form a second path. One end of the eleventh swap switch S11 is connected to the inverting input terminal (-) of the amplifier AMP and one end of the twenty-second swap switch S22. One end of the twelfth swage switch S12 is connected to the non-inverting input terminal (+) of the amplifier AMP and one end of the twenty-first swage switch S21.

The sampling section SH comprises a first sample & holder SH1 for sampling the first output voltage of the current integrator 17 and a second sample & And a second sample & holder SH2. The sampling unit SH outputs the sampled voltages to the first and second sample & holders SH1 and SH2 simultaneously through a single output channel.

The first sample & holder SH1 includes a first holding capacitor C1, a first sample switch SW21, and a first holding switch SW31. The first holding capacitor C1 stores the first output voltage output from the current integrator 17. [ The first sample switch SW21 is connected between the current integrator 17 and the first holding capacitor C1 to control the first output voltage to be stored in the first holding capacitor C1. The first sample switch SW21 stores the first output voltage outputted from the current integrator 17 in synchronism with the first swap switches S11 and S12 in the first holding capacitor C1. The first holding switch SW31 is connected between the first holding capacitor C1 and the analog-to-digital converter (ADC) to control the first output voltage stored in the first holding capacitor C1 to be output through a single output channel.

The second sample & holder SH2 includes a second holding capacitor C2, a second sample switch SW22, and a second holding switch SW32. The second holding capacitor C2 stores the second output voltage outputted from the current integrator 17. [ The second sample switch SW31 is connected between the current integrator 17 and the second holding capacitor C2 to control the second output voltage to be stored in the second holding capacitor C2. The second sample switch SW31 stores the second output voltage outputted from the current integrator 17 in synchronism with the second swage switches S21 and S22 in the second holding capacitor C2. The second holding switch SW32 is connected between the second holding capacitor C2 and the analog-to-digital converter (ADC) to control the second output voltage stored in the second holding capacitor C2 to be output through a single output channel.

The first holding switch SW31 and the second holding switch SW32 are turned on at the same time to turn on the first output voltage stored in the first holding capacitor C1 and the second output voltage stored in the second holding capacitor C2 The output voltage is output simultaneously through a single output channel. 8, the first holding switch SW31 and the second holding switch SW32 are separated from each other. However, the present invention is not limited thereto, and the first holding switch SW31 and the second holding switch SW32 may be one holding Switch.

An analog to digital converter (ADC) converts a voltage received from a single output channel of the sampling unit (SH) into a digital sensing value and outputs the digital sensing value.

9 to 11B show one sensing waveform for each of the pixels in a one line sensing on time defined by the ON pulse interval of the sensing gate pulse SCAN for sensing pixels arranged in the same row have. Referring to FIG. 9, the sensing drive may be composed of a first state and a second state. The first state is a period during which the first output voltage is outputted through the current integrator 17 and the second state is a period during which the second output voltage is outputted through the current integrator 17. [ The first output voltage is a voltage obtained by adding an offset voltage (Vos) to an output voltage to be output, and the second output voltage is defined as a voltage in which an offset voltage (Vos) is missing from an output voltage to be output.

Each of the first state and the second state includes an initialization period (Tinit), a sensing period (Tsen), and a sampling period (Tsam).

The amplifier AMP operates as a unit gain buffer having a gain of 1 due to the turn-on of the first switch SW1 in the initialization period Tinit of the first state. The first external input terminal IP1, the second external input terminal IP2, the sensing line 14B and the second node N2 of the amplifier AMP are turned off at the second reference voltage Vref + Vos to the first reference voltage Vref. The initialization period Tinit includes a first initialization period Ti1 and a second initialization period Ti2 that is a period after the first initialization period Ti1.

Referring to FIG. 10A, during the first setup period Ti1, the offset voltage controller 18 receives the first reference voltage from the first reference voltage input terminal. The first offset switch Q1 and the third offset switch Q3 provided in the offset voltage control unit 18 are simultaneously turned on and the second offset switch Q2 is turned off. The first swab switches S11 and S12 are turned on and the second swab switches S21 and S22 are turned off.

The twelfth swage switch S12 is connected to the second external input terminal IP2 and the non-inverted input terminal (+) to form a second path. The first reference voltage is applied to the second external input terminal IP2 of the amplifier AMP through the first offset switch Q1 and is input to the non-inverting input terminal + through the second path.

The eleventh swap switch S11 is connected to the first external input terminal IP1 and the inverted input terminal (-) to form a first path. A second reference voltage Vref added to the first reference voltage input through the second external input terminal IP2 and an offset voltage Vos of the amplifier AMP is applied to the first external input terminal IP1 of the amplifier AMP, + Vos) is applied through the first path. The second reference voltage Vref + Vos is stored in the offset capacitor CAZ through the third offset switch Q3 connected to the first external input terminal IP1 of the amplifier AMP. Accordingly, a first reference voltage is applied to the third node N3, and a second reference voltage Vref + Vos is applied to the fourth node N4. Therefore, a potential difference of the offset voltage Vos is generated between the third node N3 and the fourth node N4.

Referring to FIG. 10B, during the second initialization period Ti2, the offset voltage controller 18 continuously receives the first reference voltage from the first reference voltage input terminal. The second offset switch Q2 provided in the offset voltage control unit 18 is turned on and the first offset switch Q1 and the third offset switch Q3 are simultaneously turned off. The first swab switches S11 and S12 are turned on and the second swab switches S21 and S22 are turned off. The twelfth swage switch S12 is connected to the second external input terminal IP2 and the non-inverted input terminal (+) to form a second path.

The first reference voltage is applied to the fourth node N4 through the second offset switch Q2. The second reference voltage Vref + Vos applied to the fourth node N4 is lowered by the offset voltage Vos by the first reference voltage applied through the second offset switch Q2. Thus, the fourth node N4 is lowered from the second reference voltage Vref + Vos to the first reference voltage.

At the same time, the third node N3 is coupled to the fourth node N4. The third node N3 changes by the potential difference of the fourth node N4. The first reference voltage applied to the third node N3 is lowered by the offset voltage Vos. Accordingly, a third reference voltage Vref-Vos obtained by subtracting the offset voltage Vos from the first reference voltage is applied to the third node N3. The third reference voltage Vref-Vos is applied to the second external input terminal IP2 of the amplifier AMP connected to the third node N3 and inputted to the non-inverting input terminal + through the second path do.

The eleventh swap switch S11 is connected to the first external input terminal IP1 and the inverted input terminal (-) to form a first path. The first external input terminal IP1 of the amplifier AMP is connected to the third reference voltage Vref-Vos inputted through the non-inverting input terminal + A reference voltage is applied across the first path. The first reference voltage is applied to the second node N2 through the sensing line 14B connected to the inverting input terminal (-) of the amplifier AMP. And the second node N2 is connected to the source electrode of the driving TFT provided in the pixel.

The data voltage is applied to the first node N1 while the first reference voltage is applied to the second node N2. The source-drain current Ids corresponding to the potential difference (Vdata-Vref) between the first node N1 and the second node N2 flows and is stabilized in the driving TFT DT. However, during the initialization period Tinit, the amplifier AMP continues to operate as a unit gain buffer, so that the output terminal is maintained at the reference voltage Vref.

The amplifier AMP operates as the current integrator 17 and CI to turn off the source-drain current Ids (Ids) flowing in the driving TFT DT due to the turn-off of the first switch SW1 in the sensing period Tsen ). The potential difference between the ends of the integrating capacitor Cfb due to the current Ids flowing into the first external input terminal IP1 of the amplifier AMP in the sensing period Tsen becomes longer as the sensing time elapses, ) Increases. However, due to the characteristics of the amplifier AMP, it is ideal that the inverting input terminal (-) and the non-inverting input terminal (+) are short-circuited through a virtual ground so that the potential difference between them is zero, but substantially the offset voltage Vos ) ≪ / RTI > Accordingly, the potential of the inverting input terminal (-) in the sensing period Tsen becomes the second reference voltage Vref + Vos obtained by adding the offset voltage Vos to the reference voltage Vref regardless of the increase in the potential difference of the integrating capacitor Cfb. ≪ / RTI > Instead, the output terminal potential of the amplifier AMP is lowered corresponding to the potential difference across the integrating capacitor Cfb. With this principle, the current Ids flowing through the sensing line 14B in the sensing period Tsen is generated as the first integrated value Vsen1 which is the voltage value through the integrating capacitor Cfb. Here, the first integral value is defined as a first output voltage obtained by adding the offset voltage Vos. The lowering slope of the output value Vout output from the current integrator 17 increases as the amount of current Ids flowing through the sensing line 14B increases, so that the magnitude of the first integral value Vsen1 increases as the amount of current Ids increases Lt; / RTI > In the sensing period Tsen, the integration value Vsen is stored in the first holding capacitor C1 via the first sample switch SW21.

The amplifier AMP operates as a unit gain buffer having a gain of 1 due to the turn-on of the first switch SW1 in the initialization period Tinit of the second state. The first external input terminal IP1, the second external input terminal IP2, the sensing line 14B and the second node N2 of the amplifier AMP are turned off at the second reference voltage Vref + Vos to the first reference voltage Vref.

Referring to FIG. 11A, during the first setup period Ti1, the offset voltage controller 18 receives the first reference voltage from the first reference voltage input terminal. The first offset switch Q1 and the third offset switch Q3 provided in the offset voltage control unit 18 are simultaneously turned on and the second offset switch Q2 is turned off. The second swab switches S21 and S22 are turned on and the first swab switches S11 and S12 are turned off.

The twenty-second swap switch S22 is connected to the second external input terminal IP2 and the inverted input terminal (-) to form a second path. The first reference voltage is applied to the second external input terminal IP2 of the amplifier AMP through the first offset switch Q1 and input to the inverting input terminal - through the second path.

The twenty-first swap switch S21 is connected to the first external input terminal IP1 and the non-inverted input terminal (+) to form a first path. A third reference voltage Vref-1 is obtained by subtracting the offset voltage Vos of the amplifier AMP from the first reference voltage inputted through the inverting input terminal (-) to the first external input terminal IP1 of the amplifier AMP. Vos) is applied through the first path. The third reference voltage Vref-Vos is stored in the offset capacitor CAZ through the third offset switch Q3 connected to the first external input terminal IP1 of the amplifier AMP. Accordingly, a first reference voltage is applied to the third node N3, and a third reference voltage Vref-Vos is applied to the fourth node N4. Therefore, a potential difference of the offset voltage Vos is generated between the third node N3 and the fourth node N4.

Referring to FIG. 10B, during the second initialization period Ti2, the offset voltage controller 18 continuously receives the first reference voltage from the first reference voltage input terminal. The second offset switch Q2 provided in the offset voltage control unit 18 is turned on and the first offset switch Q1 and the third offset switch Q3 are simultaneously turned off. The second swab switches S21 and S22 are turned on and the first swab switches S11 and S12 are turned off. The twenty-second swap switch S12 is connected to the second external input terminal IP2 and the inverted input terminal (-) to form a second path.

The first reference voltage is applied to the fourth node N4 through the second offset switch Q2. The third reference voltage Vref-Vos applied to the fourth node N4 is increased by the offset voltage Vos by the first reference voltage applied through the second offset switch Q2. Accordingly, the fourth node N4 is raised from the third reference voltage Vref-Vos to the first reference voltage.

At the same time, the third node N3 is coupled to the fourth node N4. The third node N3 changes by the potential difference of the fourth node N4. The first reference voltage applied to the third node N3 is increased by the offset voltage Vos. Accordingly, the second reference voltage Vref + Vos obtained by adding the offset voltage Vos to the first reference voltage is applied to the third node N3. The second reference voltage Vref + Vos is applied to the second external input terminal IP2 of the amplifier AMP connected to the third node N3 and inputted to the inverting input terminal - through the second path .

The twenty-first swap switch S11 is connected to the first external input terminal IP1 and the non-inverted input terminal (+) to form a first path. The offset voltage Vos of the amplifier AMP is removed from the first external input terminal IP1 of the amplifier AMP to the second reference voltage Vref + Vos input through the second external input terminal IP2 A first reference voltage is applied across the first path. The first reference voltage is applied to the second node N2 through the sensing line 14B connected to the first external input terminal IP1 of the amplifier AMP. And the second node N2 is connected to the source electrode of the driving TFT provided in the pixel.

The data voltage is applied to the first node N1 while the first reference voltage is applied to the second node N2. The source-drain current Ids corresponding to the potential difference (Vdata-Vref) between the first node N1 and the second node N2 flows and is stabilized in the driving TFT DT.

The amplifier AMP operates as the current integrator 17 and CI to turn off the source-drain current Ids (Ids) flowing in the driving TFT DT due to the turn-off of the first switch SW1 in the sensing period Tsen ). The potential difference between the ends of the integrating capacitor Cfb due to the current Ids flowing into the first external input terminal IP1 of the amplifier AMP in the sensing period Tsen becomes longer as the sensing time elapses, ) Increases. However, due to the characteristics of the amplifier AMP, it is ideal that the inverting input terminal (-) and the non-inverting input terminal (+) are short-circuited through a virtual ground so that the potential difference between them is zero, but substantially the offset voltage Vos ) ≪ / RTI > Accordingly, the potential of the inverting input terminal (-) in the sensing period Tsen becomes equal to the third reference voltage Vref-Vos which is obtained by removing the offset voltage Vos from the reference voltage Vref irrespective of the increase in the potential difference of the integrating capacitor Cfb. ≪ / RTI > Instead, the output terminal potential of the amplifier AMP is lowered corresponding to the potential difference across the integrating capacitor Cfb. On the basis of this principle, the current Ids flowing through the sensing line 14B in the sensing period Tsen is generated as the second integral value Vsen2 which is the voltage value through the integrating capacitor Cfb. Here, the second integral value is defined as a second output voltage from which the offset voltage Vos is removed. Since the descending slope of the output value Vout output from the current integrator 17 increases as the amount of current Ids flowing through the sensing line 14B increases, the magnitude of the second integral value Vsen2 increases as the current amount Ids increases, Lt; / RTI > In the sensing period Tsen, the integration value Vsen is stored in the second holding capacitor C2 via the second sample switch SW22.

When the first holding switch SW31 and the second holding switch SW32 are turned on simultaneously in the sampling period Tsam, the first integral value Vsen1 stored in the first holding capacitor C1 becomes the first The second integration value Vsen2 stored in the second holding capacitor C2 is simultaneously output via the second holding switch SW32 through the single output channel via the holding switch SW31. As described above, the first integral value Vsen1 and the second integral value Vsen2 can be averaged and distributed by simultaneously outputting through a single output channel. Accordingly, the first integral value Vsen1 and the second integral value Vsen2 are sampled as an averaged integral value and input to the ADC through a single output channel. The ADC digitally processes the integrated value Vsen sampled with the averaged integral value Vsen output from the sampling unit SH to generate digital sensing values for offset correction of the offset voltage Vos, Lt; / RTI > The timing controller 11 calculates the deviation of the offset voltage Vos between the current integrators 17 and CI based on the digital sensing values for correcting the offset voltage Vos and outputs the calculated deviation values You can compensate. The digital sensing value SD is used to derive the threshold voltage deviation (Vth) and the mobility deviation (K) of the driving TFT in the timing controller (11). In the timing controller 11, the capacitance of the integral capacitor Cfb, the reference voltage Vref, and the sensing time Tsen are stored in advance in a digital code. Therefore, the timing controller 11 calculates the source-drain current (Ids = Cfb * Vv / t, t) flowing from the digital sensing value SD, which is a digital code to the averaged integration value Vsen, Here, ㅿ V = Vref-Vsen, ㅿ t = Tsen) can be calculated.

The timing controller 11 applies the source-to-drain current Ids flowing in the driving TFT DT to the compensation algorithm to calculate deviation values (threshold voltage deviation (Vth) and mobility deviation (K)) and deviation compensation (Vth + [Delta] Vth, K + [Delta] K). The compensation algorithm may be implemented as a look-up table or computational logic.

The capacitance of the integral capacitor Cfb included in the current integrator 17 or CI of the present invention is as small as one hundredth of the parasitic capacitance existing in the sensing line 14B, The time required for drawing the current Ids to the integrated value (Vsen) level is drastically shortened as compared with the conventional voltage sensing method. Further, in the conventional voltage sensing method, since the source voltage of the driving TFT is sampled at the sensing voltage after the source voltage of the driving TFT is sampled at the threshold voltage sensing, the sensing time becomes very long. In the current sensing method of the present invention, The source-drain current of the driving TFT can be integrated within a short time through the current sensing during the sensing, and the integrated value can be sampled, so that the sensing time can be greatly shortened.

Unlike the parasitic capacitors of the sensing line 14B, the integrated capacitor Cfb included in the current integrator 17, CI of the present invention does not change the stored value according to the display load, Acquisition is possible.

The present invention also compensates for the deviation of the offset voltage of the current integrator 17, CI through the offset voltage control unit 18, the swapping unit 17a incorporated in the amplifier AMP and the sampling unit SH By outputting the sampled integral value within the set error range, more accurate sensing value acquisition is possible.

As described above, the current sensing method of the present invention is advantageous in that low current sensing is possible and high-speed sensing is possible as compared with the conventional voltage sensing method. The current sensing method of the present invention is also capable of sensing a plurality of times for each of the pixels within one line sensing on time in order to enhance the sensing performance.

FIGS. 12 and 13 show offset voltages compensated in accordance with the present invention, and FIG. 14 shows that line noise is removed between lines arranged in the longitudinal direction according to the present invention.

12A shows a method of reducing the offset voltage Vos of the amplifier AMP using the offset voltage control unit 18 according to the embodiment of the present invention. The offset voltage control unit 18 applies a first reference voltage to the non-inverting input terminal (+) of the amplifier AMP provided in the current integrator 17 and applies a second reference voltage (-) applied to the inverting input terminal Vref + Vos), and based on this feedback The third reference voltage Vref-Vos is applied again to the non-inverting input terminal (-) of the current integrator 17. [ The offset voltage control unit 18 switches the first to third offset switches Q1 to Q3 to detect the offset voltage Vos of the amplifier AMP and detects the offset voltage Vos of the amplifier AMP The offset voltage Vos of the amplifier AMP can be easily removed by feeding back the offset voltage Vos.

13, the integral value output through the conventional current integrator not using the offset voltage control unit 18 is the sum of the offset voltage Vos of the amplifier AMP and the minimum output voltage of -50 mV , And has an error range of maximum output voltage + 50 mV. When the offset voltage (Vos) of the amplifier (AMP) is applied as it is, a difference of 100 mV occurs between the maximum output voltage and the minimum output voltage. As shown in FIG. 14 (a), since a current deviation between the channels is largely generated during the sensing period, a line noise is generated between the lines arranged in the vertical direction, and an accurate sensing value is obtained I can not.

Alternatively, the integral value output through the current integrator of the present invention to which the offset voltage control unit 18 is applied can minimize the offset voltage Vos of the amplifier AMP, so that the minimum output voltage is -11 mV, The maximum output voltage has an error range of + 11mV. The offset voltage Vos of the amplifier AMP is removed by applying the offset voltage control unit 18 so that a difference of 22 mV occurs between the maximum output voltage and the minimum output voltage. Therefore, it can be seen that 78% is improved to obtain a more accurate sensing value than the prior art.

FIG. 12 (b) shows the use of the swapping portion 17a according to the embodiment of the present invention to reduce the offset voltage Vos of the amplifier AMP.

The swapping unit 17a swaps the first path applied through the first external input terminal and the second path applied through the second external input terminal so that the first path summed from the output voltage output through the output terminal And the second output voltage obtained by removing the offset voltage from the output voltage is added and distributed. As described above, the current integrator of the present invention can easily remove the offset voltage Vos of the amplifier AMP by outputting the average output voltage through the swapping portion 17a.

The integral value output through the current integrator of the present invention to which the swapping portion 17a is applied can minimize the offset voltage Vos of the amplifier AMP, and the minimum output voltage is -8 mV and the maximum output voltage + And has an error range of 8 mV. The offset voltage Vos of the amplifier AMP is removed by applying the offset voltage control unit 18 so that a difference of 16 mV occurs between the maximum output voltage and the minimum output voltage. Thus, it can be seen that 84% is improved to obtain a more accurate sensing value than the prior art.

12C shows that the offset voltage Vos of the amplifier AMP is reduced using the offset voltage control unit 18 and the swapping unit 17a according to the embodiment of the present invention.

12A and 12B, when the offset voltage control unit 18 and the swapping unit 17a are used together, the integrated value output through the current integrator of the present invention is amplified by the amplifier AMP The offset voltage Vos can be substantially eliminated. Accordingly, the integral value has a minimum output voltage of -6 mV and an error range of maximum output voltage + 6 mV. The offset voltage Vos of the amplifier AMP is removed by applying the offset voltage control unit 18 and the swapping unit 17a at the same time so that a difference of 12 mV occurs between the maximum output voltage and the minimum output voltage. It can be seen that 88% is improved to obtain a more accurate sensing value than the conventional one.

As described above, the present invention can maintain the gate-source voltage Vgs of the driving TFT constant by removing the offset voltage Vos of the amplifier AMP. The present invention can more accurately sense the sensing value by easily removing the offset voltage (Vos) of the amplifier (AMP) and keeping the gate-source voltage (Vgs) of the driving TFT substantially constant. By compensating the panel with accurate sensing values, the reliability of sensing and compensation can be greatly enhanced.

14 (b), the present invention easily removes the offset value and maintains the gate-source voltage (Vgs) of the driving TFT substantially constant so that during the sensing period, It is possible to eliminate the deviation of the current between the electrodes. As a result, line noise can be prevented from being generated between the lines arranged in the longitudinal direction.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14A, 14B: data lines 15: gate lines
17: Current integrator 17a: Swapping part
18: Offset voltage control section

Claims (13)

A pixel having a driving transistor;
A current integrator having an amplifier and sensing a current flowing in the driving transistor; And
During the initialization period for initializing the gate-source voltage of the driving transistor, a first reference voltage is applied to the non-inverting input terminal (+) of the amplifier, and the first reference voltage applied to the inverting input terminal An offset voltage control unit for applying a third reference voltage obtained by removing an offset voltage of the amplifier from the first reference voltage to the non-inverting input terminal (+) of the amplifier based on a second reference voltage to which an offset voltage is added to the voltage;
And an organic light emitting diode (OLED). The method according to claim 1,
The offset voltage control unit
An offset capacitor connected between the third node and the fourth node;
A first offset switch connected between the third node and a first reference voltage input for inputting the first reference voltage;
A second offset switch connected between the first reference voltage input and the fourth node; And
And a third offset switch connected between the inverting input terminal (-) of the amplifier and the fourth node. 3. The method according to claim 1 or 2,
The amplifier
A first path through which the current received from the pixels is input to the inverting input terminal (-) connected to each pixel and the first reference voltage or the third reference voltage is connected to the offset voltage control section And swaps a second path that is applied to the non-inverted input terminal (+). The method of claim 3,
A first sample & holder for sampling a first output voltage of the current integrator; and a second sample & holder for sampling a second output voltage of the current integrator output following the first output voltage, And a sampling unit for simultaneously outputting the sampled voltages to the second sample & holders through a single output channel; And
An analog to digital converter (ADC) converting a voltage received from a single output channel of the sampling unit into a digital sensing value and outputting the digital sensing value;
And an organic light emitting diode (OLED). The method of claim 3,
The amplifier
A first external input terminal connected to the non-inverting input terminal (+) and directly connected to the sensing line, and a second external input terminal connected to the inverting input terminal (-) and directly connected to the offset voltage controlling unit and,
A swapping unit connected between the first external input terminal and the non-inverting input terminal (+), and between the second external input terminal and the inverting input terminal (-) to swap the first path and the second path, And the organic light emitting display device. 6. The method of claim 5,
The swapping unit
A first swap switch operative to output the first output voltage obtained by adding the offset voltage to an output voltage output from the amplifier;
And a second swap switch operative to output the second output voltage obtained by subtracting the offset voltage from the output voltage. The method according to claim 6,
The first swap switch
An 11th swap switch connected to the first external input terminal and the inverted input terminal (-); And a twelfth swap switch connected to the second external input terminal and the non-inverted input terminal (+),
The second swap switch
A twenty-second swap switch connected to the second external input terminal and the inverted input terminal (-); And a twenty-first swage switch connected to the first external input terminal and the non-inverted input terminal (+),
One end of the twelfth swap switch is connected to one end of the twelfth swap switch and one end of the twelfth swap switch is connected to one end of the twenty-first swap switch. 5. The method of claim 4,
The first sample &
A first average capacitor for storing the first output voltage outputted from the current integrator, and a second average capacitor connected between the current integrator and the first average capacitor, for controlling the first output voltage to be stored in the first average capacitor 1 sample switch; And a first holding switch connected between the first average capacitor and the analog-to-digital converter for controlling the first output voltage stored in the first average capacitor to be output through the single output channel,
The second sample &
A second average capacitor connected between the current integrator and the second average capacitor to control the second output voltage to be stored in the second average capacitor; a second average capacitor for storing the second output voltage outputted from the current integrator; 2 sample switches; And a second holding switch connected between the second average capacitor and the analog-to-digital converter for controlling the second output voltage stored in the second average capacitor to be output through the single output channel, . A driving method of an organic light emitting display device including a pixel having a driving transistor,
Applying a first reference voltage to the non-inverting input terminal (+) of the amplifier during an initialization period to initialize the gate-source voltage of the driving transistor, and
Applying a second reference voltage having an offset voltage to the first reference voltage to an inverting input terminal (-) of the amplifier, and
And applying a third reference voltage, from which the offset voltage of the amplifier is removed at the first reference voltage, to the non-inverting input terminal (+) of the amplifier based on the second reference voltage, Driving method. 10. The method of claim 9,
Wherein the initialization period includes a first initialization period and a second initialization period that is a period after the first initialization period,
During the first initialization period,
The first reference voltage is applied to the non-inverting input terminal (+) of the amplifier through a first offset switch,
And the second reference voltage is stored in an offset capacitor through a third offset switch. 11. The method of claim 10,
During the second initialization period,
The second reference voltage applied to the fourth node through the third offset switch is lowered by the first reference voltage applied to the fourth node through the second offset switch by the offset voltage,
The first reference voltage applied to the third node through the first offset switch is changed to the third reference voltage by the changed potential difference of the second reference voltage applied to the fourth node,
And the third reference voltage is applied to the non-inverting input terminal (+) of the amplifier. 12. The method of claim 11,
Wherein the first reference voltage from which the offset voltage of the amplifier is removed is applied to the source electrode of the driving transistor when the third reference voltage is applied to the non-inverting input terminal (+) of the amplifier . 13. The method according to any one of claims 9 to 12,
A first path through which a current received from the pixels is input to the inverting input terminal (-) connected to each of the pixels and the first reference voltage or the third reference voltage is applied to the non-inverting input terminal + ≪ / RTI > to swap the flowing second path.

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