KR20170080433A - Methods of Reading-out Data from Synapses of Neuromorphic Device - Google Patents

Abstract

A method of reading data from a synapse that includes a variable resistor having a gate electrode, a transistor having a first electrode, and a second electrode, and a first electrode coupled to a second electrode of the transistor is described. The data readout method comprising applying a read voltage to the gate electrode of the transistor, applying a pre-synaptic voltage to the first electrode of the transistor, and applying a post-synaptic voltage to the second electrode of the variable resistor . The read voltage may be lower than the threshold voltage of the transistor.

Description

Methods for Reading Data from Synapses of Nyomorphic Devices {Methods of Reading-Out Data from Synapses of Neuromorphic Device}

The present invention relates to a method of reading data from a synapse of a neuromorph element and more particularly to a method of reading data in a sub-threshold voltage region.

Recently, NyomopliK technology, which mimics the human brain, is attracting attention. The neuromotor technology includes multiple pre-synaptic neurons, multiple post-synaptic neurons, and multiple synapses. The neuromorph elements used in the neuromotor technology output pulses or spikes at various levels, sizes, or times depending on the learned state. Synaptics of the neuromorphic device can store multi-level data. For example, depending on the level of learning, rather than 1 and 0, you can store data at intermediate levels to store strong or weak learning levels. Therefore, when reading data from a synapse, it is advantageous that the output current value has a large difference in accordance with the resistance change.

A problem to be solved by the present invention is to provide a method for reading data from synapses of a neuromorphic device.

A problem to be solved by the present invention is to provide a method of reading data from a synapse in a sub-threshold voltage range.

The problem to be solved by the present invention is to provide a method of implementing excitatory synapses and inhibitory synapses in a read mode.

The various problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A method for reading data from a synapse of a neuromorph element according to an embodiment of the present invention includes a transistor having a gate electrode, a first electrode, and a second electrode, and a transistor connected to the second electrode of the transistor, Preparing a synapse comprising a variable resistor having one electrode, applying a read voltage to the gate electrode of the transistor, applying a pre-synaptic voltage to the first electrode of the transistor, and applying a pre- And applying a post-synaptic voltage to the electrode. The read voltage may be lower than the threshold voltage of the transistor.

The post-synaptic voltage may be zero.

The absolute value of the difference between the readout voltage and the post-synaptic voltage may be less than the threshold voltage.

The pre-synaptic voltage may be a positive voltage.

The readout voltage may be a positive voltage.

The pre-synaptic voltage may be higher than the read voltage.

The absolute value of the difference between the read voltage and the pre-synaptic voltage may be less than the threshold voltage.

The pre-synaptic voltage may be a negative voltage.

The readout voltage may be negative (-).

The pre-synaptic voltage may be lower than the read voltage.

A method for reading data from a synapse of a neuromorph element according to an embodiment of the present invention includes a transistor having a gate electrode, a first electrode, and a second electrode, and a transistor connected to the second electrode of the transistor, (+) Read voltage lower than the threshold voltage of the transistor to the gate electrode of the transistor through a gating line from a gating controller, and applying a pre-synaptic neuron Applying a positive (+) pre-synaptic voltage to the first electrode of the transistor from the post-synaptic neuron through a low line, and applying a post-synaptic voltage to the second electrode of the variable resistor from the post- Lt; / RTI >

The absolute value of the difference between the readout voltage and the post-synaptic voltage may be less than the threshold voltage.

The post-synaptic voltage may be zero.

The difference between the pre-synaptic voltage and the post-synaptic voltage may be greater than the threshold voltage.

A method for reading data from a synapse of a neuromorph element according to an embodiment of the present invention includes a transistor having a gate electrode, a first electrode, and a second electrode, and a transistor connected to the second electrode of the transistor, The method comprising: providing a synapse comprising a variable resistor having one electrode, applying a read voltage lower than the threshold voltage of the transistor from the gating controller to the gate electrode of the transistor through a gating line, Applying a negative (-) pre-synaptic voltage to the first electrode of the transistor, and applying a post-synaptic voltage from the post-synaptic neuron to the second electrode of the variable resistor through a column line have.

The absolute value of the difference between the read voltage and the pre-synaptic voltage may be less than the threshold voltage.

The readout voltage may be a positive voltage.

The readout voltage may be negative (-).

The post-synaptic voltage may be zero.

The difference between the pre-synaptic voltage and the post-synaptic voltage may be greater than the threshold voltage.

The details of other embodiments are included in the detailed description and drawings.

According to the technical idea of the present invention, the difference in the current read out due to the resistance difference of the memristor is large, so that the data sensing margin can be improved.

According to the technical idea of the present invention, accurate data can be read since the difference in the current read out due to the resistance difference of the memristor is large.

According to the technical idea of the present invention, the excitatory synaptic action and the inhibitory synaptic action can be performed independently and concurrently.

The effects of various embodiments of the present invention not otherwise mentioned will be mentioned in the text.

Figs. 1A to 1C are block diagrams conceptually showing neuromorph elements according to various embodiments of the technical idea of the present invention.
2 is a block diagram illustrating in detail a synapse of a neuromorph element according to an embodiment of the present invention.
FIG. 3A is a conceptual block diagram illustrating learning of a synapse 30 of a neuromorph element according to an embodiment of the present invention, and FIG. 3B is a conceptual block diagram illustrating learning voltage V _LN , pre- A voltage V1, and a post-synaptic voltage V2.
Figures 4a and 5a are conceptual block diagrams illustrating the reading of the learned data pattern at the synapses of a neuromorph element according to embodiments of the present invention and Figures 4b and 5b show conceptual block diagrams These are graphs that conceptually show current.
FIG. 6 is a conceptual block diagram illustrating the reading of learned data patterns in synapses of a neuromorph element according to an embodiment of the present invention.
7 is a block diagram conceptually illustrating a synaptic array system of a neuromorph element according to an embodiment of the present invention.
FIG. 8 is a block diagram conceptually showing a pattern recognition system according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

It is to be understood that one element is referred to as being 'connected to' or 'coupled to' another element when it is directly coupled or coupled to another element, One case. On the other hand, when one element is referred to as being 'directly connected to' or 'directly coupled to' another element, it does not intervene another element in the middle. &Quot; and / or " include each and every one or more combinations of the mentioned items.

Spatially relative terms such as 'below', 'beneath', 'lower', 'above' and 'upper' May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figure, an element described as 'below' or 'beneath' of another element may be placed 'above' another element.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

In this specification, the terms potentiation, set, and learning are used in the same or similar terms, and depressing, resetting, and initiation are used in the same or similar sense will be. For example, the action of lowering the resistance of the synapses will be described as enhancement, set, or learning, and the action of increasing the resistance of the synapses will be described as suppression, reset, or initialization. Also, when the synapses are enriched, set, or learned, the conductivity is increased, so that a progressively higher voltage / current can be output, and as the synapses are suppressed, reset, or initialized, . For ease of explanation, data patterns, electrical signals, pulses, spikes, and fire can be interpreted to be the same, similar, or compatible meanings. Also, voltage and current can be interpreted to be the same or compatible.

Figs. 1A to 1C are block diagrams conceptually showing neuromorph elements according to various embodiments of the technical idea of the present invention.

1A, a neuromorph element according to an exemplary embodiment of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, and post-synaptic neurons 20_1 to 20_n, column lines 25_1 to 25_n, synapses 30_11 to 30_nn, row gating controllers 41_1 to 41_n, and row gating lines 46_1 to 46_n. The row lines 15_1 to 15_n and the row gating lines 46_1 to 46_n may be parallel.

The pre-synaptic neurons 10_1 to 10_n are connected to the synapses 30_11 to 30_nn through the row lines 15_1 to 15_n in a learning mode, a reset mode, or a reading mode, Lt; / RTI >

The post-synaptic neurons 20_1 to 20_n can transmit electrical pulses to the synapses 30_1 to 30_n through the column lines 25_1 to 25_n in the learning mode or the reset mode, 25_1 through 25_n) from the synapses 30_1 through 30_n.

The row lines 15_1 to 15_n may extend in a row direction from one of the pre-synaptic neurons 10_1 to 10_n and be electrically connected to the plurality of synapses 30_1 to 30_n, respectively.

The column lines 25_1 to 25_n may extend in the column direction from one of the post-synaptic neurons 20_1 to 20_n, respectively, and may be electrically connected to the plurality of synapses 30_1 to 30_n.

The low gating controllers 41_1 to 41_n may provide the gating signals to the synapses 30_1 to 30_n through the low gating lines 46_1 to 46_n.

The low gating lines 46_1 to 46_n may extend in the low direction from one of the row gating controllers 41_1 to 41_n and be electrically connected to the plurality of synapses 30_1 to 30_n.

The synapses 30_1 to 30_n may be disposed at the intersections of the row lines 15_1 to 15_n and the column lines 25_1 to 25_n. The synapses 30_11 to 30_nn sharing the same row line 15_1 to 15_n may share the same row gating line 46_1 to 46_n.

1B, a neuromorph element according to an exemplary embodiment of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, post-synaptic neurons The column gating controllers 42_1 to 42_n and the column gating lines 47_1 to 47_n may be included in the memory cell array 20-1 to 20_n, the column lines 25_1 to 25_n, the synapses 30_11 to 30_nn, and the column gating controllers 42_1 to 42_n. The column gating controllers 42_1 to 42_n may provide gating signals to the synapses 30_11 to 30_nn via the column gating lines 47_1 to 47_n. The column gating lines 47_1 to 47_n may extend in the column direction from one of the column gating controllers 42_1 to 42_n and be electrically connected to the plurality of synapses 30_11 to 30_nn, respectively. The synapses 30_11 to 30_nn sharing the same column lines 25_1 to 25_n may share the same column gating lines 47_1 to 47_n.

1C, a neuromorph element according to an embodiment of the technical idea of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, post-synaptic neurons The column gating controllers 42_1 to 42_n, the row gating lines 46_1 to 46_n, the column gates 25_1 to 25_n, the column lines 25_1 to 25_n, the synapses 30_11 to 30_nn, the row gating controllers 41_1 to 41_n, ), And column gating lines 47_1 to 47_n. The row gating controllers 41_1 to 41_n may provide gating signals to the synapses 30_11 to 30_nn via the row gating lines 46_1 to 46_n and the column gating controllers 42_1 to 42_n may provide gating signals to the column gating And can provide a gating signal to the synapses 30_11 to 30_nn through the lines 47_1 to 47_n. Synapses 30_11 to 30_nn sharing the same row lines 15_1 to 15_n may share the same row gating lines 46_1 to 46_n and synapses 30_11 to 30_nn sharing the same column lines 25_1 to 25_n, To 30_nn may share the same column gating lines 47_1 to 47_n. That is, each of the synapses 30_11 to 30_nn includes one row line 15_1 to 15_n, one column line 25_1 to 25_n, one row gating line 46_1 to 46_n, and one column gating line 47_1 To 47_n, respectively.

2 is a block diagram illustrating in detail a synapse of a neuromorph element according to an embodiment of the present invention.

2, a synapse 30 of a neuromorph element according to an embodiment of the present invention may include a transistor 31 and a memristor 35, and a post-synaptic neuron 20 ) May include an integrator 21 and a comparator 25. The memristor 35 may include a variable resistor.

The gate electrode G of the transistor 31 of the synapse 30 may be electrically connected to the gating controller 40 through the gating line 45 and the first electrode E1 of the transistor 31 may be electrically connected to the low- And the second electrode E2 of the transistor 31 may be electrically connected to the first node N1 of the memristor 35. The pre-synaptic neuron 10 may be electrically connected to the first node N1 of the memristor 35 via the first node N1. The second node N2 of the memristor 35 may be electrically connected to the post-synaptic neuron 20 via the column line 25. [

The input terminal of the integrator 21 of the post-synaptic neuron 20 can be electrically connected to the second node N2 of the memristor 35 via the column line 25, May be electrically connected to the output terminal of the integrator 21.

The first electrode E1 and the second electrode E2 of the transistor 31 can be circuitly analyzed as a source electrode or a drain electrode depending on the direction of the current. Therefore, in the following, the first electrode E1 and the second electrode E2 will be referred to as a source electrode or a drain electrode, respectively, according to the circuit operation of the transistor 31. [

FIG. 3A is a conceptual block diagram illustrating learning of a synapse 30 of a neuromorph element according to an embodiment of the present invention, and FIG. 3B is a conceptual block diagram illustrating learning voltage V _LN , pre- A voltage V1, and a post-synaptic voltage V2.

3A and 3B, a method of learning the synapse 30 of the neuromorph element is performed by applying a learning gate voltage (V _LN ) to the gate electrode G of the transistor 31 of the synapse 30, And can apply a learning pre-synaptic voltage (V1) to the first electrode E1 of the transistor 31 and apply a learning pre-synaptic voltage V1 to the second node N2 of the memristor 35 And applying a learning post-synaptic voltage (V2). The learning gate voltage V _LN may be higher than the threshold voltage Vth of the transistor 31. (V _LN > Vth) The learning pre-synaptic voltage V1 may comprise a plurality of pulses which are positive voltages. The learning post-synaptic voltage V2 may comprise a plurality of pulses which are negative (-) voltages. Therefore, the gate-source voltage Vgs for turning on the transistor 31, that is, the voltage between the gate electrode G and the second electrode E2 of the transistor 31 is lower than the threshold voltage Vth of the transistor 31 ), And therefore the transistor 31 can be sufficiently turned on.

The difference between the learning pre-synaptic voltage V1 and the learning post-synaptic voltage V2 may be large enough to lower or raise the resistance of the memristor 35 of the synapse 30. For example, the difference between the learning pre-synaptic voltage V1 and the learning post-synaptic voltage V2 may be greater than the set voltage Vset or the reset voltage Vreset. The set voltage Vset and the reset voltage Vreset are voltages at which the resistance of the memristor 35 of the synapse 30 can be lowered or increased.

In the expanded embodiments of the inventive concept, the learning post-synaptic voltage V2 may be a voltage of zero or positive. In this case, however, the gate-source voltage Vgs of the transistor 31 may be sufficiently higher than the threshold voltage Vth.

The electrical signal passing through the memristor 35 of the synapse 30 is integrated in the integrator 21 of the post-synaptic neuron 20 to generate a voltage higher than the reference voltage of the comparator 25 An electrical signal can be output from the comparator 25. That is, the post-synaptic neuron 20 may be fired. The learning mode may end when the post-synaptic neuron 20 is fired.

4A is a conceptual block diagram illustrating the reading of a learned (i.e., stored) data pattern in a synapse 30 of a neuromorph element according to one embodiment of the present invention, and FIG. 4B Is a graph that conceptually shows the current flowing through the synapse 30. For example, an excitatory synapse, i.e., a state in which the current flowing from the synapse 30 to the post-synaptic neuron 20 increases in the read mode is described. The direction in which the current flows can be referred to by an arrow.

Referring to FIG. 4A, a method of reading a learned (i.e., stored) data pattern in a synapse 30 of a neuromorph element according to an embodiment of the present invention will first be described by referring to the gating controller 40 A readout voltage Vrd is applied to the gate electrode G of the transistor 31 of the synapse 30 through the gating line 46 and the read voltage Vrd is applied from the pre- ) To the second node N2 of the memristor 35 through the column line 25 from the post-synaptic neuron 20 and applying a pre-synaptic voltage Va to the first electrode El of the memristor 35, - applying the synaptic voltage Vb.

It is assumed that the post-synaptic voltage Vb is substantially zero. Thus, the post-synaptic neuron 20 may not apply any voltage to the second node N2 of the memristor 35. [ The readout voltage Vrd may be lower than the threshold voltage Vth of the transistor 31 and have a positive voltage higher than the post-synaptic voltage Vb. The pre-synaptic voltage Va may have a positive voltage higher than the read voltage Vrd. Thus, the post-synaptic voltage Vb may be lower than the read voltage Vrd and the pre-synaptic voltage Va. The post-synaptic voltage Vb is applied to the second node N2 of the memristor 35 and the second electrode E2 of the transistor 31 in the same manner .

The difference between the read voltage Vrd and the post-synaptic voltage Vb, i.e. the gate-source voltage Vgs of the transistor 31 is smaller or less than the threshold voltage Vth of the transistor 31, (31) may be in a turn-off state. (Vgs | <Vth) However, the difference between the pre-synaptic voltage Va and the post-synaptic voltage Vb, that is, the drain-source voltage Vds of the transistor 31 is the threshold voltage Vth of the transistor 31 The transistor current Ids can flow from the first electrode E1 of the transistor 31 to the second electrode E2. That is, the current supplied to the post-synaptic neuron 20 through the column line 25 may increase. (Excitatory synaptic state)

For example, when the threshold voltage Vth of the transistor 31 is 0.7 V, the read voltage Vrd is 0.5 V, the pre-synaptic voltage Va is 1 V, and the post-synaptic voltage Vb is substantially The gate-source voltage Vgs is 0.5 V and the transistor 31 is in the turn-off state and the potential difference between the pre-synaptic voltage Va and the post-synaptic voltage Vb A small transistor current Ids can flow from the first electrode E1 to the second electrode E2 of the transistor 31 by a voltage of 1V.

The transistor current Ids is shown in the graph shown in FIG. 4B. In detail, a change in the transistor current Ids with a change in the difference between the readout voltage Vrd and the post-synaptic voltage Vb, that is, the difference between the gate-source voltage Vgs of the transistor 31 is shown. The vertical axis is the log scale. Since the post-synaptic voltage Vb is substantially zero, the gate-source voltage Vgs and the gate voltage Vg may be substantially the same. (Vrd - Vb = Vgs = Vg)

4B, in accordance with the resistance state of the memristor 35, the read voltage Vrd, that is, the gate-source voltage Vgs is lower than the threshold voltage Vth of the transistor 31, The current Ids shows a large difference. Experimentally, the transistor current Ids is applied to the gate-source voltage Vgs at the readout voltage Vrd, i.e., the gate-source voltage Vgs is lower than the threshold voltage Vth of the transistor 31 It changes exponentially.

(I _{D_ subth:} gate-source voltage of the transistor at a lower current region than the threshold voltage of the transistor)

For example, at a period when the gate-source voltage Vgs is lower than the threshold voltage Vth of the transistor 31, the rate of change of the transistor current Ids is experimentally about 1.0E3 or more. In this embodiment, since the resistance change of the memristor 35 is small, the transistor current Ids can be abruptly changed even if the change in the gate-source voltage Vgs is small.

Specifically, assuming that the post-synaptic voltage Vb is zero, when the readout voltage Vrd is lower (lower) than the threshold voltage Vth of the transistor 31, A large difference may be seen depending on the resistance state of the resistor 35. [ For example, the transistor current Ids_LR when the memristor 35 is in the lower resistance state is at least several hundred times larger than the transistor current Ids_HR when the memristor 35 is in the high resistance state Can be high. That is, the current difference due to the learning states of the memristor 35 is very large. Therefore, by using the read voltage Vrd lower than the threshold voltage Vth, that is, the gate voltage Vg, the data pattern stored in the synapse 30 can be easily recognized. That is, whether or not the synapse 30 has been learned can be easily determined.

5A is a conceptual block diagram illustrating the reading of a learned (i.e., stored) data pattern in a synapse 30 of a neuromorph element according to one embodiment of the present invention, and FIG. 5B Is a graph that conceptually shows the current flowing through the synapse 30. For example, inhibitory synapse, a state in which the current flowing from the synapse 30 to the post-synaptic neuron 20 in a readout mode is reduced, is illustrated. The direction in which the current is supplied may refer to arrows.

Referring to FIG. 5A, a method of reading a learned (i.e., stored) data pattern in a synapse 30 of a neuromorph element according to an embodiment of the present invention is first described by referring to the gating controller 40 The read voltage Vrd is applied to the gate electrode G of the transistor 31 of the synapse 30 through the gating line 45 and the read voltage Vrd is applied to the transistor 31 through the low line 15 from the pre- ) To the second node N2 of the memristor 35 through the column line 25 from the post-synaptic neuron 20 and applying a pre-synaptic voltage Va to the first electrode El of the memristor 35, - applying the synaptic voltage Vb.

It is assumed that the post-synaptic voltage Vb is substantially zero. The pre-synaptic voltage Va may have a lower voltage, e. G., Negative, than the read voltage Vrd and the post-synaptic voltage Vb. The readout voltage Vrd may have a lower positive voltage or a negative voltage of the threshold voltage Vth of the transistor 31. [ The gate electrode G and the first electrode E1 of the transistor 31 are connected to each other because the pre-synaptic voltage Va is lower, for example, even if the readout voltage Vrd is a negative voltage. The gate-source voltage Vgs may be a positive voltage. The absolute value of the difference between the read voltage Vrd and the pre-synaptic voltage Va or the gate-source voltage Vgs of the transistor 31 is smaller or less than the threshold voltage Vth of the transistor 31, . (| Vgs | <Vth) Therefore, the transistor 31 may be in a turn-off state. However, since the difference between the post-synaptic voltage Vb and the pre-synaptic voltage Va, that is, the absolute value of the drain-source voltage Vds is greater than the threshold voltage Vth, To the first electrode E1 from the second electrode E2. That is, the current supplied to the post-synaptic neuron 20 through the column line 25 can be reduced. (Inhibitory synapse state)

For example, when the threshold voltage Vth of the transistor 31 is 0.7 V, the read voltage Vrd is 0.5 V, the pre-synaptic voltage Va is -1.0 V, and the post- The absolute value of the gate-source voltage Vgs is 0.5 V so that the transistor 31 is in the turn-off state and the post-synaptic voltage Vb and the pre-synaptic voltage Va (Va) are substantially zero A small transistor current Ids can flow from the second electrode E2 of the transistor 31 to the first electrode E1 by the potential difference of 1.0 V. In an expanded embodiment, for example, when the threshold voltage Vth of the transistor 31 is 0.7 V, the readout voltage Vrd is -0.5 V, the pre-synaptic voltage Va is -1.0 V, and When the post-synaptic voltage Vb is substantially zero, since the absolute value of the gate-source voltage Vgs is 0.5V, the transistor 31 is in the turn-off state and the post- A small transistor current Ids can flow from the second electrode E2 of the transistor 31 to the first electrode E1 by a potential difference (1.0 V) of the pre-synaptic voltage Va. In various embodiments of the technical aspects of the present invention, in the region where the absolute value of the gate-source voltage Vgs is smaller or less than the threshold voltage Vth (| Vgs | <Vth) Can be implemented.

The transistor current Ids is shown in the graph shown in FIG. 5B. In detail, a change in the transistor current Ids with a change in the difference between the readout voltage Vrd and the post-synaptic voltage Vb, that is, the difference between the gate-source voltage Vgs of the transistor 31 is shown. Since the post-synaptic voltage Vb is substantially zero, the gate-source voltage Vgs may be a negative voltage.

Referring to FIG. 5B, in the period of negative (-) when the readout voltage Vrd, that is, the gate-source voltage Vgs is higher than the threshold voltage Vth of the transistor 31, The transistor current Ids shows a large difference. The gate-source voltage Vgs is a negative value since it is the difference between the read voltage Vrd and the pre-synaptic voltage Va. The transistor current Ids is supplied from the second electrode E2 to the first electrode E1 ), It is shown to be a negative value.

In detail, the transistor current Ids may show a large difference depending on the resistance state of the MEMSR 35. For example, the transistor current Ids_LR when the memristor 35 is in the low resistance state may be at least several hundred times lower than the transistor current Ids_HR when the memristor 35 is in the high resistance state .

Therefore, by using the read voltage Vrd lower than the threshold voltage Vth, that is, the gate voltage Vg, the data pattern stored in the synapse 30 can be easily recognized. That is, whether or not the synapse 30 has been learned can be easily determined.

FIG. 6 is a conceptual block diagram illustrating the reading of learned (i.e., stored) data patterns in synapses 30a and 30b of a neuromorph element according to an embodiment of the present invention. For example, it is a block diagram illustrating that excitatory synapse 30a and inhibitory synapse 30b are performed simultaneously. Referring to Fig. 6, the first synapse system S1 can perform an excitatory synapse operation, and the second synapse system S2 can simultaneously perform inhibitory synapse operation.

Specifically, in the first synapse system S1, the first read voltage Vrd1 is applied to the gate electrode G of the first transistor 31a of the first synapse 30a, and the first pre-synapse neuron A first pre-synaptic voltage Va1 is applied to the first electrode E1 of the first transistor 31a of the first synapse 30a through the first row line 15a from the first pre- The second node N2 of the first memristor 35a of the first synapse 30a or the second electrode N2 of the first transistor 31a of the first synapse 30a from the neuron 20 through the column line 25, A post-synaptic voltage Vb1 may be applied. At the same time, in the second synapse system S2, the second read voltage Vrd2 is applied to the gate electrode G of the second transistor 31b of the second synapse 30b, and the second pre-synaptic neuron 10b A second pre-synaptic voltage Va2 is applied to the first electrode E1 of the second transistor 31b of the second synapse 30b through the second row line 15b from the second pre- A second node N2 of the second memristor 35b of the second synapse 30b or a second electrode E2 of the second transistor 31b is connected to the post- The voltage Vb2 may be applied.

The first read voltage Vrd1 may be a positive voltage lower than the threshold voltage Vth of the first transistor 31a. Accordingly, the first transistor 31a may be in a turn-off state. The second read voltage Vrd2 may be either a positive voltage lower than the threshold voltage Vth of the second transistor 31b or a positive or negative voltage having an absolute value smaller than or less than the threshold voltage Vth. (-). &Lt; / RTI &gt; In an expanded embodiment of the inventive concept, the second read voltage Vrd2 may be substantially zero. Thus, the second transistor 31b may also be in a turn-off state. Further, in the expanded embodiment of the technical idea of the present invention, the first read voltage Vrd1 and the second read voltage Vrd2 may be substantially the same.

The first pre-synaptic voltage Va1 applied to the first electrode E1 of the first transistor 31a is higher than the first readout voltage Vrdl and the threshold voltage Vth of the first transistor 31a + &Lt; / RTI &gt; The second pre-synaptic voltage Va2 that is greeted to the first electrode E1 of the second transistor 31b is lower than the second read voltage Vrd2 and the threshold voltage Vth of the second transistor 31b ). For example, the second pre-synaptic voltage Va2 may be a negative voltage.

In the first transistor 31a, the difference between the first read voltage Vrd1 and the first post-synaptic voltage Vb1, that is, the absolute value of the gate-source voltage Vgs (| Vgs |), May be smaller or less than the threshold voltage (Vth) (Vgs | <Vth) In the second transistor 31b, the difference between the second read voltage Vrd2 and the second pre-synaptic voltage Va2, that is, the absolute value of the gate-source voltage Vgs Vgs | may be lower than the threshold voltage Vth of the second transistor 31b.

In various embodiments of the present invention, the threshold voltages (Vth) of each of the transistors 30, 30a, 30b can be varied. For example, the threshold voltage of an intrinsic silicon transistor is known to be about 0.67 V, but the threshold voltage Vth may be increased or decreased by adjusting the amount of ion implantation in the well region, the source / drain region, the channel stop region, It is possible.

The second pre-synaptic voltage Va2 applied to the first electrode E1 of the second transistor 31b may be a negative voltage.

The first and second post-synaptic voltages Va2, Vb2 may be the same. For example, the first and second post-synaptic voltages Va2, Vb2 may be substantially zero.

In the first synapse system S1, the first drain-source current Ids1 may flow from the first electrode E1 of the first transistor 31a to the second electrode E2.

In the second synapse system S2, a second drain-source current Ids2 may flow from the second electrode E2 of the first transistor 31a to the first electrode E1.

In addition, the operation of the first synapse system S1 can be understood in detail with reference to Figs. 4A and 4B, and the operation of the second synapse system S2 can be understood in more detail with reference to Figs. 5A and 5B .

7 is a block diagram conceptually illustrating an array system according to an embodiment of the technical concept of the present invention. Referring to FIG. 7, an array system according to an embodiment of the present invention may include a plurality of synapse arrays SA1 to SA3 and an inter-array synapse IS. A plurality of synapse arrays SA1-SA3 may be connected in series. For example, the output of the first synapse array SA1 may be used as the input of the second synapse array SA2, and the output of the second synapse array SA2 may be used as the output of the third synapse array SA3 Can be used. The inter-array synapse IS may comprise an inter-array transistor T and an inter-array resistor R.

The inter-array synapse (IS) may perform an excitatory synaptic action or an inhibitory synaptic action. For example, the output of the third synapse array SA3 is applied with the gate voltage of the transistor T, that is, the readout voltage Vrd, and the drain-source voltage Vout is applied to the electrode of the inter- Vds), the inter-array transistor T may increase or decrease the current in the first synapse array Sa1. That is, the learned data pattern may be enhanced or suppressed. The detailed operation of the inter-array synapse IS will be understood with reference to Figs. 4A to 5B.

FIG. 8 is a block diagram conceptually showing a pattern recognition system 900 according to an embodiment of the present invention. For example, the pattern recognition system 900 may include a speech recognition system, an imaging recognition system, a code recognition system, a signal recognition system, And may be one of systems for recognizing various patterns.

8, the pattern recognition system 900 of one embodiment of the technical concept of the present invention includes a central processing unit 910, a memory unit 920, a communication control unit 930, a network 940, an output unit 950, an input unit 960, an analog-to-digital converter 970, a novel Lomographic unit 980, and / or a bus 990. The central processing unit 910 generates and transmits a variety of signals for learning of the novel Lomographic unit 980 and generates various signals for recognizing patterns such as voice, Processing, and function.

The central processing unit 910 is connected to a memory unit 920, a communication control unit 930, an output unit 950, an analog-to-digital converter 970 and a novel Lomographic unit 980 via a bus 990 .

The memory unit 920 may store various information required to be stored in the pattern recognition system 900. The memory unit 920 may be a volatile memory device such as DRAM or SRAM, non-volatile memory such as PRAM, MRAM, ReRAM, or NAND flash memory. Memory, or various storage units such as a hard disk drive (HDD) or a solid state drive (SSD).

The communication control unit 930 can transmit and / or receive the recognized voice, video, and other data via the network 940 to the communication control unit of the other system.

The output unit 950 can output the recognized voice, image, and other data in various manners. For example, the output unit 950 may include a speaker, a printer, a monitor, a display panel, a beam projector, a holographer, or various other output devices.

The input unit 960 may include at least one of a microphone, a camera, a scanner, a touch pad, a keyboard, a mouse, a mouse pen, or various sensors.

The analog-to-digital converter 970 can convert the analog data input from the input device 960 into digital data.

The neuromode unit 980 can perform learning, recognition, and the like using data output from the analog-to-digital converter 970, and can output data corresponding to the recognized pattern . The novelrom unit 980 may perform operations on various embodiments of the inventive concepts.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

10, 10a, 10b: pre-synaptic neurons
15, 15a, 15b:
20: Post-synaptic neuron
21: integrator 25: comparator
25: column line
30, 30a, 30b: Synapse
31, 31a, 31b: transistors 35, 35a, 35b:
40: Gating controller
41: low gating controller 42: column gating controller
45: Gating line 46: Low gating line
47: Column gating line
Vrd: Readout voltage
Va, Va1, Va2: pre-synaptic voltage
Vb, Vb1, Vb2: Post-Synaptic Voltage
Ids, Ids_LR, Ids_HR: drain current
IS: Inter-Array Synapse
T: transistor
R: Resistance
SA1-SA3: synapse array

Claims (20)

A method for reading data from a synapse comprising a variable resistor having a gate electrode, a transistor having a first electrode, and a second electrode, and a first electrode coupled to a second electrode of the transistor,
Applying a read voltage to the gate electrode of the transistor,
Applying a pre-synaptic voltage to the first electrode of the transistor, and
And applying a post-synaptic voltage to the second electrode of the variable resistor,
Wherein the read voltage is lower than the threshold voltage of the transistor.
The method according to claim 1,
Wherein the post-synaptic voltage is zero.
The method according to claim 1,
Wherein an absolute value of a difference between the read voltage and the post-synaptic voltage is smaller than the threshold voltage.
The method of claim 3,
Wherein the pre-synaptic voltage is a positive voltage.
5. The method of claim 4,
Wherein the read voltage is a positive voltage.
5. The method of claim 4,
Wherein the pre-synaptic voltage is higher than the read voltage.
The method according to claim 1,
Wherein an absolute value of a difference between the read voltage and the pre-synaptic voltage is smaller than the threshold voltage.
8. The method of claim 7,
Wherein the pre-synaptic voltage is a negative voltage. 9. The method of claim 8,
And the read voltage is a negative voltage.
9. The method of claim 8,
Wherein the pre-synaptic voltage is lower than the read voltage.
CLAIMS 1. A method of reading data from a synapse comprising a variable resistor having a gate electrode, a transistor having a first electrode, and a second electrode, and a first electrode coupled to the second electrode of the transistor,
Applying a positive read voltage lower than a threshold voltage of the transistor to the gate electrode of the transistor through a gating line from the gating controller,
Applying a positive (+) pre-synaptic voltage from the pre-synaptic neuron to the first electrode of the transistor through a low line, and
Applying a post-synaptic voltage from a post-synaptic neuron to a second electrode of the variable resistor through a column line.
12. The method of claim 11,
Wherein an absolute value of a difference between the read voltage and the post-synaptic voltage is smaller than the threshold voltage.
13. The method of claim 12,
Wherein the post-synaptic voltage is zero.
12. The method of claim 11,
Wherein the difference between the pre-synaptic voltage and the post-synaptic voltage is greater than the threshold voltage.
CLAIMS 1. A method of reading data from a synapse comprising a variable resistor having a gate electrode, a transistor having a first electrode, and a second electrode, and a first electrode coupled to the second electrode of the transistor,
Applying a read voltage lower than a threshold voltage of the transistor from the gating controller to the gate electrode of the transistor through a gating line,
Applying a negative (-) pre-synaptic voltage from the pre-synaptic neuron to the first electrode of the transistor through a low line, and
A data read method comprising applying a post-synaptic voltage from a post-synaptic neuron to a second electrode of the variable resistor through a column line
16. The method of claim 15,
Wherein an absolute value of a difference between the read voltage and the pre-synaptic voltage is smaller than the threshold voltage.
17. The method of claim 16,
Wherein the read voltage is a positive voltage.
17. The method of claim 16,
And the read voltage is a negative voltage.
17. The method of claim 16,
Wherein the post-synaptic voltage is zero. 17. The method of claim 16,
Wherein the difference between the pre-synaptic voltage and the post-synaptic voltage is greater than the threshold voltage.

Images