KR20170080403A - Integrated circuit including embedded memory device for performing dual-transient word line assist using triple power source and device having same - Google Patents

Abstract

The integrated circuit is posted. The integrated circuit comprising: an embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair; A timing control circuit for generating switch signals in response to an operation control signal; And a second voltage, a second voltage, and a third voltage having different levels, and responsive to the switch signals, to receive either the first voltage, the second voltage, And a switch circuit for supplying the signal to the line.

Description

Technical Field [0001] The present invention relates to an integrated circuit including an embedded memory device capable of performing a dual-transition word line assist using a triple power source, and an apparatus including the integrated circuit. AND DEVICE HAVING SAME}

An embodiment according to the inventive concept relates to an integrated circuit, and more particularly to an integrated circuit including an embedded memory device capable of performing dual-transition wordline assist using a triple power source and a device including the integrated circuit .

To create a low-power, high-efficiency application processor (AP), it is important to lower the lowest voltage of static random access memory (SRAM). However, the degree of integration of the semiconductor circuit is becoming finer as the process progresses, and the parasitic component of the semiconductor circuit is increasing. The supply voltage supplied to the SRAM gradually scales down, making it difficult to design a high quality SRAM. In addition, due to the quantized width process characteristics of FinFET, development of bit cells of SRAM with optimal performance has been difficult.

For this reason, the design of the assist circuit is essential when designing a low-power-high-efficiency SRAM.

SUMMARY OF THE INVENTION The present invention provides a word line under-driving (WLUD) scheme that lowers a word line voltage level to improve read stability, The word line over-driving (WLOD) scheme, which improves the write ability, can be performed in succession within one clock cycle, and a dual- An integrated circuit capable of performing a range word line assist, and an apparatus including the integrated circuit.

An integrated circuit in which a memory cell including a word line, a bit line pair, and a storage cell coupled to the word line and the bit line pair, according to an embodiment of the present invention, A timing control circuit; A first voltage, a second voltage, and a third voltage having different levels and outputting any one of the first voltage, the second voltage, and the third voltage in response to the switch signals ; And a driver that includes an output terminal connected to the word line and uses the one of the voltages output from the switch circuit as an operation voltage.

The switch circuit supplies the first voltage to the driver in response to the switch signals generated by the timing control circuit when the operation control signal indicates normal operation. Wherein the switch circuit supplies the second voltage to the driver in response to the switch signals generated by the timing control circuit when the operation control signal indicates an assist operation, Wherein the first voltage is higher than the second voltage and lower than the third voltage.

The second voltage and the third voltage are successively supplied to the word line within one cycle of an internal clock signal. The second voltage is a voltage for read-assist, and the third voltage is a voltage for write-assist.

The switch circuit including a first switch responsive to a first switch signal among the switch signals for outputting the first voltage to the operating voltage of the driver; A second switch for outputting the second voltage to the operating voltage of the driver in response to a second switch signal among the switch signals; And a third switch for outputting the third voltage to the operating voltage of the driver in response to a third switch signal among the switch signals.

Wherein the switch circuit comprises: a read assist signal generator for generating a read assist signal in response to the operation control signal and the internal clock signal; A write assist signal generator for generating a write assist signal using the read assist signal; A first switch signal generator for generating the first switch signal using the read assist signal and the write assist signal; A second switch signal generator for generating the second switch signal using the operation control signal, the read assist signal, and the write assist signal; And a third switch signal generator for generating the third switch signal using the operation control signal and the write assist signal.

An integrated circuit according to an embodiment of the present invention includes an embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair; A timing control circuit for generating switch signals in response to an operation control signal; And a second voltage, a second voltage, and a third voltage having different levels, and responsive to the switch signals, to receive either the first voltage, the second voltage, And a switch circuit for supplying the signal to the line.

Wherein the switch circuit supplies the first voltage to the word line in response to the switch signals generated by the timing control circuit when the operation control signal indicates normal operation, In response to the switch signals generated by the timing control circuit when the operation control signal indicates an assist operation, supplying the second voltage to the word line and subsequently supplying the third voltage to the word line , The first voltage is higher than the second voltage and lower than the third voltage.

The timing control circuit controls the timing of transition of at least one of the switch signals to adjust the time at which the second voltage and the third voltage are supplied to the word line.

The difference between the first voltage and the second voltage and the difference between the first voltage and the third voltage are different from each other. The difference between the first voltage and the third voltage is greater than the difference between the first voltage and the second voltage. The embedded memory device is a FinFET-based SRAM.

The switch circuit comprising: an inverter coupled between a ground and a voltage supply terminal, the inverter including an output terminal coupled to the word line; A first switch for supplying the first voltage to the voltage supply terminal of the inverter in response to a first switch signal among the switch signals; A second switch for supplying the second voltage to the voltage supply terminal of the inverter in response to a second switch signal among the switch signals; And a third switch for supplying the third voltage to the voltage supply terminal of the inverter in response to a third switch signal among the switch signals.

A mobile device according to an embodiment of the present invention includes an application processor; And a power management IC for supplying a first voltage, a second voltage, and a third voltage to the application processor. The application processor comprising: an embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair; A timing control circuit for generating switch signals in response to an operation control signal; And a second voltage, a second voltage, and a third voltage having different levels, and responsive to the switch signals, to receive either the first voltage, the second voltage, And a switch circuit for supplying the signal to the line.

A memory device embedded in an integrated circuit according to an embodiment of the present invention includes word line under-driving (WLUD) that lowers the voltage level of the word line of the embedded memory device to improve read stability ) Scheme and a word line over-driving (WLOD) scheme that improves the write ability by raising the voltage level of the word line to one clock cycle There is an effect that can be carried out successively.

The embedded memory device uses triple power sources (or voltages), and one of the triple power sources can be used for the storage cell of the memory device and the remaining two of the triple power sources Power sources can be used for peripheral circuits.

Conventional memory devices that use one power source or dual-power sources require an additional level shifter, but the embedded memory device using triple power sources, unlike conventional memory devices, . That is, the embedded memory device can utilize the triple power sources output from the power management IC as power sources of the memory cells included in the embedded memory device. Thus, the embedded memory device can reduce the overhead for additional level shifters.

The embedded memory device supplies a voltage for a WLUD scheme to a word line first during one clock cycle during an operating mode to perform a dual-transition word line assist, It is possible to automatically supply the voltage for the WLOD scheme.

Initially, the read stability of the hub-selected cells increases as the voltage for the WLUD scheme is supplied to the word line, and after a certain time the voltage for the WLOD scheme is supplied to the word line, .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
Figure 1 conceptually illustrates a block diagram of an embedded memory device in accordance with an embodiment of the present invention.
2 shows a control circuit for controlling a dual-transition word line assist using a triple power source, and a memory cell including a word line.
Fig. 3 shows a circuit diagram of the control circuit shown in Fig. 2. Fig.
4 is a timing chart for explaining the operation of the control circuit shown in Fig.
5 is a flowchart for explaining the operation of the control circuit shown in Fig.
Figure 6 shows triple-power sources used in an embedded memory device according to an embodiment of the present invention.
7 is a block diagram of a mobile device including an integrated circuit including an embedded memory device in accordance with an embodiment of the present invention.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example, without departing from the scope of the right according to the concept of the present invention, the first element may be referred to as a second element, The component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having" and the like are used to specify that there are features, numbers, steps, operations, elements, parts or combinations thereof described herein, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

Figure 1 conceptually illustrates a block diagram of an embedded memory device in accordance with an embodiment of the present invention. 1, a memory device 100 embedded in an integrated circuit (IC) includes a memory cell array 110, a row decoder 120, a column decoder 125, a selection circuit block 130, A read / write control circuit 135, a sense amplifier 140, and a write driver 150.

An integrated circuit (IC) is an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system-on-chip (SoC), a large-scale integration (LSI), a processor, . ≪ / RTI >

The memory cell array 110 includes a plurality of word lines WL1-WLX (X is a natural number of 3 or more), a plurality of bit line pairs (1BL-YBL, Y is a natural number of 2 or more) And a plurality of memory cells 115 coupled to the bit line pair. The bit line pair 1BL is defined as complementary bit lines BL1 and / BL1, and the bit line pair YBL is defined as complementary bit lines BLY and / BLY. The memory cell array 110 may be a FinFET-based SRAM device.

For example, as shown in FIG. 2, one memory cell 115, such as an SRAM memory cell, may include six MOSFETs. Each bit in memory cell 115 may be stored in four MOSFETs forming two cross-coupled inverters 115-2 and 115-3. The storage cell formed by two cross-coupled inverters 115-2 and 115-3 has two stable states that are used to represent zero and one. The two access MOSFETs 115-1 and 115-4 can control access to the storage cell during read and write operations. The memory cell 115 may be referred to as a 6T bit cell. According to other embodiments, the memory cell 115 may be implemented using K- MOSFETs, where K may be 4 or 8, and may be another natural number.

The row decoder 120 may perform an operation of decoding n-bit input addresses ADD and selecting any one of a plurality of word lines WL1-WLX according to the decoding result.

The column decoder 125 may perform an operation of decoding the m-bit input addresses ADD and selecting any one of the plurality of bit line pairs 1BL-YBL in accordance with the decoding result. Therefore, any one of the plurality of memory cells 115 can be selected according to the operation of the row decoder 120 and the operation of the column decoder 125. [

The selection circuit block 130 includes a plurality of transmission circuits 130-1 and 130-Y, and each of the transmission circuits 130-1 and 130-Y is controlled according to a decode result of the column decoder 125 , A connection between each bit line pair and the sense amplifier 140, or a connection between each bit line pair and the write driver 150 can be controlled.

The read / write control circuit 135 can generate the sense amplifier enable signal SEN in response to the read command RD for the read operation. The read / write control circuit 135 can generate the driver enable signal WEN in response to the write command WD for the write operation.

During the read operation, the sense amplifier 140 is enabled in response to the sense amplifier enable signal SEN, and the enabled sense amplifier 140 senses the data output from the selected bit line pair through the selected transmit circuit And generate output data DOUT.

During a write operation, the write driver 150 is enabled in response to the driver enable signal WEN, and the enabled write driver 150 transfers the input data DIN to the selected bit line pair through the selected transfer circuit .

2 shows a control circuit for controlling a dual-transition word line assist using a triple power source, and a memory cell including a word line. 2, the control circuit 121 for supplying any one of the first voltage VDD, the second voltage VDDUD, and the third voltage VDDOD to the word line WL1 is implemented in the row decoder 120 The control circuit 121 may be implemented outside the row decoder 120 according to embodiments.

The control circuit 121 may include a timing control circuit 210 and a switch circuit 230. The timing control circuit 210 may generate the switch control signals CT1, CT2, and CT3 in response to the operation control signal WRA. The operation control signal WRA may indicate a normal operation or an assist operation.

The switch circuit 230 receives the first voltage VDD, the second voltage VDDUD and the third voltage VDDOD having different levels and outputs the switch control signals CT1, CT2, and CT3 And may output any one of the first voltage VDD, the second voltage VDDUD, and the third voltage VDDOD to the word line WL1. For example, the first voltage VDD may be supplied to the operating voltage of the storage cell formed by the two cross-coupled inverters 115-2 and 115-3.

A first voltage VDD that is a steady voltage may be supplied to the word line WL1 of the memory cell 115 during normal operation (e.g., operation without a light assist or a read assist). However, when the assist operation according to the embodiment of the present invention, i.e., the dual-transient word line (DTWL) assist operation is performed, the second voltage VDDUD is initially supplied to the word line WL1 And after a predetermined time, the third voltage VDDOD may be supplied automatically to the word line WL1.

For example, the second voltage VDDUD and the third voltage VDDOD may be successively supplied to the corresponding word line for one cycle of an external clock signal or an internal clock signal generated based on the external clock signal. According to embodiments, the frequency of the external clock signal and the frequency of the internal clock signal may be the same or different from each other. The timing controller 210 may refer to a DTWL controller.

Fig. 3 shows a circuit diagram of the control circuit shown in Fig. 2, and Fig. 4 is a timing diagram illustrating the operation of the control circuit shown in Fig. Referring to FIGS. 2 and 3, the timing control circuit 210 may include a pulse generator 212 and a plurality of switch signal generators 220, 222, and 224.

The pulse generator 212 may include a word line enable signal generator 214, a lead assist signal generator 216, and a write assist signal generator 218.

The word line enable signal generator 214 may generate a signal for the word line enable signal WLE having the waveform shown in Fig. 4 in response to the operation control signal WRA.

The read assist signal generator 216 generates a word line read assist signal WLRA having a waveform as illustrated in FIG. 4 in response to an internal clock signal ICK, and the write assist signal generator 218 generates a write assist signal The read assist signal WLRA can be used to generate the word line write assist signal WLWA having the waveform exemplarily shown in Fig.

The first switch signal generator 220 may generate the first switch signal CT1 using the word line read assist signal WLRA and the word line write assist signal WLWA.

The second switch signal generator 222 may generate the second switch signal CT2 using the operation control signal WRA, the word line read assist signal WLRA and the word line write assist signal WLWA.

The third switch signal generator 220 may generate the third switch signal CT3 using the operation control signal WRA and the word line write assist signal WLWA.

For example, each switch signal generator 220, 222, and 224 may be implemented as a NAND gate, but the structure of each switch signal generator 220, 222, and 224 may be provided as a word line WL1 shown in FIG. The word line voltage VWL may be varied in various forms according to the waveform of the word line voltage VWL.

2 and 3, the switch circuit 230 includes a first switch 231, a second switch 233, a third switch 235, a NAND gate 237, and an inverter 239 .

Although the inverter 239 is implemented in the switch circuit 230 in FIGS. 2 and 3, the inverter 239 can be implemented outside the switch circuit 230. The inverter 239 may mean a driver for driving the word line WL1.

The triple power sources (or voltages VDD, VDDUD, and VDDOD) are supplied to the switch circuit 230. The first switch 231 controls the supply of the first voltage VDD to the voltage node VT of the inverter 239 in response to the first switch signal CT1. The second switch 233 controls the supply of the second voltage VDDUD to the voltage node VT of the inverter 239 in response to the second switch signal CT2. The third switch 235 controls the supply of the third voltage VDDOD to the voltage node VT of the inverter 239 in response to the third switch signal CT3. Each of the switches 231, 233, and 235 may be implemented as a P-type MOSFET.

The NAND gate 237 performs a NAND operation on the pre-word line signal PRE_WL and the word line enable signal WLE, and outputs the result of the operation to the inverter 239.

The inverter 239 includes an output terminal OT connected to the word line WL1 and includes a voltage node VT connected to an output terminal of each of the switches 231, 233 and 235. [ The inverter 239 supplies the voltage VDD, VDDUD or VDDOD or the ground voltage VSS supplied to the voltage node VT to the word line WL1 of the memory cell 115 through the output terminal OT Can supply. For example, when the output signal of the NAND gate 237 is at the high level (or 1), the word line voltage VWL of the word line WL1 is the ground voltage VSS and the output signal of the NAND gate 237 is low The word line voltage VWL of the word line WL1 is the voltage (VDD, VDDUD, or VDDOD) supplied to the voltage node VT.

5 is a flowchart for explaining the operation of the control circuit shown in Fig. The operation of the control circuit 121 will be described with reference to Figs.

When the operation mode of the memory device 100 embedded in the integrated circuit is the normal operation mode (NORMAL OPERATION or NO_ASSIST) (NO in S110), that is, when the operation control signal WRA is low level, (WLRA) and the word line write assisting signal (WLWA) are both at a high level.

The first switch signal generator 220 outputs the first switch signal CT1 having the low level and the second switch signal generator 222 outputs the second switch signal CT2 having the high level, The switch signal generator 224 outputs a third switch signal CT3 having a high level. The first voltage VDD is supplied to the voltage node VT of the inverter 239 since only the first switch 231 is turned on in response to the first switch signal CT1 having the low level.

When both the word line enable signal WLE and the pre-word line signal PRE_WL are at a high level, the NAND gate 237 outputs an output signal having a low level. Thus, the inverter 239 supplies the first voltage VDD to the word line WL1. However, when neither the word line enable signal WLE nor the pre-word line signal PRE_WL is at a high level, the NAND gate 237 outputs an output signal having a high level. Thus, the inverter 239 supplies the ground voltage VSS to the word line WL1.

When the operation mode of the memory device 100 embedded in the integrated circuit is the assist operation mode (ASSIST OPERATION or ASSIST) (YES in S110), that is, when the operation control signal WRA is at the high level, (WLE) transitions to a high level. Therefore, the NAND gate 237 outputs an output signal having a low level to the input terminal of the inverter 239. [

During the initial time ITC of the assist operation mode (ASSIST OPERATION or ASSIST), i.e., for the time for the read assist RA (YES in S110), the word line read assist signal WLRA is low level and the word line write assist signal (WLWA) is at a high level.

The second voltage VDDUD is supplied to the voltage node VT of the inverter 239 as the word line read assisting signal WLRA transits from the high level to the low level. When both the word line enable signal WLE and the pre-word line signal PRE_WL are at a high level, the NAND gate 237 outputs an output signal having a low level. Accordingly, the inverter 239 supplies the second voltage VDDUD to the word line WL1 of the memory cell 115 in response to the input signal having the low level (S120). The second voltage VDDUD is supplied to the word line WL1 for the read assist RA. The difference between the first voltage VDD and the second voltage VDDUD is dv1.

The control circuit 121 supplies a second voltage VDDUD lower than the first voltage VDD to the word line WL1 for a word line under-driving (WLUD) scheme (S120) .

For example, in the assist operation mode (ASSIST OPERATION or ASSIST) during the initial time ITC, the first switch signal generator 220 outputs the first switch signal CT1 having the high level and the second switch signal generator 222 outputs a second switch signal CT2 having a low level and the third switch signal generator 224 outputs a third switch signal CT3 having a high level. During the initial time ITC, each of the switches 231 and 235 is turned off in response to each switch signal CT1 and CT3 having a high level, and only the second switch 233 is turned off in response to a second switch signal having a low level (CT2). ≪ / RTI > Inverter 239 supplies a second voltage VDDUD supplied to voltage node VT to word line WL1 of memory cell 115 in response to an input signal having a low level.

The write assist signal generator 218 generates a word line write assisting signal WLWA that transits from a high level to a low level after a predetermined time, that is, after an initial time ITC (YES in S130). The light assist signal generator 218 may refer to an internal-timing-control circuit. The internal-timing-control circuit may be set after all the memory cells have been tested for read assist and write assist within an SRAM macro.

After a delay (e.g., a timing span; ITC) determined by the internal-timing-control circuit has elapsed, the word line write assertion signal WLWA for the write assertion WA transitions from high level to low level (S130).

The third voltage VDDOD is supplied to the voltage node VT of the inverter 239 as the word line write assisting signal WLWA transits from the high level to the low level. When both the word line enable signal WLE and the pre-word line signal PRE_WL are at a high level, the NAND gate 237 outputs an output signal having a low level. Thus, the inverter 239 supplies the third voltage VDDOD to the word line WL1 of the memory cell 115 in response to the input signal having the low level (S140). The third voltage VDDOD is supplied to the word line WL1 for the write assist WA. The difference between the third voltage VDDOD and the first voltage VDD is dv2. The dv1 and the dv2 may be different from each other, and the dv2 may be greater than the dv1.

The control circuit 121 supplies a third voltage VDDOD to the word line WL1 that is higher than the first voltage VDD for the word line over-driving (WLOD) scheme (S140) .

For example, during the write assist WA, the first switch signal generator 220 outputs a first switch signal CT1 having a high level, and the second switch signal generator 222 outputs a second switch signal (CT2), and the third switch signal generator 224 outputs the third switch signal CT3 having the low level. During the write assertion WA, each of the switches 231 and 233 is turned off in response to each of the switch signals CT1 and CT2 having a high level, and only the third switch 235 is turned off in response to the third switch signal (CT3). Inverter 239 supplies a third voltage VDDOD supplied to voltage node VT to word line WL1 of memory cell 115 in response to an input signal having a low level.

An embedded memory device, e.g., an SRAM, according to an embodiment of the present invention includes a third voltage (VDDD = VDD-dv1), a third voltage (VDDOD = VDD- dv2).

Figure 6 shows triple-power sources used in an embedded memory device according to an embodiment of the present invention. The embedded memory device 100 may use triple power sources (Cell_pw = VDD1, Pe_pw1 = VDDUD, and Pe_pw2 = VDDOD).

7 is a block diagram of a mobile device including an integrated circuit including an embedded memory device in accordance with an embodiment of the present invention. 1 through 7, a mobile device 300 may include an integrated circuit 310 including a embedded memory device 100 and a power management IC 330. As described above, the integrated circuit 310 may include a SoC, an ASIC, an FPGA, a SoC, an LSI, a processor, an AP, or a mobile AP.

The mobile device 300 may be a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal digital assistant navigation device or portable navigation device, handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device, a drone, or an e-book.

The embedded memory device 100 using the triple power sources VDD, VDDUD and VDDOD uses the triple power sources VDD, VDDUD, and VDDOD from the power management IC 330, Additional circuitry, such as a level shifter, must be implemented in the memory device when the memory device uses one power source or dual power sources), thereby reducing the additional circuit overhead. In addition, although the integrated circuit 310 includes a plurality of embedded memory devices, the plurality of embedded memory devices commonly use the triple power sources VDD, VDDUD, and VDDOD supplied from the power management IC 330 .

The second voltage VDDUD and the third voltage VDDOD are stored in one cycle of the external clock signal or the internal clock signal ICK related to the external clock signal as described with reference to FIGS. 115 are successively supplied to the word line WL1 to improve the disturb margin such as the hold margin of the half-selected cells and the write ability, Is also improved. For example, the control circuit 121 can perform the functions of the lead assist and the light assist circuit.

An embedded memory device (e.g., SRAM) in accordance with embodiments of the present invention may utilize triple power sources (triple powers or three voltages), unlike conventional memory devices (e.g., SRAM). The control circuit 121 implemented in the embedded SRAM supplies the first voltage VDD to the word line WL1 of the memory cell 115 during normal operation and outputs both the read assist RA and the write assist WA The second voltage VDDUD and the third voltage VDDOD are successively supplied to the word line WL1 of the memory cell 115 for one clock cycle during the DTWL assist operation. Therefore, the read assist (RA) and the write assist (WA) can be implemented at the same time.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: a memory device embedded in an integrated circuit
121: Control circuit
210: Timing control circuit
230: Switch circuit
231: first switch
233: second switch
235: third switch
212: Pulse generator
214: Word line enable signal generator
216: a lead assist signal generator
218: Light assist signal generator or internal-timing-control circuit
310: Integrated Circuit
330: Power Management IC
VDD: first voltage
VDDUD: second voltage
VDDOD: third voltage

Claims (20)

1. An integrated circuit embedded with a memory cell comprising a word line, a bit line pair, and a storage cell coupled to the word line and the bit line pair,
A timing control circuit for generating switch signals in response to an operation control signal;
A first voltage, a second voltage, and a third voltage having different levels and outputting any one of the first voltage, the second voltage, and the third voltage in response to the switch signals ; And
And an output terminal connected to the word line, wherein the driver uses any one of the voltages output from the switch circuit as an operation voltage. The method according to claim 1,
Wherein the switch circuit supplies the first voltage to the driver in response to the switch signals generated by the timing control circuit when the operation control signal indicates normal operation,
Wherein the switch circuit supplies the second voltage to the driver in response to the switch signals generated by the timing control circuit when the operation control signal indicates an assist operation, Lt; / RTI >
Wherein the first voltage is higher than the second voltage and lower than the third voltage. 3. The method of claim 2,
Wherein the second voltage and the third voltage are serially supplied to the word line within one cycle of an internal clock signal. The method of claim 3,
The second voltage is a voltage for lead-assist,
Wherein the third voltage is a voltage for write-assist. The semiconductor integrated circuit according to claim 3,
A first switch for outputting the first voltage to the operating voltage of the driver in response to a first switch signal among the switch signals;
A second switch for outputting the second voltage to the operating voltage of the driver in response to a second switch signal among the switch signals; And
And a third switch responsive to a third switch signal among the switch signals for outputting the third voltage to the operating voltage of the driver. 6. The semiconductor memory device according to claim 5,
A read assist signal generator for generating a read assist signal in response to the operation control signal and the internal clock signal;
A write assist signal generator for generating a write assist signal using the read assist signal;
A first switch signal generator for generating the first switch signal using the read assist signal and the write assist signal;
A second switch signal generator for generating the second switch signal using the operation control signal, the read assist signal, and the write assist signal; And
And a third switch signal generator for generating the third switch signal using the operation control signal and the write assist signal. An embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair;
A timing control circuit for generating switch signals in response to an operation control signal; And
A first voltage, a second voltage, and a third voltage having different levels, and responsive to the switch signals, to supply either the first voltage, the second voltage, And a switch circuit for supplying the switch circuit to the switch circuit. 8. The method of claim 7,
Wherein the switch circuit supplies the first voltage to the word line in response to the switch signals generated by the timing control circuit when the operation control signal indicates normal operation,
Wherein the switch circuit supplies the second voltage to the word line in response to the switch signals generated by the timing control circuit when the operation control signal indicates an assist operation, Word line,
Wherein the first voltage is higher than the second voltage and lower than the third voltage. 9. The method of claim 8,
Wherein the second voltage and the third voltage are supplied to the word line within one cycle of an internal clock signal. 10. The method of claim 9,
The second voltage is a voltage for lead-assist,
Wherein the third voltage is a voltage for write-assist. 11. The timing control circuit according to claim 10,
And controls the timing of transition of at least one of the switch signals to adjust the time that the second voltage and the third voltage are supplied to the word line. 9. The method of claim 8,
Wherein the difference between the first voltage and the second voltage and the difference between the first voltage and the third voltage are different. 9. The method of claim 8,
Wherein the difference between the first voltage and the third voltage is greater than the difference between the first voltage and the second voltage. 8. The method of claim 7,
Wherein the embedded memory device is a FinFET-based SRAM. 8. The switching circuit according to claim 7,
An inverter coupled between ground and a voltage supply terminal, said inverter comprising an output terminal coupled to said word line;
A first switch for supplying the first voltage to the voltage supply terminal of the inverter in response to a first switch signal among the switch signals;
A second switch for supplying the second voltage to the voltage supply terminal of the inverter in response to a second switch signal among the switch signals; And
And a third switch for supplying the third voltage to the voltage supply terminal of the inverter in response to a third switch signal among the switch signals. 16. The switch circuit according to claim 15,
A read assist signal generator for generating a read assist signal in response to the operation control signal and the internal clock signal;
A write assist signal generator for generating a write assist signal using the read assist signal;
A first switch signal generator for generating the first switch signal using the read assist signal and the write assist signal;
A second switch signal generator for generating the second switch signal using the operation control signal, the read assist signal, and the write assist signal; And
And a third switch signal generator for generating the third switch signal using the operation control signal and the write assist signal. An application processor; And
And a power management IC for supplying a first voltage, a second voltage, and a third voltage to the application processor,
The application processor,
An embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair;
A timing control circuit for generating switch signals in response to an operation control signal; And
A first voltage, a second voltage, and a third voltage having different levels, and responsive to the switch signals, to supply either the first voltage, the second voltage, And a switching circuit for supplying the switching circuit to the switching circuit. 18. The method of claim 17,
Wherein the switch circuit supplies the first voltage to the word line in response to the switch signals generated by the timing control circuit when the operation control signal indicates normal operation,
Wherein the switch circuit supplies the second voltage to the word line in response to the switch signals generated by the timing control circuit when the operation control signal indicates an assist operation, Word lines,
Wherein the first voltage is higher than the second voltage and lower than the third voltage. 19. The method of claim 18,
Wherein the second voltage and the third voltage are supplied to the word line in one cycle of an internal clock signal,
The second voltage is a voltage for lead-assist,
Wherein the third voltage is a voltage for write-assist. 20. The method of claim 19,
An inverter coupled between ground and a voltage supply terminal, said inverter comprising an output terminal coupled to said word line;
A first switch for supplying the first voltage to the voltage supply terminal of the inverter in response to a first switch signal among the switch signals;
A second switch for supplying the second voltage to the voltage supply terminal of the inverter in response to a second switch signal among the switch signals; And
And a third switch for supplying the third voltage to the voltage supply terminal of the inverter in response to a third switch signal among the switch signals.

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