KR20170080234A - Data driving circuit and display device including the same - Google Patents

Data driving circuit and display device including the same Download PDF

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Publication number
KR20170080234A
KR20170080234A KR1020150191545A KR20150191545A KR20170080234A KR 20170080234 A KR20170080234 A KR 20170080234A KR 1020150191545 A KR1020150191545 A KR 1020150191545A KR 20150191545 A KR20150191545 A KR 20150191545A KR 20170080234 A KR20170080234 A KR 20170080234A
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South Korea
Prior art keywords
voltage
power supply
node
supply line
output
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KR1020150191545A
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Korean (ko)
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김대환
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엘지디스플레이 주식회사
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Publication of KR20170080234A publication Critical patent/KR20170080234A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
    • G09G2300/0838—Several active elements per pixel in active matrix panels forming a linear amplifier or follower with level shifting

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A data driving circuit and a display device including the same are provided. The data driving circuit includes a first intermediate voltage element connected to the first power supply line and the second power supply line, a second intermediate voltage element connected to the second power supply line and the ground line, an output node of the first intermediate voltage element, And a switching block configured to supply either the AVDD voltage or the HVDD voltage through the first power supply line to the first intermediate voltage element, and the HVDD voltage is supplied to the second power supply line. The data driving circuit according to the embodiment of the present invention can remarkably reduce the damage of the intermediate voltage element.

Figure P1020150191545

Description

TECHNICAL FIELD [0001] The present invention relates to a data driving circuit and a display device including the data driving circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving circuit and a display device including the same, and more particularly, to a data driving circuit and a display device including the same that can improve the reliability of an intermediate voltage device.

A flat panel display (FPD) has been employed in various electronic devices such as mobile phones, tablets, notebook computers, televisions and monitors. Recently, FPD includes a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device. Such a display device includes a pixel array including a plurality of pixels, in which an image is displayed and composed of a plurality of pixels, and a driving circuit that controls light to be transmitted or emitted in each of the plurality of pixels. The driving circuit of the display device is a data driving circuit for supplying a data signal to the data lines of the pixel array, and sequentially supplies a gate signal (or a scanning signal) synchronized with the data signal to the gate lines (or scan lines) And a timing controller for controlling the gate driver circuit (or the scan driver circuit) and the data driver circuit and the gate driver circuit.

1 is a schematic block diagram for explaining a conventional data driving circuit. 2 is a waveform diagram of a voltage input to the conventional data driving circuit shown in FIG.

Referring to FIG. 1, a data driving circuit 100 includes a plurality of elements 111, 112, 113, 121, 122, 123 and an output switch 130. Specifically, in the data driving circuit 100, the first voltage element 110 of the plurality of elements 111, 112, 113, 121, 122, and 123 is disposed between the first power source line and the second power source line, The two-voltage device 120 is disposed between the second power supply line and the ground line. That is, the first voltage device 110 is electrically connected to the first power line and the second power line, and the second voltage device 120 is electrically connected to the second power line and the ground line. Here, the first voltage device 110 includes a first gamma output buffer 111, a first conversion unit 112, and a first output buffer 113, and the second voltage device 120 includes a second gamma output A buffer 121, a second conversion unit 122, and a second output buffer 123. [

Accordingly, the first voltage element 110 of the plurality of elements 111, 112, 113, 121, 122, and 123 is driven by a difference in voltage supplied to the first power line and the second power line, The voltage device 120 is driven by a difference in voltage supplied to the second power supply line and the ground line, respectively.

1 and 2, when power is applied to the data driving circuit 100, the first voltage line 110 is supplied with the first power line voltage at a high speed through the first power line, The second power line voltage is supplied through the line at a speed slower than the first power line voltage. Here, the AVDD voltage is supplied from the ground voltage (GND), which is the minimum voltage, to the AVDD voltage, which is the minimum voltage, and the HVDD voltage, which is the maximum voltage, is supplied from the ground voltage (GND) which is the minimum voltage to the second power supply line. Since the HVDD voltage generated through the resistor divider is supplied to the second power supply line, the HVDD voltage is delayed from the AVDD voltage and supplied to the second power supply line. That is, the first power supply line voltage supplied to the first power supply line quickly reaches the maximum voltage than the second power supply line voltage supplied to the second power supply line. Accordingly, the voltage difference DELTA VDD between the first power supply line and the second power supply line gradually increases and then gradually decreases from the time t when the AVDD voltage starts to be supplied to the first power supply line, and the frame starts HVDD voltage at the time point. That is, the voltage difference DELTA VDD between the first power supply line and the second power supply line may be higher than the HVDD voltage for a certain period after power is applied and before the frame starts.

1 and 2, when the first voltage device 110 is an intermediate voltage device having a maximum operating range of HVDD voltage, the voltage difference DELTA VDD between the first power supply line and the second power supply line becomes HVDD A problem may arise in the reliability of the intermediate voltage device during a period exceeding the voltage. That is, if a voltage exceeding the driving range is applied to the first voltage device 110, the first voltage device 110 may be damaged or not operate properly.

Accordingly, there is a need for a data driving circuit and a display device including the same that can improve the reliability of an intermediate voltage device after power is applied to the data driving circuit.

[Related Technical Literature]

One. Data driver and display device having the same (Korean Patent Registration No. 10-0817302)

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data driving circuit and a display device including the same that can operate correctly without damaging an intermediate voltage device.

Another object of the present invention is to provide a data driving circuit and a display device including the same that can improve the reliability of an intermediate voltage device.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a data driving circuit including a first intermediate voltage element connected to a first power line and a second power line, a second power line connected to the first power line, An output switch coupled to the output node of the first intermediate voltage element and to the output node of the second intermediate voltage element, and to the first intermediate voltage element to supply either the AVDD voltage or the HVDD voltage via the first power supply line Switching block, and the second power supply line is supplied with the HVDD voltage.

According to another aspect of the present invention, there is provided a liquid crystal display device including a pixel array in which a plurality of data lines and a plurality of gate lines cross each other, pixels are arranged in each of the crossed regions, And a plurality of data driving circuits each having a plurality of output channels configured to supply a data voltage to the plurality of data driving circuits, wherein each of the plurality of data driving circuits includes a first intermediate voltage element disposed between the first power source line and the second power source line, An output switch connected to an output node of the first intermediate voltage element and an output node of the second intermediate voltage element, and a second intermediate voltage element disposed between the second power supply line and the ground line, and an output switch connected between the output node of the second intermediate voltage element and the output node of the AVDD voltage and the HVDD voltage And a switching block configured to selectively supply one.

The details of other embodiments are included in the detailed description and drawings.

The present invention can manufacture a data driving circuit and a display device including the same that can improve reliability that may occur in an intermediate voltage device until the first frame starts after power is applied.

Further, the present invention can manufacture a data driving circuit and a display device including the same that can remarkably reduce the damage of an intermediate voltage device.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a schematic block diagram for explaining a conventional data driving circuit.
2 is a waveform diagram of a voltage input to the conventional data driving circuit shown in FIG.
3 is a block diagram schematically showing a configuration of a liquid crystal display device according to an embodiment of the present invention.
4 is a block diagram schematically showing the configuration of the data driving circuit shown in FIG. 3 according to an embodiment of the present invention.
5 is a block diagram schematically showing a configuration of a switching block in the X region shown in FIG. 4 according to an embodiment of the present invention.
6 is an input / output waveform diagram of the switching block shown in FIG. 5 according to an embodiment of the present invention.
7 is a wiring diagram schematically showing a power supply line of the data driving circuit shown in FIG. 3 according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It will be understood that when an element or layer is referred to as being on another element or layer, it encompasses the case where it is directly on or intervening another element or intervening another element or element.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a block diagram schematically showing a configuration of a liquid crystal display device according to an embodiment of the present invention. Referring to FIG. 3, the liquid crystal display 1000 includes a liquid crystal display panel 200, a gate driver 300, a data driver 400, a timing controller 500, and a printed circuit board 600.

The liquid crystal display panel 200 includes a display unit 210 having a pixel array in which a plurality of gate lines GL and a plurality of data lines DL are intersected and pixels P are arranged for each intersected region, And a non-display portion 220 disposed in the periphery of the display portion 220.

The timing control unit 500 is disposed on the printed circuit board 600. The timing controller 500 supplies various signals to the gate driver 300 and the data driver 400. Specifically, the timing controller 500 generates a gate driver control signal (GDC) and supplies the gate driver control signal GDC to the gate driver circuit 380 of the gate driver 300. The data driver control signal (DDC) to the data driving circuit 480 of the data driving unit 400. [ The gate drive circuit control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. Here, the gate start pulse GSP is a pulse input to one gate line GL per frame, and indicates one frame period based on one gate line GL.

The gate driver 300 is disposed on at least one side of the non-display portion 220 of the liquid crystal display panel 200. That is, a plurality of gate drivers 300 may be disposed on the non-display portion 220 of the liquid crystal display panel 200. Here, the gate driver 300 includes a gate driver circuit 380 and a flexible circuit film 390. The gate driver 300 supplies a gate voltage to the plurality of pixels P through a plurality of gate lines GL connected to the gate driver circuit 380.

The data driver 400 is disposed on a side of the non-display portion 220 of the liquid crystal display panel 200 where the gate driver 300 is not disposed. The data driver 400 is disposed on the non-display unit 220 and the printed circuit board 600 of the liquid crystal display panel 200 in a superimposed manner. In particular, the data driver 400 may be disposed in a plurality of non-display units 220 of the liquid crystal display panel 200. Further, the plurality of data driving circuits 480 included in the data driver 400 have a plurality of output channels configured to supply data voltages to the plurality of data lines DL.

The data driver 400 includes a data driving circuit 480 and a flexible circuit film 490. The data driver 400 is electrically connected to the output channel disposed in the non-display portion 220 of the liquid crystal display panel 200 and the flexible circuit film 490 in pads disposed on the printed circuit board 600. Accordingly, the data driver 400 can electrically connect various lines of the data line DL of the liquid crystal display panel 200 and the printed circuit board 600.

Here, the data driving circuit 480 includes a data latch, a gamma output buffer, a digital-analog converter (DAC), an output buffer, and the like so as to supply a data voltage to a plurality of data lines DL . That is, the data driving circuit 480 includes various elements for generating the data voltage, and a separate power source for driving the elements included in the data driving circuit 480 is also required. Accordingly, the data driving circuit 480 includes elements constituting a gamma output buffer, a digital-analog converting section, and an output buffer, and AVDD voltage and HVDD voltage can be supplied as power to these elements. The specific elements constituting the data driver circuit 480 and the power supply line for supplying power to the elements will be described later with reference to Fig.

4 is a block diagram schematically showing the configuration of the data driving circuit shown in FIG. 3 according to an embodiment of the present invention. 4, the data driving circuit 480 includes a first intermediate voltage element 410, a second intermediate voltage element 420, an output switch 430, and a switching block 450. [

Referring to FIG. 4, a first intermediate voltage device 410 is disposed between the first power supply line and the second power supply line. Further, the first intermediate voltage device 410 is connected to the first power supply line and the second power supply line. Likewise, the second intermediate voltage device 420 is disposed between the second power supply line and the ground line. Further, the second intermediate voltage device 420 is connected to the second power supply line and the ground line. Herein, the ground voltage is supplied as the minimum value and the AVDD voltage is supplied as the maximum value to the first power supply line, and the ground voltage is supplied as the minimum value and the HVDD voltage is supplied as the maximum value to the second power supply line.

The first intermediate voltage device 410 includes a first gamma output buffer 411, a first digital-analog converter 412, and a first output buffer 413. Similarly, the second intermediate voltage device 420 includes a second gamma output buffer 421, a second digital-analog converter 422, and a second output buffer 423.

Each of the first intermediate voltage element 410 and the second intermediate voltage element 420 has a driving voltage set to be able to operate properly. Specifically, each of the first intermediate voltage element 410 and the second intermediate voltage element 420 has a driving voltage set such that a voltage difference across the both ends is operable between the ground voltage and the HVDD voltage.

Here, the fact that each of the first intermediate voltage element 410 and the second intermediate voltage element 420 can operate properly means that the expected output from each of the first intermediate voltage element 410 and the second intermediate voltage element 420 This means that the occurrence or expected operation is performed.

4, the voltage? VDD supplied to the first intermediate voltage device 410 is applied to the first intermediate voltage device 410 through the first power source line connected to the upper portion of the first intermediate voltage device 410, And a second power supply line connected to the second power supply line. That is, the voltage? VDD supplied to the first intermediate voltage element 410 is a voltage obtained by subtracting the voltage supplied to the second voltage line from the voltage supplied to the first voltage line.

Accordingly, when a voltage between the ground voltage and the HVDD voltage is supplied to the first intermediate voltage device 410 and the second intermediate voltage device 420, the first intermediate voltage device 410 and the second intermediate voltage device 420 420 may operate properly. On the other hand, when a voltage higher than the HVDD voltage is applied to each of the first intermediate voltage device 410 and the second intermediate voltage device 420, the first intermediate voltage device 410 and the second intermediate voltage device 420 are destroyed And the first intermediate voltage device 410 and the second intermediate voltage device 420 may have reliability problems. That is, when the voltage (? VDD) supplied to the first intermediate voltage device 410 is the ground voltage to the HVDD voltage, the first intermediate voltage device 410 can operate normally.

The output switch 430 is connected to either the output node of the first intermediate voltage device 410 or the output node of any one of the second intermediate voltage device 420. Specifically, the output switch 430 is connected to the output node of the first output buffer 413 and the output node of the second output buffer 423. Accordingly, the output switch 430 supplies the data voltage received from each of the output buffers to the data lines.

Referring to FIG. 4, in the data driving circuit 480, the switching block 450 is configured to supply either the AVDD voltage or the HVDD voltage to the first intermediate voltage device 410 through the first power supply line. Specifically, the switching block 450 includes a first switch SW1 and a second switch SW2, and the first switch SW1 and the first switch SW2 are connected to the first power line via the first switch SW1 and the second switch SW2. It is possible to selectively supply either the AVDD voltage or the HVDD voltage to the voltage device 410. That is, the AVDD voltage and the HVDD voltage are not simultaneously applied to the first power supply line connected to the first intermediate voltage device 410.

Thus, in order to selectively supply the AVDD voltage and the HVDD voltage in the switching block 450, the first switch SW1 and the second switch SW2 in the switching block 450 alternately operate. That is, the first switch SW1 and the second switch SW2 are alternately turned on.

The first switch SW1 is configured to selectively supply the HVDD voltage to the first power supply line. Thus, the first switch SW1 selects whether or not the second power line is connected to the first power line. Here, the first switch SW1 is disposed on a second power supply line connected to a part of the first power supply line to which the first intermediate voltage device 410 is connected. That is, the first switch SW1 is disposed between the HVDD power supply line and the first power supply line, and selectively supplies the HVDD voltage to the first power supply line.

Accordingly, when the first switch SW1 is turned on, the first power supply line and the second power supply line are electrically connected to each other. That is, when the first switch SW1 is turned on, the HVDD power supply line is connected to the first power supply line, so that the HVDD voltage is supplied to both the first power supply line and the second power supply line. Accordingly, the HVDD voltage can be supplied to the upper and lower portions of the first intermediate voltage element 410.

And the second switch SW2 is configured to selectively supply the AVDD voltage to the first power supply line. That is, the second switch SW2 selects whether or not the AVDD voltage is supplied to the first intermediate voltage element 410. Here, the second switch SW2 is disposed on an extension line to the first power supply line to which the first intermediate voltage element 410 is connected. That is, the second switch SW2 is disposed between the AVDD power supply line and the first power supply line.

Accordingly, when the second switch SW2 is turned on, the AVDD power supply line may be directly connected to the first power supply line to supply the AVDD voltage to the upper portion of the first intermediate voltage device 410. [

The data driving circuit 480 according to an embodiment of the present invention includes a first intermediate voltage element 410 and a second intermediate voltage element 420. In addition, the data driving circuit 480 selectively supplies the driving voltage through the switching block 450 so that the first intermediate voltage device 410 can operate properly. Specifically, the switching block 450 selectively supplies either the AVDD voltage or the HVDD voltage to the first intermediate voltage element 410 through the first switch SW1 and the second switch SW2.

The data driving circuit 480 outputs the voltage? VDD supplied to the first intermediate voltage element 410 through the first switch SW1 and the second switch SW2 of the switching block 450 to the set driving voltage Within a range of < / RTI > Furthermore, damage due to the voltage supplied to the plurality of intermediate voltage elements included in the data driving circuit 480 is suppressed. The specific configuration and driving of the switching block 450 will be described later with reference to Figs. 5 and 6. Fig.

5 is a block diagram schematically showing a configuration of a switching block in the X region shown in FIG. 4 according to an embodiment of the present invention. 6 is an input / output waveform diagram of the switching block shown in FIG. 5 according to an embodiment of the present invention. 5 is a block diagram showing an enlarged view of the X region in the data driving circuit 480 shown in FIG. 4. Therefore, a duplicated description of substantially the same configuration will be omitted. For convenience of description, FIG. 4 will be described later with reference to FIG.

Referring to FIGS. 5 and 6, the switching block 450 includes a latch 451, a level shifter 452, a first transistor TFT1, and a second transistor TFT2. Here, the first transistor TFT1 corresponds to the first switch SW1 in Fig. 4, and the second transistor TFT2 corresponds to the second switch SW2 in Fig.

The latch 451 includes a SET signal, a RESET signal, and an input node for receiving the gate start pulse GSP as a clock signal, and has a Q node and a QB node as output nodes. Here, the latch 451 is connected to the first transistor TFT1 and the second transistor TFT2. Specifically, the latch 451 is electrically connected to the first transistor TFT1 at the QB node, and electrically connected to the second transistor TFT2 at the Q node.

The level shifter 452 has an input node connected to the Q node and the QB node, and an output node connected to the first transistor TFT1 and the second transistor TFT2. Thus, the level shifter 452 level-shifts the output voltage of the QB node to supply it to the gate electrode of the first transistor TFT1, and level-shifts the output voltage of the Q node to the gate electrode of the second transistor TFT2 Supply.

Referring to FIG. 5, the first transistor TFT1 has a gate electrode connected to the QB node and a drain electrode connected to the drain electrode of the second transistor TFT2. The second transistor TFT2 has a gate electrode connected to the Q node and a drain electrode connected to the drain electrode of the first transistor TFT1. Each of the first transistor TFT1 and the second transistor TFT2 may be a PMOS transistor.

5 and 6, all the signals input to and outputted from the latch 451 before the data driving circuit 480 is powered on are all low voltages. Specifically, the SET signal, the RESET signal, and the gate start pulse GSP input to the latch 451 are both low voltage, and the output voltage of the Q node and the output voltage of the QB node output from the latch 451 are both low to be. That is, the switching block 450 does not operate until the data driving circuit 480 is powered on.

Referring to FIGS. 5 and 6, a period from a time when power is turned on to a data driving circuit 480 until a frame starts is defined as a first state. That is, the first state is a period between the rising edge of the SET signal and the rising edge of the gate start pulse GSP, which is a clock signal.

In the first state, as the power is turned on to the data driving circuit 480, the SET signal is input to the latch 451 as a high voltage, and the RESET signal delayed for a predetermined time period from the SET signal is input as a high voltage do. The SET signal is a power supply signal for the data driving circuit 480 and the RESET signal is a signal for indicating that the data driving circuit 480 is in the first state.

In the first state, as the SET signal is input to the latch 451 at a high voltage, the output voltage of the Q node rises to a high voltage and the output voltage of the QB node is continuously output to the low voltage. Accordingly, the output voltage of the QB node is input to the gate electrode of the first transistor TFT1, and the first transistor TFT1, which is a PMOS transistor, is turned on.

Then, in the first state, the first transistor TFT1 is turned on so that the HVDD power supply line is connected to the first power supply line, and the first intermediate voltage element 410 and the first intermediate voltage element 410 are turned on, The HVDD power line is connected to the lower portion of the HVDD.

Accordingly, the first power supply line voltage connected to the upper portion of the first intermediate voltage device 410 and the second power supply line voltage connected to the lower portion of the first intermediate voltage device 410 rise to the HVDD voltage until the start of the frame do. In addition, the voltage? VDD supplied to the first intermediate voltage element 410 is shorted to the second power supply line and held at the ground voltage.

Referring to FIGS. 5 and 6, a period after the start of a frame is defined as a second state. That is, the second state includes a period after the rising edge of the gate start pulse GSP which is a clock signal. However, although the second state is not shown in FIG. 6, the second state may be limited to a point in time when power is not applied to the data driving circuit 480 (power off).

In the second state, the latch 451 receives the gate start pulse GSP as a clock signal and inverts the output voltage of the Q node and the output voltage of the QB node at the rising edge of the first pulse of the gate start pulse GSP . Specifically, as the gate start pulse GSP, which is a clock signal, is input to the latch 451 at a high voltage, the output voltage of the Q node falls to the low voltage in the rising edge of the first pulse of the gate start pulse GSP, The output voltage of the QB node rises to the high voltage as opposed to the output voltage of the Q node. Accordingly, the output voltage of the QB node is input to the gate electrode of the first transistor TFT1, and the first transistor TFT1 is turned off. Conversely, as the output voltage of the Q node is input to the gate electrode of the second transistor TFT2, the second transistor TFT2 is turned on.

Then, in the second state, the second transistor TFT2 is turned on, and the AVDD power supply line is connected to the first power supply line and connected to the upper portion of the first intermediate voltage device 410. [ Conversely, the first transistor TFT1 is turned off, and the connection between the HVDD power supply line and the first power supply line is cut off. That is, an AVDD power supply line is connected to an upper portion of the first intermediate voltage device 410, and an HVDD voltage is supplied to a lower portion of the first intermediate voltage device 410 through a second power supply line.

Accordingly, when the second state starts, the AVDD voltage is supplied to the upper portion of the first intermediate voltage device 410 through the first power source line, and the AVDD voltage is supplied to the lower portion of the first intermediate voltage device 410 through the second power source line. HVDD voltage is supplied. Since the AVDD voltage is supplied to the first power supply line from the time when the power is turned on to the data driving circuit 480, the first power supply line voltage is maintained at the moment when the second transistor TFT2 is turned on It can rise to the AVDD voltage. The voltage? VDD supplied to the first intermediate voltage element 410 is supplied to the lower portion of the first intermediate voltage element 410 at the first power line voltage supplied to the upper portion of the first intermediate voltage element 410 And the second power line voltage. That is, the voltage (? VDD) supplied to the first intermediate voltage element 410 becomes the HVDD voltage.

In the second state, the SET signal and the RESET signal input to the latch 451 are all at a high voltage, and the output voltage of the Q node is a low voltage and the output voltage of the QB node is a high voltage. Thus, in the second state, the latch 451 holds the output voltage of the Q node and the output voltage of the QB node without inverting even when receiving the gate start pulse GSP with the clock signal. That is, the latch 451 drives the switching block 450 by inverting the output voltage of the Q node and the output voltage of the QB node only by the first gate-start pulse GSP.

The data driving circuit 480 according to an embodiment of the present invention controls the voltage DELTA VDD supplied to the first intermediate voltage element 410 through the switching block 450. [ Here, the switching block 450 includes a second transistor TFT2 disposed between the AVDD power supply line and the first power supply line, a first transistor TFT1 disposed between the HVDD power supply line and the first power supply line, a latch 451, And a level shifter 452.

The SET signal is input to the latch 451 to turn on the first transistor TFT1 and turn on the second transistor TFT2 when the data driving circuit 480 is powered on and the first state is started The output voltage of the Q node is raised to a high voltage and the output voltage of the QB node is kept at a low voltage to turn off the QB node.

Accordingly, the voltage (? VDD) supplied to the first intermediate voltage device (410) during the first state is maintained at the ground voltage, and a voltage lower than the HVDD voltage is supplied to the first intermediate voltage device (410). That is, a voltage lower than the HVDD voltage is applied to both the first intermediate voltage element 410 and the second intermediate voltage element 420 during the first state. Thus, the intermediate voltage elements in the data driving circuit 480 are not damaged during the first state.

When the frame starts and the first gate start pulse GSP is inputted to the latch 451 as a clock signal to enter the second state, the latch 451 latches the rising edge of the first pulse of the gate start pulse GSP, And the output voltage of the QB node. As the output voltage of the Q node and the output voltage of the QB node are inverted in the second state, the first transistor TFT1 is turned off and the second transistor TFT2 is turned on.

Accordingly, the AVDD voltage is supplied to the upper portion of the first intermediate voltage device 410 through the first power supply line, and the HVDD voltage is supplied to the lower portion of the first intermediate voltage device 410 through the second power supply line. That is, the voltage? VDD supplied to the first intermediate voltage device 410 during the second state is maintained at the HVDD voltage. Thus, the intermediate voltage elements in the data driving circuit 480 are not damaged during the second state.

As a result, the data driving circuit 480 according to an embodiment of the present invention controls the voltage (? VDD) supplied to the first intermediate voltage device 410 during the entire driving period through the switching block 450 to be controlled to be equal to or lower than the HVDD voltage It is possible to suppress the damage of the intermediate voltage elements arranged in the data driving circuit 480 and improve the reliability of the intermediate voltage elements.

7 is a wiring diagram schematically showing a power supply line of the data driving circuit shown in FIG. 3 according to another embodiment of the present invention.

Referring to FIG. 7, the data driving circuit 780 may include a plurality of switching blocks 751, 752, and 753. Specifically, the first switching block 751 is connected to the left of the data driving circuit 780, the second switching block 752 is connected to the center of the data driving circuit 780, and the third switching block 753 is connected to the data driving circuit 780, respectively. The number of switching blocks included in the data driving circuit 780 shown in FIG. 7 and the positions where the switching blocks are disposed are illustrative and not limited to those shown in FIG. 7, and the number of switching blocks and switching The positions in which the blocks are arranged can be different.

Accordingly, a plurality of switching blocks 751, 752, and 753 can be disposed in a plurality of regions of the data driving circuit 780 to selectively connect the first power line to the AVDD power line and the HVDD power line.

The data driving circuit 780 according to another embodiment of the present invention includes a plurality of switching blocks 751, 752 and 753 so that the voltage supplied to the intermediate voltage element included in the data driving circuit 780 is set to be equal to or less than the HVDD voltage . Specifically, each of the plurality of switching blocks 751, 752, and 753 selectively connects either the AVDD voltage or the HVDD voltage to the first intermediate voltage element connected to the first power supply line and the second power supply line through the first power supply line Supply. Here, the plurality of switching blocks 751, 752, and 753 are arranged in parallel in the data driving circuit 780.

Accordingly, the resistors of the switches in the plurality of switching blocks 751, 752, and 753 in the data driving circuit 780 can be connected in parallel. Therefore, in the data driving circuit 780, the resistance of the switches by the switching blocks 751, 752 and 753 can be reduced, and the AVDD voltage and the HVDD voltage supplied to the first voltage line, The problem of dropping can be suppressed.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

200: liquid crystal display panel
210:
220: Non-display portion
300: Gate driver
380, 780: Gate drive circuit
390, 490: Flexible circuit film
400:
410: first intermediate voltage element
411: first gamma output buffer
412: first digital-analog conversion section
413: first output buffer
420: second intermediate voltage element
421: Second gamma output buffer
422: a second digital-analog conversion section
423: Second output buffer
430: Output switch
450: Switching block
451: Latch
452: Level shifter
480: Data driving circuit
500:
600: printed circuit board
751: first switching block
752: Second switching block
753: Third switching block
1000: liquid crystal display

Claims (11)

A first intermediate voltage element connected to the first power supply line and the second power supply line;
A second intermediate voltage element connected to the second power supply line and the ground line;
An output switch connected to the output node of the first intermediate voltage element and the output node of the second intermediate voltage element; And
And a switching block configured to supply either one of an AVDD voltage and an HVDD voltage to the first intermediate voltage element via the first power line,
And the HVDD voltage is supplied to the second power supply line. The method according to claim 1,
The switching block includes:
A first switch configured to selectively supply the HVDD voltage to the first power supply line; And
And a second switch configured to selectively supply the AVDD voltage to the first power supply line. 3. The method of claim 2,
Wherein when the first switch is turned on, the first power line and the second power line are electrically connected to each other. 3. The method of claim 2,
The first switch is a first transistor, the second switch is a second transistor,
The switching block includes:
A latch coupled to the first transistor and the second transistor and having a Q node and a QB node as output nodes; And
And a level shifter having an input node connected to the Q node and the QB node, and an output node connected to the first transistor and the second transistor. 5. The method of claim 4,
Wherein the first transistor comprises:
A gate electrode connected to the QB node, and a drain electrode connected to a drain electrode of the second transistor. 5. The method of claim 4,
Wherein the second transistor comprises:
A gate electrode connected to the Q node, and a drain electrode connected to the drain electrode of the first transistor. 5. The method of claim 4,
The latch
Receives a gate start pulse as a clock signal,
And inverts the output voltage of the Q node and the output voltage of the QB node at a rising edge of a first pulse of the gate start pulse. 8. The method of claim 7,
Wherein the first transistor and the second transistor are PMOS transistors,
Wherein the latch lowers the output voltage of the Q node to a low voltage and raises the output voltage of the QB node to a high voltage at a rising edge of the first pulse of the gate start pulse. The method according to claim 1,
Wherein the first intermediate voltage element and the second intermediate voltage element comprise:
And a drive voltage set to operate between the ground voltage and the HVDD voltage. A pixel array in which a plurality of data lines and a plurality of gate lines cross each other and pixels are arranged in each of the crossed regions; And
And a plurality of data driving circuits having a plurality of output channels configured to supply data voltages to the plurality of data lines,
Wherein each of the plurality of data driving circuits includes:
A first intermediate voltage element disposed between the first power supply line and the second power supply line;
A second intermediate voltage element disposed between the second power supply line and the ground line;
An output switch connected to the output node of the first intermediate voltage element and the output node of the second intermediate voltage element; And
And a switching block configured to selectively supply one of the AVDD voltage and the HVDD voltage to the first power supply line. 10. The method of claim 9,
Wherein each of the plurality of data driving circuits includes a plurality of switching blocks.
KR1020150191545A 2015-12-31 2015-12-31 Data driving circuit and display device including the same KR20170080234A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11436963B2 (en) 2020-03-18 2022-09-06 Silicon Works Co., Ltd Level shift circuit and source driver including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11436963B2 (en) 2020-03-18 2022-09-06 Silicon Works Co., Ltd Level shift circuit and source driver including the same

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