KR20170078051A - Display device and method for driving the same - Google Patents

Abstract

When the timing control circuit according to the embodiment of the present invention is switched to a dynamic section for displaying an operation image in a static section for displaying a still image, the frame frequency of the timing signal for a plurality of frame periods is switched to a second frame And outputs it to the data driver. The embodiment of the present invention alters the liquid crystal at a high frame frequency in the dynamic section, thereby rapidly shaking the liquid crystal having deviated from the static section and alleviating the degree of deviation. Accordingly, the embodiment of the present invention can prevent a residual image, a flicker phenomenon, and a cross talk from being displayed on the image due to accumulation of the liquid crystal DC.

Description

DISPLAY APPARATUS AND METHOD FOR DRIVING THE SAME

An embodiment of the present invention relates to a display device and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

When the display device is implemented as a liquid crystal display device, each of the pixels drives liquid crystal of the liquid crystal layer by an electric field generated by a potential difference between a data voltage supplied to the pixel electrode and a common voltage supplied to the common electrode, It is possible to adjust the amount of transmitted light.

The liquid crystal display repeats the positive polarity and the negative polarity according to the frame frequency. Repeating the positive and negative polarities while displaying the still image, repeats tilt at a constant angle in one direction at positive polarity and at a constant angle in opposite direction at negative polarity. Ideally, the DC voltage is not accumulated when the liquid crystal is operated in positive polarity with a constant period.

However, in actual liquid crystal display devices, the tilt angle is different in the positive polarity and the negative polarity due to the capacitor component of the liquid crystal and the operation characteristics of the thin film transistor (TFT). As a result, there is a polarity that is more tilted among the positive polarity and the negative polarity. For example, a liquid crystal that is more tilted in positive polarity tilts continuously in positive polarity while displaying still images. If the still image continues, the liquid crystal tilts in a direction tilting more. As a result, there may arise a problem that a residual image in which liquid crystal DCs accumulate on an image, a flicker phenomenon of an image, and a cross talk visible in parallel to a line are displayed on the image.

Embodiments of the present invention are intended to provide a display device and a method of driving the same that prevent a residual image, a flicker phenomenon, and a cross talk from being displayed on a picture by accumulating liquid crystal DCs.

An embodiment of the present invention includes data lines, and includes a display panel for displaying still images and operation images, a data driver for supplying data voltages to the data lines, and a timing control circuit. A timing control circuit according to an embodiment of the present invention receives timing signals and digital video data from a system board. When the timing control circuit according to the embodiment of the present invention is switched to a dynamic section for displaying an operation image in a static section for displaying a still image, the frame frequency of the timing signal for a plurality of frame periods is switched to a second frame And outputs it to the data driver.

The embodiment of the present invention changes the frame frequency of the timing signal to a second frame frequency higher than the first frame frequency in a plurality of frame periods when switching to a dynamic section for displaying an operation image in a static section displaying a still image, And outputs it to the driving unit. The embodiment of the present invention changes the tilt angle of the liquid crystal in which the tilt occurs in the static section by varying the liquid crystal at a high frame frequency in the dynamic section to alleviate the degree of deviation of the liquid crystal. Accordingly, the embodiment of the present invention can prevent a residual image, a flicker phenomenon, and a cross talk from being displayed on the image due to accumulation of the liquid crystal DC.

1 is a block diagram of a display apparatus according to an embodiment of the present invention;
2 is an exemplary view of the pixel of Fig.
3 is a block diagram showing a timing control circuit of a display device according to an embodiment of the present invention.
4 is a block diagram showing a frame frequency of a vertical synchronization signal of a display device according to an embodiment of the present invention;
FIG. 5 is a waveform diagram showing a vertical synchronization signal according to the first frame frequency of FIG. 4; FIG.
FIG. 6 is a waveform diagram showing a vertical synchronization signal according to the second frame frequency of FIG. 4; FIG.
7 is a graph showing a frame frequency and an accumulated DC voltage of a display device according to an embodiment of the present invention.
8 is a flowchart of a method of driving a display device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1, a display device according to an embodiment of the present invention includes a display panel 10, a gate driver 20, a data driver 30, a timing control circuit 60, and a common voltage sensing unit 70 do.

The display panel 10 includes a lower substrate and an upper substrate. The data lines D1 to Dm and m are positive integers of two or more), gate lines (G1 to Gn, n is a positive integer of 2 or more), and data lines D1 to Dm and gate lines A display area DA including pixels P arranged in an intersection area of the pixels G1 to Gn is formed. The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area where pixels P are provided to display an image. The non-display area NDA is an area provided in the periphery of the display area DA, and is an area where no image is displayed.

Each of the pixels P may be connected to any one of the data lines D1 to Dm and one of the gate lines G1 to Gn. As a result, each of the pixels P receives a data voltage of the data line Dj when the gate signal is supplied to the gate line Gk as shown in FIG. 2, and emits light at a predetermined brightness according to the supplied data voltage .

When the display device is implemented as a liquid crystal display device, each of the pixels P includes a transistor T, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and a storage capacitor Cst ). The transistor T is connected to the gate of the gate line Gk at a jth (j is a positive integer satisfying 1? J? M) in response to the gate signal of the k-th gate line Gk (k is a positive integer satisfying 1? And supplies the data voltage of the data line Dj to the pixel electrode PE. Each of the pixels P drives the liquid crystal of the liquid crystal layer LC by an electric field generated by a potential difference between a data voltage supplied to the pixel electrode PE and a common voltage supplied to the common electrode CE The amount of light transmitted from the backlight unit can be adjusted. The common electrode CE is supplied with a common voltage from the common line CL. The storage capacitor Cst is provided between the pixel electrode PE and the common electrode CE to maintain a constant voltage difference between the pixel electrode PE and the common electrode CE.

The gate driver 20 supplies gate signals to the gate lines G1 to Gn. Specifically, the gate driver 20 receives the gate control signal GCS, generates gate signals according to the gate control signal GCS, and supplies the gate signals to the gate lines G1 to Gn.

The gate driver 20 may be provided in a non-display area NDA by a gate driver in panel (GIP) scheme. 1, the gate driver 20 is provided in the non-display area NDA outside the one side of the display area DA, but the present invention is not limited thereto. For example, the gate driver 20 may be provided in the non-display area NDA outside both sides of the display area DA.

Alternatively, the gate driver 20 may include a plurality of gate drive integrated circuits (hereinafter referred to as "ICs "), and the gate drive ICs may be mounted on the gate flexible films. Each of the gate flexible films may be a tape carrier package (TCP) or a chip on film (COF). The gate flexible films may be attached to the non-display area NDA of the display panel 10 by a TAB (tape automated bonding) method using an anisotropic conductive film (ACF) And may be connected to lines G1 to Gn.

The data driver 30 is connected to the data lines D1 to Dm. The data driver 30 receives the digital video data DATA and the data control signal DCS from the timing control circuit 60 and converts the digital video data DATA into analog data voltages in accordance with the data control signal DCS. Conversion. The data driver 30 supplies analog data voltages to the data lines D1 to Dm. The data driver 30 may include at least one source driver IC.

The timing control circuit 60 receives digital video data (DATA) and timing signals (TS) from the system board 200. The timing signals TS include a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE and a dot clock DCLK. . ≪ / RTI >

The timing control circuit 60 generates a gate control signal GCS for controlling the operation timing of the gate driver 20 based on the timing signals TS and the drive timing information, And a data control signal DCS for controlling the data control signal DCS. The timing control circuit 60 supplies the gate control signal GCS to the gate driver 20. The timing control circuit 60 supplies digital video data (DATA) and a data control signal (DCS) to the data driver 30. The timing control circuit 60 will be described later in detail with reference to FIG.

The common voltage sensing unit 70 senses the common voltage Vcom of the display panel 10. The common voltage sensing unit 70 generates common voltage information VCS using the sensed common voltage Vcom. The common voltage sensing unit 70 supplies the common voltage information VCS to the timing control circuit 60. [

The common voltage information VCS is information that can confirm whether the display panel 10 is the static section SM or the dynamic section DM. The common voltage information VCS is information that can confirm whether the display panel 10 is the static section SM or the dynamic section DM. The common voltage information VCS changes according to the image gradation. It means that the same image lasts when the common voltage information (VCS) between adjacent frames is the same. It means that the image changes when the common voltage information (VCS) between adjacent frames is different. Accordingly, the common voltage information VCS between the adjacent frames can be compared to determine whether the static section SM for displaying a still image or the dynamic section DM for displaying a dynamic image.

The common voltage sensing unit 70 senses the average of the common voltage Vcom during a certain frame period to generate the common voltage information VCS. Preferably, the root mean square (rms) average value of the common voltage during a certain frame period is sensed. The common voltage sensing unit 70 senses the maximum value and the minimum value of the common voltage Vcom during an arbitrary frame period to generate the common voltage information VCS.

In addition, the common voltage sensing unit 70 senses the waveform of the common voltage Vcom during an arbitrary frame period to generate the common voltage information VCS. The common voltage sensing unit 70 measures rise, fall, tilt, and ripple in the waveform of the common voltage Vcom to calculate common voltage information VCS. Accordingly, the shape of the common voltage Vcom can be sensed more accurately than when the common voltage Vcom is sensed with only some of the parameters such as an intermediate value, and it is possible to clearly distinguish whether the image is changed or not.

The system board 200 supplies the timing signals TS and the digital video data DATA to the timing control circuit 60.

Hereinafter, the timing control circuit 60 of the display device according to the embodiment will be described in detail with reference to FIG. The timing control circuit 60 includes a mode check unit 61, first and second frame frequency output units 62 and 63, a data transfer unit 64, and a data output unit 65.

The mode check section 61 receives the timing signal TS and the digital video data DATA. The mode check unit 61 confirms whether or not it corresponds to a plurality of frame periods (FM).

The plurality of frame periods FM are used to change the frame frequency of the timing signal TS when the display panel 10 is switched from the static section SM for displaying the still image to the dynamic section DM for displaying the operation image, .

The first frame frequency F1 is a frequency of the frame period FM after elapse of a plurality of frame periods FM out of a static section SM for displaying a still image and a dynamic section DM for displaying an operation image, The frequency of the timing signal TS that occurs during the period excluding the period of time T. For example, the first frame frequency F1 may be 60 Hz, but is not limited thereto and may have a frequency sufficient to display a still image. Particularly, in order to reduce power consumption, it is desirable to lower the first frame frequency F1 in the static section SM where the image does not change, and the first frame frequency F1 may be 30 Hz.

The second frame frequency F2 is the frequency of the timing signal TS generated during the plurality of frame periods FM. The second frame frequency F2 is higher than the first frame frequency F1. For example, the second frame frequency F2 may be (60 + alpha) (where alpha is a positive number) Hz.

The mode check unit 61 outputs the timing signal TS to the first frame frequency output unit 62 when it is not a plurality of frame periods FM. The mode check unit 61 outputs the timing signal TS to the second frame frequency output unit 63 in the case of a plurality of frame periods FM. 3 illustrates the case where the mode check unit 61 outputs only the dot clock DCLK and the data enable signal DE but the mode check unit 61 outputs the vertical and horizontal synchronization signals Vsync and Hsync You may.

The mode check unit 61 outputs digital video data (DATA) to the data transfer unit 64. The mode identifying unit 61 distinguishes between a case of a plurality of frame periods FM and a case of a case of not a plurality of frame periods FM to selectively activate the first and second frame frequency output units 62 and 63 . As a result, the frequency that is variable to the second frame frequency (F2) can be output only in the case of a plurality of frame periods (FM).

The first frame frequency output unit 62 receives the timing signal TS when it is not a plurality of frame periods FM. The first frame frequency output unit 62 outputs the data control signal DCS of the first frame frequency F1 to the data output unit 65. [ The first frame frequency output unit 62 outputs the data enable signal DE among the timing signals TS to the data transfer unit 64.

The second frame frequency output section 63 receives the timing signal TS in the case of a plurality of frame periods FM. The second frame frequency output unit 63 outputs the data control signal DCS of the second frame frequency F2 to the data output unit 65. [ The second frame frequency output unit 63 outputs the data enable signal DE among the timing signals TS to the data transfer unit 64.

The data transfer unit 64 receives the digital video data DATA from the mode check unit 61 and receives the data enable signal DE from the first or second frame frequency output unit 62 or 63. The data transfer unit 64 outputs the digital video data DATA to the data output unit 65 in accordance with the data enable signal DE.

The data output unit 65 receives the digital video data DATA from the data transfer unit 64 and receives the data control signal DCS from the first or second frame frequency output unit 62 or 63. The data output unit 65 outputs the digital video data DATA and the data control signal DCS to the gate driver 30.

4 is a block diagram showing a frame frequency of a display device according to an embodiment of the present invention. All of the timing signals TS may have the same frame frequency per section.

The first frame frequency F1 is a frame frequency of a section after a plurality of frame periods FM among the static section SM and the dynamic section DM, i.e., a section excluding a plurality of frame periods FM.

The second frame frequency F2 is a frame frequency of a section corresponding to a plurality of frame periods FM. The second frame frequency F2 is higher than the first frame frequency F1. Therefore, on the time axis, one frame (frame) of the second frame frequency F2 is shorter than one frame (first frame) of the first frame frequency F1.

5 and 6 are waveform diagrams showing a vertical synchronization signal Vsync according to the first and second frame frequencies F1 and F2 of FIG. 5 and 6 illustrate the vertical synchronization signal Vsync, but not limited thereto, all the timing signals TS have the same frame frequency.

The vertical synchronization signal (Vsync) has the number of frames equal to the frame frequency in one second. The vertical synchronization signal Vsync of the first frame frequency F1 has the same number of frames as the first frame frequency F1.

The vertical synchronization signal Vsync of the second frame frequency F1 has the same number of frames as the second frame frequency F2. The number of frames at the second frame frequency F2 is larger than the number of frames at the first frame frequency F1. The frame length at the second frame frequency F2 is shorter than the frame length at the first frame frequency F1.

One frame (frame) of the vertical synchronization signal (Vsync) includes an active section (AT) and a blank section (BT). The active period AT is a period in which the vertical synchronization signal Vsync supplies the data voltages in a high state. The blank interval BT is a period during which the vertical synchronization signal Vsync does not supply data voltages in a low state.

7 is a graph showing the frame frequency and the accumulated DC voltage (V) of the display device according to the embodiment of the present invention.

In the static section SM for displaying the still image, the accumulated DC voltage V increases while continuously displaying the same image. In the dynamic section DM, the accumulated DC voltage V decreases while the image continuously changes. As the frame frequency increases in the dynamic range (DM), the liquid crystal can be quickly tilted. As the liquid crystal is rapidly tilted, the accumulated DC voltage (V) can be reduced more quickly.

The first frame frequency F1 is used in a section other than the plurality of frame periods FM. During a plurality of frame periods (FM), a second frame frequency (F2) faster than the first frame frequency (F1) is used. The stored DC voltage V can be reduced more quickly during a plurality of frame periods FM.

The plurality of frame periods FM is proportional to the duration of the static section SM. In the static section SM, the accumulated DC voltage V increases proportionally. The longer the plurality of frame periods (FM), the faster the DC voltage (V) accumulated can be reduced, but the power consumption increases. The mode check section 61 adjusts a plurality of frame periods FM capable of rapidly reducing the accumulated DC voltage V to be proportional to the duration of the static section SM. Thereby, it is possible to have a plurality of frame periods (FM) corresponding to the stored DC voltage (V), so that the accumulated DC voltage (V) can be reduced without leaving unnecessary power consumption .

Hereinafter, a driving method of a display apparatus according to an embodiment of the present invention will be described with reference to FIG.

First, the timing control circuit 60 receives the timing signal TS and the digital video data DATA. The timing control circuit 60 performs the following process to determine whether it is a plurality of frame periods (FM).

The common voltage sensing unit 70 generates common voltage information VCS that can be verified as a static section SM or a dynamic section DM. The common voltage information (VCS) is generated using the common voltage (Vcom) sensed by the common voltage sensing unit (70). When generating the common voltage information VCS, the average, maximum value, minimum value, and waveform of the common voltage Vcom in an arbitrary frame are sensed and calculated as described above. (S101 in Fig. 8)

It is verified that the common voltage information VCS during a certain frame period is the same as the common voltage information VCS of the previous frame of the arbitrary frame. (S102 in Fig. 8)

When the two common voltage information (VCS) are the same, the common voltage information (VCS) between adjacent frames is the same. The same common voltage information (VCS) indicates that the image remains unchanged. Accordingly, the mode identifying unit 61 determines that the static section SM is the one in which the image does not change when the two common voltage information VCS are the same. (S103 in Fig. 8)

The static section SM does not correspond to a plurality of frame periods (FM). The first frame frequency output unit 62 receives the timing signal TS and outputs the data control signal DCS of the first frame frequency F1. (S104 in Fig. 8)

The timing control circuit 60 outputs the data control signal DCS and digital video data DATA of the first frame frequency F1 to the data driver 30. [ (S105 in Fig. 8)

When the two common voltage information (VCS) are different, the common voltage information (VCS) between adjacent frames is different. The difference of the common voltage information (VCS) is that an image between adjacent frames is changed. Accordingly, the mode check unit 61 determines the static interval SM in which the image changes when the two common voltage information VCS are different. (S106 in Fig. 8)

In the case of the dynamic range DM, it is determined whether a plurality of frame periods FM have elapsed from the start of the dynamic range DM. The plurality of frame periods (FM) are the number of frames preset in the timing control circuit (60). The plurality of frame periods FM may be proportional to the duration of the static section SM. (S107 in Fig. 8)

And does not correspond to a plurality of frame periods (FM) when a plurality of frame periods (FM) have elapsed. The first frame frequency output unit 62 receives the timing signal TS and outputs the data control signal DCS of the first frame frequency F1 when a plurality of frame periods FM have elapsed. (S104 in Fig. 8)

And corresponds to a plurality of frame periods (FM) when a plurality of frame periods (FM) have not elapsed. The second frame frequency output unit 63 receives the timing signal TS and outputs the data control signal DCS of the second frame frequency F2 in the case of a plurality of frame periods FM. (S108 in Fig. 8)

The timing control circuit 60 outputs the data control signal DCS and the digital video data DATA of the second frame frequency F2 to the data driver 30. [ (S105 in Fig. 8)

The embodiment of the present invention changes the frame frequency of the timing signal to a second frame frequency higher than the first frame frequency in a plurality of frame periods when switching to a dynamic section for displaying an operation image in a static section displaying a still image, And outputs it to the driving unit. The embodiment of the present invention changes the tilt angle of the liquid crystal in which the tilt occurs in the static section by varying the liquid crystal at a high frame frequency in the dynamic section to alleviate the degree of deviation of the liquid crystal. Accordingly, the embodiment of the present invention can prevent a residual image, a flicker phenomenon, and a cross talk from being displayed on the image due to accumulation of the liquid crystal DC.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: gate driver
30: Data driver 60: Timing control circuit
61: mode check unit 62: first frame frequency output unit
63: second frame frequency output unit 64: data transmission unit
65: Data output unit 70: Common voltage sensing unit
200: System board SM: Static section
DM: dynamic range FM: multiple frame periods
DA: display area NDA: non-display area
P: Pixels D1 to Dm: Data lines
G1 to Gn: Gate lines

Claims (9)

A display panel 10 including data lines D1 to Dm;
A data driver 30 for supplying data voltages to the data lines D1 to Dm; And
When the timing signal TS and the digital video data DATA are received from the system board 200 and switched from the static section SM for displaying the still image to the dynamic section DM for displaying the operation image, A timing control circuit 60 for varying the frame frequency of the timing signal TS to a second frame frequency F2 higher than the first frame frequency F1 and outputting the second frame frequency F2 to the data driver 30 during a period FM, . The method according to claim 1,
Wherein the plurality of frame periods (FM) are proportional to the duration of the static section (SM). The semiconductor memory device according to claim 1, wherein the timing control circuit (60)
A mode check unit 61 for receiving the timing signal TS and the digital video data DATA and confirming whether the timing signal TS and the digital video data DATA are the plurality of frame periods FM;
A first frame frequency output unit (62) receiving the timing signal (TS) when not in the plurality of frame periods (FM) and outputting a data control signal (DCS) of the first frame frequency (F1); And
And a second frame frequency output unit (63) for receiving the timing signal (TS) in case of the plurality of frame periods (FM) and outputting a data control signal (DCS) of the second frame frequency (F2) Display device. The method according to claim 1,
And a common voltage sensing unit (70) for providing the timing control circuit (60) with common voltage information (VCS) which can confirm whether the display panel (10) is a static section (SM) Display device. 5. The method of claim 4,
The common voltage information (VCS) senses and calculates an average, a maximum value, a minimum value, and a waveform of the common voltage (Vcom) during an arbitrary frame period. Receiving a timing signal (TS) and digital video data (DATA) and confirming whether it is a plurality of frame periods (FM);
And outputs the data control signal DCS of the first frame frequency F1 upon receipt of the timing signal TS when the frame period FM is not the plurality of frame periods FM, Receiving a timing signal (TS) and outputting a data control signal (DCS) of a second frame frequency (F2) higher than the first frame frequency (F1); And
And outputting the digital video data (DATA) and the data control signal (DCS) to the data driver (30). The method according to claim 6,
Wherein the plurality of frame periods (FM) are proportional to the duration of a static section (SM) for displaying a still image in the display panel (10). 7. The method of claim 6, wherein determining whether the plurality of frame periods (FM)
Generating common voltage information (VCS) that can be confirmed by the common voltage sensing unit (70) as the static interval (SM) or the dynamic interval (DM) for displaying the operation image on the display panel (10);
Comparing the common voltage information (VCS) for the arbitrary frame period with the common voltage information (VCS) of a previous frame of the arbitrary frame to determine the static interval (SM) when the two common voltage information (VCS) Determining the dynamic range DM if the two common voltage information VCS are different; And
And determining whether the plurality of frame periods (FM) have elapsed when switching from the static section (SM) to the dynamic section (DM). 9. The method of claim 8,
The common voltage information (VCS) senses and calculates an average, a maximum value, a minimum value, and a waveform of a common voltage (Vcom) in an arbitrary frame.

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