KR20170060407A - Memory module and memory system including the same - Google Patents

Memory module and memory system including the same Download PDF

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Publication number
KR20170060407A
KR20170060407A KR1020150164830A KR20150164830A KR20170060407A KR 20170060407 A KR20170060407 A KR 20170060407A KR 1020150164830 A KR1020150164830 A KR 1020150164830A KR 20150164830 A KR20150164830 A KR 20150164830A KR 20170060407 A KR20170060407 A KR 20170060407A
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South Korea
Prior art keywords
memory
chips
group
data bus
module
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KR1020150164830A
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Korean (ko)
Inventor
이재준
조정현
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삼성전자주식회사
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Publication of KR20170060407A publication Critical patent/KR20170060407A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/12—Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory module according to the present invention includes a plurality of memories, wherein the memory module transmits and receives a plurality of data signals via a first data bus and a second data bus, And a second memory group including N memories for transmitting and receiving a second data signal via the second data bus, and a second memory group including N memories for transmitting and receiving a second data signal through N second data buses (N is a natural number of 2 or more).

Figure P1020150164830

Description

[0001] The present invention relates to a memory module and a memory system including the memory module,

TECHNICAL FIELD OF THE INVENTION The present invention relates to a memory module and a memory system including the memory module, and more particularly, to a memory module including memories sharing a data bus and a memory system including the memory module.

Computers use various kinds of memory to store data. Initially, the computer directly mounted each memory on the main board, but a memory module with a large number of memories has been proposed in order to solve the problem of the size and complexity of the computer. However, as the memory modules are mounted on the connectors of the main board, the signal integrity is reduced due to the impedance discontinuity due to the connector, so that the high speed There is a need for a way to overcome this by interfering with the operation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory module including memory chips sharing a data bus and a memory system including the memory module.

A memory module according to the present invention includes a plurality of memory chips, wherein the memory module is configured to transmit and receive a plurality of data signals through a first data bus and a second data bus, A second memory group including N memory chips for transmitting and receiving a second data signal via the second data bus and a first memory group including N memory chips for transmitting and receiving signals (N is a natural number of 2 or more) .

In addition, the memory chips of the first memory group share the first data bus, and the memory chips of the second memory group share the second data bus.

The first memory group may include data buffers corresponding to memory chips included in the first memory group, and the first memory group may include data buffers corresponding to the memory chips included in the first memory group Data buffers of the first memory group share the first data bus and data buffers of the second memory group share the second data bus.

In addition, the memory module may include a memory buffer chip that provides the plurality of data signals received from the outside to the plurality of memory chips, and the memory chips of the first memory group include memory chips of the first memory group Wherein the memory chips of the second memory group share the first data bus between the memory chips of the second memory group and the memory buffer chip, And a second data bus for transferring a signal.

The memory module may be a dual in-line memory module (DIMM).

The first memory group and the second memory group are included in a first side of the memory module and the second side of the memory module transmits and receives the first data signal through the first data bus, And a fourth memory group including a third memory group including N memory chips and N memory chips receiving the second data signal via the second data bus, respectively.

The memory module may further include a memory module for receiving a plurality of control signals and activating any one of the memory chips of the first memory module and the memory chips of the second memory module based on the control signals, And activates any one of the memory chips of the third memory module and the memory chips of the fourth memory module.

A memory system according to another embodiment of the present invention includes a first memory group including a plurality of memory chips sharing a first data bus and a second memory group including a plurality of memory chips sharing a second data bus A third memory group including a plurality of memory chips sharing a third data bus, and a fourth memory group including a plurality of memory chips sharing a fourth data bus, And a memory controller for providing data signals to the first memory module and the second memory module via the data buses.

The memory controller may be configured to select one of the memory chips of the first memory group, one of the memory chips of the second memory group, one of the memory chips of the third memory group, The plurality of control signals are provided to the first memory module and the second memory module, respectively, in order to simultaneously activate any one of the chips.

The first memory module further includes a first RCD, and the second memory module further includes a second RCD, wherein the first RCD and the second RCD are connected to the plurality of The memory chips of any one of the memory chips of the first memory group, any one of the memory chips of the second memory group, any one of the memory chips of the third memory group, Is activated at the same time.

The memory module of the present invention and the memory system including the memory module of the present invention include the memory chips of the memory group sharing the data bus in the memory module so that the signal failures that may occur when a plurality of memory modules are mounted in the main mode connectors This can reduce the loss of the property.

1 is a block diagram illustrating a memory module according to embodiments of the present invention.
2 is a block diagram illustrating a memory module according to another embodiment of the present invention.
3 is a block diagram illustrating a memory module according to another embodiment of the present invention.
4 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
5 is a block diagram of a memory system for illustrating a method for activating memory chips of a memory system in accordance with an embodiment of the invention.
6 is a block diagram of a memory system to illustrate a method for activating memory chips of a memory system in accordance with another embodiment of the present invention.
7 is a block diagram of a memory system to illustrate a method for activating memory chips of a memory system in accordance with another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a block diagram illustrating a memory module according to embodiments of the present invention.

As shown in FIG. 1, the memory module 100a includes a plurality of memory groups 110a-130a. The memory module 100a may be a Fully Buffered Dual In-Line Memory Module (FB-DIMM), a Registered Dual In-Line Memory Module (RDIMM), a Load Reduced Dual In-Line Memory Module (LRDIMM)

The first memory group 110a includes a plurality of memory chips 111a-113a, the second memory group 120a includes a plurality of memory chips 121a-123a, and the third memory group 130a includes And includes a plurality of memory chips 131a-133a. The memory module 100a actually includes data buses DQ1-DQ3 for exchanging data signals with the memory chips 111a-113a, 121a-123a and 131a-133a, a command for instructing data read / / Address / clock / control signal to the memory controller. A memory controller can be directly connected to a central processing unit (CPU). The memory controller may be directly connected to the CPU directly, and in another embodiment, the memory controller may be manufactured as part of the CPU itself. The memory controller and the memory module can configure the memory system.

In one embodiment, the memory chips include a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), an LPDDR (Low Power Double Data Rate) SDRAM, a GDDR (Graphics Double Data Rate) SDRAM, a RDRAM Such as a dynamic random access memory (DRAM), or any other volatile memory device.

The plurality of memory chips 111a-113a of the first memory group 110a according to the embodiment of the present invention can transmit and receive the first data signal through the first data bus DQ1. The plurality of memory chips 121a-123a of the second memory group 120a can transmit and receive the second data signal through the second data bus DQ2. The plurality of memory chips 131a-133a of the third memory group 130a can transmit and receive the third data signal through the third data bus DQ3. Further, the plurality of memory chips 111a-113a of the first memory group 110a may share the first data bus DQ1 and the plurality of memory chips 121a-123a of the second memory group 120a May share a second data bus DQ2 and a plurality of memory chips 131a-133a of the third memory group 130a may share a third data bus DQ3.

By including the memory chips of the memory group sharing the data bus in the memory module as described above, it is possible to reduce the signal integrity defect that may occur when a plurality of memory modules are mounted in the main mode connectors, There is a possible effect.

2 is a block diagram illustrating a memory module according to another embodiment of the present invention.

As shown in FIG. 2, the memory module 100b includes a plurality of memory groups 110b-130b and a memory buffer chip 140. The memory buffer chip 140 receives a command, an address, a clock, a control and a data signal from the memory controller and supplies the received command, address, clock, control and data signal to the memory chips 111b-113b, 121b- 133b. The memory controller can interface with the memory module 100b by driving only the load of the memory buffer chip 140 since the memory buffer chip 140 buffers all of the command, address, clock, control, and data signals.

Sharing a first data bus DQ1 for transferring a first data signal between a plurality of memory chips 111b-113b of the first memory group 110b and the memory buffer chip 140, And a second data bus DQ2 for transferring a second data signal between the plurality of memory chips 121b-123b of the third memory group 130b and the memory buffer chip 140, And a third data bus DQ3 for transferring a third data signal between the memory buffer chip 140 and the memory buffer chip 140. [

3 is a block diagram illustrating a memory module according to another embodiment of the present invention.

As shown in FIG. 3, the memory module 100c includes a plurality of memory groups 110c-130c and a registering clock driver (RCD) 150. Referring to FIG. The first to third memory groups 110c-130c include a plurality of data buffers 114c-116c, 124c-126c, 134c-136c, respectively, as compared to the first memory group 110a of Figure 1 .

Each of the memory chips 111c-113c, 121c-123c, 131c-133c may be correspondingly connected to each of the data buffers 114c-116c, 124c-126c, 134c-136c. In the case where the printed circuit board of the memory module 100c is made of a multi layer, the inner connection layer of the memory chips 100a to 100c is electrically connected to the electrical connection pads of the memory chips 111c to 113c, 121c to 123c, 114c-116c, 124c-126c, 134c-136c, respectively. The signal lines may serve to transmit data signals. The data buffers 114c-116c, 124c-126c, and 134c-136c can buffer data signals input to / output from / to the memory module 100c. The data buffers 114c-116c of the first memory group 110c share the first data bus DQ1 and the data buffers 124c-126c of the second memory group 120c share the second data Bus DQ2 and the data buffers 134c-136c of the third memory group 130c may share the third data bus DQ3.

The RCD 150 may have a function of buffering and resuming commands, addresses, clocks, and control signals received from the memory controller. The command, address, clock, and control signal output from the RCD 150 may be provided to the memory chips 111c-113c, 121c-123c, 131c-133c.

4 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.

The memory system 200 includes a first memory module 210, a second memory module 220, a third memory module 230, and a memory controller 240, as shown in FIG.

The first memory module 210 may include a first memory group 211, a first memory group 212, and a first memory group 213. The memory chips 211_1-211_3 of the first memory group 211 share the first data bus DQ1 and the memory chips 212_1-212_3 of the first memory group 212 share the second data And the memory chips 213_1 to 213_3 of the first memory group 213 may share the third data bus DQ3.

The memory chips 221_1-221_3 of the 2-1 memory group 221 share the fourth data bus DQ4 and the memory chips 222_1-222_3 of the 2-2 memory group 222 share the fifth data And the memory chips 223_1 to 223_3 of the second to third memory group 223 may share the sixth data bus DQ6.

The memory chips 231_1-231_3 of the 3-1 memory group 231 share the seventh data bus DQ7 and the memory chips 232_1-232_3 of the 3-2 memory group 232 share the eighth data And the memory chips 313_1-313_3 of the third-third memory group 313 may share the ninth data bus DQ9.

The first memory module 210 may be connected to the first data bus DQ1, the fourth data bus DQ4 and the seventh data bus DQ7 to transmit and receive data signals. The second memory module 220 may be connected to the second data bus DQ2, the fourth data bus DQ4 and the seventh data bus DQ7 to transmit and receive data signals through the second data bus DQ2, the fourth data bus DQ4 and the seventh data bus DQ7. The third memory module 230 is connected to the third data bus DQ3, the sixth data bus DQ6 and the ninth data bus DQ9 to transmit and receive data signals through the third data bus DQ3, the sixth data bus DQ6 and the ninth data bus DQ9.

Thus, each memory module can be connected to the same number of data buses as the number of memory groups included in each memory module. For example, when the number of memory groups 211 to 213 included in the first memory module 210 is three, the first memory module 210 is connected to the three data buses DQ1, DQ4, and DQ7 .

Conventionally, a configuration in which memory chips between memory modules share a data bus is applied to a memory system. For example, the memory chip 211_1 of the first memory module 210, the memory chip 221_1 of the second memory module 220, and the memory chip 231_1 of the third memory module 230 are connected to the first data bus (DQ1). Due to such a structure, a plurality of junctions are generated in the signal lines corresponding to the data bus, and a problem that signal integrity is hindered due to a connection to which the memory module is mounted occurs.

Thus, the memory system 200 according to the embodiment of the present invention applies a structure in which memory chips in each memory module 210-230 can share a data bus, thereby reducing the junctions, It has the effect of reducing non-defective disturbance.

5 is a block diagram of a memory system for illustrating a method for activating memory chips of a memory system in accordance with an embodiment of the invention.

The memory system 300 includes a first memory module 310, a second memory module 320, a third memory module 330, and a memory controller 340, as shown in FIG. The first through third memory modules 310-330 may include memory chips on a first side and a second side, respectively, with a dual in-line memory module (DIMM). In one embodiment, the first memory module 310 includes a first memory group 311_A, a first memory group 312_A, and a first memory group 313_A. The first memory module 310 includes a first memory group 311_B, a first memory group 312_B, and a first memory group 313_B. As described above, each of the memory groups 311_A-313_B may include memory chips that share a data bus. The first memory group 311_A and the first memory group 311_B, the first memory group 312_A and the first memory group 312_B, the first memory group 313_A And the 1-6 memory group 316_B may each include memory chips that share a data bus. For example, the memory chips R1_1, R1_3, and R1_5 of the 1-1 memory group 311_A share the memory chips R1_2, R1_4, and R1_5 of the 1-4 memory group 311_B when sharing the first data bus, R1_6 may also share the first data bus.

The second memory module 320 includes a second-1 memory group 321_A, a second-2 memory group 322_A, and a second-third memory group 323_A on the first surface thereof. The second memory module 320 includes a second-fourth memory group 321_B, a second-fifth memory group 322_B, and a second-sixth memory group 323_B on the second surface thereof. Also, as described above, each memory group 321_A-323_B may include memory chips that share a data bus. The 2-1 memory group 321_A and the 2-4 memory group 321_B, the 2-2 memory group 322_A and the 2-5 memory group 322_B, the 2-3 memory group 323_A And the second 2-6 memory group 326_B may each include memory chips that share a data bus. For example, the memory chips R2_1, R2_3, and R2_5 of the 2-1 memory group 321_A share the memory chips R2_2, R2_4, and R2_4 of the 2-4 memory group 321_B when sharing the fourth data bus. R2_6 may also share the fourth data bus.

The third memory module 330 includes a third memory group 331_A, a third memory group 332_A, and a third memory group 333_A on the first side. The third memory module 330 includes a third-fourth memory group 331_B, a third-fifth memory group 332_B, and a third-sixth memory group 333_B on the second side. Also, as described above, each memory group 331_A-333_B may include memory chips that share a data bus. The third-1 memory group 331_A and the third-fourth memory group 331_B, the third-second memory group 332_A and the third-fifth memory group 332_B, the third-third memory group 333_A And the third 3-6 memory group 336_B may each include memory chips that share a data bus. For example, the memory chips R3_1, R3_3, and R3_5 of the 3-1 memory group 331_A share the memory chips R3_2, R3_4, and R4_5 of the 3-4 memory group 331_B when sharing the seventh data bus. R3_6 may also share the seventh data bus. Hereinafter, in the embodiment of the present invention, the memory chips included in the first face of the memory module may be referred to as memory chips of the first rank, and the memory chips included in the second face may be referred to as the memory chips of the second rank .

The memory controller 340 provides the first to sixth control signals Ctrl1 to Ctrl6 to the first memory module 310, the second memory module 320 and the third memory module 330, It is possible to select and activate predetermined memory chips among the memory chips. In one embodiment, the first control signal line is connected to the first memory chips R1_1 of the memory groups 311_A-313_A on the first side of the first memory module 310, The third control signal line is connected to the second memory chips R1_3 of the memory groups 311_A-313_A of the memory module 310 and the fifth control signal line is connected to the third memory of the memory groups 311_A-313_A of the first memory module 310, Lt; RTI ID = 0.0 > R1_5. ≪ / RTI > The second control signal line is connected to the first memory chips R1_2 of the memory groups 311_B-313_B on the second side of the first memory module 310 and the fourth control signal line is connected to the first memory module The fifth control signal line is connected to the third memory chips R1_6 of the memory groups 311_A-313_A of the first memory module 310 and the third memory chips R1_4 of the memory groups 311_B-313_B of the first memory module 310, Lt; / RTI > Through such a structure, the memory chips of the first rank or the memory chips of the second rank of the first to third memory modules 310 to 330 can be selected and activated.

In addition, in one embodiment, the memory controller 340 may provide a plurality of control signals (Ctrl1-Ctrl6) to select one of memory chips included in each memory group of the first through third memory modules 310-330 Any one can be selected and activated. For example, any one of the memory chips of the 1-1 memory group 311_A of the first memory module 310, any of the memory chips of the 1-2 memory group 312_A, It is possible to activate any one of the memory chips of the memory 313_A. In summary, the memory chips (R1_2, R1_4, R1_6) in the second rank of the first memory module 310 can be inactivated using the second, fourth, and sixth control signals, and the first, Only the memory chips R1_3 of the first rank memory chips R1_1, R1_3, and R1_5 can be activated using the fifth control signal. The activated memory chips R1_3 can input and output the data signal through the corresponding data signal, respectively.

In this manner, the memory chips R_3 of the first rank of the second memory module 320 and the memory chips R_3 of the first rank of the third memory module 330 can be selected and activated. In one embodiment, in the case where one memory chip is an I / OX8 configuration and one rank has an I / Ox72 configuration including nine memory chips, according to one embodiment of the present invention, Nine memory chips in the memory chips of the memory modules 310-330 may be activated and the size of data that can be input and output using the activated memory chips may be the same as before.

6 is a block diagram of a memory system to illustrate a method for activating memory chips of a memory system in accordance with another embodiment of the present invention.

6, the memory controller 440 provides only the first to third control signals (Ctrl1 to Ctrl3) to select predetermined memory chips from among the plurality of memory chips to activate them . The memory chips R1_1 to R3_6 included in the first memory module 410, the second memory module 420 and the third memory module 430 are all connected to the first control signal line to the third control signal line . In addition, the memory chips R1_1 to R2_6 may have respective unique activation IDs, and the activation ID information may be stored in the control logic included in each of the memory chips R1_1 to R2_6.

In one embodiment, on the basis of the first to third control signals (Ctrl1 to Ctrl3), a memory chip having an activation ID corresponding to the first to third control signals (Ctrl1 to Ctrl3) among the memory chips (R1_1 to R3_6) Can be activated. For example, when the signal values of the first to third control signals (Ctrl1 to Ctrl3) are respectively 111, the memory chips (R1_5, R2_5, R3_5) having the same activation ID as the signal value of 111 can be activated have. Accordingly, a fewer number of control signals than the memory controller of FIG. 5 may be provided to the memory modules 410-430 to activate some of the memory chips.

7 is a block diagram of a memory system to illustrate a method for activating memory chips of a memory system in accordance with another embodiment of the present invention.

As shown in FIG. 7, unlike FIG. 5, the first to third memory modules 510 to 530 further include first to third RCDs 515, 525, and 535, respectively. Also, the memory controller 540 may provide the first to third control signals (Ctrl1 to Ctrl3) to the first to third RCDs 515, 525, and 535, respectively. The first to third RCDs 515, 525 and 535 can activate some of the memory chips R1_1 to R3_6 based on the first to third control signals (Ctrl1 to Ctrl3). In one embodiment, the first to third RCDs 515, 525, and 535 store an activation information table including memory chip ID information to be activated according to the signal values of the first to third control signals (Ctrl1 to Ctrl3) . For example, when the signal values of the first to third control signals (Ctrl1 to Ctrl3) are 100, the first to third RCDs 515, 525, and 535 refer to the activation information tables included therein, It is possible to activate the memory chips having the memory chip ID corresponding to the signal value. Accordingly, the first to third RCDs 515, 525, and 535 can select and activate some of the memory chips R1_1, R2_1, and R3_1.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

1. A memory module comprising a plurality of memory chips,
The memory module comprising:
Transmitting and receiving a plurality of data signals through a first data bus and a second data bus,
A first memory group including N (N is a natural number of 2 or more) memory chips for transmitting and receiving a first data signal through the first data bus; And
And a second memory group including N memory chips for transmitting and receiving a second data signal via the second data bus. The method according to claim 1,
Wherein the memory chips of the first memory group share the first data bus,
And the memory chips of the second memory group share the second data bus. The method according to claim 1,
Wherein the first memory group comprises:
And data buffers corresponding to each of the memory chips included in the first memory group,
Wherein the first memory group comprises:
And data buffers corresponding to each of the memory chips included in the first memory group,
Wherein the data buffers of the first memory group share the first data bus and the data buffers of the second memory group share the second data bus. The method according to claim 1,
The memory module comprising:
And a memory buffer chip for providing the plurality of data signals received from the outside to the plurality of memory chips,
The memory chips of the first memory group,
A first data bus sharing the first data signal between the memory chips of the first memory group and the memory buffer chip,
Wherein the memory chips of the second memory group include:
And a second data bus for transferring the second data signal between the memory chips of the second memory group and the memory buffer chip. The method according to claim 1,
Wherein the memory module is a dual in-line memory module (DIMM). 6. The method of claim 5,
Wherein the first memory group and the second memory group are included on a first side of the memory module,
A second side of the memory module,
A third memory group including N memory chips for transmitting and receiving the first data signals through the first data bus, respectively; And
And a fourth memory group including N memory chips for receiving the second data signal via the second data bus, respectively. The method according to claim 6,
The memory module receives a plurality of control signals,
Activating either one of the memory chips of the first memory module and the memory chips of the second memory module based on the control signals or activating any one of the memory chips of the third memory module and the fourth And activates any one of the memory chips of the memory module. A first memory module including a first memory group including a plurality of memory chips sharing a first data bus and a second memory group including a plurality of memory chips sharing a second data bus;
A second memory module including a third memory group including a plurality of memory chips sharing a third data bus and a fourth memory group including a plurality of memory chips sharing a fourth data bus; And
And a memory controller for providing a data signal to the first memory module and the second memory module via the data buses. 9. The method of claim 8,
The memory controller includes:
One of the memory chips of the first memory group, one of the memory chips of the second memory group, one of the memory chips of the third memory group, and one of the memory chips of the fourth memory group Wherein the first and second memory modules provide the same plurality of control signals, respectively, to the first memory module and the second memory module. 10. The method of claim 9,
Wherein the first memory module further comprises a first RCD,
Wherein the second memory module further comprises a second RCD,
Wherein the first RCD (Register Clock Driver) and the second RCD are configured to select one of the memory chips of the first memory group, one of the memory chips of the second memory group, And simultaneously activates any one of the memory chips of the third memory group and the memory chips of the fourth memory group.
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