CN117350232A - Storage structure and memory - Google Patents
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- CN117350232A CN117350232A CN202210759006.1A CN202210759006A CN117350232A CN 117350232 A CN117350232 A CN 117350232A CN 202210759006 A CN202210759006 A CN 202210759006A CN 117350232 A CN117350232 A CN 117350232A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The invention discloses a storage structure and a memory, wherein the storage structure comprises: a first memory chip and a second memory chip; the first memory chip is stacked on one side of the second memory chip, and the first memory chip and the second memory chip are connected in a three-dimensional manner; the first memory chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first memory chip is connected with the pins, and a signal transmission line of the second memory chip passes through the first memory chip to be connected with the pins; the storage structure is configured to read or write the first storage chip through a signal transmission line of the first storage chip after receiving a preset first chip selection signal; and the memory device is also configured to read or write the second memory chip through the signal transmission line of the second memory chip after receiving a preset second chip selection signal. The invention avoids increasing the wiring resource of the PCB in the process of realizing the expansion of the storage capacity and reduces the packaging cost.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a storage structure and a storage.
Background
Currently, when capacity expansion is performed by using two or more memory chips, the two or more memory chips are generally arranged on a PCB (Printed Circuit Board ) and then routed on the PCB to connect command lines of the two or more memory chips together and address lines of the two or more memory chips together. Thereby realizing expansion of the storage capacity.
Although the prior art can realize the expansion of the storage capacity, the mode wastes wiring resources on the PCB and has high packaging cost.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a memory structure and a memory, which avoid increasing wiring resources of a PCB board and reduce packaging cost in the process of realizing memory capacity expansion.
In a first aspect, there is provided a storage structure comprising: a first memory chip and a second memory chip; the first memory chip is stacked on one side of the second memory chip, and the first memory chip and the second memory chip are connected in a three-dimensional manner; the first memory chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first memory chip is connected with the pins, and a signal transmission line of the second memory chip passes through the first memory chip to be connected with the pins; the storage structure is configured to read or write the first storage chip through a signal transmission line of the first storage chip after receiving a preset first chip selection signal; and the memory device is also configured to read or write the second memory chip through the signal transmission line of the second memory chip after receiving a preset second chip selection signal.
Optionally, the signal transmission line of the first memory chip includes a first address command line and a first data line; the signal transmission line of the second memory chip comprises a second address command line and a second data line; the plurality of pins includes a command pin set and a data pin set.
Optionally, a second address command line is connected to the first address command line, and the second data line is connected to the first data line; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
Optionally, the second address command line is connected to the command pin group through the first memory chip, and the second data line is connected to the data pin group through the first memory chip; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
Optionally, the second address command line is connected to the first address command line, and the second data line is connected to the data pin group through the first memory chip; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
Optionally, the first memory chip is provided with a first chip selection interface and a second chip selection interface; the first chip selection interface receives the first chip selection signal so that the storage structure can read or write the first storage chip based on the first chip selection signal; the second chip selection interface receives the second chip selection signal, so that the storage structure reads or writes the second storage chip based on the second chip selection signal.
Optionally, the first memory chip is provided with a first chip selection interface and a multiplexer, and the multiplexer is connected with the first chip selection interface and is configured to receive an initial chip selection signal and a control signal; the multiplexer is configured to output a first chip select signal to the first chip select interface based on the control signal and the initial chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal; the multiplexer is configured to output a second chip select signal to the first chip select interface based on the control signal and the initial chip select signal to cause the memory structure to read or write to the second memory chip based on the second chip select signal.
Optionally, the multiplexer includes an inverter, a first and gate, and a second and gate; the output end of the inverter is connected with the first input end of the first AND gate, the input end of the inverter is configured to be connected with the control signal, and the second input end of the first AND gate is configured to be connected with the initial chip selection signal; the first input end of the second AND gate is configured to be connected with the initial chip selection signal, and the second input end of the second AND gate is configured to be connected with the control signal; the output end of the first AND gate and the output end of the second AND gate are both connected with the first chip selection interface.
Optionally, the memory device further comprises a third memory chip; the third memory chip is stacked on one side, far away from the first memory chip, of the second memory chip, and the second memory chip and the third memory chip are connected in a three-dimensional mode; the signal transmission line of the third memory chip passes through the second memory chip and the first memory chip to be connected with the pin; the storage structure is configured to read or write the third memory chip through the signal transmission line of the third memory chip after receiving a preset third chip selection signal.
In a second aspect, there is provided a memory comprising: the storage structure of any one of the preceding first aspects; and the logic chip is arranged on one side, far away from the first storage chip, of the second storage chip, and the logic chip is connected with the second storage chip in a three-dimensional mode.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
the embodiment of the invention provides a storage structure and a memory, wherein the storage structure comprises: a first memory chip and a second memory chip; the first memory chip is stacked on one side of the second memory chip, and the first memory chip and the second memory chip are connected in a three-dimensional manner; the first memory chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first memory chip is connected with the pins, and a signal transmission line of the second memory chip passes through the first memory chip to be connected with the pins; the storage structure is configured to read or write the first storage chip through a signal transmission line of the first storage chip after receiving a preset first chip selection signal; and the memory device is also configured to read or write the second memory chip through the signal transmission line of the second memory chip after receiving a preset second chip selection signal. In the memory structure of the embodiment of the invention, the first memory chip and the second memory chip are connected in three dimensions, and the first memory chip and the second memory chip are respectively read and written by the first chip selection signal and the second chip selection signal, so that the capacity expansion of the memory structure is realized; meanwhile, the signal transmission line of the second memory chip passes through the first memory chip and is connected with the pins on the circuit board, so that the wiring area of the circuit board and the occupied area of the pins are saved, and the packaging cost and the material cost are reduced.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a first embodiment of a memory structure according to the present invention;
FIG. 2 is a schematic diagram of a second embodiment of a memory structure according to the present invention;
FIG. 3 is a schematic diagram of a third embodiment of a memory structure according to the present invention;
FIG. 4 is a timing diagram of chip select signal control for the memory structure of FIG. 3;
FIG. 5 is a schematic diagram of a fourth embodiment of a memory structure according to the present invention;
FIG. 6 is a schematic diagram of the multiplexer of FIG. 5;
FIG. 7 is a schematic diagram of a fifth embodiment of a memory structure according to the present invention;
FIG. 8 is a schematic diagram of a memory according to an embodiment of the invention. .
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The embodiment of the invention provides a storage structure, which is formed by stacking a plurality of storage chips and leading out metal wires of the storage chips through one storage chip, so that the wiring area on a PCB (printed circuit board) is reduced, the number of pins is reduced, and the packaging cost is reduced. The inventive concept is illustrated and described in detail below by way of specific examples.
Referring to FIG. 1, in one embodiment of the present invention, a memory structure 10 is provided, comprising: a first memory chip 11 and a second memory chip 12; the first memory chip 11 is stacked on one side of the second memory chip 12, and the first memory chip 11 and the second memory chip 12 are connected in three dimensions; the first memory chip 11 is provided with a plurality of pins (not shown in the drawings) for connection to a predetermined circuit board, and it is understood that the plurality of pins are provided on a surface of the first memory chip 11 remote from the second memory chip 12. The signal transmission line 110 of the first memory chip 11 is connected with the pin, and the signal transmission line 120 of the second memory chip 12 passes through the first memory chip 11 to be connected with the pin; the memory structure 10 is configured to read or write to the first memory chip 11 through the signal transmission line 110 of the first memory chip 11 after receiving a preset first chip select signal; and is further configured to read or write the second memory chip 12 through the signal transmission line 120 of the second memory chip 12 after receiving a preset second chip selection signal, thereby realizing capacity expansion. Since the signal transmission line of the second memory chip passes through the first memory chip 11, a plurality of shared pins can be arranged, and the connection is realized by leading out the metal wire from the first memory chip 11 and the pins on the PCB board; that is, only the corresponding pin area and the corresponding contact of one memory chip are required to be arranged on the PCB, so that the area of wiring on the PCB is saved, and the material cost is reduced.
The first memory chip 11 and the second memory chip 12 may be random access memories (Random Access Memory, RAM), such as dynamic random access memories; a Read-Only Memory (ROM) is also possible, without limitation.
Further, the signal transmission line 110 of the first memory chip 11 includes a first address command line 111 and a first data line 112; the signal transmission line 120 of the second memory chip 12 includes a second address command line 121 and a second data line 122; the plurality of pins includes a command pin set and a data pin set.
In some implementations, the second address command line 121 is connected to the first address command line 111, and the second data line 122 is connected to the first data line 112, as shown in fig. 1; the first address command line 111 is connected to the command pin group; the first data line 112 is connected to the data pin group. By this design, the second address command line 121 and the second data line 122 of the second memory chip 12 can be partially implemented in the first memory chip 11 in common with the first address command line 111 and the first data line 112, realizing capacity expansion, and saving wiring cost. When the address command lines are shared and the data lines are shared, the chip selection signals can be used for controlling the first memory chip 11 to read or write data at different times or the second memory chip 12 to read or write data; the same data may also be read or written at the same time.
For example, upon receiving a data write command: if the memory structure 10 receives the first select signal valid, the first memory chip 11 analyzes the command and address and receives the written data; at this time, the second chip select signal is not valid, the second memory chip 12 does not parse the command and address, and does not receive the written data; if the memory structure 10 receives the second chip select signal valid, then the command and address are resolved in the second memory chip 12 and the written data is received; at this time, the first select signal is not valid, and the first memory chip 11 does not parse the command and address, and does not receive the written data. Upon receiving a data read command: if the memory structure 10 receives the first chip select signal valid, the first memory chip 11 analyzes the command and address and sends out the read data; at this time, the second chip select signal is invalid, the second memory chip 12 does not parse the command and address, and does not send out the read data; if the memory structure 10 receives the second chip select signal valid, then the second memory chip 12 analyzes the command and address and sends out the read data; at this time, the first select signal is not valid, and the first memory chip 11 does not parse the command and address, and does not send out the read data. So that the time-sharing access is realized by the control process under the condition of sharing the data transmission line.
In some implementations, as shown in fig. 2, the second address command lines 121 are connected to the command pin group through the first memory chip 11, and the second data lines 122 are connected to the data pin group through the first memory chip 11, as shown in fig. 2; the first address command line 111 is connected to the command pin group; the first data line 112 is connected to the data pin group. That is, pins for connecting the first address command line 111 and pins for connecting the second address command line 121 may be provided in the command pin group, to achieve separation of the first address command line 111 and the second address command line 121; in the data pin group, pins for connecting the first data line 112 and pins for connecting the second data line 122 may be provided to separate the first data line 112 and the second data line 122. At this time, the first memory chip 11 and the second memory chip 12 can be controlled to read or write simultaneously or in a time-sharing manner by the chip selection signal, and the first memory chip 11 and the second memory chip 12 do not affect each other to read or write data, and the data transmission performance can be improved.
For example, upon receiving a data operation command: if the memory structure 10 receives the first chip select signal valid and receives the second chip select signal valid, the first memory chip 11 and the second memory chip 12 can respectively send a command and an address to the first memory chip 11 and the second memory chip 12 through the first address command line and the second address command line which are independent of each other, and the first memory chip 11 and the second memory chip 12 can simultaneously analyze the received command and address and simultaneously read or write the first memory chip 11 and the second memory chip 12 through the first data line 112 and the second data line 122 which are independent of each other. Specifically, it may be that the first memory chip 11 and the second memory chip 12 may each receive write data; the first memory chip 11 and the second memory chip 12 may both send out read data; one of the first memory chip 11 and the second memory chip 12 may receive write data, and the other may send read data.
In some implementations, as shown in fig. 3, the second address command line 121 is connected to the first address command line 111, and the second data line 122 is connected to the data pin group through the first memory chip 11; the first address command line 111 is connected to the command pin group; the first data line 112 is connected to the data pin group. Referring to fig. 4, the address command lines can be shared by the design mode, the data lines are independent, the corresponding chip selection signals (chip selection 1 and chip selection 2) are given to the first memory chip 11 and the second memory chip 12 in a time sharing manner, the corresponding address command signals (command/address) are given in a time sharing manner, continuous writing operation in the two memory chips can be realized, the writing data in the two memory chips are not affected, and bandwidth doubling can be realized when the data is read or written.
For example, upon receiving a data write command: if the first slice selection signal is valid, the first memory chip 11 analyzes the command and the address and receives the written data; when the first chip select signal is valid, the second chip select signal is not valid; after the first memory chip 11 completes the analysis, the second chip select signal may be controlled to be valid, and the first chip select signal may be controlled to be invalid, and at this time, the second memory chip 12 performs the analysis of the command and the address, and may receive the written data. Since the first data line 112 and the second data line 122 are independent from each other, the first memory chip 11 and the second memory chip 12 may receive the written data differently, so as to implement time-sharing processing, and the bandwidth is doubled when writing the data. Upon receiving a data read command: if the first chip selection signal is valid, the first memory chip 11 analyzes the command and the address and sends out read data; when the first chip select signal is valid, the second chip select signal is not valid; after the first memory chip 11 finishes analysis, the second chip selection signal can be controlled to be effective, the first chip selection signal is not effective, and at the moment, the second memory chip 12 performs command and address analysis and can send out read data; since the first data line 112 and the second data line 122 are independent from each other. Since the first data line 112 and the second data line 122 are independent from each other, the read data sent from the first memory chip 11 and the second memory chip 12 may be different, so that time-sharing processing is implemented, and the bandwidth is doubled when the data is read.
It will be appreciated that the following implementations are possible in selecting a memory chip by a chip select signal:
referring to fig. 1 to 3, a first chip selection interface 101 and a second chip selection interface 102 may be disposed on a first memory chip 11; the first chip select interface 101 may be connected to the first memory chip 11 and the second chip select interface 102 may be connected to only the second memory chip 12. The first chip select interface 101 may be configured to receive a first chip select signal to cause the memory structure 10 to read or write to the first memory chip 11 based on the first chip select signal. The second chip select interface 102 receives a second chip select signal to cause the memory structure 10 to read from or write to the second memory chip 12 based on the second chip select signal. The read-write selection control of the two memory chips is realized through the two chip selection interfaces, and the two chip selection interfaces are arranged on the first memory chip 11, so that the wiring and the connection of the PCB are facilitated. When the scheme is common to the data lines, the first memory chip 11 and the second memory chip 12 may be given corresponding chip selection signals in a time-sharing manner. When the scheme is not common to the data lines, there is no limitation on the time for which the chip select signals are given to the first memory chip 11 and the second memory chip 12.
In addition, referring to fig. 5, in some implementations, only the first chip select interface 101 may be provided, and the chip select signal may be controlled by the multiplexer 103. Specifically, the first memory chip 11 is provided with a first chip select interface 101 and a multiplexer 103, the multiplexer 103 connecting the first chip select interface 101 and being configured to receive an initial chip select signal (chip select 0) and a control signal based on the first chip select interface 101; the multiplexer 103 is configured to output a first chip select signal (chip select 1) to the first memory chip 11 based on the control signal and the initial chip select signal, so that the memory structure 10 reads or writes to the first memory chip 11 based on the first chip select signal; the multiplexer 103 is configured to output a second chip select signal (chip select 2) to the second memory chip 12 based on the control signal and the initial chip select signal, so that the memory structure 10 can read or write to the second memory chip 12 based on the second chip select signal.
Further, referring to fig. 6, the multiplexer 103 can be implemented as follows, but is not limited thereto. The multiplexer 103 may include an inverter, a first and gate, and a second and gate; the output end of the inverter is connected with the first input end of the first AND gate, the input end of the inverter is configured to be connected with the control signal, and the second input end of the first AND gate is configured to be connected with an initial chip selection signal; the first input end of the second AND gate is configured to be accessed with an initial chip selection signal, and the second input end of the second AND gate is configured to be accessed with a control signal; the output of the first and gate and the output of the second and gate are both connected to the first chip select interface 101. That is, in this implementation, the first chip select signal and/or the second chip select signal may be output by inputting an initial chip select signal to the multiplexer 103 and being controlled by the control signal. For example, the selector may be used as a first chip select signal when outputting a low level to select the first memory chip 11; the selector may be used as a second chip select signal when it outputs a high level to select the second memory chip 12. Also, when the scheme is common to the data lines, the corresponding chip select signals may be given to the first memory chip 11 and the second memory chip 12 in a time-sharing manner. When the scheme is not common to the data lines, there is no limitation on the time for which the chip select signals are given to the first memory chip 11 and the second memory chip 12. This implementation may require only one chip select interface to achieve select control of two memory chips.
Further, referring to fig. 7, in some embodiments, a third memory chip 13 may be stacked; specifically, the third memory chip 13 is stacked on one side of the second memory chip 12 away from the first memory chip 11, and three-dimensional connection is performed between the second memory chip 12 and the third memory chip 13; the signal transmission line of the third memory chip 13 passes through the second memory chip 12 and the first memory chip 11 to be connected with the pin; the memory structure 10 is configured to read or write the third memory chip 13 through the signal transmission line 130 of the third memory chip 13 after receiving a preset third chip select signal. Similarly, the relationship between the signal transmission line 130 of the third memory chip 13 and the signal transmission line 120 of the second memory chip 12 can be designed with reference to the relationship between the signal transmission line 120 of the second memory chip 12 and the signal transmission line 110 of the first memory chip 11, which is not described in detail in this embodiment. In addition, an implementation manner of stacking three or more memory chips is also possible, for example, the memory structure 10 of the present embodiment may further include a fourth memory chip three-dimensionally connected to the third memory chip 13, a fifth memory chip three-dimensionally connected to the fourth memory chip, and so on.
It should be noted that, in this embodiment, a TSV (Through-Silicon-Via) process and/or Hybrid bonding (Hybrid bonding) technology may be used to implement the three-dimensional connection.
In summary, in this embodiment, after the first memory chip 11 and the second memory chip 12 are three-dimensionally connected, the first memory chip 11 and the second memory chip 12 are respectively read-write controlled by the first chip select signal and the second chip select signal, so as to realize capacity expansion of the memory structure 10; further, the signal transmission lines 120 of the second memory chip 12 are connected with the pins after penetrating through the first memory chip 11, so that the pins can be arranged only for the first memory chip 11, thereby saving the wiring area and the pin area of the circuit board and reducing the packaging cost and the material cost.
Referring to fig. 8, in accordance with the same inventive concept, a memory 400 is further provided in another embodiment of the present invention, including the memory structure 10 according to any one of the foregoing embodiments, and a logic chip 40, where the logic chip 40 is disposed on a side of the second memory chip 12 away from the first memory chip 11, and the logic chip 40 is three-dimensionally connected to the second memory chip 12. It should be noted that, the memory 400 in the embodiment of the present invention includes the memory structure 10 in the foregoing embodiment, and the beneficial effects and implementation methods of the memory structure 10 are described in the foregoing embodiment, so that it can be understood that the embodiments of the memory structure 10 are not described in detail in the embodiments of the memory and the electronic device.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that modules in the apparatus corresponding to the control method of the memory in the embodiment may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
Claims (10)
1. A memory structure, comprising: a first memory chip and a second memory chip; the first memory chip is stacked on one side of the second memory chip, and the first memory chip and the second memory chip are connected in a three-dimensional manner; the first memory chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first memory chip is connected with the pins, and a signal transmission line of the second memory chip passes through the first memory chip to be connected with the pins;
the storage structure is configured to read or write the first storage chip through a signal transmission line of the first storage chip after receiving a preset first chip selection signal; and the memory device is also configured to read or write the second memory chip through the signal transmission line of the second memory chip after receiving a preset second chip selection signal.
2. The memory structure of claim 1, wherein the signal transmission line of the first memory chip comprises a first address command line and a first data line;
the signal transmission line of the second memory chip comprises a second address command line and a second data line;
the plurality of pins includes a command pin set and a data pin set.
3. The storage structure of claim 2, wherein,
a second address command line connected to the first address command line, the second data line connected to the first data line; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
4. The storage structure of claim 2, wherein,
the second address command line is connected to the command pin group through the first memory chip, and the second data line is connected to the data pin group through the first memory chip; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
5. The storage structure of claim 2, wherein,
the second address command line is connected to the first address command line, and the second data line passes through the first memory chip and is connected to the data pin group; the first address command line is connected to the command pin set; the first data line is connected to the data pin group.
6. The storage structure of any one of claims 3 to 5, wherein,
the first memory chip is provided with a first chip selection interface and a second chip selection interface;
the first chip selection interface receives the first chip selection signal so that the storage structure can read or write the first storage chip based on the first chip selection signal;
the second chip selection interface receives the second chip selection signal, so that the storage structure reads or writes the second storage chip based on the second chip selection signal.
7. The storage structure of any one of claims 3 to 5, wherein,
the first memory chip is provided with a first chip selection interface and a multiplexer, and the multiplexer is connected with the first chip selection interface and is configured to receive an initial chip selection signal and a control signal based on the first chip selection interface;
the multiplexer is configured to output a first chip select signal to the first memory chip based on the control signal and the initial chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal;
the multiplexer is configured to output a second chip select signal to the second memory chip based on the control signal and the initial chip select signal, so that the memory structure can read or write to the second memory chip based on the second chip select signal.
8. The memory structure of claim 7, wherein the multiplexer comprises an inverter, a first and gate, and a second and gate; the output end of the inverter is connected with the first input end of the first AND gate, the input end of the inverter is configured to be connected with the control signal, and the second input end of the first AND gate is configured to be connected with the initial chip selection signal; the first input end of the second AND gate is configured to be connected with the initial chip selection signal, and the second input end of the second AND gate is configured to be connected with the control signal; the output end of the first AND gate and the output end of the second AND gate are both connected with the first chip selection interface.
9. The memory structure of claim 1, further comprising a third memory chip; the third memory chip is stacked on one side, far away from the first memory chip, of the second memory chip, and the second memory chip and the third memory chip are connected in a three-dimensional mode; the signal transmission line of the third memory chip passes through the second memory chip and the first memory chip to be connected with the pin;
the storage structure is configured to read or write the third memory chip through the signal transmission line of the third memory chip after receiving a preset third chip selection signal.
10. A memory, comprising:
the storage structure of any one of claims 1-9; and
the logic chip is arranged on one side, far away from the first storage chip, of the second storage chip, and the logic chip is connected with the second storage chip in a three-dimensional mode.
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