CN116680205B

CN116680205B - DDR memory data channel interface expansion circuit, system and method

Info

Publication number: CN116680205B
Application number: CN202310971734.3A
Authority: CN
Inventors: 薛超; 乔晓冬; 魏育成
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2023-08-03
Filing date: 2023-08-03
Publication date: 2023-10-03
Anticipated expiration: 2043-08-03
Also published as: CN116680205A

Abstract

The invention provides a DDR memory data channel interface expansion circuit, a system and a method, which are used for bidirectionally transmitting data signals in real time and comprise the following steps: a first data signal port which is respectively connected with all or part of the data signal ports of the DDR memory in a one-to-one correspondence manner, and a second data signal port which is respectively connected with the data signal ports of at least two processors in a corresponding manner; a switch matrix is disposed between the first data signal port and the second data signal port. The interface of the memory is directly expanded, one DDR memory is connected with a plurality of processors, and DDR memory sharing is realized from the perspective of hardware. The DDR memory data channel interface expansion system and the DDR memory data channel interface expansion method provided by the invention have corresponding advantages.

Description

DDR memory data channel interface expansion circuit, system and method

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a DDR memory data channel interface expansion circuit, a system and a corresponding expansion method.

Background

With the development of integrated circuits and microelectronic technologies, integrated circuit chips are used in various fields as carriers of information. Taking FPGA (field programmable gate array) as an example, FPGA circuit products are widely applied to the fields of financial acceleration, data centers, intelligent network cards and the like. And the memory circuit is very critical to the application of circuit products such as FPGA. Taking DDR memory as an example, DDR memory is known as SDRAM synchronous Dynamic Random Access Memory (DRAM) which has a synchronous interface. SDRAM is widely used in computers, from the initial SDRAM to the later generation DDR (or DDR 1), followed by DDR2, DDR3, DDR4 and DDR 5. DDR memory is generally used as a memory circuit of a processor chip such as a CPU, FPGA, or ASIC. When the processor chips such as the FPGA and the CPU communicate, data needs to be cached in the DDR memory, and the data transmission process is limited by the process of transmitting the memory data of the FPGA or the CPU to the CPU or the FPGA memory. The DDR memory has the characteristics of large wiring area, high wiring requirement, high chip cost and the like in the hardware design. The existing DDR memory channel expansion technology refers to that a processor chip such as a CPU, an FPGA or an ASIC is provided with a plurality of DDR memory interfaces, so that a plurality of DDR memories are connected simultaneously. This is not a true solution for expanding DDR memory channels, and the use of DDR memory is limited by the design of the processor chip, and if multiple processors are to be connected and use the same DDR memory, the existing solution for increasing the memory interface of the processor chip cannot be implemented. It is known that DDR memory applications are limited, which is disadvantageous for deep applications and for the development of processor chips.

Therefore, research on a DDR memory data channel interface expansion circuit, an expansion system and a corresponding expansion method is needed to realize data signal expansion of the DDR memory, and improve flexibility of DDR memory application, so as to advance further development of integrated circuit technology.

Disclosure of Invention

In order to solve all or part of the problems in the prior art, the invention provides a DDR memory data channel interface expansion circuit, which can realize the connection application of a DDR memory to a multiprocessor from hardware. The invention further provides a DDR memory data channel interface expansion system, which can realize that a plurality of processors share DDR memory to perform quick data interaction. The invention also provides a DDR memory data channel interface expansion method.

The invention provides a DDR memory data channel interface expansion circuit, which is used for bidirectionally transmitting data signals in real time, and comprises the following components: a first data signal port which is respectively connected with all or part of the data signal ports of the DDR memory in a one-to-one correspondence manner, and a second data signal port which is respectively connected with the data signal ports of at least two processors in a corresponding manner; a switch matrix is arranged between the first data signal port and the second data signal port; the switch matrix comprises radio frequency switch units which are arranged in one-to-one correspondence with the first data signal ports; the radio frequency switch unit includes: the control module is used for receiving a switching-on control signal, and comprises a first interface which is switched on with the first data signal port, a second interface which is arranged in one-to-one correspondence with the second data signal port and is switched on; the conduction control signal is used for controlling the on-off of the first interface and the second interface.

And receiving a conduction control signal through a switch matrix, switching the second data signal port currently connected with the first data signal port, realizing bidirectional data signal rotation transmission of a plurality of processors and one DDR memory, wherein the data time of writing and reading once of the DDR memory is the minimum switching time, and the nanosecond conduction control achieves the effect of DDR memory sharing from a hardware level. The first data signal ports are arranged in one-to-one correspondence with the data signal ports, which are high-speed storage interfaces for transmitting data signals, of the DDR memory, so that on one hand, the wiring complexity is reduced as much as possible, and on the other hand, the minimum number of wirings is beneficial to impedance control.

The control module includes: at least two control voltage terminals and a ground terminal; the two control voltage ends are a group of common external control signal input ends. The control module comprises at least two control voltage output ends, the control is realized by conducting control signals through the voltage levels of the at least two control voltage output ends, the signal interference is less, and the control accuracy is higher.

The two control voltage ends of the same group are respectively marked as a first control voltage end and a second control voltage end; the first control voltage end of each radio frequency switch unit is short-circuited together; the second control voltage terminal of each of the radio frequency switch units is shorted together.

An inverter is arranged between the first control voltage end or the second control voltage end and the external control signal input end; the control module is configured such that the first interface is in communication with the second interface connected to a data signal port of a processor when the external control signal input is at a level of 1.

The second data signal ports which are connected with all or part of the data signal ports of the same processor in a one-to-one correspondence mode are marked as a group; and the data signal lines between the second data signal ports and the corresponding first data signal ports in the same group are equal in length.

The wire length between the first data signal port and the second data signal port is less than 6 inches.

The frequency of the transmission signal of the radio frequency switch unit is more than 1.6GHz.

The radio frequency switch unit is a miniaturized multi-pin patch packaged chip.

The invention also provides a DDR memory data channel interface expansion system, which comprises a DDR memory, at least two processors and the DDR memory data channel interface expansion circuit provided by the invention; the DDR memory and the processor transmit data signals through the expansion circuit; the DDR memory and the processor directly transmit non-data signals.

The wiring length for transmitting address signals and command signals between the DDR memory and the processor is below 13.15 inches.

The wiring length for transmitting clock signals between the DDR memory and the processor is less than 10.59 inches.

The wiring length for transmitting data signals between the DDR memory and the processor is less than 6 inches.

The invention also provides a DDR memory data channel interface expansion method, which comprises the following steps: dividing all signals of a DDR memory into two groups, wherein one group is a data signal, and the other group is a non-data signal; directly connecting the non-data signals with a plurality of processor chips respectively; dividing the data signals into multiple paths of data channels after passing through the DDR memory data channel interface expansion circuit, wherein the multiple paths of data channels are respectively in one-to-one correspondence with the processor chips; setting the number of the multiple paths of data channels according to the number of the multiple processor chips; and configuring the interface expansion circuit to be in real-time bidirectional transmission, and disconnecting the rest data channels when one data channel is connected with the processor chip.

The processor chip uses an independent memory control core to generate a control signal and sends the control signal to the interface expansion circuit to control the on/off of the direct data channel between the processor chip and the DDR memory.

Compared with the prior art, the invention has the main beneficial effects that:

1. the DDR memory data channel interface expansion circuit provided by the invention can be used for bidirectionally transmitting data signals and directly expanding the interfaces of memories, so that one DDR memory is connected with a plurality of processors, DDR memory sharing is realized from the perspective of hardware, and the circuit design is more flexible and is suitable for more application scenes.

2. According to the DDR memory data channel interface expansion system provided by the invention, one DDR memory is commonly connected with a plurality of processors, so that data signal interaction between different processors can be realized, the time for switching the data channels by the interface expansion circuit is nanosecond, the influence of delay time on the data signal exchange speed is reduced to the minimum, the data signal exchange efficiency is greatly improved, and the overall working performance of a chip product is optimized.

3. The DDR memory data channel interface expansion method provided by the invention divides DDR memory signals into two groups, namely data signals and non-data signals, fully utilizes the half-duplex communication mode of the DDR memory to realize data signal exchange between one DDR memory and a plurality of processor chips, is beneficial to improving the on-chip integration level of products and optimizing resource allocation.

Drawings

Fig. 1 is a process diagram of a fast data exchange method between multiple processors according to a first embodiment of the present invention.

Fig. 2 is a signal interaction schematic diagram of two processors according to a first embodiment of the present invention.

Fig. 3 is a schematic diagram of a DDR memory shared by two processors according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram of a heterogeneous circuit board card for interconnecting DDR memory and non-data signals of two processor chips according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a heterogeneous circuit board card for interconnecting data signals of a DDR memory and two processor chips according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of an interface expansion system according to a first embodiment of the present invention.

Fig. 7 is a schematic diagram of an interface expansion circuit according to a second embodiment of the present invention.

Fig. 8 is a schematic diagram of an interface expansion circuit according to a second embodiment of the invention.

Fig. 9 is a schematic diagram of a rf switch unit according to a second embodiment of the invention.

Fig. 10 is a schematic diagram of a control module according to a second embodiment of the invention.

Fig. 11 is a general block diagram of a DDR4 of a second embodiment of the present invention that connects two processor chips simultaneously for communication.

Fig. 12 is a schematic diagram of signal grouping and connection modes of DDR4 particles according to a second embodiment of the present invention.

Fig. 13 is a schematic diagram of signal grouping and connection modes of DDR4 particles according to a second embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully, and it is apparent that the embodiments described are only some, but not all, of the embodiments of the present invention.

Example 1

In the method for quickly exchanging data among the multiple processors, which is exemplified in the embodiment of the invention, the multiple processors are in communication connection with the same DDR memory, and the two processors which are currently used for exchanging data are respectively marked as a first processor and a second processor; the first processor is communicatively coupled to the second processor. As shown in fig. 1, the data fast exchange method includes: the first processor interacts DDR use state signals with the second processor; the first processor or the second processor generates and outputs a control signal based on the currently received DDR use state signal, and controls the DDR memory to be connected with the first processor or the second processor so as to transmit a data signal.

In this embodiment, the DDR memory is described using an 8-bit DDR4 SDRAM as an example, but the present invention is equally applicable to DDR2, DDR3, DDR4, DDR5, and other memories, and is also applicable to 8-bit to 72-bit memories, and the specific type of DDR memory is not limited herein. The DDR memory has only one data channel, and the data reading and writing operations are shared, but the DDR memory belongs to a half duplex communication mode, and the reading and writing of the memory data are completed in different time periods.

Referring to fig. 2 in combination, for simplicity of the drawing, the data exchange between two processor chips through DDR4 granule is taken as an example in this embodiment, but the type and number of processors are not limited. As shown in fig. 2, in the example case, the first processor and the second processor are different types of chips. The first processor is an FPGA chip, and the second processor is a CPU chip. The example multiprocessor being communicatively coupled to the same DDR memory means that the non-data signal interface of the DDR memory is always coupled to the first processor and the second processor; the data signal interface of the DDR memory is controlled by a control signal to be connected with the first processor or the second processor. The CPU and the FPGA respectively write memory data into the DDR4 and read the memory data, so that quick data transmission between the two chips is realized. The different processors for performing data signal interaction through one DDR memory can be an FPGA and a CPU, an FPGA and an FPGA, a CPU and a CPU, a GPU and a CPU, etc., and can also be the same type of chip without limitation, and the processors can also be ASIC chips without limitation.

Referring to fig. 2 in combination, interface signals (I/O signals) of the ddr4 SDRAM are generally composed of clock signals, address signals, command signals, control signals, other signals, and data signals, as shown in table 1 below:

in this embodiment, the DDR use status signals include a DDR write request signal, a DDR write done signal, a DDR read request signal, a DDR read done signal, and a DDR available signal; the control signal is a logic signal stored in the second processor and includes opposite first and second levels (0 or 1). The processor chip can alternately bidirectionally transmit data signals through the DDR memory by using an independent memory control core to generate control signals, package protocol core protocol analysis is not needed for data, DDR reading and writing are directly realized through the control signals, and switching time is the data time of DDR memory writing and reading once.

With reference to fig. 2 and 3, a process of transmitting data from a first processor to a second processor and a process of transmitting data from the second processor to the first processor are illustrated as implementation processes of multiprocessor nanosecond data exchange, respectively. In the case illustrated in fig. 3, the communication port through which the first processor interacts with the second processor with DDR use status signals includes first output terminals F1, F2 and second output terminal C3 for outputting DDR use status signals, first receiving terminal F3 and second receiving terminals C1, C2 for receiving DDR use status signals; the logic levels of the first output ends F1 and F2 and the second receiving ends C1 and C2 are the same; the second output terminal C3 has the same logic level as the first receiving terminal F3.

The port for outputting the control signal is denoted as a third output port C4, and the third output port C4 has the same logic level as the first output terminal or the second output terminal, and is opposite to the logic level of the first receiving terminal or the second receiving terminal. In the example case, the control signal is a level signal of which the signal is 0 or 1, and is configured to: c4 defaults to output 0, i.e., port B is on with port C. In fig. 3, K1 is a strobe pin, pin signal 1: the port A is conducted to the port C; pin signal 0: port B to port C are conductive. In fig. 3, F1 and C1, F2 and C2, and C4 and K1 are respectively commonly connected to an input voltage VCC; f3 and C3 are commonly connected to ground.

F1, C1 and F2, C2 are states of the FPGA requesting to use DDR, examples are as follows:

1X the FPGA has no DDR use requirement or is used completely.

The fpga writes the DDR request.

The fpga reads out the DDR request.

F3 and C3 are states of whether the FPGA fed back by the CPU can use DDR currently, and examples are as follows:

1:fpga can use DDR.

0:fpga cannot use DDR.

An example process of a first processor sending data to a second processor includes: step A1, a first processor sends a DDR write request signal to a second processor; a2, outputting a first level by the second processor, conducting the first processor of the DDR memory, and outputting a DDR available signal to the first processor; a3, after delaying the preset time, the first processor starts to write data which needs to be sent to the second processor into the DDR memory; a4, the first processor sends DDR writing-in finishing signals to the second processor, the second processor outputs a second level, the DDR memory is communicated with the second processor, and the second processor reads data. Referring to fig. 3, an exemplary FPGA send data to CPU process is:

the FPGA sends a write DDR request to the CPU;

the CPU starts the data receiving process: c4 Outputting high level, closing the switch group A, and conducting the port A to the port C; meanwhile, C3 outputs high level to inform the FPGA that writing can be performed at the moment;

the F3 end of the FPGA receives high level, the DDR can be used, and after delaying for a certain time TD, the port A to port C direction at the moment is ensured to be determined to be conducted;

the FPGA starts to write data to be sent into the DDR;

after the FPGA finishes writing, the F1 pin outputs high level to inform the CPU that the data is written completely;

after the C1 pin of the CPU receives the high level, the C4 pin immediately outputs the low level, the switch group B is closed, and the port B is conducted to the port C;

the CPU is connected with the DDR again, the DDR data can be read, and the process that the FPGA sends the data to the CPU is realized.

An example process of the second processor sending data to the first processor includes: step B1, presetting a control signal to enable the DDR memory to be communicated with a second processor, and writing data to be transmitted into the DDR memory by the second processor; b2, after the writing is finished, the second processor inverts the control signal, conducts the DDR memory with the first processor, and simultaneously outputs DDR available signals to the second processor; b3, the first processor sends a DDR reading request signal to the second processor, and starts to read data in the DDR memory; in step B4., the first processor sends a DDR read completion signal to the second processor, which inverts the control signal again, conducts with the DDR memory, and disconnects the data transmission between the first processor and the DDR memory.

In an exemplary case, between the step B2 and the step B3, the first processor determines whether the step A1 is currently executed, and if yes, the steps A2 to A4 are continuously executed; if not, directly executing the step B3.

The process of the CPU of the example of fig. 3 sending data to the FPGA:

the default C4 outputs a low level, namely the switch group B is closed, the direction from the port B to the port C is conducted, and the CPU firstly writes the data to be transmitted into the DDR;

after the CPU finishes writing, C4 outputs high level, controls switch group A to be closed, switches switch group B to be opened, switches to the connection of port A to port C channel, and simultaneously C3 outputs high level to inform FPGA;

after the F3 pin of the FPGA receives the high level, judging that the CPU actively sends the 'DDR state used by the FPGA' according to the operation of the self-non-prepositive step A1, namely, data is required to be transmitted;

the FPGA starts the DDR reading operation, F1 and F2 output low level at the same time, and the CPU is informed to start reading data in the DDR;

after the FPGA finishes reading, the F1 pin outputs a high level to inform the CPU that the data is read;

after the C1 pin of the CPU receives the high level, the C4 pin immediately outputs the low level, and the control switch group B is closed and switched to the port B to the port C for conduction;

the CPU is connected with the DDR again, and the DDR data can be written again, so that the process that the CPU sends the data to the FPGA is realized.

Referring to fig. 4 and 5 in combination, the fpga+cpu heterogeneous circuit board card of the example of the present embodiment arranges FPGA, CPU and DDR4 in Top Layer of the board card, and external signals enter from Bottom Layer of the board card. The DDR4 interfaces of the FPGA and the CPU are interconnected with clock signals, address signals, command signals, control signals and other signals of DDR4 particles, and the connection sequence is CPU, FPGA, DDR particles. The connection order may be CPU, FPGA, DDR or FPGA, CPU, DDR4, but is not limited thereto, and wiring requirements of the circuit design need to be satisfied so as not to reduce the operation frequency of DDR 4.

The embodiment also provides a DDR memory data channel interface expansion system, which comprises a DDR memory, at least two processors and a DDR memory data channel interface expansion circuit; data signals are transmitted between the DDR memory and the processor through the expansion circuit; the DDR memory and the processor directly transmit the non-data signals. The data signal path of DDR4 SDRAM, FPGA, CPU in the case of the example of fig. 6 bi-directionally transmits data signals through the interface expansion circuit; the non-data signals are directly interconnected.

Example two

In order to more fully understand the present invention, specific examples are given to DDR memory data channel interface expansion circuits, systems, and expansion methods according to the second embodiment.

The embodiment provides a DDR memory data channel interface expansion method, which comprises the following steps: dividing all signals of a DDR memory into two groups, wherein one group is a data signal, and the other group is a non-data signal; directly connecting the non-data signals with the multiple processor chips respectively; dividing a data signal into N paths of data channels after passing through the DDR memory data channel interface expansion circuit, wherein N is the number of the multiple processor chips; the interface expansion circuit is configured to be transmitted in a real-time bidirectional mode, and when one path of data channel is conducted with the processor chip, the N-1 path of data channel is disconnected. Referring to fig. 4, 5 and 7 in combination, in one example case, all signals of DDR4 are first divided into two groups in a wiring manner when DDR4 particles are connected to a plurality of processor chips. The first group is a non-data signal, and can be directly connected with a plurality of processor chips without expansion, wherein the method comprises the following steps: clock signals, address signals, command signals, control signals, and other signals in table 1 above. The second group of data signals are divided into two parts after passing through the interface expansion circuit and are respectively connected with the two processor chips.

As shown in fig. 8, the interface expansion circuit divides the input 12 data signal lines into two groups, namely, B1 group and B2 group, and can be connected to two different processor chips. Referring to fig. 8 in combination, the ddr memory data channel interface expansion circuit for bi-directional real-time transmission of data signals, comprises: the data processing device comprises a DDR memory, a first data signal port and a second data signal port, wherein the DDR memory is provided with all or part of data signal ports; a switch matrix is arranged between the first data signal port and the second data signal port; the switch matrix comprises radio frequency switch units which are arranged in one-to-one correspondence with the first data signal ports; the radio frequency switch unit includes: the control module is used for receiving the conduction control signals, and comprises a first interface conducted with the first data signal port, a second interface which is arranged in one-to-one correspondence with the second data signal port and is conducted; the conduction control signal is used for controlling the on-off of the first interface and the second interface. The DDR4 only has one data channel, and data reading and writing operations are shared, so the interface expansion circuit has the function of bidirectional transmission. The DDR4 of 8 bits is 12 lines, and the 16 bits is 24 lines, can reach 72 bits, understand correspondingly. In the case illustrated in fig. 8, there are twelve data signals, all of which are provided with first data signal ports in one-to-one correspondence, and twelve radio frequency switch units; the second data signal port has twenty-four second data signal ports divided into a B1 group and a B2 group, and twelve second data signal ports of each group can be connected with two processors.

In this embodiment, the control module includes: at least two control voltage terminals and a ground terminal; the two control voltage terminals are a group of common external control signal input terminals.

In the case illustrated in fig. 8, the control module includes two control voltage terminals and one ground terminal GND. In the example case, two control voltage terminals of the same group are denoted as a first control voltage terminal Vcont1 and a second control voltage terminal Vcont2, respectively. The first control voltage end Vcont1 of each radio frequency switch unit is short-circuited together; the second control voltage terminal Vcont2 of each radio frequency switching unit is shorted together.

In the case illustrated in fig. 9, an inverter is provided between the second control voltage terminal Vcont2 and the input terminal of the external control signal CONT 0. The example external control signal CONT0 is a GPIO control signal.

The control module is configured such that the first interface is in conduction with the second interface connected to the data signal port of one processor when the level of the input terminal of the external control signal CONT0 is "1". In the case illustrated in fig. 9, the radio frequency switching unit is implemented with a miniaturized six-pin patch-packaged switching chip. Referring to fig. 10 in combination, the pin definitions are shown in table 2 below:

referring to fig. 9 in combination, the conduction control table is shown in table 3 below:

when the chip illustrated in fig. 10 is used as the radio frequency switch unit, the second data signal port of the B1 group is connected to PIN1 (OUTPUT 1) of the chip; the second data signal port of group B2 is connected to PIN3 (OUTPUT 2) of the chip. The current DDR4 supports the maximum data transmission speed of 3200MHz, and the frequency of the data signal waveform on the signal line is 1600HMz, so the transmission signal frequency of the interface expansion circuit is not lower than 1.6GHz. In this embodiment, the frequency of the transmission signal of the radio frequency switch unit is above 1.6GHz, and the chip of the example can transmit signals with frequencies of 0.05 to 3.0GHz, and meanwhile has bidirectional transmission capability, and meets the design requirement of the interface expansion circuit.

The switch control PINs of the chip are PIN4 and PIN6, and the control logic is as follows:

when PIN 4=1 and PIN 6=0, PIN1 and PIN5 are conducted, namely the processor chip connected with the B1 group signal is conducted with DDR 4; when PIN 4=0 and PIN 6=1, PIN3 is conducted with input PIN5, i.e. the processor chip connected with the B2 group signal is conducted with DDR 4.

In the case of the example of fig. 8, PIN4 of 12 chips is shorted together, labeled "cont2"; the PINs 6 of the 12 chips are shorted together, labeled "cont1". It is also possible to provide an inverter between cont2 or cont1 and the external control signal INPUT terminal INPUT, which is not limited. Referring to fig. 8 and 10 in combination, resistors with the same resistance value are respectively arranged between the chip PINs PIN1, 3 and 5 and the data signal port; and capacitors with the same capacitance value are respectively arranged between the PINs PIN4 and PIN6 and the grounding end, and the capacitance value of an example is 1 mu F. The chip PINs PIN1, 3, 5 illustrated in fig. 10 are provided with a capacitance C0 between them and the interface, respectively.

In combination with the signal control logic, the control mode in this embodiment is that of the single pole double throw switch: when the INPUT external control signal CONT0 is 1, vcont1 is Low, vcont2 is High, and the second data signal port of the B1 group is conducted with the signal INPUT terminal INPUT; when the INPUT external control signal CONT0 is 0, vcont1 is High, vcont2 is Low, and the second data signal port of the B2 group is turned on with the signal INPUT terminal INPUT.

The method comprises the steps that second data signal ports which are connected with all or part of data signal ports of the same processor in a one-to-one correspondence mode are marked as a group; the data signal lines between the same group of second data signal ports and the corresponding first data signal ports are equal in length. As shown in the drawing, the data signal lines of the B1 group and the data signal lines of the B2 group are equal in length according to the wiring requirements of DDR 4.

In this embodiment, the DDR4 SDRAM and the processor chip communicate through the interface expansion circuit of this embodiment as shown in fig. 11. In the case illustrated in fig. 11, the interface expansion circuit is a split-into-two expansion, DDR4 SDRAM communicating with processor chip 1 and processor chip 2, respectively. Namely, one path of the data signal is divided into two paths by the interface expansion circuit: a B1 group data signal and a B2 group data signal. In some embodiments, the interface expansion circuit may be a split into three or more extensions, which is not limited in this regard.

As shown in fig. 12 and 13, the DDR memory data channel interface expansion system provided in still other embodiments includes a DDR4 memory and N processor chips, N >2 in the example case.

Referring to fig. 12 and 13, namely address, command, control signal transmissions: the wire length of DDR4 to the furthest processor cannot exceed 13.15 inches; clock signal: CK to DQS, cannot exceed 10.59 inches; data signal transmission: the wire length of DDR4 to the furthest processor cannot exceed 6 inches. The wiring requirement of DDR4 is higher, and the switch matrix formed by the delay-stable (delay-stable) one-to-many radio frequency switch units can connect DDR4 with 3 or more processor chips through the interface expansion circuit of this embodiment. N may be equal to 2, and is not limited. In the board design of this embodiment, the wiring length for transmitting address signals and command signals between the DDR memory and the processor is 13.15 inches or less. The wiring length for transmitting clock signals between the DDR memory and the processor is less than 10.59 inches. The wiring length for transmitting data signals between the DDR memory and the processor is less than 6 inches.

The interface expansion circuit of the embodiment realizes the data signal expansion of the DDR memory, so that the DDR memory is more flexible to apply and can meet one-to-many connection application. The DDR memory sharing is realized based on the hardware design, so that the circuit design is more flexible, the multiprocessor exchanges data signals through the DDR memory, the speed is higher, nanosecond low delay can be realized, the development of a chip is particularly facilitated, the software is not relied on, and the method is applicable to more application scenes.

The use of certain conventional english terms or letters for the sake of clarity of description of the invention is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the invention in terms of its possible chinese translations or specific letters.

Claims

1. A DDR memory data channel interface expansion circuit for bi-directional real-time transmission of data signals, comprising:

a first data signal port which is respectively connected with all or part of the data signal ports of the DDR memory in a one-to-one correspondence manner, and a second data signal port which is respectively connected with the data signal ports of at least two processors in a corresponding manner;

a switch matrix is arranged between the first data signal port and the second data signal port;

the switch matrix comprises radio frequency switch units which are arranged in one-to-one correspondence with the first data signal ports;

the radio frequency switch unit includes: the control module is used for receiving a switching-on control signal, and comprises a first interface which is switched on with the first data signal port, a second interface which is arranged in one-to-one correspondence with the second data signal port and is switched on;

the conduction control signal is used for controlling the on-off of the first interface and the second interface.

2. The DDR memory data channel interface expansion circuit of claim 1, wherein said control module comprises: at least two control voltage terminals and a ground terminal; the two control voltage ends are a group of common external control signal input ends.

3. The DDR memory data channel interface expansion circuit of claim 2, wherein two of said control voltage terminals of a same group are respectively designated as a first control voltage terminal and a second control voltage terminal;

the first control voltage end of each radio frequency switch unit is short-circuited together; the second control voltage terminal of each of the radio frequency switch units is shorted together.

4. The DDR memory data channel interface expansion circuit of claim 3, wherein an inverter is provided between said first control voltage terminal or said second control voltage terminal and said external control signal input terminal; the control module is configured such that the first interface is in communication with the second interface connected to a data signal port of a processor when the external control signal input is at a level of 1.

5. The DDR memory data channel interface expansion circuit of claim 1, wherein said second data signal ports connected in one-to-one correspondence with all or part of the data signal ports of the same processor are grouped; and the data signal lines between the second data signal ports and the corresponding first data signal ports in the same group are equal in length.

6. The DDR memory data channel interface expansion circuit of claim 1, wherein a wire length between said first data signal port and said second data signal port is less than 6 inches.

7. The DDR memory data channel interface expansion circuit of any of claims 1-6, wherein a transmission signal frequency of said radio frequency switch unit is above 1.6GHz.

8. The DDR memory data channel interface expansion circuit of claim 7, wherein said radio frequency switch unit is a miniaturized multi-pin chip-on-chip package.

9. A DDR memory data channel interface expansion system comprising a DDR memory, at least two processors and the interface expansion circuit of any of claims 1-8; the DDR memory and the processor transmit data signals through the expansion circuit; the DDR memory and the processor directly transmit non-data signals.

10. The DDR memory data channel interface expansion system of claim 9, wherein a wire length for transmitting address signals, command signals between said DDR memory and said processor is less than 13.15 inches.

11. The DDR memory data channel interface expansion system of claim 9, wherein a wiring length for transferring clock signals between said DDR memory and said processor is less than 10.59 inches.

12. The DDR memory data channel interface expansion system of claim 9, wherein a wire length for transmitting data signals between said DDR memory and said processor is less than 6 inches.

13. The DDR memory data channel interface expansion method is characterized by comprising the following steps: dividing all signals of a DDR memory into two groups, wherein one group is a data signal, and the other group is a non-data signal; directly connecting the non-data signals with a plurality of processor chips respectively; dividing the data signal into multiple paths of data channels after passing through the interface expansion circuit according to any one of claims 1-8, wherein the multiple paths of data channels are respectively in one-to-one correspondence with the processor chips; setting the number of the multiple paths of data channels according to the number of the multiple processor chips; and configuring the interface expansion circuit to be in real-time bidirectional transmission, and disconnecting the rest data channels when one data channel is connected with the processor chip.

14. The method of claim 13, wherein the processor chip uses a separate memory control core to generate a control signal to send to the interface expansion circuit to control the processor chip to turn on or off a data channel directly from the DDR memory.