KR20170060247A

KR20170060247A - Semiconductor device

Info

Publication number: KR20170060247A
Application number: KR1020150164373A
Authority: KR
Inventors: 신창환; 조재성; 조가람
Original assignee: 서울시립대학교 산학협력단
Priority date: 2015-11-24
Filing date: 2015-11-24
Publication date: 2017-06-01
Also published as: KR101743987B1

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which improves a subthreshold slope (SS) characteristic of a transistor through coupling a transistor with a ferroelectric capacitor having a negative capacitance and can implement steep switching To a semiconductor device.
According to the present invention, A capacitor having a negative capacitance; And a connection portion for electrically connecting the transistor and the capacitor.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which improves a subthreshold slope (SS) characteristic of a transistor through coupling a transistor with a ferroelectric capacitor having a negative capacitance and can implement steep switching To a semiconductor device.

As interest in transparent optoelectronic devices has increased, research and development on transparent oxide semiconductors (TOS) is under way. Among various TOS, amorphous IZO (amorphous Indium Zinc Oxide) is attracting attention as an active layer material of a transparent thin film transistor. However, a thin film transistor using an oxide semiconductor material has a disadvantage that its driving voltage range is very wide and power consumption is high.

In general, it is known that when a transistor is miniaturized, the electrical characteristics of a transistor such as a threshold voltage and a subthreshold slope are deteriorated. It is also necessary to improve the subthreshold slope characteristic in order to lower the driving voltage of the transistor.

For example, Korean Patent Laid-Open No. 10-2015-0094783 entitled " Oxide for Semiconductor Layer of Thin Film Transistor and Sputtering Target and Thin Film Transistor " filed by Kobe Seiko Co., Ltd. and Samsung Display Co., (Patent Document 1) discloses an oxide for a thin film transistor capable of realizing high mobility and also excellent in stress resistance and a thin film transistor using the same.

However, in Korean Patent Laid-Open No. 10-2015-0094783, it is disadvantageous in that it is impossible to lower the driving voltage of the thin film transistor because it is evaluated that the subthreshold slope is less than 1 V / dec.

1. Korean Patent Publication No. 10-2015-0094783.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of improving the subthreshold slope characteristic of a transistor by connecting a ferroelectric capacitor having a negative capacitance to a transistor and implementing stiff switching.

According to an aspect of the present invention, A capacitor having a negative capacitance; And a connection part for electrically connecting the transistor and the capacitor.

In the semiconductor device according to the present invention, the capacitor may include a lower electrode having a protrusion; An insulating film disposed on a side surface of the protrusion; A ferroelectric layer disposed on the lower electrode except for the protrusions and the insulating film; An upper electrode disposed on the ferroelectric layer and positioned below the protrusion; And a conductive layer disposed on the upper electrode and applying a driving voltage to the upper electrode.

Further, in the semiconductor device according to the present invention, each of the lower electrode, the upper electrode, the conductive layer, and the connection portion may include a material selected from the group consisting of TiN, TaN, Pt, Au, have.

Further, in the semiconductor device according to the present invention, the insulating film may include a material selected from the group including SiO ₂ , HfO ₂ , Al ₂ O _3, and high-k material.

In the semiconductor device according to the present invention, the ferroelectric layer may be formed of a material selected from the group consisting of P (VDF-TrFE) [poly (vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate) .

In the semiconductor device according to the present invention, the connection portion may connect the protrusion to the transistor.

In addition, in the semiconductor device according to the present invention, the transistor may include a thin film transistor.

In the semiconductor device according to the present invention, the transistor may include a back gate; A gate insulating film covering the back gate; A channel region disposed on the gate insulating film; And source and drain regions disposed on both sides of the channel region.

In addition, in the semiconductor device according to the present invention, each of the back gate, the source region, and the drain region may include a material selected from the group including TiN, TaN, Pt, Au, Al and polysilicon.

Further, in the semiconductor device according to the present invention, the gate insulating film may be formed from a group including SiO _x , SiN _x , Si ₂ N ₃ , HfO _x and AlO _x (where x is a real number greater than 0 and less than or equal to 4) And may include selected materials.

In addition, in the semiconductor device according to the present invention, the channel region may include a material selected from the group consisting of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and ZnO.

Further, in the semiconductor device according to the present invention, the connection portion may connect the protrusion and the back gate.

Further, in the semiconductor device according to the present invention, the transistor may include: a back gate; A gate insulating film covering the back gate; A channel region disposed on the gate insulating film; And source and drain regions disposed on both sides of the channel region.

In the semiconductor device according to the present invention, the transistor may be disposed in parallel with the capacitor.

The present invention also provides a semiconductor device comprising: a plurality of transistors; A capacitor having a negative capacitance; And a connection part electrically connecting the plurality of transistors and the capacitor.

In the semiconductor device according to the present invention, the connection portion may include a decoding portion for applying a voltage from the capacitor to at least one of the plurality of transistors.

Further, in the semiconductor device according to the present invention, the capacitor may include: a lower electrode having a protrusion; An insulating film disposed on a side surface of the protrusion; A ferroelectric layer disposed on the lower electrode except for the protrusions and the insulating film; An upper electrode disposed on the ferroelectric layer and positioned below the protrusion; And a conductive layer disposed on the upper electrode and applying a driving voltage to the upper electrode.

In the semiconductor device according to the present invention, the ferroelectric layer may include a material selected from the group consisting of P (VDF-TrFE), PZT, and BTO.

Further, in the semiconductor device according to the present invention, the connection portion may connect the protrusion to the plurality of transistors.

Further, in the semiconductor device according to the present invention, each of the plurality of transistors may include a thin film transistor.

Further, in the semiconductor device according to the present invention, each of the plurality of transistors includes: a back gate; A gate insulating film covering the back gate; A channel region disposed on the gate insulating film; And source and drain regions disposed on both sides of the channel region.

Further, in the semiconductor device according to the present invention, the channel region may include a material selected from the group including IGZO, IZO, and ZnO.

Further, in the semiconductor device according to the present invention, the connection portion may connect the protrusion and the back gate of each of the plurality of transistors.

Further, in the semiconductor device according to the present invention, each of the plurality of transistors may be disposed in parallel with the capacitor.

According to the present invention, by connecting a ferroelectric capacitor having a negative capacitance to a transistor, the subthreshold slope characteristic of the transistor can be improved and the stiff switching can be realized.

Particularly, it can be manufactured by using a manufacturing process of an existing transistor, and low power operation of the semiconductor device is possible.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an exemplary configuration of a semiconductor device according to an embodiment of the present invention. Fig.
2 is a diagram showing an exemplary configuration of a capacitor in a semiconductor device according to an embodiment of the present invention;
3 is a diagram showing an exemplary configuration of a transistor in a semiconductor device according to an embodiment of the present invention;
4 is a graph showing a relationship between a gate voltage and a drain current in an experimental example of a semiconductor device according to an embodiment of the present invention.
5 is a graph showing a relationship between a gate voltage and an internal voltage in an experimental example of a semiconductor device according to an embodiment of the present invention.
6 is a view showing an exemplary configuration of a semiconductor device according to another embodiment of the present invention;

Hereinafter, embodiments of the semiconductor device of the present invention will be described more specifically with reference to the accompanying drawings.

1 is a diagram showing an exemplary configuration of a semiconductor device according to an embodiment of the present invention. In Fig. 1, the shape or ratio of each part may differ from the actual shape or ratio for the sake of explanation. Also, parts irrelevant to the features of the invention may be omitted. These matters are the same in the following drawings.

Referring to FIG. 1, a semiconductor device according to the present invention includes a capacitor 100, a transistor 200, and a connection portion 300.

The capacitor 100 and the transistor 200 are arranged parallel to each other with reference to FIG.

The connection part 300 electrically connects the capacitor 100 and the transistor 200.

The connection 300 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al and polysilicon.

The capacitor 100 is a capacitor having a negative capacitance.

2 is a diagram showing an exemplary configuration of a capacitor in a semiconductor device according to an embodiment of the present invention, and is a diagram showing a cross-sectional view of a capacitor.

2, the capacitor 100 includes a lower electrode 110, an insulating layer 130, a ferroelectric layer 150, an upper electrode 170, and a conductive layer 190.

The lower electrode 110 includes a protrusion 115 as shown.

The protrusion 115 transfers the driving voltage applied through the conductive layer 190 to the transistor 200.

The lower electrode 110 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al and polysilicon.

The insulating film 130 is disposed on the side of the protrusion 115 of the lower electrode 110. The insulating layer 130 is a layer for electrically insulating the protrusions 115 of the lower electrode 110 from the ferroelectric layer 150 and the upper electrode 170. The insulating layer 130 may be disposed between the protruding portion 115 and the ferroelectric layer 150 and the upper electrode 170 and may not be formed on the upper portion 170 of the protruding portion 115 .

The insulating layer 130 may comprise a material selected from the group including, for example, SiO ₂ , HfO ₂ , Al ₂ O _3, and high-k materials. The high-k material includes, for example, hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and the like.

The ferroelectric layer 150 is disposed on the lower electrode 110. Referring to FIG. 2, the ferroelectric layer 150 is disposed on the lower electrode 110 except for the portion corresponding to the protrusion 115 and the insulating layer 130.

The ferroelectric layer 150 may include a material selected from the group including, for example, P (VDF-TrFE), PZT, BTO.

The upper electrode 170 is disposed on the ferroelectric layer 150. Referring to FIG. 2, the upper end of the upper electrode 170 is disposed below the protrusion 115, that is, the upper end of the protrusion 115 is positioned below.

The upper electrode 170 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al, and polysilicon.

The conductive layer 190 is disposed on the upper electrode 170 and applies a driving voltage to the upper electrode 170. Referring to FIG. 2, the conductive layer 190 is disposed on a portion of the upper electrode 170 that does not contact the protrusion 115.

The conductive layer 190 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al, and polysilicon.

Referring to FIGS. 1 and 2, the connection unit 300 is configured to electrically connect the protrusion 115 and the transistor 200.

3 is a diagram showing an exemplary configuration of a transistor in a semiconductor device according to an embodiment of the present invention, showing a cross-sectional view of a transistor.

The transistor 200 includes, for example, a thin film transistor. Transistor 100 may include other transistors besides thin film transistors, such as FinFETs.

Referring to FIG. 3, a thin film transistor in the form of a transistor 200 having, for example, a back gate is shown.

Referring to FIG. 3, the transistor 200 includes a back gate 210, a gate insulating film 230, a channel region 250, a source region 270, and a drain region 290.

Back gate 210 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al, and polysilicon.

The back gate 210 may be electrically connected to the protrusion 115 by, for example, a connection portion 300.

Referring to FIGS. 1 and 3, the gate insulating layer 230 is disposed to cover the back gate 210.

The gate insulating film 230 may include a material selected from the group including, for example, SiO _x , SiN _x , Si ₂ N ₃ , HfO _x and AlO _x (where x is a real number greater than 0 and less than or equal to 4) have.

The channel region 250 is disposed on the gate insulating film 230. The channel region 250 may comprise a material selected from the group consisting of IGZO, IZO, and ZnO.

A source region 270 and a drain region 290 are disposed on both sides of the channel region 250. The source region 270 and the drain region 290 may comprise a material selected from the group including, for example, TiN, TaN, Pt, Au, Al, and polysilicon.

Hereinafter, experimental results using a semiconductor device according to an embodiment of the present invention will be described in detail.

Particularly, in order to experimentally verify the influence of the capacitor 100 having a negative capacitance, a semiconductor device was manufactured as follows.

As the capacitor 100 having a negative capacitance, the structure of FIGS. 2 and 3, that is, a metal-insulator-metal (MIM) structure is used.

P (VDF _0.75 -TrFE _0.25 ) was dissolved in methyl ethyl ketone (MEK) solvent to have 1.4 wt% (weight percent), and the solution was spin-coated while rotating the TiN substrate at 3000 rpm Respectively. Then annealed at < RTI ID = 0.0 > 150 C < / RTI > The upper electrode was then deposited using gold. The upper electrode was patterned using a shadow mask having a diameter of 0.2 mm.

As the thin film transistor 200, an a-IZO (amorphous IZO) thin film transistor was used. First, a silicon oxide film (SiO ₂ ) of 100 nm was formed on an n ++ heavily doped silicon substrate. Thereafter, an IZO channel region of 15 nm was formed on the silicon oxide film. Thereafter, an aluminum source / drain electrode was formed. The source / drain electrodes were patterned using a shadow mask. The gate length and width were set to 200 탆 and 2000 탆, respectively.

Then, the thin film transistor 200 is connected to the capacitor 100 having a negative capacitance. In order to evaluate the input characteristics of the thin film transistor 200 according to the capacitor 100 having a negative capacitance, the gate voltage was biased at -20 V to + 20 V and the drain voltage was fixed at 20 V. Measurements were made using a Keithly 4200-SCS semiconductor measurement system.

4 is a graph showing a relationship between a gate voltage and a drain current in an experimental example of a semiconductor device according to an embodiment of the present invention.

4, the gate of the thin film transistor 200 in the case of being connected to the capacitor 100 having a negative capacitance (indicated by 'o' in FIG. 4) and not connected to the capacitor 100 The relationship between voltage and drain current is shown.

Referring to FIG. 4, when the gate voltage is -7.5 V, the subthreshold slope (SS) value is about 342 mV / dec, when the gate voltage is not connected to the capacitor 100 having a negative capacitance. However, when connected to the capacitor 100 having a negative capacitance, the subthreshold slope (SS) value is about 102 mV / dec when the gate voltage is -17.5V. This result implies that the accumulation mode of the thin film transistor 200 can be implemented even more at the negative gate voltage when connected to the capacitor 100 having a negative capacitance. It also means that the SS of the gate voltage can be greatly improved.

As a result of the experiment, it was confirmed that the characteristics of the thin film transistor 200 were not deteriorated even when the capacitor 100 was connected to the capacitor having the negative capacitance. That is, referring to FIG. 4, a drastic increase in drain current is observed only at a single gate voltage. This indicates that the effect of the negative capacitance is static and not dynamic.

5 is a graph showing a relationship between a gate voltage and an internal voltage in an experimental example of a semiconductor device according to an embodiment of the present invention. FIG. 5 shows the relationship between the gate voltage and the internal voltage when connected to a capacitor having a negative capacitance.

Referring to FIG. 5, it was observed that the internal voltage instantaneously rises when the gate voltage is -17.5 V, that is, when the drain current rapidly increases in FIG. For conventional MOSFETs, the internal voltage gain is less than one due to the voltage drop in the gate stack. However, in the experimental example of the semiconductor device according to the embodiment of the present invention, it is confirmed that the internal voltage gain is measured to be greater than 1 by the influence of the capacitor having the negative capacitance.

6 is a diagram showing an exemplary configuration of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 6, a semiconductor device according to another embodiment of the present invention includes a capacitor 100, a plurality of transistors 200, and a connection portion 300.

6, a semiconductor device according to another embodiment of the present invention has a structure in which a plurality of transistors 200 are arranged in accordance with the embodiment of FIGS. 1 to 5, Except for the differences, the descriptions are similar, so the detailed description is omitted and only the differences are described.

In the semiconductor device according to another embodiment of the present invention with reference to FIG. 6, the capacitor 100 and the plurality of transistors 200 are arranged parallel to each other.

2) of the capacitor 100 and the back gate 210 (see FIG. 4) of each of the plurality of transistors 200. The connection portion 300 connects the protrusion 115 of the capacitor 100 (see FIG.

The connection unit 300 may further include a decoding unit for applying a voltage, not shown, through the protrusion 115 of the capacitor 100 (see FIG. 2) to at least one of the plurality of transistors 200.

That is, the decoding unit selects at least a part of the plurality of transistors 200 in order to apply a voltage applied to only a part of the plurality of transistors 200 through the protrusion 115 (see FIG. 2) of the capacitor 100. Therefore, when the plurality of transistors 200 are configured in an array form, random access to each of the plurality of transistors 200 is possible through the decoding unit.

According to the present invention described above, the subthreshold slope characteristic of the transistor can be improved and the stiff switching can be realized by connecting the ferroelectric capacitor having a negative capacitance to the transistor.

Although the present invention has been described in detail, it should be understood that the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications may be made without departing from the essential characteristics of the present invention. Will be possible.

Therefore, the embodiments disclosed in the present specification are intended to illustrate rather than limit the present invention, and the scope and spirit of the present invention are not limited by these embodiments. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

100: Capacitor 110: Lower electrode
115: protrusion 130: insulating film
150: ferroelectric layer 170: upper electrode
190: conductive layer 200: transistor
210: back gate 230: gate insulating film
250: channel region 270: source region
290: drain region 300:

Claims

transistor;
A capacitor having a negative capacitance; And
A connection part electrically connecting the transistor and the capacitor,
.

The method according to claim 1,
The capacitor
A lower electrode having a protrusion;
An insulating film disposed on a side surface of the protrusion;
A ferroelectric layer disposed on the lower electrode except for the protrusions and the insulating film;
An upper electrode disposed on the ferroelectric layer and positioned below the protrusion; And
A conductive layer disposed on the upper electrode and applying a driving voltage to the upper electrode,
The semiconductor device comprising: a semiconductor substrate;

3. The method of claim 2,
Wherein each of the lower electrode, the upper electrode, the conductive layer, and the connection portion comprises a material selected from the group consisting of TiN, TaN, Pt, Au, Al, and polysilicon.

3. The method of claim 2,
The semiconductor device and the insulating film comprises a material selected from the group consisting of _{SiO 2, HfO 2, Al 2} O 3 and a high-k material.

3. The method of claim 2,
Wherein the ferroelectric layer comprises a material selected from the group consisting of P (VDF-TrFE) [poly (vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate).

3. The method of claim 2,
And the connection portion connects the protrusion and the transistor.

The method according to claim 1,
Wherein the transistor comprises a thin film transistor.

8. The method of claim 7,
The transistor comprising:
Back gate;
A gate insulating film covering the back gate;
A channel region disposed on the gate insulating film; And
A source region and a drain region disposed on both sides of the channel region,
The semiconductor device comprising: a semiconductor substrate;

9. The method of claim 8,
Wherein each of the back gate, the source region, and the drain region comprises a material selected from the group consisting of TiN, TaN, Pt, Au, Al, and polysilicon.

9. The method of claim 8,
Wherein the gate insulating film comprises a material selected from the group consisting of SiO _x , SiN _x , Si ₂ N ₃ , HfO _x, and AlO _x (where x is greater than 0 and less than or equal to 4 real numbers) .

9. The method of claim 8,
Wherein the channel region comprises a material selected from the group consisting of Indium Gallium Zinc Oxide (IGZO), IZO (Indium Zinc Oxide), and ZnO.

9. The method of claim 8,
And the connecting portion connects the protrusion and the back gate.

3. The method of claim 2,
The transistor comprising:
Back gate;
A gate insulating film covering the back gate;
A channel region disposed on the gate insulating film; And
A source region and a drain region disposed on both sides of the channel region,
The semiconductor device comprising: a semiconductor substrate;

14. The method of claim 13,
And the connecting portion connects the protrusion and the back gate.

The method according to claim 1,
And the transistor is disposed in parallel with the capacitor.

A plurality of transistors;
A capacitor having a negative capacitance; And
And a connection portion electrically connecting the plurality of transistors and the capacitor,
.

17. The method of claim 16,
And the connection portion includes a decoding portion for applying a voltage from the capacitor to at least one of the plurality of transistors.

17. The method of claim 16,
The capacitor
A lower electrode having a protrusion;
An insulating film disposed on a side surface of the protrusion;
A ferroelectric layer disposed on the lower electrode except for the protrusions and the insulating film;
An upper electrode disposed on the ferroelectric layer and positioned below the protrusion; And
A conductive layer disposed on the upper electrode and applying a driving voltage to the upper electrode,
The semiconductor device comprising: a semiconductor substrate;

19. The method of claim 18,
Wherein each of the lower electrode, the upper electrode, the conductive layer, and the connection portion comprises a material selected from the group consisting of TiN, TaN, Pt, Au, Al, and polysilicon.

19. The method of claim 18,
The semiconductor device and the insulating film comprises a material selected from the group consisting of _{SiO 2, HfO 2, Al 2} O 3 and a high-k material.

19. The method of claim 18,
Wherein the ferroelectric layer includes a material selected from the group consisting of P (VDF-TrFE), PZT, and BTO.

19. The method of claim 18,
And the connection portion connects the protrusion and the plurality of transistors.

17. The method of claim 16,
And each of the plurality of transistors includes a thin film transistor.

24. The method of claim 23,
Wherein each of the plurality of transistors includes:
Back gate;
A gate insulating film covering the back gate;
A channel region disposed on the gate insulating film; And
A source region and a drain region disposed on both sides of the channel region,
The semiconductor device comprising: a semiconductor substrate;

25. The method of claim 24,
Wherein each of the back gate, the source region, and the drain region comprises a material selected from the group consisting of TiN, TaN, Pt, Au, Al, and polysilicon.

25. The method of claim 24,
Wherein the gate insulating film comprises a material selected from the group consisting of SiO _x , SiN _x , Si ₂ N ₃ , HfO _x, and AlO _x (where x is greater than 0 and less than or equal to 4 real numbers) .

25. The method of claim 24,
Wherein the channel region comprises a material selected from the group consisting of IGZO, IZO, and ZnO.

25. The method of claim 24,
And the connecting portion connects the protrusion and the back gate of each of the plurality of transistors.

19. The method of claim 18,
Wherein each of the plurality of transistors includes:
Back gate;
A gate insulating film covering the back gate;
A channel region disposed on the gate insulating film; And
A source region and a drain region disposed on both sides of the channel region,
The semiconductor device comprising: a semiconductor substrate;

30. The method of claim 29,
And the connecting portion connects the protrusion and the back gate of each of the plurality of transistors.

17. The method of claim 16,
And each of the plurality of transistors is disposed in parallel with the capacitor.