KR20170058475A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of minimizing electric field interference and motion interference of liquid crystal molecules in adjacent pixels. The liquid crystal display device includes a liquid crystal layer disposed between a first substrate and a second substrate; a plurality of gate lines and a plurality of data lines disposed on the first substrate; a plurality of pixels connected to the plurality of gate lines and the plurality of data lines and having pixel electrodes and switching elements connected to the pixel electrodes. The pixel electrodes of one row among an odd-numbered row and an even-numbered row are located in an odd-numbered column. The pixel electrodes of the other row among the odd-numbered row and the even-numbered row are located in an even-numbered column.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of minimizing electric field interference and motion interference of liquid crystal molecules in adjacent pixels.

2. Description of the Related Art A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPDs), and is composed of two substrates on which electrodes are formed and a liquid crystal layer sandwiched therebetween. A liquid crystal display device is a display device that adjusts the amount of light transmitted by applying voltages to two electrodes to rearrange the liquid crystal molecules in the liquid crystal layer.

The liquid crystal display device includes a plurality of pixels arranged in a matrix form. As the liquid crystal display device becomes larger, the interval between the pixels is further reduced. As a result, the electric fields generated in the pixels adjacent to each other can affect each other. Also, when the distance between the pixels is very close, the movement of the liquid crystal molecules in one pixel may affect the movement of the liquid crystal molecules in the adjacent pixels. As a result, the electric field of the pixel and the movement of the liquid crystal molecules may be distorted and the image quality may be deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of minimizing an electric field between neighboring pixels and motion interference of liquid crystal molecules.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a liquid crystal layer disposed between a first substrate and a second substrate; A plurality of gate lines and a plurality of data lines disposed on the first substrate; A plurality of pixels connected to the plurality of gate lines and the plurality of data lines and having switching elements connected to the pixel electrodes and the pixel electrodes; The pixel electrodes of one row among the odd-numbered rows and the even-numbered rows are located in odd-numbered columns; And the pixel electrodes of the other row among the odd-numbered rows and the even-numbered rows are located in the even-numbered columns.

The pixel electrodes of one row are not located between the pixel electrodes of adjacent rows.

The pixel electrode includes a first pixel electrode located in one row, a second pixel electrode located in another row and adjacent to the first pixel electrode, a third pixel electrode located in another row, adjacent to the first pixel electrode, A pixel electrode; The first pixel electrode is located between imaginary extension lines extending from the opposite sides of the second pixel electrode and the third pixel electrode, respectively.

The pixel electrode further includes a fourth pixel electrode adjacent to the first pixel electrode and the second pixel electrode and positioned in one row; The first pixel electrode is located between imaginary extension lines extending from opposite sides of the second pixel electrode and the fourth pixel electrode, respectively.

The switching elements connected to the pixel electrodes in the (2k-1) -th row (k is a natural number) and the pixel electrodes connected to the pixel electrodes in the 2k-th row are commonly connected to one gate line.

The switching element connected to the pixel electrode of the 2k-th row is located between the two pixel electrodes adjacent to the pixel electrode of the 2k-th row and located in the 2k + 1-th row.

The switching element connected to the pixel electrode of the 2k-th row is located between the two pixel electrodes adjacent to the pixel electrode of the 2k-th row and located in the 2k-1-th row.

The width of the pixel electrode located on any one of the two adjacent rows is shorter or smaller than or equal to the distance between two pixel electrodes adjacent to the pixel electrode and located in another row.

A part of the pixel electrodes located in one row is located between the pixel electrodes in another row adjacent to one row and the pixel electrodes in another row adjacent to the row.

The pixel electrodes of the other row and the pixel electrodes of the other row are located in the same column.

An imaginary first line segment that connects each center of two adjacent pixel electrodes in one row and a second line segment that connects the center of one of the two pixel electrodes and the center of the pixel electrode adjacent to the two pixel electrodes, The second line segment has an interior angle of 50 to 55 degrees.

The distance between the data lines located on both sides of the pixel electrode is larger than the distance between the data lines located on both sides of the switching element.

The gate lines have a jig-jag shape.

The data lines have a linear shape or a jig-jig shape.

The pixel electrode is located in the pixel region of each pixel; The switching element is located in the non-pixel region of each pixel; The ratio of the area of the pixel area to the area of the non-pixel area is 3: 7.

Two pixels adjacent to one row and one pixel adjacent to two pixels and located in another row display different colors.

Three pixels are commonly connected to one gate line.

Each of the plurality of pixels further includes a connection electrode connecting the pixel electrode and the switching element.

The connection electrode is formed integrally with the pixel electrode or the source electrode of the switching element.

The liquid crystal display device according to the present invention provides the following effects.

The pixels of the liquid crystal display according to the present invention are adjacent to each other in the diagonal direction. Further, the pixel electrode of any one of the two adjacent rows is not located between the adjacent two pixel electrodes of the other row. As a result, the distances between the adjacent pixel electrodes are different from each other. Therefore, electric field interference between neighboring pixels and motion interference of liquid crystal molecules can be minimized.

1 is a plan view of one pixel according to one embodiment of the present invention.
2 is a sectional view taken along the line I-I 'in FIG.
FIG. 3 is a view showing a part of a liquid crystal display device including a plurality of pixels having a structure as shown in FIG.
FIG. 4 is a view showing only a few pixel electrodes located in a specific portion in FIG.
FIG. 5 is another view showing only a few pixel electrodes located at a specific portion in FIG.
6 is a view for explaining an angle formed by two pixel electrodes adjacent in a diagonal direction.
FIG. 7 is another view showing a part of a liquid crystal display device including a plurality of pixels having the structure shown in FIG.
FIG. 8 is another diagram showing a part of a liquid crystal display device including a plurality of pixels having the structure shown in FIG.
FIG. 9 is another diagram showing a part of a liquid crystal display device including a plurality of pixels having the structure shown in FIG.

In the drawings, the thickness is enlarged to clearly represent the layers and regions.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "below " another portion, it includes not only a case where it is" directly underneath "another portion but also another portion in between. Conversely, when a part is "directly underneath" another part, it means that there is no other part in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

In this specification, when a part is connected to another part, it includes not only a direct connection but also a case where the part is electrically connected with another part in between. Further, when a part includes an element, it does not exclude other elements unless specifically stated to the contrary, it may include other elements.

The terms first, second, third, etc. in this specification may be used to describe various components, but such components are not limited by these terms. The terms are used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second or third component, and similarly, the second or third component may be alternately named.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

FIG. 1 is a plan view of one pixel according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line I-I 'of FIG.

1 and 2, the pixel PX includes a switching element TFT, a gate insulating film 311, an interlayer insulating film 318, a protective film 320, a color filter 354, a capping layer 391 A pixel electrode PE, a liquid crystal layer 333, a light shielding layer 376, an overcoat layer 722, and a common electrode 330.

The pixel electrode PE is located in the pixel region 151 of the pixel PX and the switching element TFT is located in the non-pixel region 152 of the pixel PX. The pixel region 151 has a smaller area than the non-pixel region 152. For example, the ratio of the area of the pixel area 151 to the area of the non-pixel area 152 may be 3: 7.

The switching element TFT is connected to the gate line GL, the data line DL and the pixel electrode PE. To this end, the switching element TFT includes a gate electrode GE connected to the gate line GL, a drain electrode DE connected to the data line DL, and a source electrode connected to the pixel electrode PE And a semiconductor layer 321 to which the drain electrode DE and the source electrode SE are connected.

The switching element (TFT) may include a thin film transistor (Thin Film Transistor).

A gate line GL, a data line DL, a gate insulating film 311, an interlayer insulating film 318, a protective film 320, a color filter 354, a capping layer 391 and a pixel electrode (not shown) PE) are located on the first substrate 301.

The light shielding layer 376, the overcoat layer 722, and the common electrode 330 are located on the second substrate 302.

The gate line GL includes a plurality of gate electrodes GE. On the other hand, although not shown, the gate line GL may have a larger area of its connecting portion (for example, an end portion) than other portions thereof for connection with another layer or an external driving circuit.

The gate line GL may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy or a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) Or a molybdenum series metal such as molybdenum (Mo) or molybdenum alloy. Alternatively, the gate line GL may be made of any one of chromium (Cr), tantalum (Ta), and titanium (Ti). On the other hand, the gate line GL may have a multi-film structure including at least two conductive films having different physical properties.

The gate electrode GE may have the same material and structure (multi-film structure) as the gate line GL. The gate electrode GE and the gate line GL can be formed simultaneously in the same process.

The gate insulating film 311 is located on the gate line GL and the gate electrode GE, as shown in Fig. At this time, the gate insulating film 311 is located on the entire surface of the first substrate 301 including the gate line GL and the gate electrode GE. The gate insulating film 311 may be made of silicon nitride (SiNx), silicon oxide (SiOx) or the like. The gate insulating film 311 may have a multi-film structure including at least two insulating layers having different physical properties.

The semiconductor layer 321 is located on the gate insulating film 311, as shown in Fig. The semiconductor layer 321 overlaps at least part of the gate electrode GE, as shown in Figs. 1 and 2. The semiconductor layer 321 may be made of amorphous silicon, polycrystalline silicon, or the like.

The interlayer insulating film 318 is located on the semiconductor layer 321 and the gate insulating film 311 as shown in Fig. At this time, the interlayer insulating film 318 is located on the entire surface of the first substrate 301 including the semiconductor layer 321. The interlayer insulating film 318 has first and second contact holes CH1 and CH2. Silicon nitride (SiNx), silicon oxide (SiOx), or the like. The interlayer insulating film 318 may have a multi-film structure including at least two insulating layers having different physical properties.

The data line DL and the drain electrode DE are located on the interlayer insulating film 318, as shown in Fig. At this time, the drain electrode DE is connected to the semiconductor layer 321 through the first contact hole CH1 of the interlayer insulating film 318. [ Although not shown, a resistive contact layer may further be located at the interface between the drain electrode DE and the semiconductor layer 321. [

The resistive contact layer may be made of a material such as n + hydrogenated amorphous silicon, which is heavily doped with n-type impurity ions such as phosphorus or hydrogen phosphide (PH3), or may be made of silicide.

Although not shown, the data line DL may have a larger area of its connecting portion (for example, an end portion) than other portions thereof for connection with another layer or an external driving circuit.

The data line DL crosses the gate line GL. Although not shown, where the data line DL and the gate line GL intersect, the data line DL may have a line width smaller than other portions thereof. Thus, the parasitic capacitance between the data line DL and the gate line GL can be reduced.

The data lines DL may be made of refractory metals such as molybdenum, chromium, tantalum, and titanium, or alloys thereof. The data line DL may have a multi-film structure including a refractory metal film and a low-resistance conductive film. Examples of the multilayer structure include a double layer film of a chromium or molybdenum (or molybdenum alloy) lower film and an aluminum (or aluminum alloy) upper film, a lower film of molybdenum (or molybdenum alloy), an aluminum (or aluminum alloy) interlayer, molybdenum ) Triple layer of the upper layer. On the other hand, the data line DL may be made of various other metals or conductors.

The drain electrode DE protrudes from the data line DL, as shown in Fig. The drain electrode DE may be part of the data line DL. The drain electrode DE may have the same material and structure (multi-film structure) as the data line DL. The drain electrode DE and the data line DL can be formed simultaneously in the same process.

The protective film 320 is located on the data line DL and the interlayer insulating film 318, as shown in Fig. At this time, the protective film 320 is located on the entire surface of the first substrate 301 including the data line DL and the interlayer insulating film 318. The protective film 320 has a second contact hole CH2 penetrating a part thereof.

The protective layer 320 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the inorganic insulating material may have photosensitivity and dielectric constant of about 4.0 Can be used. Alternatively, the passivation layer 320 may have a double-layer structure of a lower inorganic layer and an upper organic layer so as not to damage the exposed semiconductor layers 321 and 322 while having excellent insulating properties. The thickness of the protective layer 320 may be about 5000 ANGSTROM or more, and may be about 6000 ANGSTROM to about 8000 ANGSTROM.

The source electrode SE is located on the protective film 320, as shown in Fig. At this time, the source electrode SE is connected to the semiconductor layer 321 through the protection film 320 and the second contact hole CH2 of the interlayer insulating film 318. Although not shown, a resistive contact layer may further be located at the interface between the source electrode SE and the semiconductor layer 321. [

The source electrode SE may have the same material and structure (multi-film structure) as the data line DL described above.

The color filter 354 is located on the source electrode SE and the protective film 320, as shown in Fig. The edge of the color filter 354 is located on the gate line GL and the data line DL. However, the color filter 354 is not located at the portion corresponding to the third contact hole CH3. On the other hand, the edge of the color filter 354 may overlap the edge of another color filter 354 adjacent thereto. The color filter 354 may be made of a photosensitive organic material.

The capping layer 391 is located on the color filter 354, as shown in Fig. The capping layer 391 prevents the impurities generated from the color filter 354 from diffusing into the liquid crystal layer 333. The capping layer 391 has a third contact hole CH3. The capping layer 391 may be made of silicon nitride, silicon oxide, or the like.

The pixel electrode PE is located on the capping layer 391 of the pixel region P as shown in Figs.

The pixel electrode PE may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). At this time, the ITO may be a polycrystalline or single crystal material. IZO may also be a polycrystalline or single crystal material. Alternatively, the IZO can be an amorphous material.

The connecting electrode 443 is located on the capping layer 391. The connection electrode 443 extends from the pixel electrode PE to the non-pixel region 152. The connection electrode 443 is formed integrally with the pixel electrode PE. The connection electrode 443 is located in the pixel region 151 and the non-pixel region 152. The connection electrode 443 is connected to the source electrode SE through the third contact hole CH3 of the capping layer 391. [

The connection electrode 443 may be formed of the same material as the pixel electrode PE. The connection electrode 443 and the pixel electrode PE can be formed simultaneously in the same process. Alternatively, the connection electrode 443 may be formed of the same material as the source electrode SE. For example, the connection electrode 443 may be integrally formed with the source electrode SE. In this case, the connection electrode 443 is formed simultaneously with the same process as the source electrode SE. At this time, the connection electrode 443 is connected to the pixel electrode PE through the contact hole.

The light shielding layer 376 is located on the second substrate 302, as shown in Fig. The light shielding layer 376 is located in the remaining portion except for the pixel region 151. [ Alternatively, the light shielding layer 376 may be located on the first substrate 301.

The overcoat layer 722 is located on the light shielding layer 376. At this time, the overcoat layer 722 may be located on the entire surface of the second substrate 302 including the light shielding layer 376. The overcoat layer 722 may be formed from a combination of components located between the overcoat layer 722 and the second substrate 302 such as the components of the second substrate 302 such as the shading layer 376 described above To minimize the height difference between the two. The overcoat layer 722 may be omitted.

The common electrode 330 is located on the overcoat layer 722. At this time, the common electrode 330 may be positioned on the entire surface of the second substrate 302 including the overcoat layer 722. Alternatively, the common electrode 330 may be located on the overcoat layer 722 to correspond to the pixel region 151. A common voltage is applied to the common electrode 330.

Meanwhile, although not shown, the pixel PX may further include a first polarizing plate and a second polarizing plate. When the opposing surfaces of the first substrate 301 and the second substrate 302 are defined as the upper surfaces of the corresponding substrates and the surfaces located on opposite sides of the upper surfaces are respectively defined as the lower surface of the substrate, The first polarizing plate is positioned on the lower surface of the first substrate 301 and the second polarizing plate is located on the lower surface of the second substrate 302.

The transmission axis of the first polarizing plate and the transmission axis of the second polarizing plate are orthogonal to each other. One of these transmission axes is arranged parallel to the gate line GL. On the other hand, the liquid crystal display device may include only one of the first polarizing plate and the second polarizing plate.

The first substrate 301 and the second substrate 302 are insulating substrates made of glass or plastic.

The liquid crystal layer 333 disposed between the first substrate 301 and the second substrate 302 includes liquid crystal molecules, and these liquid crystal molecules may be twisted nematic liquid crystal molecules.

3 is a diagram showing a part of a liquid crystal display device including a plurality of pixels PX having the structure shown in FIG.

Each of the plurality of pixels PX shown in FIG. 3 has the same structure as the pixel PX of FIG. 1 described above. That is, each pixel PX in FIG. 3 has the same plane and sectional structure as the pixel PX shown in FIG.

The pixels PX in a certain column are shifted downward or further upward than the pixels PX in the other column. For example, as shown in FIG. 3, the pixels PX of the even-numbered columns (any one of C2, C4, and C6) are connected to the pixels PX of the odd-numbered columns C1, And are further shifted down along the length direction of the data lines (for example, DL2). In other words, if a data driver (not shown) for driving the data lines DL1, DL2, DL3, DL4, DL5, DL6 and DL7 is located above the data lines DL1 to DL7 , And the pixels PX in the even-numbered columns are arranged in order from the farther (row) in the data driver than the pixels PX in the odd-numbered column. Accordingly, the switching element (TFT) connected to the pixel electrode PE of the 2k-th (k is a natural number) row is adjacent to the pixel electrode PE of the 2k-th row and is connected to two pixels And are located between the electrodes PE. 3, the pixel electrode PE located in the second row R2 and the second column C2 is defined as the first pixel electrode, and the third row R3 and the first column C1 are defined as the first pixel electrode, And the pixel electrode PE located in the third row R3 and the third column C3 is defined as a third pixel electrode, the first pixel electrode PE is defined as a second pixel electrode, The switching element TFT is connected between the second pixel electrode and the third pixel electrode.

(TFTs) connected to each of the pixel electrodes PE in the (2k-1) th row and the switching elements (TFTs) connected to the pixel electrodes PE in the 2k-th row are common to one gate line Lt; / RTI > 3, the switching elements (TFTs) connected to the pixel electrodes PE of the first row R1 and the pixel electrodes PE of the second row R2, for example, The switching elements (TFT) connected to each of the gate lines GL1 and GL2 are commonly connected to the first gate line GL1. The first gate line GL1 includes a plurality of gate electrodes GE connected to each other and the odd gate electrodes GE include a switching element TFT for driving the pixel electrodes PE of the first row R1, And the even gate electrodes GE are connected to the respective switching elements TFTs driving the pixel electrodes PE of the second row R2. Thus, the first gate line GL1 including the plurality of gate electrodes GE arranged as described above has a jig-jag shape. The remaining gate lines have the same shape as the first gate line GL1. However, each gate line is not connected to each other. For example, the first gate line GL1 and the second gate line GL2 are not connected.

The pixel electrodes PE belonging to the odd-numbered rows (one of R1, R3, and R5) are located in the odd-numbered columns C1, C3, and C5. In other words, the pixel electrodes PE arranged along the odd-numbered rows are located between the 2x-th (n is a natural number) data line and the 2x-th data line. For example, as shown in Fig. 3, the pixel electrodes PE belonging to the first row R1 are located in the first column C1, the third column C3 and the fifth column C5, respectively . In other words, the pixel electrodes PE arranged along the first row R1 are arranged between the first data line DL1 and the second data line DL2, between the third data line DL3 and the fourth data line DL3, DL4 and the fifth data line DL5 and the sixth data line DL6, respectively.

The pixel electrodes PE belonging to the even-numbered rows (any one of R2, R4, and R6) are located in the even-numbered columns C2, C4, and C6. In other words, the pixel electrodes PE arranged along the even-numbered rows are located between the 2xth data line and the 2x + 1th data line. For example, as shown in FIG. 3, the pixel electrodes PE belonging to the second row R2 are located in the second column C2, the fourth column C4, and the sixth column C6, respectively . In other words, the pixel electrodes PE arranged along the second row R2 are connected between the second data line DL2 and the third data line DL3, the fourth data line DL4 and the fifth data line DL4, DL5 and the sixth data line DL6 and the seventh data line DL7, respectively. However, the pixel electrode located at the outermost one of the pixel electrodes PE of the even-numbered row is located between the data line and the edge of the first substrate 301. [

Although not shown, the pixel electrodes PE belonging to the odd-numbered rows (one of R1, R3 and R5) are located in the even-numbered columns C2, C4 and C6 and the even- The pixel electrodes PE may be located in the odd-numbered columns C1, C3, and C5. In this case, the pixel electrodes PE arranged along the odd-numbered row are located between the 2x-th data line and the 2x + 1-th data line, and the pixel electrodes PE arranged along the even- And is located between the data line and the 2x-th data line.

Each pixel PX is connected to one of the data lines on both sides. For example, as shown in Fig. 3, each pixel PX may be connected to a data line located on its left side. The pixel PX is connected to the data line through the switching element TFT.

The pixel electrode PE of any one of the adjacent two rows is not located between the adjacent two pixel electrodes PE of the other row. For example, in FIG. 3, the pixel electrode located in the second row R2 and the second column C2 is defined as the first pixel electrode, and the pixel electrode located in the first row R1 and the first column C1 When the pixel electrode defined in the first row R1 and the third column C3 is defined as the third pixel electrode, any portion of the first pixel electrode is defined as the second pixel electrode, And is not located between the third pixel electrodes.

Since the adjacent pixel electrodes are adjacent to each other in the diagonal direction and the pixel electrodes in any one of the two adjacent rows are not located between the adjacent two pixel electrodes in the other row, The distance between them becomes far. Therefore, the movement of the electric field and the liquid crystal molecules in one pixel hardly affects the electric field of the other pixels adjacent to the pixel and the movement of the liquid crystal molecules.

In FIG. 3, the reference character R on the pixel electrode PE means that the pixel PX including the pixel electrode PE is a red pixel R indicating red color, G indicates that the pixel PX including the pixel electrode PE is a green pixel G indicating green and the reference B indicated on the pixel electrode PE includes the pixel electrode PE And the pixel PX is a blue pixel B that displays blue. Three pixels PX connected in common to one gate line and adjacent to each other constitute one main pixel. For example, in FIG. 3, a red pixel R, a green pixel G and a blue pixel B, which are commonly connected to the first gate line GL1 and are adjacent to each other, constitute one main pixel.

Meanwhile, the first pixel electrode may be located in a region defined as follows, which will be described in detail with reference to FIG.

FIG. 4 is a view showing only a few pixel electrodes PE located at a specific portion in FIG.

4, the pixel electrode PE located in the second row R2 and the second column C2 is defined as the first pixel electrode PE1 and the pixel electrode PE1 adjacent to the first pixel electrode PE1 Four pixel electrodes PE located in two rows are defined as second, third, fourth and fifth pixel electrodes PE2, PE3, PE4 and PE5, respectively. That is, the pixel electrode located in the first row R1 and the first column C1 is referred to as the second pixel electrode PE2 and the pixel electrode PE located in the third row R3 and the first column C1 The pixel electrode PE located in the first row R1 and the third column C3 is referred to as a fourth pixel electrode PE4 and the third row R3 and the third column And the pixel electrode PE located at the pixel electrode C3 is defined as a fifth pixel electrode PE5.

At this time, a virtual extension line extending from one side (the side of the second pixel electrode) of the opposite sides of the second pixel electrode PE2 and the third pixel electrode PE3 is defined as a first straight line VL1 , And an imaginary extension line extending from the other side (the side of the third pixel electrode) is defined as a second straight line VL2. An imaginary extension line extending from one side of the opposing sides of the second pixel electrode PE2 and the fourth pixel electrode PE4 (the side of the second pixel electrode PE2) is referred to as a third straight line VL3. And a virtual extension line extending from the other side (the side of the fourth pixel electrode PE4) is defined as a fourth straight line VL4.

At this time, the first pixel electrode PE1 is located between the first straight line VL1 and the second straight line VL2 described above. In this case, the first pixel electrode PE1 is not located between the second pixel electrode PE2 and the fourth pixel electrode PE4. Also, the second pixel electrode PE2 is not located between the third pixel electrode PE3 and the fifth pixel electrode PE5.

The first pixel electrode PE1 may be positioned between the first straight line VL1 and the second straight line VL2 described above and between the third straight line VL3 and the fourth straight line VL4 described above. That is, the first pixel electrode PE1 may be located within the defined region 444 surrounded by the first, second, third and fourth straight lines VL1, VL2, VL3, VL4. In this case, the first pixel electrode PE1 is not located between the second pixel electrode PE2 and the fourth pixel electrode PE4. Also, the second pixel electrode PE2 is not located between the third pixel electrode PE3 and the fifth pixel electrode PE5.

The width of the pixel electrode PE located on any one of the two adjacent rows may be smaller than the distance between the two pixel electrodes PE located on the other row adjacent to the pixel electrode PE. For example, as shown in FIG. 4, the width W1 of the first pixel electrode PE1 may be smaller than the distance D1 between the second pixel electrode PE2 and the third pixel electrode PE3 .

On the other hand, each pixel electrode PE can overlap the data lines. This will be described in detail with reference to FIG.

FIG. 5 is another view showing only a few pixel electrodes located at a specific portion in FIG.

Each pixel electrode PE may overlap at least one of two adjacent data lines on both sides of the pixel electrode PE. For example, as shown in FIG. 5, one side of the first pixel electrode PE1 may extend toward the second data line DL2 and be located on the second data line DL2. The other side of the first pixel electrode PE1 may further extend toward the third data line DL3 and be located on the third data line DL3. The remaining pixel electrodes PE including the second to fifth pixel electrodes PE2 to PE5 may overlap the data lines like the first pixel electrode PE1 described above.

In such a case, a part of the pixel electrode PE located in one row is arranged between the pixel electrode PE in another row adjacent to the row and the pixel electrode PE in another row adjacent to the row, Can be located. Here, the above-described pixel electrodes PE in the other row and the pixel electrodes PE in the other row are located in the same column. For example, in FIG. 5, a part of the first pixel electrode PE1 may be located between the second pixel electrode PE2 and the third pixel electrode PE3. In other words, an imaginary straight line extending along one side of the first pixel electrode PE1 on the second data line DL2 is connected to the second pixel electrode PE2 and the third pixel electrode PE3, You can cross.

The width of the pixel electrode PE located on one of the two adjacent rows may be greater than or equal to the distance between the two pixel electrodes PE located on the other row and adjacent to the pixel electrode. 5, the width W2 of the first pixel electrode PE1 is greater than the distance D3 between the second pixel electrode PE2 and the fourth pixel electrode PE4, Or may be equal to the distance.

The pixel electrode (for example, PE1) of FIG. 5 has a width larger than that of the pixel electrode (for example, PE1) of FIG. 4 (W2> W1) (L2 < L1). At this time, a distance D4 between one side of the first pixel electrode PE1 and one side of the second pixel electrode PE2 shown in FIG. 5 is equal to one side of the first pixel electrode PE1 shown in FIG. Is larger than the distance D2 between one side of the second pixel electrode PE2.

6 is a view for explaining an angle formed by two pixel electrodes adjacent in a diagonal direction.

A virtual line segment connecting each center of two adjacent pixel electrodes in a row is defined as a first line segment and a center line of the pixel electrode adjacent to the two pixel electrodes and a center portion of the two pixel electrodes When defining a line segment connecting a center portion of one of them to a second line segment, an interior angle formed by the first line segment and the second line segment is from 50 degrees to 55 degrees. 6, a first line segment VL11 connecting the center portion CP2 of the second pixel electrode PE2 and the center portion CP3 of the third pixel electrode PE3, The internal angle formed by the second line segment VL22 connecting the center portion CP2 of the electrode PE2 and the center portion CP1 of the first pixel electrode PE1 is from 50 degrees to 55 degrees. For example,? 1 may be 52 degrees.

On the other hand, an angle formed by the imaginary straight line VL33 passing through the center portion CP1 of the first pixel electrode PE1 and perpendicularly intersecting the data line DL3 (for example, DL3) and the second line segment VL22 described above is 50 Lt; / RTI &gt; to 55 degrees. For example,? 2 may be 52 degrees. If the first line segment VL11 and the straight line VL33 are parallel,? 1 and? 2 are the same.

FIG. 7 is another view showing a part of a liquid crystal display device including a plurality of pixels having the structure shown in FIG.

Each of the plurality of pixels PX shown in Fig. 7 has the same structure as the pixel PX of Fig. 1 described above. That is, each pixel PX in Fig. 7 has the same plane and sectional structure as the pixel PX shown in Fig.

7, the interval d1 between the data lines DL1 and DL2 located on both sides of the pixel electrode PE is set to be shorter than the interval d1 between the data lines DL1 and DL2 located on both sides of the switching element TFT . Due to this, the data lines DL1 to DL7 have a jig-jag shape.

7 is the same as that of the liquid crystal display of FIG. 3 except for the shape of the data lines, the description of the components shown in FIG. 7 will be omitted from FIGS. 1 to 6 and the related description .

FIG. 8 is another diagram showing a part of a liquid crystal display device including a plurality of pixels PX having the structure shown in FIG.

Each of the plurality of pixels PX shown in Fig. 8 has the same structure as the pixel PX of Fig. 1 described above. That is, each pixel PX in Fig. 8 has the same plane and sectional structure as the pixel PX shown in Fig.

The pixels PX in a specific column have a shape opposite to the pixels PX in the other column. For example, as shown in FIG. 8, the pixels PX of the even-numbered columns (any one of C2, C4, and C6) are connected to the pixels PX of the odd-numbered columns C1, As shown in FIG. For example, each of the pixels PX in the odd-numbered column has the same shape as the pixel PX shown in Fig. 1 described above, and each of the pixels PX in the even- Also has an inverted shape. Accordingly, the switching element (TFT) connected to the pixel electrode PE in the 2k-th row is located between the two pixel electrodes PE located in the 2k-1-th row and adjacent to the pixel electrode in the 2k-th row do. 8, the pixel electrode PE located in the second row R2 and the second column C2 is defined as the first pixel electrode, and the first row R1 and the first column C1 are defined as the first pixel electrode, And the pixel electrode PE located in the first row R1 and the third column C3 is defined as a third pixel electrode, the first pixel electrode PE is defined as a second pixel electrode, The switching element TFT is connected between the second pixel electrode and the third pixel electrode.

8 except for the positions of the switching elements are the same as those of the liquid crystal display of FIG. 3 described above. Therefore, the description of the components shown in FIG. 8 will be omitted from FIGS. 1 to 6 and related description .

FIG. 9 is another diagram showing a part of a liquid crystal display device including a plurality of pixels PX having the structure shown in FIG.

Each of the plurality of pixels PX shown in Fig. 9 has the same structure as the pixel PX of Fig. 1 described above. That is, each pixel PX in Fig. 9 has the same plane and sectional structure as the pixel PX shown in Fig.

9, the interval d11 between the data lines DL1 and DL2 located on both sides of the pixel electrode PE is equal to the interval d11 between the data lines DL1 and DL2 located on both sides of the switching element TFT (d22). Due to this, the data lines DL1 to DL7 have a jig-jag shape.

9 is the same as the liquid crystal display of FIG. 8 except for the shape of the data line, the description of the components shown in FIG. 9 will be made with reference to FIG. 8 and the related description .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

DL1-DL7: first to seventh data lines
R1 to R6: first to sixth rows
C1-C6: first to sixth columns
PE: pixel electrode
TFT: switching element
GE: gate electrode
GL1-GL3: First to third gate lines
PX: Pixels
R: Red pixel
G: green pixel
B: blue pixel

Claims (19)

A liquid crystal layer disposed between the first substrate and the second substrate;
A plurality of gate lines and a plurality of data lines disposed on the first substrate;
A plurality of pixels connected to the plurality of gate lines and the plurality of data lines and having a pixel electrode and a switching element connected to the pixel electrode;
The pixel electrodes of one row among the odd-numbered rows and the even-numbered rows are located in odd-numbered columns;
And the pixel electrodes of the other row among the odd-numbered rows and the even-numbered rows are located in even-numbered columns. The method according to claim 1,
And the pixel electrodes of one row are not located between adjacent pixel electrodes of the other row. 3. The method of claim 2,
Wherein the pixel electrode includes a first pixel electrode positioned in one row, a second pixel electrode positioned in another row and adjacent to the first pixel electrode, a second pixel electrode positioned in another row, adjacent to the first pixel electrode, A third pixel electrode facing the first pixel electrode;
Wherein the first pixel electrode is located between imaginary extension lines extending from opposing sides of the second pixel electrode and the third pixel electrode. The method of claim 3,
The pixel electrode further includes a fourth pixel electrode adjacent to the first pixel electrode and the second pixel electrode and located in the one row;
Wherein the first pixel electrode is located between imaginary extension lines extending from opposite sides of the second pixel electrode and the fourth pixel electrode, respectively. The method according to claim 1,
Switching elements connected to each of the pixel electrodes in the (2k-1) -th row (k is a natural number), and pixel electrodes connected to the pixel electrodes in the 2k-th row are commonly connected to one gate line. The method according to claim 1,
And the switching element connected to the pixel electrode of the 2k-th row is located between the two pixel electrodes adjacent to the 2k-th row and adjacent to the 2k + 1-th row. The method according to claim 1,
And the switching element connected to the pixel electrode in the 2k-th row is located between the two pixel electrodes adjacent to the 2k-th row and located in the 2k-1-th row. The method according to claim 1,
The width of the pixel electrode located on one of the two adjacent rows is greater than or smaller than the distance between two pixel electrodes adjacent to the pixel electrode and located on another row. 9. The method of claim 8,
Wherein a part of the pixel electrodes located in one row is located between pixel electrodes in another row adjacent to the one row and pixel electrodes in another row adjacent to the one row. 10. The method of claim 9,
And the pixel electrodes of the other row and the pixel electrodes of the another row are located in the same column. The method according to claim 1,
An imaginary first line segment that connects each center of two adjacent pixel electrodes in one row and a second line segment that connects the center of one of the pixel electrodes adjacent to the two pixel electrodes to the center of one of the two pixel electrodes, And an interior angle formed by the imaginary second line segment is from 50 degrees to 55 degrees. The method according to claim 1,
Wherein an interval between data lines located at both sides of the pixel electrode is greater than an interval between data lines located at both sides of the switching device. The method according to claim 1,
Wherein the gate lines have a jig-jig shape. 14. The method of claim 13,
Wherein the data lines have a linear shape or a jig-jig shape. The method according to claim 1,
The pixel electrode is located in a pixel region of each pixel;
The switching element is located in a non-pixel region of each pixel;
And the ratio of the area of the pixel area to the area of the non-pixel area is 3: 7. The method according to claim 1,
Wherein two pixels adjacent to one row and one pixel adjacent to the two pixels and located in another row display different colors. 17. The method of claim 16,
And the three pixels are commonly connected to one gate line. The method according to claim 1,
Wherein each of the plurality of pixels further includes a connection electrode connecting the pixel electrode and the switching element. 19. The method of claim 18,
And the connection electrode is integrated with the pixel electrode or the source electrode of the switching element.

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