KR20170109137A

KR20170109137A - Liquid crystal display device

Info

Publication number: KR20170109137A
Application number: KR1020160032356A
Authority: KR
Inventors: 노정훈; 송근규; 이현섭; 전형일; 최병석
Original assignee: 삼성디스플레이 주식회사
Priority date: 2016-03-17
Filing date: 2016-03-17
Publication date: 2017-09-28

Abstract

The present invention relates to a liquid crystal display device capable of minimizing electric field interference and motion interference of liquid crystal molecules in adjacent pixels. The liquid crystal display device includes: a liquid crystal layer disposed between a first substrate and a second substrate; a plurality of gate lines and a plurality of data lines disposed on the first substrate; and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines and including pixel electrodes and switching elements connected to the pixel electrodes. The pixel electrodes of one row of the odd-numbered rows and the even-numbered rows are located in odd-numbered columns. The pixel electrodes of the other row of the odd-numbered rows and the even-numbered rows are located in even-numbered columns. The switching element of at least one pixel includes a gate electrode connected to the gate line, a drain electrode connected to the data line, and a source electrode connected to the pixel electrode. The pixel electrode of the at least one pixel overlaps with the drain electrode.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of minimizing electric field interference and motion interference of liquid crystal molecules in adjacent pixels.

2. Description of the Related Art A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPDs), and is composed of two substrates on which electrodes are formed and a liquid crystal layer sandwiched therebetween. A liquid crystal display device is a display device that adjusts the amount of light transmitted by applying voltages to two electrodes to rearrange the liquid crystal molecules in the liquid crystal layer.

The liquid crystal display device includes a plurality of pixels arranged in a matrix form. As the liquid crystal display device becomes larger, the interval between the pixels is further reduced. As a result, the electric fields generated in the pixels adjacent to each other can affect each other. Also, when the distance between the pixels is very close, the movement of the liquid crystal molecules in one pixel may affect the movement of the liquid crystal molecules in the adjacent pixels. As a result, the electric field of the pixel and the movement of the liquid crystal molecules may be distorted and the image quality may be deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of minimizing interference between an electric field and liquid crystal molecules between adjacent pixels.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a liquid crystal layer disposed between a first substrate and a second substrate; A plurality of gate lines and a plurality of data lines disposed on the first substrate; A plurality of pixels connected to the plurality of gate lines and the plurality of data lines and having switching elements connected to the pixel electrodes and the pixel electrodes; The pixel electrodes of one row among the odd-numbered rows and the even-numbered rows are located in odd-numbered columns; The pixel electrodes of the other row among the odd-numbered row and the even-numbered row are located in the even-numbered columns; The switching element of at least one of the pixels includes a gate electrode connected to the gate line, a drain electrode connected to the data line, and a source electrode connected to the pixel electrode; The pixel electrode of at least one pixel overlaps the drain electrode.

And a connection electrode connecting the pixel electrode and the source electrode of at least one pixel.

The connection electrode overlaps the gate electrode, the drain electrode, and the source electrode.

The distance between the pixel electrode and the data line of at least one pixel is smaller than the distance between the connecting electrode and the data line.

The connection electrode is formed integrally with the pixel electrode or the drain electrode.

The liquid crystal display further includes a light-shielding layer having openings corresponding to the pixel electrodes.

The pixel electrodes and the light shielding layer are located on the first substrate.

And a color filter disposed corresponding to the opening of the light shielding layer.

The pixel electrodes of one row are not located between the pixel electrodes of adjacent rows.

Wherein the pixel electrodes are arranged in a row, a first pixel electrode positioned in a row, a second pixel electrode positioned in another row and adjacent to the first pixel electrode, a second pixel electrode positioned in another row, adjacent to the first pixel electrode, A third pixel electrode facing the first pixel electrode; The first pixel electrode is located between imaginary extension lines extending from the opposite sides of the second pixel electrode and the third pixel electrode, respectively.

The pixel electrodes further include a first pixel electrode and a fourth pixel electrode adjacent to the second pixel electrode and located in the one row; The first pixel electrode is located between imaginary extension lines extending from opposite sides of the second pixel electrode and the fourth pixel electrode, respectively.

The switching element of at least one pixel comprises a semiconductor layer, wherein the semiconductor layer is made of indium-gallium-zinc-oxide (IGZO) or amorphous indium-gallium-zinc-oxide (a-IGZO; amorphous Indium-Gallium-Zinc-Oxide).

An imaginary first line segment connecting the center portions of two adjacent pixel electrodes in one row and a virtual first line segment connecting the central portion of the pixel electrode adjacent to the two pixel electrodes and the center portion of one of the two pixel electrodes, The second line segment has an interior angle of 50 to 55 degrees.

The liquid crystal display device according to the present invention provides the following effects.

The pixels of the liquid crystal display according to the present invention are adjacent to each other in the diagonal direction. Further, the pixel electrode of any one of the two adjacent rows is not located between the adjacent two pixel electrodes of the other row. As a result, the distances between the adjacent pixel electrodes are different from each other. Therefore, electric field interference between neighboring pixels and motion interference of liquid crystal molecules can be minimized.

1 is a plan view of one pixel according to one embodiment of the present invention.
2 is a sectional view taken along the line I-I 'in FIG.
FIG. 3 is a view showing a part of a liquid crystal display device including a plurality of pixels having a structure as shown in FIG.
FIG. 4 is a view showing only a few pixel electrodes located in a specific portion in FIG.
5 is a view for explaining the angle formed by three adjacent pixel electrodes.
6 is a plan view of the light-shielding film of FIG. 2. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures, and well-known techniques are not specifically described to avoid an undesirable interpretation of the present invention. Like reference numerals refer to like elements throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "below " another portion, it includes not only a case where it is" directly underneath "another portion but also another portion in between. Conversely, when a part is "directly underneath" another part, it means that there is no other part in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

In this specification, when a part is connected to another part, it includes not only a direct connection but also a case where the part is electrically connected with another part in between. Further, when a part includes an element, it does not exclude other elements unless specifically stated to the contrary, it may include other elements.

The terms first, second, third, etc. in this specification may be used to describe various components, but such components are not limited by these terms. The terms are used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second or third component, and similarly, the second or third component may be alternately named.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to FIGS. 1 to 6. FIG.

FIG. 1 is a plan view of one pixel according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line I-I 'of FIG.

1 and 2, the pixel PX includes a first substrate 301, a switching element (TFT), a light blocking film 265, a buffer layer 508, a semiconductor layer 321, a gate insulating film 511, a protective film 581, a color filter 354, an organic film 554, a capping layer 582, a connecting electrode 443, a pixel electrode PE, a light shielding layer 576, a column spacer 586, A liquid crystal layer 333, a second substrate 302, and a common electrode 330.

The pixel electrode PE is located in the pixel region 151 of the pixel PX and the switching element TFT is located in the non-pixel region 152 of the pixel PX. The pixel region 151 has a smaller area than the non-pixel region 152. For example, the ratio of the area of the pixel area 151 to the area of the non-pixel area 152 may be 3: 7.

The switching element TFT is connected to the gate line GL, the data line DL and the pixel electrode PE. To this end, the switching element TFT includes a gate electrode GE connected to the gate line GL, a drain electrode DE connected to the data line DL, and a source electrode connected to the pixel electrode PE And a semiconductor layer 321 to which the drain electrode DE and the source electrode SE are connected.

The semiconductor layer 321 includes a drain region 321a, a source region 321b, and a channel region 321c. 1, the channel region 321c is located between the drain region 321a and the source region 321b. 2, the channel region 321c is located between the gate electrode GE and the light shielding film 265. In addition, as shown in FIG. The drain region 321a is connected to the drain electrode DE and the source region 321b is connected to the source electrode SE.

The switching element (TFT) may include a thin film transistor (Thin Film Transistor).

A light shielding film 265, a buffer layer 508, a semiconductor layer 321, a gate insulating film 511, a protective film 581, a drain electrode DE, a source electrode SE, a color filter 354 The organic layer 554, the capping layer 582, the connecting electrode 443, the pixel electrode PE, the light shielding layer 576 and the column spacer 586 are located on the first substrate 301.

The common electrode 330 is located on the second substrate 302. Although not shown, the light shielding layer 576 and the column spacers 586 may be located on the second substrate 302. In this case, the light shielding layer 576 is located between the second substrate 302 and the common electrode 330.

The light blocking film 265 is located on the first substrate 301. Light from the backlight of the liquid crystal display device can be applied to the channel region 321c of the semiconductor layer 321 through the first substrate 301. [ Then, the channel region 321c of the semiconductor layer 321 is activated to cause a photo leakage. The light shielding film 265 prevents the light from the backlight from being applied to the channel region 321c of the semiconductor layer 321, thereby suppressing the occurrence of the above-described light leakage current. The light blocking film 265 may be made of a material such as a metal. On the other hand, although not shown, the light shielding film 265 can be further extended to the non-pixel region 152 where the source electrode SE and the source contact hole CH2 are overlapped with those SE and CH2.

The buffer layer 508 is located on the light blocking film 265 and the first substrate 301. The buffer layer 508 is located on the entire surface of the first substrate 301 including the light blocking film 265.

The buffer layer 508 may be made of silicon nitride (SiNx), silicon oxide (SiOx) or the like. The buffer layer 508 may have a multi-layer structure including at least two insulating layers having different physical properties.

The semiconductor layer 321 is located on the buffer layer 508. The semiconductor layer 321 includes a drain region 321a, a source region 321b and a channel region 321c. The channel region 321c overlaps with the light shielding film 265.

The semiconductor layer 321 may include indium-gallium-zinc-oxide (IGZO) or amorphous indium-gallium-zinc-oxide (a-IGZO) . The drain region and the source region of the semiconductor layer 321 each contain impurities. The impurity may be hydrogen (H ₂ ). The indium-gallium-zinc-oxide has high transparency and exhibits high electrical conductivity characteristics by implantation of impurities such as hydrogen. That is, when hydrogen is injected into the indium-gallium-zinc-oxide, the density of electrons which increase its electric conductivity increases. In addition, even if impurities such as hydrogen are implanted, the inherent transparency of the indium-gallium-zinc-oxide does not deteriorate. Therefore, although the source region 321b of the semiconductor layer 321 is located in the pixel region 151, the transmittance of the pixel region 151 is not substantially reduced. Alternatively, the semiconductor layer 321 may comprise amorphous silicon or polycrystalline silicon.

The gate insulating film 511 is located on the semiconductor layer 321 and the buffer layer 508 as shown in Fig. The gate insulating film 511 is located on the entire surface of the first substrate 301 including the semiconductor layer 321 and the buffer layer 508. The gate insulating film 511 has a drain contact hole CH1 located corresponding to the drain region 321a and a source contact hole CH2 located corresponding to the source region 321b.

The gate insulating film 511 may be made of silicon nitride (SiNx), silicon oxide (SiOx) or the like. The gate insulating film 511 may have a multi-film structure including at least two insulating layers having different physical properties.

The gate line GL and the gate electrode GE are located on the gate insulating film 511. [ At this time, the gate electrode GE overlaps the channel region 321c of the semiconductor layer 321. Thus, the channel region 321c is located between the gate electrode GE and the light shielding film 265. [

Although not shown, the gate insulating film 511 may have the same shape as the gate line GL and the gate electrode GE. For example, when an element including the gate line GL and the gate electrode GE is defined as a gate transfer portion, the gate insulating layer 511 may have the same shape as the gate transfer portion.

The gate line GL includes a plurality of gate electrodes GE. On the other hand, although not shown, the gate line GL can be connected to another layer or to an external driving circuit, for which the connecting portion of the gate line (for example, the end portion of the gate line) It can have a large area.

The gate line GL may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy or a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) Or a molybdenum series metal such as molybdenum (Mo) or molybdenum alloy. Alternatively, the gate line GL may be made of any one of chromium (Cr), tantalum (Ta), and titanium (Ti). On the other hand, the gate line GL may have a multi-film structure including at least two conductive films having different physical properties.

The gate electrode GE may have the same material and structure (multi-film structure) as the gate line GL. The gate electrode GE and the gate line GL can be formed simultaneously in the same process.

The protective film 581 is located on the gate insulating film 511 and the gate electrode GE, as shown in Fig. Although not shown, the protective film 581 is also located on the gate line GL. The protective film 581 is located on the entire surface of the first substrate including the gate insulating film 511, the gate electrode GE and the gate line GL.

The protective film 581 has a drain contact hole CH1 corresponding to the drain region 321a and a source contact hole CH2 located corresponding to the source region 321b.

The protective film 581 can be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the inorganic insulating material has photosensitivity and a dielectric constant of about 4.0 Can be used. Alternatively, the protective film 581 may have a bilayer structure of a lower inorganic film and an upper organic film. The thickness of the protective film 581 may be about 5000 ANGSTROM or more, and may be about 6000 ANGSTROM to about 8000 ANGSTROM.

The drain electrode DE is located on the drain region 321a of the semiconductor layer 321, as shown in Figs. And the drain electrode DE is connected to the drain region 321a through the drain contact hole CH1. On the other hand, the drain electrode DE may be further located on the protective film 581. [

The drain electrode DE may be made of a refractory metal such as molybdenum, chromium, tantalum, and titanium or an alloy thereof. The drain electrode DE may have a multi-film structure including a refractory metal film and a low-resistance conductive film. Examples of the multilayer structure include a double layer film of a chromium or molybdenum (or molybdenum alloy) lower film and an aluminum (or aluminum alloy) upper film, a lower film of molybdenum (or molybdenum alloy), an aluminum (or aluminum alloy) interlayer, molybdenum ) Triple layer of the upper layer. On the other hand, the drain electrode DE may be made of various other metals or conductors.

The data line DL is located on the protective film 581. The data line DL is formed integrally with the drain electrode DE. The data line DL may be made of the same material as the drain electrode DE described above.

The source electrode SE is located on the source region 321b of the semiconductor layer 321, as shown in Figs. The source electrode SE is connected to the source region 321b through the source contact hole CH2. On the other hand, the source electrode SE may be further disposed on the protective film 581. [ The source electrode SE may be made of the same material as the drain electrode DE described above.

The color filter 354 is located on the protective film 581 and the drain electrode DE, as shown in Fig. The edge of the color filter 354 is located on the data line DL. However, the color filter 354 is not located at the portion corresponding to the source contact hole CH2. On the other hand, the edge of the color filter 354 may overlap the edge of another color filter 354 adjacent thereto. The color filter 354 may be made of a photosensitive organic material.

The organic film 554 is located on the color filter 354. The organic film 554 may be made of a photosensitive organic material having a low dielectric constant. For example, the organic film 554 may be made of a photosensitive organic material having a lower dielectric constant than the protective film 581.

The capping layer 582 is located on the organic film 554, the color filter 354, the protective film 581 and the source electrode SE. The capping layer 582 has a source contact hole CH2 located corresponding to the source region 321b. The capping layer 582 may be made of silicon nitride, silicon oxide, or the like.

The pixel electrode PE is located on the capping layer 582 of the pixel region 151, as shown in Figs.

The pixel electrode PE may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). At this time, the ITO may be a polycrystalline or single crystal material. IZO may also be a polycrystalline or single crystal material. Alternatively, the IZO can be an amorphous material.

The connection electrode 443 is located on the capping layer 582. The connection electrode 443 extends from the pixel electrode PE to the non-pixel region 152. The connection electrode 443 is formed integrally with the pixel electrode PE. The connection electrode 443 is located in the pixel region 151 and the non-pixel region 152. The connection electrode 443 is connected to the source electrode SE through the source contact hole CH2 of the capping layer 582. [

The connection electrode 443 may be formed of the same material as the pixel electrode PE. The connection electrode 443 and the pixel electrode PE can be formed simultaneously in the same process. Alternatively, the connection electrode 443 may be formed of the same material as the source electrode SE. For example, the connection electrode 443 may be integrally formed with the source electrode SE. In this case, the connection electrode 443 is formed simultaneously with the same process as the source electrode SE. At this time, the connection electrode 443 is connected to the pixel electrode PE through a separate contact hole.

The gap between the pixel electrode PE and the data line DL is smaller than the gap between the connection electrode 443 and the data line DL. For example, in Fig. 1, a distance between a data line DL (data line on the right side of two data lines) connected to the pixel PX and a pixel electrode PE of the pixel PX is defined as d1 , And the distance between the data line DL and the connecting electrode 443 of the pixel PX is defined as d2, d1 is smaller than d2.

The light shielding layer 576 is located on the connection electrode 443, the pixel electrode PE and the capping layer 582, as shown in Fig. The light shielding layer 576 is located substantially at the remaining portion except for the pixel region 151.

The column spacer 586 is located on the light shielding layer 576, as shown in Fig. The column spacer 586 may be integrated with the light shielding layer 576.

The common electrode 330 is located on the second substrate 302. The common electrode 330 may be positioned on the entire surface of the second substrate 302. Alternatively, the common electrode 330 may be located on the second substrate 302 in correspondence with the pixel region 151. A common voltage is applied to the common electrode 330.

Meanwhile, although not shown, the pixel PX may further include a first polarizing plate and a second polarizing plate. When the opposing surfaces of the first substrate 301 and the second substrate 302 are defined as the upper surfaces of the corresponding substrates and the surfaces located on opposite sides of the upper surfaces are respectively defined as the lower surface of the substrate, The first polarizing plate is positioned on the lower surface of the first substrate 301 and the second polarizing plate is located on the lower surface of the second substrate 302.

The transmission axis of the first polarizing plate and the transmission axis of the second polarizing plate are orthogonal to each other. One of these transmission axes is arranged parallel to the gate line GL. On the other hand, the liquid crystal display device may include only one of the first polarizing plate and the second polarizing plate.

The first substrate 301 and the second substrate 302 are insulating substrates made of glass or plastic.

The liquid crystal layer 333 disposed between the first substrate 301 and the second substrate 302 includes liquid crystal molecules, and these liquid crystal molecules may be twisted nematic liquid crystal molecules.

FIG. 3 is another diagram showing a part of a liquid crystal display device including a plurality of pixels PX having the structure shown in FIG.

Each of the plurality of pixels PX shown in FIG. 3 has the same structure as the pixel PX of FIG. 1 described above. That is, each pixel PX in FIG. 3 has the same plane and sectional structure as the pixel PX shown in FIG.

The pixels PX in a specific column have a shape opposite to the pixels PX in the other column. For example, as shown in FIG. 3, the pixels PX of the even-numbered columns (any one of C2, C4 and C6) are connected to the pixels PX of the odd-numbered columns C1, As shown in FIG. For example, each of the pixels PX in the odd-numbered column has the same shape as the pixel PX shown in Fig. 1 described above, and each of the pixels PX in the even- Also has an inverted shape. Accordingly, the switching element (TFT) connected to the pixel electrode PE in the 2k-th row is located between the two pixel electrodes PE located in the 2k-1-th row and adjacent to the pixel electrode in the 2k-th row do. 3, the pixel electrode PE located in the second row R2 and the second column C2 is defined as the first pixel electrode, and the first row R1 and the first column C1 are defined as the first pixel electrode, And the pixel electrode PE located in the first row R1 and the third column C3 is defined as a third pixel electrode, the first pixel electrode PE is defined as a second pixel electrode, The switching element TFT is connected between the second pixel electrode and the third pixel electrode.

(TFTs) connected to each of the pixel electrodes PE in the (2k-1) th row and the switching elements (TFTs) connected to the pixel electrodes PE in the 2k-th row are common to one gate line Lt; / RTI > 3, the switching elements (TFTs) connected to the pixel electrodes PE of the first row R1 and the pixel electrodes PE of the second row R2, for example, The switching elements (TFT) connected to each of the gate lines GL1 and GL2 are commonly connected to the first gate line GL1. The first gate line GL1 includes a plurality of gate electrodes GE connected to each other and the odd gate electrodes GE include a switching element TFT for driving the pixel electrodes PE of the first row R1, And the even gate electrodes GE are connected to the respective switching elements TFTs driving the pixel electrodes PE of the second row R2.

The pixel electrodes PE belonging to the odd-numbered rows (one of R1, R3, and R5) are located in the even-numbered columns C2, C2, and C6. In other words, the pixel electrodes PE arranged along the odd-numbered rows are located between the 2x-th (n is a natural number) data line and the 2x-th data line. For example, as shown in FIG. 3, the pixel electrodes PE belonging to the first row R1 are located in the second column C2, the fourth column C4, and the sixth column C6, respectively . In other words, the pixel electrodes PE arranged along the first row R1 are arranged between the first data line DL1 and the second data line DL2, between the third data line DL3 and the fourth data line DL3, DL4 and the fifth data line DL5 and the sixth data line DL6, respectively.

The pixel electrodes PE belonging to the even-numbered rows (any one of R2, R4, and R6) are located in the odd-numbered columns C1, C3, and C5. In other words, the pixel electrodes PE arranged along the even-numbered rows are located between the 2xth data line and the 2x + 1th data line. For example, as shown in FIG. 3, the pixel electrodes PE belonging to the second row R2 are located in the first column C1, the third column C3 and the fifth column C5, respectively . In other words, the pixel electrodes PE arranged along the second row R2 are connected between the second data line DL2 and the third data line DL3, the fourth data line DL4 and the fifth data line DL4, DL5, and between the sixth data line DL6 and the seventh data line, respectively. However, the pixel electrode located at the outermost one of the pixel electrodes PE of the even-numbered row is located between the first data line DL1 and the edge of the first substrate 301. [

Although not shown, the pixel electrodes PE belonging to the odd-numbered rows (one of R1, R3 and R5) are located in the odd-numbered columns C1, C3 and C5 and the even- The pixel electrodes PE belonging to the even-numbered columns C2, C4, and C6 may be located. In this case, the pixel electrodes PE arranged along the odd-numbered row are located between the 2x-th data line and the 2x + 1-th data line, and the pixel electrodes PE arranged along the even- And is located between the data line and the 2x-th data line.

Each pixel PX is connected to one of the data lines on both sides. For example, as shown in Fig. 3, each pixel PX may be connected to a data line located on its right side. The pixel PX is connected to the data line through the switching element TFT.

The pixel electrode PE of any one of the adjacent two rows is not located between the adjacent two pixel electrodes PE of the other row. For example, in FIG. 3, the pixel electrodes located in the second row R2 and the fifth column C5 are defined as the first pixel electrodes, and the pixels located in the first row R1 and the fourth column C4 When the pixel electrode defined as the second pixel electrode and the pixel electrode located in the third row R3 and the fourth column C4 are defined as the third pixel electrode, any portion of the first pixel electrode is defined as the second pixel electrode, And is not located between the third pixel electrodes.

Since the adjacent pixel electrodes PE are adjacent to each other in the diagonal direction and the pixel electrodes of any one of the two adjacent rows are not located between the adjacent two pixel electrodes of the other row, The distance between the pixel electrodes is increased. Therefore, the movement of the electric field and the liquid crystal molecules in one pixel hardly affects the electric field of the other pixels adjacent to the pixel and the movement of the liquid crystal molecules.

In FIG. 3, the reference character R on the pixel electrode PE means that the pixel PX including the pixel electrode PE is a red pixel R indicating red color, G indicates that the pixel PX including the pixel electrode PE is a green pixel G indicating green and the reference B indicated on the pixel electrode PE includes the pixel electrode PE And the pixel PX is a blue pixel B that displays blue. Three pixels PX connected in common to one gate line and adjacent to each other constitute one main pixel. For example, in FIG. 3, a red pixel R, a green pixel G and a blue pixel B, which are commonly connected to the first gate line GL1 and are adjacent to each other, constitute one main pixel.

Meanwhile, the first pixel electrode may be located in a region defined as follows, which will be described in detail with reference to FIG.

FIG. 4 is a view showing only a few pixel electrodes PE located at a specific portion in FIG.

4, a pixel electrode PE located in a second row R2 and a fifth column C5 is defined as a first pixel electrode PE1, and a pixel electrode PE1 adjacent to the first pixel electrode PE1 Four pixel electrodes PE located in two rows are defined as second, third, fourth and fifth pixel electrodes PE2, PE3, PE4 and PE5, respectively. That is, the pixel electrode PE located in the first row R1 and the fourth column C4 is referred to as the second pixel electrode PE2 and the pixel electrode PE located in the third row R3 and the fourth column C4 PE to the third pixel electrode PE3 and the pixel electrode PE located in the first row R1 and the sixth column C6 to the fourth pixel electrode PE4 and in the third row R3 and And the pixel electrode PE located in the sixth column C6 is defined as a fifth pixel electrode PE5.

At this time, a virtual extension line extending from one side (the side of the second pixel electrode) of the opposite sides of the second pixel electrode PE2 and the third pixel electrode PE3 is defined as a first straight line VL1 , And an imaginary extension line extending from the other side (the side of the third pixel electrode) is defined as a second straight line VL2. An imaginary extension line extending from one side of the opposing sides of the second pixel electrode PE2 and the fourth pixel electrode PE4 (the side of the second pixel electrode PE2) is referred to as a third straight line VL3. And a virtual extension line extending from the other side (the side of the fourth pixel electrode PE4) is defined as a fourth straight line VL4.

At this time, the first pixel electrode PE1 is located between the first straight line VL1 and the second straight line VL2 described above. In this case, the first pixel electrode PE1 is not located between the second pixel electrode PE2 and the third pixel electrode PE3. Also, the first pixel electrode PE1 is not located between the fourth pixel electrode PE4 and the fifth pixel electrode PE5.

The first pixel electrode PE1 may be positioned between the first straight line VL1 and the second straight line VL2 described above and between the third straight line VL3 and the fourth straight line VL4 described above. That is, the first pixel electrode PE1 may be located within the defined region 444 surrounded by the first, second, third and fourth straight lines VL1, VL2, VL3, VL4. In this case, the first pixel electrode PE1 is not located between the second pixel electrode PE2 and the fourth pixel electrode PE4. Also, the first pixel electrode PE1 is not located between the third pixel electrode PE3 and the fifth pixel electrode PE5.

The width of the pixel electrode PE located on any one of the two adjacent rows may be smaller than the distance between the two pixel electrodes PE located on the other row adjacent to the pixel electrode PE. For example, as shown in FIG. 4, the width W1 of the first pixel electrode PE1 may be smaller than the distance D1 between the second pixel electrode PE2 and the third pixel electrode PE3 .

5 is a view for explaining the angle formed by three adjacent pixel electrodes.

A virtual line segment connecting each center of two adjacent pixel electrodes in a row is defined as a first line segment and a center line of the pixel electrode adjacent to the two pixel electrodes and a center portion of the two pixel electrodes When defining a line segment connecting a center portion of one of them to a second line segment, an interior angle formed by the first line segment and the second line segment is from 50 degrees to 55 degrees. 5, a first line segment VL11 connecting the center portion CP2 of the second pixel electrode PE2 and the center portion CP3 of the third pixel electrode PE3, The inner angle? 1 formed by the second line segment VL22 connecting the center portion CP2 of the electrode PE2 and the center portion CP1 of the first pixel electrode PE1 is 50 degrees to 55 degrees. For example,? 1 may be 52 degrees.

On the other hand, the angle? 2 (? 2) between the imaginary straight line VL33 passing through the center portion CP1 of the first pixel electrode PE1 and perpendicular to the data line DL3, for example, ) May be between 50 and 55 degrees. For example, &thetas; 2 may be 52 degrees. If the first line segment VL11 and the straight line VL33 are parallel,? 1 and? 2 are the same.

6 is a plan view of the light-shielding film of FIG. 2. FIG.

The light shielding layer 576 includes a plurality of openings 576a, as shown in Fig. The size of the opening 576a may be equal to or smaller than the size of the pixel region 151. [

The openings 576a are located corresponding to the pixel electrodes PE. Therefore, the openings 576a belonging to the odd-numbered rows (one of R1, R3, and R5) are located in the even-numbered columns C2, C2, and C6. In other words, the openings 576a arranged along the odd-numbered rows are located between the 2x-1th (x is a natural number) data line and the 2xth data line. For example, as shown in Fig. 6, the openings 576a belonging to the first row R1 are located in the second column C2, the fourth column C4 and the sixth column C6, respectively. In other words, the openings 576a arranged along the first row R1 are connected between the first data line DL1 and the second data line DL2, between the third data line DL3 and the fourth data line DL4 , And between the fifth data line DL5 and the sixth data line DL6, respectively.

The openings 576a belonging to the even-numbered rows (any one of R2, R4, and R6) are located in the odd-numbered columns C1, C3, and C5. In other words, the openings 576a arranged along the even-numbered row are located between the 2xth data line and the 2x + 1th data line. For example, as shown in Fig. 6, the openings 576a belonging to the second row R2 are located in the first column C1, the third column C3 and the fifth column C5, respectively. In other words, the openings 576a arranged along the second row R2 are connected between the second data line DL2 and the third data line DL3, the fourth data line DL4 and the fifth data line DL5 , And between the sixth data line DL6 and the seventh data line, respectively. However, the pixel electrode located at the outermost one of the openings 576a of the even-numbered row is located between the first data line DL1 and the edge of the first substrate 301. [

Although not shown, the openings 576a belonging to the odd-numbered rows (one of R1, R3 and R5) are located in the odd-numbered columns C1, C3 and C5 and the even- The corresponding openings 576a may be located in the even-numbered columns C2, C4, and C6. In this case, the openings 576a arranged along the odd-numbered rows are located between the 2x-th data lines and the 2x + 1-th data lines, and the openings 576a arranged along the even- And the 2xth data line.

The opening 576a of any one row of adjacent two rows is not located between adjacent two openings 576a of the other row. 6, openings located in the second row R2 and the fifth column C5 are defined as the first openings, and openings located in the first row R1 and the fourth column C4 are defined as the first openings, 2 openings, and the openings located in the third row R3 and the fourth column C4 are defined as the third openings, no part of the first openings is located between the second openings and the third openings .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

DL1-DL6: First to sixth data lines
R1 to R6: first to sixth rows
C1-C6: first to sixth columns
PE: pixel electrode
TFT: switching element
GE: gate electrode
GL1-GL3: First to third gate lines
PX: Pixels
R: Red pixel
G: green pixel
B: blue pixel

Claims

A liquid crystal layer disposed between the first substrate and the second substrate;
A plurality of gate lines and a plurality of data lines disposed on the first substrate;
A plurality of pixels connected to the plurality of gate lines and the plurality of data lines and having a pixel electrode and a switching element connected to the pixel electrode;
The pixel electrodes of one row among the odd-numbered rows and the even-numbered rows are located in odd-numbered columns;
The pixel electrodes of the other row among the odd-numbered rows and the even-numbered rows are located in the even-numbered columns;
The switching element of at least one of the pixels includes a gate electrode connected to the gate line, a drain electrode connected to the data line, and a source electrode connected to the pixel electrode;
And the pixel electrode of the at least one pixel overlaps the drain electrode.

The method according to claim 1,
And a connection electrode connecting the pixel electrode of the at least one pixel and the source electrode.

3. The method of claim 2,
And the connection electrode overlaps the gate electrode, the drain electrode, and the source electrode.

3. The method of claim 2,
Wherein an interval between the pixel electrode of the at least one pixel and the data line is smaller than an interval between the connection electrode and the data line.

3. The method of claim 2,
And the connection electrode is integrated with the pixel electrode or the drain electrode.

The method according to claim 1,
And a light shielding layer having openings corresponding to the pixel electrodes.

The method according to claim 6,
Wherein the pixel electrodes and the light shielding layer are disposed on the first substrate.

The method according to claim 6,
And a color filter disposed corresponding to the opening of the light shielding layer.

The method according to claim 1,
And the pixel electrodes of one row are not located between adjacent pixel electrodes of the other row.

10. The method of claim 9,
Wherein the pixel electrodes are arranged in a row, a first pixel electrode positioned in a row, a second pixel electrode positioned in another row and adjacent to the first pixel electrode, a second pixel electrode positioned in another row, adjacent to the first pixel electrode, A third pixel electrode facing the first pixel electrode;
Wherein the first pixel electrode is located between imaginary extension lines extending from opposing sides of the second pixel electrode and the third pixel electrode.

11. The method of claim 10,
The pixel electrodes further include a fourth pixel electrode adjacent to the first pixel electrode and the second pixel electrode and positioned in the one row;
Wherein the first pixel electrode is located between imaginary extension lines extending from opposite sides of the second pixel electrode and the fourth pixel electrode, respectively.

The method according to claim 1,
The switching element of at least one pixel comprises a semiconductor layer, wherein the semiconductor layer is made of indium-gallium-zinc-oxide (IGZO) or amorphous indium-gallium-zinc-oxide (a-IGZO; amorphous Indium-Gallium-Zinc-Oxide).

The method according to claim 1,
An imaginary first line segment that connects each center of two adjacent pixel electrodes in one row and a second line segment that connects the center of one of the pixel electrodes adjacent to the two pixel electrodes to the center of one of the two pixel electrodes, And an interior angle formed by the imaginary second line segment is from 50 degrees to 55 degrees.