KR20170043979A - Three Dimensional Semiconductor Memory Devices - Google Patents

Abstract

A three dimensional semiconductor memory device comprises: a lower and an upper selection line layered on a substrate in a first direction perpendicular to an upper surface of the substrate; a cell gate structure which is provided between the lower and the upper selection line, and includes cell gate electrodes layered in the first direction; a lower dummy structure which is provided between the lower selection line and the cell gate structure, and includes a lower dummy gate line separated from a lowermost cell gate electrode among the cell gate electrodes in the first direction by a first distance; and an upper dummy structure which is provided between the upper selection line and the cell gate structure, and includes an upper dummy gate line separated from an uppermost cell gate electrode among the cell gate electrodes in the first direction by a second distance. The cell gate electrodes are separated from each other in the first direction by a third distance. The first and the second distance are larger than the third distance.

Description

[0001] The present invention relates to a three-dimensional semiconductor memory device,

The present invention relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device having three-dimensionally arranged memory cells.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor devices, the degree of integration is an important factor in determining the price of the product, and therefore, an increased degree of integration is required in particular. In the case of a conventional two-dimensional or planar semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern forming technique. However, the integration of the two-dimensional semiconductor device is increasing, but it is still limited, because the ultrafast equipment is required for the miniaturization of the pattern.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, there is a demand for a process technology capable of reducing the manufacturing cost per bit compared to that of the two-dimensional semiconductor device and realizing reliable product characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensional semiconductor memory device with improved electrical characteristics.

Another object of the present invention is to provide a three-dimensional semiconductor memory device having excellent reliability.

A three-dimensional semiconductor memory device according to the present invention includes: a lower select line and an upper select line stacked in a first direction perpendicular to an upper surface of the substrate; a lower select line provided between the lower select line and the upper select line, And cell gate electrodes stacked in the first direction. A lower dummy gate line provided between the lower select line and the cell gate structure and spaced a first distance from the lowest cell gate electrode of the cell gate electrodes along the first direction; And an upper dummy gate line provided between the upper select line and the cell gate structure and spaced a second distance from the uppermost cell gate electrode of the cell gate electrodes along the first direction can do. The lower dummy gate line and the upper dummy gate line may be directly adjacent to the cell gate electrode of the lowest layer and the cell gate electrode of the uppermost layer, respectively. The cell gate electrodes may be spaced apart from each other by a third distance along the first direction, and the first distance and the second distance may be greater than the third distance, respectively.

According to one embodiment, the upper dummy structure may include a plurality of upper dummy gate lines stacked in the first direction. The upper dummy gate line may be the lowest dummy gate line among the plurality of upper dummy gate lines.

According to one embodiment, the plurality of upper dummy gate lines may be spaced apart from each other by the second distance along the first direction.

According to one embodiment, the upper select line may be spaced a fourth distance from the upper dummy gate line of the uppermost one of the plurality of the upper dummy gate lines along the first direction. The fourth distance may be greater than the second distance.

According to an embodiment, the upper select line may be provided in a plurality, and a plurality of the upper select lines may be stacked in the first direction on the upper dummy structure. The lowest selected upper select line of the plurality of upper select lines may be spaced from the uppermost upper dummy gate line by the fourth distance.

According to an embodiment, the lower dummy structure may include a plurality of lower dummy gate lines stacked in the first direction. The lower dummy gate line may be the uppermost dummy gate line among the plurality of the lower dummy gate lines.

According to one embodiment, the plurality of lower dummy gate lines may be spaced apart from each other by the first distance along the first direction.

According to one embodiment, the lower select line may be spaced a fifth distance from the lower one of the plurality of the lower dummy gate lines along the first direction from the lower dummy gate line. The fifth distance may be greater than the first distance.

According to one embodiment, the fifth distance may be greater than the fourth distance.

According to one embodiment, the first distance and the second distance may be equal to each other.

According to an embodiment, the lower selection line, the upper selection line, the cell gate structure, the lower dummy structure, and the upper dummy structure may be defined as a laminated structure. The stacked structure may extend in a second direction parallel to the upper surface of the substrate.

The three-dimensional semiconductor memory device according to the present invention may further include a channel structure that is connected to the substrate through the stacked structure.

According to one embodiment, the channel structure may include a lower semiconductor pattern passing through at least a portion of the substrate, and an upper semiconductor pattern spaced apart from the substrate across the lower semiconductor pattern. The lower dummy structure may include a plurality of lower dummy gate lines stacked in the first direction, and the lower dummy gate line may be a lower dummy gate line of the uppermost one of the plurality of the lower dummy gate lines. The upper surface of the lower semiconductor pattern may be located at a height between the upper surface of the lower selected line and the lower surface of the lower dummy gate line of the plurality of the lower dummy gate lines.

According to one embodiment, the upper semiconductor pattern includes a first semiconductor pattern covering the inner wall of the laminated structure and spaced apart from the lower semiconductor pattern, and a second semiconductor pattern covering the inner wall of the first semiconductor pattern, . ≪ / RTI >

The three-dimensional semiconductor memory device according to the present invention may further include insulating films provided in the laminated structure and extending in the second direction, and a lower insulating film interposed between the substrate and the laminated structure. The upper select line, the upper dummy structure, the cell gate structure, the lower dummy structure, and the lower select line may be separated from each other by the insulating films interposed therebetween. Each of the insulating films and the lower insulating film has a thickness along the first direction, and the lower insulating film has a thickness thinner than the insulating films.

A three-dimensional semiconductor memory device according to the present invention includes a first selection line on a substrate, a plurality of cell gate electrodes provided between the substrate and the first selection line and stacked in a first direction perpendicular to an upper surface of the substrate, And a first dummy structure provided between the first select line and the cell gate structure and including at least one first dummy gate line. The plurality of cell gate electrodes are separated from each other by first insulating films interposed therebetween, and the first dummy structure and the cell gate structure can be separated from each other by a second insulating film interposed therebetween. Each of the first insulating films and the second insulating film has a thickness along the first direction, and the second insulating film has a thickness larger than that of the first insulating films.

According to one embodiment, the first select line and the first dummy structure may be separated from each other by a third insulating film interposed therebetween. The third insulating layer may have a thickness along the first direction, and the third insulating layer may have a thickness larger than that of the second insulating layer.

A three-dimensional semiconductor memory device according to the present invention includes a second select line between the substrate and the cell gate structure, and at least one second dummy word line provided between the second select line and the cell gate structure And the second dummy structure. The second dummy structure and the cell gate structure may be separated from each other by a fourth insulating film interposed therebetween. The fourth insulating layer may have a thickness in the first direction, and the fourth insulating layer may have a thickness larger than that of the first insulating layers.

According to one embodiment, the second select line and the second dummy structure may be separated from each other by a fifth insulating film interposed therebetween. The fifth insulating layer may have a thickness along the first direction, and the fifth insulating layer may have a thickness larger than that of the fourth insulating layer.

According to an exemplary embodiment, the fifth insulating layer may have a thickness greater than that of the third insulating layer.

According to an embodiment, the second insulating layer may have the same thickness as the fourth insulating layer.

According to an embodiment, the first dummy structure includes a plurality of first dummy gate lines stacked in the first direction, and the plurality of first dummy gate lines are separated from each other by insulating films interposed therebetween . Each of the insulating films between the plurality of first dummy gate lines has a thickness along the first direction and may have the same thickness as the second insulating film.

According to one embodiment, the second dummy structure includes a plurality of second dummy gate lines stacked in the first direction, and the plurality of second dummy gate lines are separated from each other by insulating films interposed therebetween . Each of the insulating films between the plurality of second dummy gate lines has a thickness along the first direction and may have the same thickness as the fourth insulating film.

According to one embodiment, the first select line, the second select line, the cell gate structure, the first dummy structure, and the second dummy structure may be defined as a laminated structure. The stacked structure may extend in a second direction parallel to the upper surface of the substrate.

The three-dimensional semiconductor memory device according to the present invention may further include a channel structure that is connected to the substrate through the stacked structure.

According to the concept of the present invention, electrical interference between the selection line and the adjacent cell gate electrode can be minimized. Thereby, a three-dimensional semiconductor memory device with improved electrical characteristics and excellent reliability can be provided.

1 is a schematic block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.
2 is a schematic circuit diagram of a three-dimensional semiconductor memory device according to some embodiments of the present invention.
3 is a perspective view of a three-dimensional semiconductor memory device according to some embodiments of the present invention.
FIG. 4 is a sectional view of the three-dimensional semiconductor memory device according to some embodiments of the present invention, taken along the direction of D1 and D3 in FIG.
5 is a perspective view for explaining the laminated structure SS of FIG. 3 in detail.
6 is an enlarged view of a portion A in Fig.
FIGS. 7 to 12 are views for explaining a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the present invention, and are cross-sectional views along the directions of D1 and D3 in FIG.
13 is a simplified circuit diagram of a three-dimensional semiconductor memory device according to another embodiment of the present invention.
14 is a cross-sectional view of a three-dimensional semiconductor memory device according to another embodiment of the present invention.
15 to 18 are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a three-dimensional semiconductor memory device may include a memory cell array 1, a row decoder 2, a page buffer 3, and a column decoder 4.

The memory cell array 1 may include a plurality of memory blocks BLK0 to BLKn, which are data erase units. Each of the memory blocks BLK0 to BLKn may include a plurality of memory cells, and a plurality of word lines and a plurality of bit lines electrically connected to the memory cells. The memory cell array 1 will be described in detail with reference to FIG.

The row decoder 2 may decode an externally input address to select any one of the word lines. The row decoder 2 is commonly connected to the plurality of memory blocks BLK0 to BLKn and may provide a driving signal to word lines of selected memory blocks BLK0 to BLKn according to a block selection signal have. The row decoder 2 may provide a word line voltage generated from a voltage generating circuit (not shown) to selected word lines and unselected word lines, respectively, in response to control of a control circuit (not shown).

The page buffer 3 may temporarily store data to be stored in the memory cells or sense data stored in the memory cells according to an operation mode. The page buffer 3 may operate as a write driver circuit in a program operation mode and as a sense amplifier circuit in a read operation mode.

According to one embodiment, the page buffer 3 may read data from the memory cell array 1 via first bit lines and write data to the memory cell array 1 via second bit lines Can be written.

The column decoder 4 may decode an externally input address to select any one of the bit lines. The column decoder 4 is commonly connected to the plurality of memory blocks BLK0 to BLKn and may provide data information to the bit lines of the selected memory blocks BLK0 to BLKn according to a block select signal. The column decoder 4 may provide a data transmission path between the page buffer 3 and an external device (for example, a memory controller).

2 is a schematic circuit diagram of a three-dimensional semiconductor memory device according to some embodiments of the present invention.

2, a cell array of a three-dimensional semiconductor memory device includes a common source line CSL, a plurality of bit lines BL, and a plurality of bit lines BL arranged between the common source line CSL and the bit lines BL. And a plurality of cell strings CSTR.

The common source line CSL may be an electrically conductive thin film disposed on the substrate or an impurity region formed in the substrate. The bit lines BL may be conductive patterns (e.g., metal lines) spaced from the substrate and disposed on the substrate. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of the cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CSL. According to one embodiment, the common source lines CSL are provided in plural and can be arranged two-dimensionally. Here, electrically the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, And a plurality of memory cell transistors MCT disposed between the memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, a ground selection line GSL, a plurality of word lines WL0-WL2, and a string selection line SSL, which are disposed between the common source line CSL and the bit lines BL, Can be used as gate electrodes of the ground selection transistor (GST), the memory cell transistors (MCT), and the string selection transistor (SST), respectively. In addition, each of the memory cell transistors MCT may include a data storage element.

Each of the cell strings CSTR may include at least one lower dummy cell transistor DCT0 between the ground selection transistor GST and the immediately adjacent memory cell transistor MCT. The lower dummy cell transistor DCT0 may be configured the same as the memory cell transistors MCT. At least one lower dummy word line DWL0 may be provided between the ground selection line GSL and the immediately adjacent word line WL0 and may be connected to the at least one lower dummy cell transistor DCT0 . In addition, each of the cell strings CSTR may include at least one upper dummy cell transistor DCT1 between the string selection transistor SST and the immediately adjacent memory cell transistor MCT. The upper dummy cell transistor DCT1 may be the same as the memory cell transistors MCT. At least one upper dummy word line DWL1 may be provided between the string selection line SSL and immediately adjacent word line WL2 and may be coupled to the at least one upper dummy cell transistor DCT1 . During the program operation, a dummy pass voltage may be applied to the lower dummy word line DWL0 and the upper dummy word line DWL1, and the dummy pass voltage may be applied to the word lines WL0- .

3 is a perspective view of a three-dimensional semiconductor memory device according to some embodiments of the present invention. FIG. 4 is a cross-sectional view of the three-dimensional semiconductor memory device according to some embodiments of the present invention, taken along the direction D1 and D3 of FIG. 3; 5 is a perspective view for explaining the laminated structure SS of FIG. 3 in detail. 6 is an enlarged view of a portion A in Fig.

Referring to FIGS. 3, 4, and 5, insulating films 110 and gate lines are alternately formed on a substrate 100 along a first direction D1 perpendicular to an upper surface of the substrate 100 Can be repeatedly stacked. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

The gate lines may include a lower select line 150G and an upper select line 150S stacked on the substrate 100 in the first direction D1. According to one embodiment, the upper select line 150S may be provided in plurality and the plurality of upper select lines 150S may be stacked in the first direction D1 on the lower select line 150G. . The lower selection line 150G may constitute the ground selection line GSL described with reference to FIG. 2, and the plurality of the upper selection lines 150S may be commonly connected to one conductive line , The string selection line (SSL) described with reference to Fig. 2 can be configured.

The gate lines may be provided between the lower selection line 150G and the upper selection line 150S and may include the cell gate electrodes 150 stacked in the first direction D1. The cell gate electrodes 150 stacked on the substrate 100 may be defined as a cell gate structure CGS. The cell gate structure CGS may be formed between the lower selection line 150G and the uppermost selection line 150S of the plurality of the upper selection lines 150S when the upper selection lines 150S are provided in plural, As shown in FIG. The cell gate electrodes 150 may respectively constitute the word lines WL0 to WL2 described with reference to FIG.

The gate lines may include at least one lower dummy gate line 150LD provided between the lower select line 150G and the cell gate structure CGS. Accordingly, a lower dummy structure LDS including the at least one lower dummy gate line 150LD may be defined between the lower selection line 150G and the cell gate structure CGS. The lower dummy gate line 150LD may constitute the lower dummy word line DWL0 described with reference to FIG. According to one embodiment, the lower dummy structure LDS may include a plurality of lower dummy gate lines 150LD, and the plurality of lower dummy gate lines 150LD may include a lower select line 150G, And the cell gate structure CGS in the first direction D1.

The gate lines may include at least one upper dummy gate line 150UD provided between the upper select line 150S and the cell gate structure CGS. Accordingly, an upper dummy structure UDS including the at least one upper dummy gate line 150UD may be defined between the upper select line 150S and the cell gate structure CGS. The upper dummy gate line 150UD may constitute the upper dummy word line DWL1 described with reference to FIG. According to one embodiment, the upper dummy structure UDS may include a plurality of upper dummy gate lines 150UD, and the plurality of upper dummy gate lines 150UP may include the cell gate structure CGS. And the upper select line 150S in the first direction D1. The upper dummy structure UDS may be formed between the upper select line 150S of the lowest layer among the plurality of the upper select lines 150S and the cell gate structure CGS when a plurality of the upper select lines 150S are provided, As shown in FIG.

The lower selection line 150G, the lower dummy structure LDS, the cell gate structure CGS, the upper dummy structure UDS, and the upper dummy structure UDS, which are sequentially stacked in the first direction D1 on the substrate 100, And the upper select line 150S may be defined as a stacked structure SS. The stacked structure SS may extend in a second direction D2 parallel to the upper surface of the substrate 100. [ The plurality of stacked structures SS may be provided on the substrate 100 and the plurality of stacked structures SS may be parallel to the upper surface of the substrate 100 and may extend in the second direction D2 And may be spaced from each other in a third direction D3 that intersects.

5, the lower dummy structure LDS extends from the lowest cell gate electrode 150 of the cell gate electrodes 150 along a first distance d1 along the first direction D1, And a lower dummy gate line 150LD spaced apart from the lower dummy gate line 150LD. When the lower dummy structure LDS includes the plurality of the lower dummy gate lines 150LD, the uppermost lower dummy gate line 150LD among the plurality of the lower dummy gate lines 150LD is connected to the lowermost May be spaced apart from the cell gate electrode 150 of the first region 150 by the first distance d1. In addition, the plurality of the lower dummy gate lines 150LD may be spaced apart from each other at the first distance d1 along the first direction D1.

The upper dummy structure UDS includes upper dummy gate lines 150UD spaced apart from the uppermost cell gate electrode 150 of the cell gate electrodes 150 by a second distance d2 along the first direction D1. ). When the upper dummy structure UDS includes the plurality of upper dummy gate lines 150UD, the uppermost dummy gate line 150UD of the lower one of the plurality of upper dummy gate lines 150UD is connected to the uppermost May be spaced apart from the cell gate electrode 150 of the second distance d2. In addition, the plurality of upper dummy gate lines 150UD may be spaced apart from each other at the second distance d2 along the first direction D1.

The cell gate electrodes 150 may be spaced apart from each other by a third distance d3 along the first direction D1. The first distance d1 and the second distance d2 may be greater than the third distance d3, respectively. According to one embodiment, the first distance d1 and the second distance d2 may be substantially equal to each other.

The upper select line 150S may be spaced from the upper dummy gate line 150UD immediately adjacent thereto by a fourth distance d4 along the first direction D1. When a plurality of the upper select lines 150S are provided, the upper select line 150S of the lowest layer among the plurality of the upper select lines 150S is connected to the fourth dummy gate line 150UD immediately adjacent thereto, (d4). When the upper dummy structure UDS includes the plurality of upper dummy gate lines 150UD, the upper dummy gate line 150UD of the uppermost one of the plurality of upper dummy gate lines 150UD is directly connected to the upper dummy gate line 150UD. And may be spaced from the adjacent upper select line 150S by the fourth distance d4. According to one embodiment, as shown in the figure, the upper select line 150S and the upper dummy gate line 150UD may be provided in plural, The selection line 150S may be spaced apart from the uppermost dummy gate line 150UD of the plurality of the upper dummy gate lines 150UD by the fourth distance d4. The fourth distance d4 may be greater than the second distance d2. Accordingly, the interval between the gate lines may increase as the cell gate structure CGS is transferred to the upper selection line 150S.

The lower select line 150G may be spaced from the lower dummy gate line 150LD immediately adjacent thereto by a fifth distance d5 along the first direction D1. When the lower dummy structure LDS includes the plurality of the lower dummy gate lines 150LD, the lower selection line 150G includes a lower dummy gate line 150LD among the plurality of the lower dummy gate lines 150LD, And may be spaced from the gate line 150LD by the fifth distance d5. The fifth distance d5 may be greater than the first distance d1. Accordingly, the gap between the gate lines may be increased from the cell gate structure CGS to the lower selection line 150G. The fifth distance d5 may be greater than the fourth distance d4.

3, 4, and 5, the gate lines may be separated from each other by the insulating films 110 interposed therebetween. The insulating films 110 may extend in the second direction D2 along the gate lines. The insulating films 110 may include at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, for example. The gate lines may include, for example, a monocrystalline or polycrystalline silicon or may comprise a metal and a conductive metal nitride.

4, the cell gate structure CGS and the lower dummy structure LDS may be separated from each other by a first insulating film 110a interposed therebetween, and the cell gate structure CGS and the upper dummy structure UDS may be separated from each other by a second insulating film 110b interposed therebetween. The cell gate electrodes 150 may be separated from each other by third insulating films 110c interposed therebetween. Each of the insulating films 110 may have a thickness along the first direction D1. The first thickness T1 of the first insulating layer 110a and the second thickness T2 of the second insulating layer 110b are greater than the third thickness T3 of the third insulating layers 110c, It can be big. That is, the first insulating layer 110a and the second insulating layer 110b may each have a thickness greater than that of the third insulating layers 110c. According to one embodiment, the first thickness T1 may be substantially equal to the second thickness T2. That is, the first insulating layer 110a may have substantially the same thickness as the second insulating layer 110b.

When the upper dummy structure UDS includes the plurality of the upper dummy gate lines 150UD stacked in the first direction D1, the upper dummy gate lines 150UD are interposed between the upper dummy gate lines 150UD Can be separated from each other by the insulating films 110. In this case, each of the insulating films 110 between the upper dummy gate lines 150UD may have the same thickness as the second insulating film 110b. When the lower dummy structure LDS includes the plurality of the lower dummy gate lines 150LD stacked in the first direction D1, the lower dummy gate lines 150LD are interposed between them Can be separated from each other by the insulating films 110. In this case, each of the insulating films 110 between the lower dummy gate lines 150LD may have the same thickness as the first insulating film 110a.

The upper select line 150S and the upper dummy structure UDS may be separated from each other by a fourth insulating film 110d interposed therebetween. According to an embodiment, the upper select line 150S may be provided in plurality, and the plurality of upper select lines 150S may be formed on the upper dummy structure UDS in the first direction D1, . In this case, the upper dummy structure UDS may be interposed between the upper select line 150S of the lowest layer among the plurality of the upper select lines 150S and the cell gate structure CGS, (110d) may be interposed between the uppermost upper select line (150S) and the upper dummy structure (UDS). The fourth thickness T4 of the fourth insulating layer 110d may be greater than the second thickness T2 of the second insulating layer 110b. That is, the fourth insulating layer 110d may have a thickness greater than that of the second insulating layer 110b. Accordingly, the thickness of the insulating films 110 interposed between the gate lines may increase from the cell gate structure CGS to the upper select line 150S.

The lower selection line 150G and the lower dummy structure LDS may be separated from each other by a fifth insulating film 110e interposed therebetween. The fifth thickness T5 of the fifth insulating layer 110e may be greater than the first thickness T1 of the first insulating layer 110a. That is, the fifth insulating layer 110e may have a thickness larger than that of the first insulating layer 110a. Accordingly, the thickness of the insulating films 110 interposed between the gate lines may increase from the cell gate structure CGS to the lower selection line 150G. The fifth thickness T5 of the fifth insulating layer 110e may be greater than the fourth thickness T4 of the fourth insulating layer 110d. That is, the fifth insulating film 110e may be thicker than the fourth insulating film 110d. The fifth insulating layer 110e may have a greater thickness than the insulating layers 110 stacked thereon.

 3, 4, and 5, a lower insulating layer 102 may be provided between the substrate 100 and the stacked structure SS. The lower insulating film 102 may be, for example, a silicon oxide film, a silicon nitride film, a high-k film (for example, an aluminum oxide film and a hafnium oxide film), or a combination thereof. The lower insulating layer 102 may have a thickness smaller than that of the insulating layers 110.

The substrate 100 may include common source regions 170 doped with impurities. The common source regions 170 may be provided in the substrate 100 on both sides of the stacked structure SS. The common source regions 170 may have a line shape extending along the second direction D2 and may be spaced from each other in the third direction D3.

A channel structure CS may be electrically connected to the substrate 100 through the stacked structure SS. The channel structure CS may be provided in a plurality of the stacked structures SS and may be arranged in the second direction D2 from a plan view of the plurality of channel structures CS. The plurality of channel structures CS may be arranged in a zigzag shape along the second direction D2 from a plan view, unlike the structure shown in FIG.

The channel structure CS includes a lower semiconductor pattern LSP connected to the substrate 100 through a lower portion of the stacked structure SS and at least a portion of the substrate 100, And an upper semiconductor pattern USP connected to the lower semiconductor pattern LSP through an upper portion of the lower semiconductor pattern LSP.

The upper semiconductor pattern USP may be pipe-shaped or macaroni-shaped. The lower end of the upper semiconductor pattern USP may be in a closed state. The inside of the upper semiconductor pattern USP may be filled with a buried insulating pattern 140. The bottom surface of the upper semiconductor pattern USP may be located at a lower level than the upper surface of the lower semiconductor pattern LSP. That is, the upper semiconductor pattern USP may be inserted into the lower semiconductor pattern LSP. The upper semiconductor pattern USP may include a first semiconductor pattern 130 and a second semiconductor pattern 135. The first semiconductor pattern 130 may cover the inner wall of the laminated structure SS. The first semiconductor pattern 130 may be an open pipe shape or a macaroni shape. The first semiconductor pattern 130 may be spaced apart from the lower semiconductor pattern LSP. The second semiconductor pattern 135 may have a closed pipe shape or a macaroni shape. The inside of the second semiconductor pattern 135 may be filled with the buried insulation pattern 140. The second semiconductor pattern 135 may contact an inner wall of the first semiconductor pattern 130 and an upper portion of the lower semiconductor pattern LSP. The bottom surface of the second semiconductor pattern 135 may be located at a lower height than the top surface of the lower semiconductor pattern LSP. That is, the second semiconductor pattern 135 has a structure inserted into the lower semiconductor pattern LSP, and can electrically connect the first semiconductor pattern 130 and the lower semiconductor pattern LSP. The first and second semiconductor patterns 130 and 135 may include a semiconductor material. For example, the first and second semiconductor patterns 130 and 135 may include silicon (Si), germanium (Ge), or a mixture thereof. The first and second semiconductor patterns 130 and 135 may be doped with impurities or doped with impurities It may be an intrinsic semiconductor. The first and second semiconductor patterns 130 and 135 may have a crystal structure of at least one of single crystal, amorphous, and polycrystalline.

The lower semiconductor pattern LSP may be formed of a conductive semiconductor material such as the substrate 100. According to one embodiment, the lower semiconductor pattern LSP may be an epitaxial pattern formed by using the substrate 100 made of a semiconductor material as a seed. In this case, the lower semiconductor pattern LSP may include a semiconductor material having a single crystal structure or a polycrystalline structure. According to one embodiment, the lower semiconductor pattern LSP may contact the inner wall of the substrate 100. [ The lower semiconductor pattern LSP may have a pillar shape passing through at least a part of the substrate 100.

The lower selection line 150G may be adjacent to the lower semiconductor pattern LSP and may be used as a gate electrode of the ground selection transistor GST described with reference to FIG. That is, the lower selection line 150G may be used as a gate electrode of the ground selection transistor GST for controlling an electrical connection between the common source region 170 and the lower semiconductor pattern LSP. The lower dummy gate lines 150LD, the cell gate electrodes 150, the upper dummy gate lines 150UD and the upper select line 150S may be adjacent to the upper semiconductor pattern USP . The cell gate electrodes 150 may be used as the gate electrodes of the memory cell transistors MCT described with reference to FIG. The upper selection line 150S may be used as a gate electrode of the string selection transistor SST described with reference to FIG. That is, the upper select line 150S may be used as a gate electrode of the string select transistor SST which controls the electrical connection between the bit line BL and the channel structure CS.

The fifth insulating layer 110e interposed between the lower selection line 150G and the lower dummy structure LDS of the insulating layers 110 may directly contact one side wall of the lower semiconductor pattern LSP. The upper surface of the lower semiconductor pattern LSP may be located at a height between the upper surface of the lower selection line 150G and the lower surface of the lower dummy gate line 150LD immediately adjacent to the lower selection line 150G. When the lower dummy structure LDS includes the plurality of the lower dummy gate lines 150LD stacked in the first direction D1, the upper surface of the lower semiconductor pattern LSP is connected to the lower selection line The upper surface of the lower dummy gate line 150G and the lower surface of the lower dummy gate line 150LD among the plurality of the lower dummy gate lines 150LD.

A gate dielectric pattern 160 may be disposed between the lower semiconductor pattern LPS and the lower select line 150G. The gate dielectric pattern 160 may include, for example, a silicon oxide layer.

A vertical insulator 120 may be interposed between the stacked structure SS and the upper semiconductor pattern USP. According to one embodiment, the vertical insulator 120 may extend on the sidewalls of the insulating films 110 extending in the first direction D1 and interposed between the gate lines. The vertical insulator 120 may be in a pipe shape or a macaroni shape with open upper and lower ends. The bottom surface of the vertical insulator 120 may contact at least a part of the upper surface of the lower semiconductor pattern LSP.

Referring to FIG. 6, the vertical insulator 120 may include a memory element of a flash memory device. That is, the vertical insulator 120 may include a charge storage layer CL of a flash memory device. Data stored in the vertical insulator 120 may be changed using Fowler-Nordheim tunneling caused by a voltage difference between the upper semiconductor pattern USP and the gate lines adjacent thereto. Alternatively, the vertical insulator 120 may comprise a thin film (e.g., a thin film for a phase change memory or a thin film for a variable resistance memory) capable of storing information based on other operating principles. According to one embodiment, the vertical insulator 120 may include the charge storage film CL and the tunnel insulating film TL sequentially stacked. The tunnel insulating film TL may directly contact the upper semiconductor pattern USP and the charge storage film CL may be interposed between the tunnel insulating film TL and the gate lines. According to some embodiments, the vertical insulator 120 may further include a blocking insulating film (BIL) interposed between the charge storage film CL and the gate lines. The charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a laminated trap layer . ≪ / RTI > The tunnel insulating film TL may include a material having a band gap larger than that of the charge storage film CL. For example, the tunnel insulating film TL may be a silicon oxide film. The blocking insulating layer (BIL) may include a material having a larger energy band gap than the charge storage layer (CL). For example, the blocking insulating film BIL may be a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film. The vertical insulator 120 may include a capping layer (not shown) interposed between the upper semiconductor pattern USP and the insulating layers 110 although not shown. The capping film is in direct contact with the insulating films 110 and can be vertically separated by the gate lines. According to another embodiment, the capping film may extend vertically between the upper semiconductor pattern USP and the gate lines adjacent thereto. The capping layer has etch selectivity with respect to the charge storage layer CL and may include an insulating material different from the insulating layers 110. For example, the capping film may include at least one of a silicon film, a silicon oxide film, a polysilicon film, a silicon carbide film, and a silicon nitride film, and may include a material different from the insulating films 110. As another example, the capping film may be a high dielectric constant film such as a tantalum oxide film (Ta ₂ O ₅ ), a titanium oxide film (TiO ₂ ), a hafnium oxide film (HfO ₂ ), and / or a zirconium oxide film (ZrO ₂ ).

3, 4, and 5, horizontal insulators 145 may be provided on the top and bottom surfaces of each of the gate lines. A portion of the horizontal insulators 145 may extend between the vertical insulator 120 and adjacent gate lines and another portion of the horizontal insulators 145 may extend between the gate dielectric pattern 160 and the bottom And may extend between select lines 150G. The horizontal insulators 145 may be formed of one thin film or a plurality of thin films. According to one embodiment, the horizontal insulators 145 may include a blocking insulating film of a charge trap type flash memory transistor.

A conductive pad 165 may be provided on the channel structure CS and connected to the upper semiconductor pattern USP. The conductive pad 165 may be in contact with the inner wall of the vertical insulator 120 and the upper surface of the conductive pad 165 may be substantially coplanar with the upper surface of the vertical insulator 120. The lower surface of the conductive pad 165 may directly contact the upper semiconductor pattern USP. The vertical insulator 120 may be interposed between the conductive pad 165 and the insulating layer 110 adjacent to the conductive pad 165. The conductive pad 165 may be an impurity region doped with an impurity, or may include a conductive material.

The electrode separation patterns 180 may be disposed on both sides of the laminated structure SS. The electrode separation patterns 180 may cover the common source regions 170. [ The electrode separation patterns 180 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

A bit line BL crossing the stacked structure SS may be disposed on the stacked structure SS. The bit line BL may be connected to the conductive pad 165 through a contact plug PLG and may be separated from the stacked structure SS by an interlayer insulating film 190. [

According to the concept of the present invention, the interval between the gate lines can be increased from the cell gate structure CGS to the upper selection line 150S, and the distance from the cell gate structure CGS to the lower selection line The spacing between the gate lines may increase as the distance from the gate lines increases. Accordingly, electrical interference between the upper select line 150S and the adjacent cell gate electrode 150 and between the lower select line 150G and the adjacent cell gate electrode 150 can be minimized.

In addition, the thickness of the fifth insulating film 110e interposed between the lower selection line 150G and the lower dummy structure LDS may be thicker than the thickness of the insulating films 110 provided thereon. Thus, during the process of forming the lower semiconductor pattern LSP, the upper surface of the lower semiconductor pattern LSP is electrically connected to the upper surface of the lower selection line 150G and the upper surface of the lower dummy gate 150G, It can be easily controlled to be positioned between the lower surface of the line 150LD.

FIGS. 7 to 12 are views for explaining a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the present invention, and are cross-sectional views along the directions of D1 and D3 in FIG.

Referring to FIG. 7, a lower insulating layer 102 may be formed on a substrate 100. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. For example, the lower insulating layer 102 may be a silicon oxide layer formed through a thermal oxidation process or a silicon oxide layer formed using a deposition technique.

The thin film structure TS may be formed by alternately and repeatedly depositing the sacrificial films 112 and the insulating films 110 on the lower insulating film 102. [ According to one embodiment, the sacrificial films 112 may be formed to have the same thickness. According to another embodiment, the lowermost sacrificial layer 112 of the sacrificial layers 112 may be formed thicker than the sacrificial layers 112 stacked thereon. According to another embodiment, the topmost sacrificial layer 112 of the sacrificial layers 112 may be formed thicker than the sacrificial layers 112 provided below the sacrificial layers 112, The film 112 and the sacrificial film 112 provided directly under it may be formed thicker than the sacrificial films 112 provided below them. Each of the insulating films 110 may be formed to have a predetermined thickness described with reference to FIG. The lower insulating layer 102 may have a thickness smaller than that of the sacrifice layers 112 and the insulating layers 110 formed thereon.

The sacrificial layers 112 and the insulating layers 110 may be formed by thermal chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (CVD), physical vapor deposition (CVD), or atomic layer deposition (Atomic Layer Deposition) (ALD) process. According to one embodiment, the sacrificial films 112 and the insulating films 110 may include materials having different etch selectivities. For example, the sacrificial layers 112 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film. The insulating films 110 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, and may be a material different from the sacrificial films 112. For example, the sacrificial films 112 may be formed of a silicon nitride film, and the insulating films 110 may be formed of a silicon oxide film. However, according to another embodiment, the sacrificial films 112 may be formed of a conductive material, and the insulating films 110 may be formed of an insulating material.

Referring to FIG. 8, a through hole H may be formed through the thin film structure TS to expose the substrate 100. The through holes H may be formed in a plurality of the thin film structures TS and the plurality of through holes H may be formed two dimensionally on the upper surface of the thin film structure TS . According to one embodiment, the through-holes H may be arranged along the second direction D2. According to another embodiment, the through-holes H may be arranged in a zigzag manner along the second direction D2.

The formation of the through-holes H may include forming a first mask pattern (not shown) having openings on the thin film structure TS to define areas through which the through-holes H are to be formed, And anisotropically etching the thin film structure (TS) using the first mask pattern as an etch mask. The first mask pattern may be formed of a material having etch selectivity with respect to the sacrificial films 112 and the insulating films 110. The upper surface of the substrate 100 is over-deflected by the etching process, and the upper portion of the substrate 100 can be recessed. Accordingly, the through hole H may expose at least a part of the substrate 100. [

The lower semiconductor pattern LSP may be formed to fill the lower region of the through hole H. [ The lower semiconductor pattern LSP may be formed by performing a selective epitaxial growth process using the substrate 100 exposed by the through holes H as a seed. The lower semiconductor pattern LSP may be formed in a pillar shape passing through at least a part of the substrate 100. According to one embodiment, the lower semiconductor pattern LSP may cover the sidewalls of the insulating film 110 of the lowest layer among the insulating films 110. As described with reference to FIG. 4, since the insulating film 110 of the lowermost layer, that is, the fifth insulating film 110e of FIG. 4 is formed to have a thicker thickness than the insulating films 110 formed thereon, The upper surface of the lower semiconductor pattern LSP may be located at a height between the sacrificial films 112 adjacent to each other with the insulating film 110 as the lowest layer therebetween.

The lower semiconductor pattern LSP may include a single crystal structure or a polycrystalline structure. The lower semiconductor pattern LSP may include, but is not limited to, silicon. In one example, carbon nanostructures, organic semiconductor materials, and compound semiconductors can be used for the lower semiconductor pattern (LSP). The lower semiconductor pattern LSP may have the same conductivity type as that of the substrate 100. The lower semiconductor pattern LSP can be doped in-situ during the selective epitaxial growth process. Alternatively, impurities may be implanted into the lower semiconductor pattern LSP after forming the lower semiconductor pattern LSP.

9, the vertical insulator 120 and the first semiconductor pattern 130, which cover the inner wall of the through hole H formed with the lower semiconductor pattern LSP and expose the lower semiconductor pattern LSP, May be formed.

Specifically, a vertical insulating film and a first semiconductor film covering the inner wall of the through hole H formed with the lower semiconductor pattern LSP may be formed in order. The vertical insulating film and the first semiconductor film may be formed to fill a part of the through hole (H). That is, the through hole H may not be completely filled with the vertical insulating film and the first semiconductor film. Further, the vertical insulating layer may cover the upper surface of the lower semiconductor pattern LSP exposed by the through hole H.

The vertical insulating layer may be formed of a plurality of thin films. For example, plasma enhanced chemical vapor deposition (CVD), physical CVD, or atomic layer deposition (ALD) Can be deposited. The vertical insulating film may include a charge storage film used as a memory element of a flash memory device. For example, the charge storage film may be an insulating film including a trap insulating film or conductive nano dots. Alternatively, the vertical insulating layer may comprise a thin film for a phase change memory or a thin film for a variable resistance memory. According to one embodiment, as shown in FIG. 6, A blocking insulating film (BIL), a charge storage film (CL), and a tunnel insulating film (TL) stacked in this order. The blocking insulating layer BIL may cover the sacrificial layers 112 exposed by the through holes H and the upper surfaces of the sidewalls of the insulating layers 110 and the lower semiconductor pattern LSP. The blocking insulating layer BIL may be formed of, for example, a silicon oxide layer. The charge storage layer CL may include a trap insulating layer, or an insulating layer including conductive nano dots. For example, the charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a laminated trap layer . ≪ / RTI > The tunnel insulating film TL may be one of materials having a larger bandgap than the charge storage film CL. For example, the tunnel insulating film TL may be a silicon oxide film.

The first semiconductor film may be formed on the vertical insulating film. According to one embodiment, the first semiconductor film is a semiconductor material (e.g., a polycrystalline silicon film, a monocrystalline silicon film, or an amorphous silicon film) formed using one of atomic layer deposition (ALD) or chemical vapor deposition Silicon film).

After the vertical insulating film and the first semiconductor film are sequentially formed, the first semiconductor film and the vertical insulating film on the upper surface of the lower semiconductor pattern LSP may be anisotropically etched to expose the lower semiconductor pattern LSP. Accordingly, the first semiconductor pattern 130 and the vertical insulator 120 may be formed on the inner wall of the through hole H. That is, the vertical insulator 120 and the first semiconductor pattern 130 may be formed into a cylindrical shape having open ends. The lower semiconductor pattern LSP exposed by the first semiconductor pattern 130 and the vertical insulator 120 as a result of overetching during the anisotropic etching of the first semiconductor film and the vertical insulating film, May be recessed. On the other hand, a part of the vertical insulating film located under the first semiconductor pattern 130 may not be etched by the anisotropic etching process. In this case, the vertical insulator 120 may have a bottom portion interposed between a bottom surface of the first semiconductor pattern 130 and an upper surface of the lower semiconductor pattern LSP. Accordingly, the bottom surface of the vertical insulator 120 may contact at least a portion of the upper surface of the lower semiconductor pattern LSP. In addition, during the anisotropic etching process for the first semiconductor film and the vertical insulating film, the upper surface of the thin film structure TS may be exposed. Accordingly, the vertical insulator 120 and the first semiconductor pattern 130 may be locally formed in the through hole H. That is, the vertical insulator 120 and the first semiconductor pattern 130 may be formed in each of the plurality of through holes H, and the plurality of the vertical insulators 120 and the plurality of the first semiconductors The patterns 130 may be two-dimensionally arranged in plan view.

Referring to FIG. 10, a second semiconductor pattern 135 and a buried insulating pattern 140 may be formed on the resultant product in which the vertical insulator 120 and the first semiconductor pattern 130 are formed.

Specifically, a second semiconductor film and a buried insulating film may be sequentially formed in the through hole H in which the vertical insulator 120 and the first semiconductor pattern 130 are formed. The second semiconductor film may be formed in conformity with the through hole (H) to a thickness that does not completely fill the through hole (H). The second semiconductor film may connect the lower semiconductor pattern LSP and the first semiconductor pattern 130. The second semiconductor film may be a semiconductor material (e.g., a polycrystalline silicon film, a monocrystalline silicon film, or an amorphous silicon film) formed using one of atomic layer deposition (ALD) or chemical vapor deposition . The buried insulating film may be formed so as to completely fill the inside of the through hole (H). The buried insulating film may be one of insulating materials and a silicon oxide film formed using an SOG (SOG) technique. The second semiconductor film 135 and the buried insulating pattern 140 are formed in the through hole H by planarizing the second semiconductor film and the buried insulating film to expose the upper surface of the thin film structure TS, As shown in FIG.

The second semiconductor pattern 135 may be a pipe-shaped pipe having one end closed in the through hole H, a hollow cylindrical shape having one end closed, or a cup- As shown in FIG. However, according to another embodiment, the second semiconductor pattern 135 may be formed in the form of a pillar that fills the through hole H. The buried insulation pattern 140 may be formed to fill the inside of the through hole H in which the second semiconductor pattern 135 is formed. Accordingly, an upper semiconductor pattern USP defined by the first and second semiconductor patterns 130 and 135 may be formed. The upper semiconductor pattern USP may be formed on the lower semiconductor pattern LSP. The upper semiconductor pattern USP and the lower semiconductor pattern LSP may be defined as a channel structure CS.

Referring to FIG. 11, the thin film structure TS may be patterned to form trenches T exposing the substrate 100 between adjacent channel structures CS.

Specifically, forming the trenches T may include forming second mask patterns (not shown) defining a planar position on which the trenches T are to be formed on the thin film structure TS, And anisotropically etching the thin film structure (TS) using the second mask patterns as an etching mask. The trenches T may be formed to separate the sacrificial films 112 and the sidewalls of the insulating films 110 from the upper and lower semiconductor patterns USP and LSP. The trenches T may be formed in a line or a rectangle in plan view, and the trenches T may be formed to expose the upper surface of the substrate 100 in terms of one cross section. During the etching process, the top of the substrate 100 is over-deflected so that the top of the substrate 100 can be recessed. The trenches T may have different widths depending on the distance from the substrate 100 by an anisotropic etching process. That is, the width of the lower portion of the trenches T may be narrower than the width of the upper portion of the trenches T.

As the trenches T are formed, the thin film structure TS may have a line shape extending in one direction. The thin film structure (TS) in the form of a single line can be penetrated by a plurality of the channel structures (CS).

The sacrificial films 112 exposed by the trenches T may be removed to form the recessed regions R between the insulating films 110. [ More specifically, the recessed regions R may be formed on the insulating films 110, the vertical insulator 120, the lower semiconductor pattern LSP, the lower insulating film 102, May be formed by isotropically etching the sacrificial films 112 using etching conditions having etching selectivity. The sacrificial films 112 may be completely removed by the isotropic etching process. For example, when the sacrificial films 112 are silicon nitride films and the insulating films 110 are silicon oxide films, the etching process may be performed using an etchant containing phosphoric acid.

The recessed region R in the lowest layer among the recessed regions R is formed in the recessed region R from the trenches T horizontally between the insulating film 110 in the lowermost layer and the lower insulating film 102 in the insulating films 110 And may expose a part of the side wall of the lower semiconductor pattern LSP. The remaining recess regions R of the recess regions R may extend horizontally from the trenches T to the insulating films 110 and may extend to a portion of the sidewalls of the vertical insulator 120. [ Can be exposed. That is, the lowermost recess region R can be defined by the bottom insulating film 110, the bottom insulating film 102, and one side wall of the bottom semiconductor pattern LSP, R may be defined by insulating films 110 vertically adjacent to each other and one side wall of the vertical insulator 120. [

After the recessed regions R are formed, the gate dielectric pattern 160 may be formed in the bottom recessed region R. [ For example, forming the gate dielectric pattern 160 may include performing a thermal oxidation process to oxidize a portion of a sidewall of the lower semiconductor pattern LSP exposed by the recessed region R of the lowermost layer can do. The gate dielectric pattern 160 may comprise, for example, silicon oxide.

12, horizontal insulators 145 covering the inner walls of the recess regions R and gate lines filling the remaining spaces of the recess regions R may be formed. The formation of the horizontal insulators 145 and the gate lines may include forming a horizontal insulation film and a conductive film sequentially covering the recess regions R and forming the horizontal insulation film and the horizontal insulation film R in the trenches T. [ And locally forming the horizontal insulators 145 and the gate lines in the recess regions R by removing the conductive film.

The horizontal insulating film may be composed of one thin film or a plurality of thin films, similar to the vertical insulating film. According to one embodiment, the horizontal insulating film may include a blocking insulating film of a charge trap type flash memory transistor. The blocking insulating film may be one of materials having a band gap smaller than the tunnel insulating film TL and larger than the charge storage film CL, which has been described with reference to FIG. For example, the blocking insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film. The conductive film may be formed to conformally cover the inner wall of the trenches (T) while filling the recessed regions (R). In this case, forming the gate lines may include removing the conductive film in the trenches T by a method of isotropic etching. Alternatively, according to another embodiment, the conductive film may be formed to fill the trenches T, in which case the gate lines are removed in the trenches T by anisotropic etching ≪ / RTI > According to one embodiment, forming the conductive film may include depositing a barrier metal film and a metal film in sequence. The barrier metal film may be formed of a metal nitride film such as TiN, TaN or WN. The metal film may include a metal material such as W, Al, Ti, Ta, Co or Cu.

According to one embodiment, in the bottom recess region R, the horizontal insulator 145 may be in direct contact with the gate dielectric pattern 160 on the bottom semiconductor pattern LSP, The horizontal insulators 145 may contact the vertical insulator 120 directly.

The gate lines may include a lower select line 150G and an upper select line 150S stacked on the substrate 100 in the first direction D1. According to one embodiment, the upper select line 150S may be provided in plurality and the plurality of upper select lines 150S may be stacked in the first direction D1 on the lower select line 150G. . The gate lines may be provided between the lower selection line 150G and the upper selection line 150S and may include the cell gate electrodes 150 stacked in the first direction D1. The cell gate electrodes 150 stacked on the substrate 100 may be defined as a cell gate structure CGS. When the upper select lines 150S are provided in plural numbers, the cell gate structure CGS includes the upper select line 150S of the lowest layer among the lower select line 150G and the plurality of the upper select lines 150S, . ≪ / RTI > The gate lines may include at least one lower dummy gate line 150LD provided between the lower select line 150G and the cell gate structure CGS. Accordingly, a lower dummy structure LDS including the at least one lower dummy gate line 150LD may be defined between the lower selection line 150G and the cell gate structure CGS. According to one embodiment, the lower dummy structure LDS may include a plurality of lower dummy gate lines 150LD, and the plurality of lower dummy gate lines 150LD may include a lower select line 150G, And the cell gate structure CGS in the first direction D1. In addition, the gate lines may include at least one upper dummy gate line 150UD provided between the upper select line 150S and the cell gate structure CGS. Accordingly, an upper dummy structure UDS including the at least one upper dummy gate line 150UD may be defined between the upper select line 150S and the cell gate structure CGS. According to one embodiment, the upper dummy structure UDS may include a plurality of upper dummy gate lines 150UD, and the plurality of upper dummy gate lines 150UP may include the upper select line 150S, And the cell gate structure CGS in the first direction D1. The upper dummy structure UDS may be connected to the uppermost select line 150S and the cell gate structure CGS of the plurality of the upper select lines 150S when the upper select lines 150S are provided in plural, . ≪ / RTI >

The lower selection line 150G, the lower dummy structure LDS, the cell gate structure CGS, the upper dummy structure UDS, and the upper dummy structure UDS, which are sequentially stacked in the first direction D1 on the substrate 100, And the upper select line 150S may be defined as a stacked structure SS. The laminated structure SS may have a line shape extending in the second direction D2, as described with reference to Figs. 3 to 5. Fig. The plurality of stacked structures SS may be provided on the substrate 100 and the plurality of stacked structures SS may be spaced apart from each other in the third direction D3. The insulating films 110 may be provided between the gate lines and extend in the second direction D2, as described with reference to FIGS.

Referring again to FIG. 4, common source regions 170 may be formed in the substrate 100 after the horizontal insulator 145 and the gate lines are formed. The common source regions 170 may be formed by performing an ion implantation process on the substrate 100 exposed by the trenches T. [ The common source regions 170 may have a different conductivity type from the lower semiconductor pattern LSP. Alternatively, the region of the substrate 100 in contact with the lower semiconductor pattern LSP may have the same conductivity type as the lower semiconductor pattern LSP. According to one embodiment of the present invention for a flash memory device, each of the common source regions 170 may be connected to one another and may be in an equipotential state. However, according to another embodiment, each of the common source regions 170 may be electrically isolated so as to have different potentials. According to yet another embodiment, the common source regions 170 may constitute a plurality of independent source groups, including a plurality of different common source regions 170, And can be electrically separated to have different potentials.

And electrode separation patterns 180 filling the trenches T on the common source regions 170 may be formed. The electrode separation patterns 180 may be formed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In addition, a conductive pad 165 connected to the first and second semiconductor patterns 130 and 135 may be formed. The conductive pad 165 may be formed by recessing the upper region of the first and second semiconductor patterns 130 and 135, and then filling the recessed region with a conductive material. The conductive pad 165 may be formed by doping impurities of a conductive type different from that of the first and second semiconductor patterns 130 and 135.

A contact plug PLG connected to the conductive pad 165 and a bit line BL connected to the contact plug PLG may be formed on the stacked structure SS. The bit line BL may be electrically connected to the first and second semiconductor patterns 130 and 135 through the contact plug PLG. The bit line BL may be formed to cross the gate lines or the trenches T. [ The bit line BL may be formed spaced apart from the stacked structure SS by an interlayer insulating film 190.

13 is a simplified circuit diagram of a three-dimensional semiconductor memory device according to another embodiment of the present invention.

13, the cell error of the three-dimensional semiconductor memory device includes a common source line CSL, a bit line BL, and a cell string CSTR between the common source line CSL and the bit line BL. . ≪ / RTI >

The common source line CSL may be a conductive thin film disposed on the substrate, and the bit line BL may be conductive patterns (for example, a metal line) disposed on the substrate.

The cell string CSTR may include a first string CSTR1 coupled to the bit line BL and a second string CSTR2 coupled to the common source line CSL. The first string CSTR1 may be connected to the second string CSTR2 via a switching element SW.

The first string CSTR1 includes a string selection transistor SST connected to the bit line BL and a plurality of first memory cell transistors SUB arranged between the string selection transistor SST and the switching element SW. Lt; RTI ID = 0.0 > MCT1. ≪ / RTI > The string selection transistor SST and the first memory cell transistors MCT1 may be connected in series. The first string CSTR1 may further include a first dummy cell transistor DCT1 provided between the string selection transistor SST and the first memory cell transistor MCT1 immediately adjacent thereto.

The second string CSTR2 includes a ground selection transistor GST connected to the common source line CSL and a plurality of second memory cells GND disposed between the ground selection transistor GST and the switching element SW. Transistors MCT2. The ground selection transistor GST and the second memory cell transistors MCT2 may be connected in series. The second string CSTR2 may further include a second dummy cell transistor DCT2 provided between the ground selection transistor GST and the second memory cell transistor MCT2 immediately adjacent thereto.

Each of the first and second memory cell transistors MCT1 and MCT2 may include a data storage element. During the program operation, a dummy pass voltage may be applied to the first dummy cell transistor DCT1 and the second dummy cell transistor DCT2, and the dummy pass voltage may be applied to the first and second memory cell transistors MCT1 , And MCT2, respectively.

14 is a cross-sectional view of a three-dimensional semiconductor memory device according to another embodiment of the present invention.

14, a three-dimensional semiconductor memory device includes a bit line BL on a substrate 200, a stacked structure SS between the substrate 200 and the bit line BL, a stacked structure SS of the stacked structure SS, A common source line CSL between the bit lines BL and a semiconductor pattern SP penetrating the stacked structure SS. The semiconductor pattern SP may connect the bit line BL and the common source line CSL. The semiconductor pattern SP may be connected to the bit line BL through a contact plug PLG provided between the stacked structure SS and the bit line BL.

The stacked structure SS includes a plurality of word lines WL sequentially stacked on the substrate 200 in a direction perpendicular to the top surface of the substrate 200 And selection lines disposed between the word lines WL and the bit lines BL. The selection lines include a string selection line SSL disposed between the word lines WL and the bit lines BL and a word line WL disposed between the word lines WL and the common source line CSL And a ground selection line GSL. The stacked structure SS may further include dummy word lines DWL disposed between the word lines WL and the selection lines.

The string selection line SSL and the ground selection line GSL may be spaced apart from each other in a direction parallel to the upper surface of the substrate 200 (e.g., x direction). The word lines WL may include first word lines WL1 disposed between the substrate 200 and the string select line SSL and first word lines WL2 between the substrate 200 and the ground select line GSL. Lt; RTI ID = 0.0 > WL2 < / RTI > The second word lines WL2 may be spaced apart from the first word lines WL1 in the x direction. The dummy word lines DWL include a first dummy word line DWL1 disposed between the string selection line SSL and a first word line WL1 immediately adjacent thereto, And a second dummy word line DWL2 disposed between the immediately adjacent second word lines WL2. The first dummy word line DWL1 and the second dummy word line DWL2 may be spaced apart from each other in the x direction.

The string selection line SSL and the ground selection line GSL may be respectively connected to the string selection transistor SST and the ground selection transistor GST described with reference to FIG. The first word lines WL1 and the second word lines WL2 are connected to the first memory cell transistors MCT1 and the second memory cell transistors MCT2 described with reference to FIG. Can be connected. The first dummy word line DWL1 and the second dummy word line DWL2 are connected to the first dummy cell transistor DCT1 and the second dummy cell transistor DCT2 respectively described with reference to Fig. .

The stacked structure SS is formed between the word lines WL, between the word lines WL and the dummy word lines DWL, and between the dummy word lines DWL and the selection lines. And may include insulating films 210 provided thereon. The insulating films 210 are formed on the first insulating films 210a, the first dummy word lines DWL1 and the first insulating films 210b provided between the first word lines WL1 and the second word lines WL2. Second insulating films 210b provided between immediately adjacent first word lines WL1 and between the second dummy word lines DWL2 and a second word line WL2 immediately adjacent to the second dummy word lines DWL2, And third insulating films 210c provided between the first dummy word line DWL1 and the first dummy word line DWL1 and between the ground selection line GSL and the second dummy word line DWL2.

Each of the insulating films 210 may have a thickness along the y direction. Each of the first insulating films 210a may have a first thickness t1 and each of the second insulating films 210b may have a second thickness t2, 210c may have a third thickness t3. The second thickness t2 may be greater than the first thickness t1 and the third thickness t3 may be greater than the second thickness t2. As a result, the distance from the first word lines WL1 to the string selection line SSL and the distance from the second word lines WL2 to the ground selection line GSL increases, Can be thickened.

The stacked structure SS may extend in one direction parallel to the upper surface of the substrate 200 and intersecting the x direction. And a second dummy word line DWL2 connected between the string selection line SSL and the ground selection line GSL and between the first dummy word line DWL1 and the second dummy word line DWL2, An electrode separation pattern 280 may be provided between the second word lines WL2. The electrode separation pattern 280 may extend along a direction in which the laminated structure SS extends. The electrode separation pattern 280 may include at least one of a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film, for example. A lower insulating layer 205 may be interposed between the substrate 200 and the stacked structure SS. The lower insulating film 205 may include at least one of a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film, for example.

The semiconductor pattern SP includes a pair of vertical portions VP passing through the stacked structure SS and a pair of vertical portions VP provided below the stacked structure SS to connect the pair of vertical portions VP And may include a horizontal portion HP. One of the pair of vertical portions VP may be connected to the common source line CSL through the stacked structure SS and the other of the vertical portions VP may be connected to the stacked structure SS And may be connected to the bit line BL. The horizontal portion HP may be provided between the substrate 200 and the stacked structure SS to connect the pair of vertical portions VP. Specifically, one of the pair of vertical portions VP passes through the second word lines WL2, the second dummy word line DWL2, and the ground selection line GSL, Line CSL while the other is connected to the contact plug PLG through the first word lines WL1, the first dummy word line DWL1, and the string select line SSL. To the bit line BL. The horizontal portion HP may extend below the second word lines WL2 under the first word lines WL1 to connect the pair of vertical portions VP to each other. From a plan viewpoint, the horizontal portion HP may be in the form of a plate across the electrode separation pattern 280. The semiconductor pattern SP may include a semiconductor material. For example, the semiconductor pattern SP may include silicon (Si), germanium (Ge), or a mixture thereof, and may be an impurity-doped semiconductor or an intrinsic semiconductor without doping the impurity have. In addition, the semiconductor pattern SP may have a crystal structure of at least one of single crystal, amorphous, and polycrystalline. The semiconductor pattern SP may be in an unselected state or may be doped with an impurity having the same conductivity type as that of the substrate 200.

A charge storage structure 250 may be interposed between the semiconductor pattern SP and the stacked structure SS. The charge storage structure 250 may extend between the semiconductor pattern SP and the substrate 200. The charge storage structure 250 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer that sequentially cover an outer wall of the semiconductor pattern SP, although not shown.

The word lines WL1 and WL2 may be configured to control the potential of the semiconductor pattern SP. For example, an electrical connection between the bit lines BL and the common source line CSL is provided to the word lines WL1 and WL2, the string selection line SSL, and the ground selection line GSL Lt; / RTI > According to this structure, the semiconductor pattern SP can constitute a unit cell string of a NAND type cell array structure. Although not shown, a switching element (not shown) may be provided in the substrate 200 to selectively control the flow of charges passing through the horizontal portion HP of the semiconductor pattern SP.

15 to 18 are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the present invention.

Referring to FIG. 15, a buried sacrificial pattern 202 may be formed in the substrate 200. The bottom insulating layer 205 may be formed on the resultant product in which the buried sacrificial pattern 202 is formed and the thin film structure TS may be formed on the bottom insulating layer 205. The thin film structure TS may include a plurality of insulating films 210 and a plurality of conductive films 213 which are alternately and repeatedly stacked. The insulating films 210 may be formed to have a predetermined thickness described with reference to FIG. The substrate 200 may include a semiconductor material (e.g., a silicon substrate).

The buried sacrificial pattern 202 may be formed of a material having etch selectivity with respect to the insulating films 210 and the conductive films 213. The buried sacrificial pattern 202 may be formed using a process of forming an insulating pattern for device isolation.

Referring to FIG. 16, vertical holes H1 may be formed through the thin film structure TS to expose an upper surface of the buried sacrificial pattern 202. Referring to FIG. Thereafter, the buried sacrificial pattern 202 exposed by the vertical holes H1 may be selectively removed to form the horizontal hole H2. A pair of the vertical holes H1 may be formed on one buried sacrificial pattern 202. The pair of vertical holes H1 may be connected to each other through the horizontal hole H2. One opening through the thin film structure TS can be defined by the pair of vertical holes H1 and the horizontal holes H2 connected to each other.

Referring to FIG. 17, a charge storage structure 250 that conformationally covers the inner wall of the opening may be formed. The charge storage structure 250 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer, which are not shown, which in turn cover the inner wall of the opening. Thereafter, a semiconductor pattern SP filling the remaining portion of the opening may be formed. The semiconductor pattern SP may include a pair of vertical portions VP provided in each of the pair of vertical holes H1 and a horizontal portion HP provided in the horizontal hole H2 .

Referring to FIG. 18, a trench T may be formed by patterning the thin film structure TS to expose the insulating films 210 and the inner walls of the conductive films 213. The trench T may traverse the horizontal portion HP of the semiconductor pattern SP. The trench T may be formed between the pair of vertical portions VP of the semiconductor pattern SP. The trench T may expose a portion of the top surface of the charge storage structure 250 surrounding the outer wall of the horizontal portion HP. Thereafter, an electrode separation pattern 280 filling the trench T may be formed.

As the trenches T are formed, the conductive layers 213 may be separated into conductive patterns. The conductive patterns of the uppermost layer among the conductive patterns may be used as a string selection line (SSL) and a ground selection line (GSL), which constitute a cell array of the three-dimensional semiconductor memory device. The string selection line SSL and the ground selection line GSL may be spaced apart from each other in the x direction with the electrode separation pattern 280 therebetween. The conductive patterns provided directly below the conductive patterns of the uppermost layer among the conductive patterns may be defined as dummy word lines DWL. The dummy word lines DWL are connected to a first dummy word line DWL1 provided between the string selection line SSL and the substrate 200 and between the ground selection line GSL and the substrate 200 And a second dummy word line DWL2 provided. The first dummy word line DWL1 and the second dummy word line DWL2 may be spaced apart from each other in the x direction with the electrode separation pattern 280 therebetween. The conductive patterns interposed between the first dummy word line DWL1 and the substrate 200 among the conductive patterns may be defined as first word lines WL1, The conductive patterns interposed between the word line DWL2 and the substrate 200 may be defined as the second word lines WL2. The first word lines WL1 may be spaced apart from the second word lines WL2 with the electrode separation pattern 180 therebetween. The word lines WL1 and WL2, the dummy word lines DWL, the string selection line SSL, the ground selection line GSL, and the insulating films (not shown) stacked on the substrate 200 110 may be defined as a laminated structure SS.

Wherein one of the pair of vertical portions VP of the semiconductor pattern SP includes a first word line WL1, a first dummy word line DWL1, and a string selection line SSL, And the other may pass through the second word lines WL2, the second dummy word line DWL2, and the ground selection line GSL. The horizontal portion HP of the semiconductor pattern SP may be provided below the stacked structure SS to connect the pair of vertical portions VP.

Referring again to FIG. 14, a bit line BL may be formed on the stacked structure SS, and a common source line CSL may be formed between the stacked structure SS and the bit line BL . One of the pair of vertical portions VP of the semiconductor pattern SP may be connected to the bit line BL via a contact plug PLG and the other may be connected to the common source line CSL .

According to the concept of the present invention, a three-dimensional semiconductor memory device may include vertically stacked gate lines on a substrate, the gate lines being arranged on a cell gate electrode (i. E. , A word line), a dummy gate line (i.e., a dummy word line), and a select line (i.e., a string select line or a ground select line). And the interval between the gate lines may increase from the cell gate electrode toward the selection line. Thereby, electrical interference between the select line and the cell gate electrode can be minimized.

Thereby, the electrical characteristics of the three-dimensional semiconductor memory device can be improved, and a three-dimensional semiconductor memory device having excellent reliability can be provided.

The foregoing description of embodiments of the present invention provides illustrative examples for the description of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It is clear.

100: substrate 102: lower insulating film
110: insulating film 150G: lower select line
150LD: lower dummy gate line 150: cell gate electrode
150UD: upper dummy gate line 150S: upper select line
CGS: Cell gate structure LDS: Lower dummy structure
UDS: upper dummy structure SS: laminated structure
LSP: lower semiconductor pattern USP: upper semiconductor pattern
130: first semiconductor pattern 135: second semiconductor pattern
CS: Channel structure 120: Vertical insulator
140: buried insulation pattern 145: horizontal insulator
165: conductive pad 160: gate dielectric pattern
170: common source region 180: electrode separation pattern
190: interlayer insulating film PLG: contact plug
BL: bit line

Claims (20)

A lower select line and an upper select line stacked on a substrate in a first direction perpendicular to an upper surface of the substrate;
A cell gate structure provided between the lower select line and the upper select line and including cell gate electrodes stacked in the first direction;
A lower dummy gate line provided between the lower select line and the cell gate structure and spaced a first distance from the lowest cell gate electrode of the cell gate electrodes along the first direction; And
And an upper dummy gate line provided between the upper select line and the cell gate structure and spaced a second distance from the uppermost cell gate electrode of the cell gate electrodes along the first direction However,
The lower dummy gate line and the upper dummy gate line are immediately adjacent to the cell gate electrode of the lowest layer and the cell gate electrode of the uppermost layer,
Wherein the cell gate electrodes are spaced apart from each other by a third distance along the first direction, and the first distance and the second distance are respectively greater than the third distance. The method according to claim 1,
Wherein the upper dummy structure includes a plurality of upper dummy gate lines stacked in the first direction,
Wherein the upper dummy gate line is an upper dummy gate line of the lowest layer among the plurality of upper dummy gate lines. The method of claim 2,
Wherein the plurality of upper dummy gate lines are spaced apart from each other at the second distance along the first direction. The method of claim 2,
The upper select line is spaced a fourth distance from the upper dummy gate line of the uppermost one of the plurality of upper dummy gate lines along the first direction,
And the fourth distance is larger than the second distance. The method of claim 4,
Wherein the upper select line is provided in a plurality of,
A plurality of the upper select lines are stacked in the first direction on the upper dummy structure,
And an upper select line of a lowest layer among the plurality of upper select lines is spaced from the upper dummy gate line of the uppermost layer by the fourth distance. The method of claim 4,
Wherein the lower dummy structure includes a plurality of lower dummy gate lines stacked in the first direction,
Wherein the lower dummy gate line is a lower dummy gate line of the uppermost one of the plurality of lower dummy gate lines. The method of claim 6,
Wherein the plurality of lower dummy gate lines are spaced apart from each other by the first distance along the first direction. The method of claim 6,
The lower select line is spaced a fifth distance from the lower one of the plurality of lower dummy gate lines along the first direction,
And the fifth distance is larger than the first distance. The method of claim 8,
And the fifth distance is larger than the fourth distance. The method of claim 9,
Wherein the first distance and the second distance are equal to each other. The method according to claim 1,
Wherein the lower selection line, the upper selection line, the cell gate structure, the lower dummy structure, and the upper dummy structure are defined as a laminated structure,
Wherein the stacked structure extends in a second direction parallel to the upper surface of the substrate. The method of claim 11,
And a channel structure that is connected to the substrate through the stacked structure. The method of claim 12,
The channel structure comprising:
A lower semiconductor pattern penetrating at least a part of the substrate; And
And an upper semiconductor pattern spaced apart from the substrate with the lower semiconductor pattern interposed therebetween,
Wherein the lower dummy structure line includes a plurality of lower dummy gate lines stacked in the first direction, the lower dummy gate line is a lower dummy gate line of the uppermost one of the plurality of the lower dummy gate lines,
Wherein the upper surface of the lower semiconductor pattern is located at a height between the upper surface of the lower select line and the lower surface of the lower dummy gate line of the plurality of the lower dummy gate lines. A first select line on the substrate;
A cell gate structure comprising a plurality of cell gate electrodes provided between the substrate and the first select line and stacked in a first direction perpendicular to an upper surface of the substrate; And
And a first dummy structure provided between the first select line and the cell gate structure and including at least one first dummy gate line,
The plurality of cell gate electrodes are separated from each other by first insulating films interposed therebetween,
The first dummy structure and the cell gate structure are separated from each other by a second insulating film interposed therebetween,
Wherein each of the first insulating films and the second insulating film has a thickness along the first direction, and the second insulating film has a thickness thicker than the first insulating films. 15. The method of claim 14,
The first select line and the first dummy structure are separated from each other by a third insulating film interposed therebetween,
Wherein the third insulating film has a thickness along the first direction, and the third insulating film has a thickness larger than that of the second insulating film. 16. The method of claim 15,
A second select line between the substrate and the cell gate structure; And
Further comprising a second dummy structure provided between the second select line and the cell gate structure and including at least one second dummy word line,
The second dummy structure and the cell gate structure are separated from each other by a fourth insulating film interposed therebetween,
Wherein the fourth insulating film has a thickness along the first direction, and the fourth insulating film has a thickness thicker than the first insulating films. 18. The method of claim 16,
The second selection line and the second dummy structure are separated from each other by a fifth insulating film interposed therebetween,
Wherein the fifth insulating film has a thickness along the first direction, and the fifth insulating film has a thickness larger than that of the fourth insulating film. 18. The method of claim 17,
And the fifth insulating film has a thickness larger than that of the third insulating film. 18. The method of claim 17,
Wherein the first selection line, the second selection line, the cell gate structure, the first dummy structure, and the second dummy structure are defined as a laminated structure,
Wherein the stacked structure extends in a second direction parallel to the upper surface of the substrate. The method of claim 19,
And a channel structure that is connected to the substrate through the stacked structure.

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