KR20170043149A

KR20170043149A - Dc-dc converter

Info

Publication number: KR20170043149A
Application number: KR1020150142439A
Authority: KR
Inventors: 김태진; 신대중; 김봉섭
Original assignee: 주식회사 더즈텍
Priority date: 2015-10-12
Filing date: 2015-10-12
Publication date: 2017-04-21
Also published as: KR101746425B1

Abstract

Disclosed is a DC-DC converter which can reduce loss due to a switching operation. The DC-DC converter can comprise: a pulse skip detection module detecting whether or not a pulse is skipped in a switch signal and outputting the detection result; and a pulse width adding module increasing the width of a pulse inputted for the first time after the pulse is skipped when the purse skip detection module detects that the pulse is skipped.

Description

[0001] DC-DC CONVERTER [0001]

The present invention relates to a DC-DC converter, and more particularly, to a DC-DC converter operating in a pulse skip mode (PSM).

The conventional DC-DC converter uses a method of reducing the loss due to the switching operation by reducing the number of switching by skipping the pulse of the switch signal in order to reduce the loss due to the switching operation. However, even with this method, the loss due to the switching operation in the DC-DC converter is still considered to be a problem to be solved.

It is an object of the present invention to provide a DC-DC converter capable of reducing a loss due to a switching operation.

It is another object of the present invention to provide a DC-DC converter capable of reducing the number of switching operations and reducing loss due to a switching operation.

It is another object of the present invention to provide a DC-DC converter capable of reducing a loss due to a switching operation by increasing the number of pulse skips of a DC-DC converter operating in a pulse skip mode.

According to an aspect of the present invention, there is provided a pulse skip detection module for detecting whether a pulse is skipped in a switch signal and outputting the detection result; And a pulse width adding module for increasing a width of a pulse input first after the pulse skip if a skip of a pulse is detected by the pulse skip detecting unit.

According to another aspect of the present invention, there is provided a semiconductor device including: a PWM module for generating a switch signal; A pulse skip detection module for monitoring the switch signal to detect a pulse skip and outputting a pulse skip detection signal as a result of detection; And a pulse width adding module for outputting a signal obtained by increasing the pulse width of the switch signal by the delay time based on the switch signal and the delay signal obtained by delaying the switch signal by a predetermined time .

According to another aspect of the present invention, there is also provided an error amplifier for comparing a reference voltage and an output of a DC-DC converter; A PWM module for generating a switch signal by adjusting a pulse width based on a comparison result of the error amplifier; A pulse skip detection module for detecting whether or not the switch signal is skipped based on a clock signal and outputting a pulse skip detection signal; And a pulse width adding module for increasing a width of a first pulse of the switch signal after the pulse skip.

According to the embodiment of the present invention, the loss due to the switching operation of the DC-DC converter can be reduced.

According to the embodiment of the present invention, loss due to the switching operation can be reduced by using pulse skipping of the DC-DC converter.

According to the embodiment of the present invention, it is possible to reduce the loss due to the switching operation by increasing the number of pulse skipping in the pulse skipping mode of the DC-DC converter.

1 is a block diagram showing the configuration of a DC-DC converter according to an embodiment of the present invention.
2 is a diagram illustrating an embodiment of a pulse skipping module according to an embodiment of the present invention.
3 is a view for explaining the operation of the pulse skipping module shown in FIG.
FIG. 4 is a diagram illustrating another embodiment of a pulse skipping module according to an embodiment of the present invention. Referring to FIG.
5 is a view for explaining the operation of the pulse skip module shown in FIG.
6 is a diagram illustrating an embodiment of a pulse width adding module according to an embodiment of the present invention.
7 is a view for explaining the operation of the pulse width adding module shown in FIG.
8 is a diagram for comparing the switching times of the DC-DC converter according to the present invention and the conventional DC-DC converter.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of known related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the singular phrases used in the present specification and claims should be interpreted generally to mean "one or more " unless otherwise stated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout. .

1 is a block diagram of a DC-DC converter according to an embodiment of the present invention. 1, the DC-DC converter includes a switching circuit 110, a feedback gain module 120, an error amplifier 130, a PWM module 140, a switch control logic 150 A Switch Control Logic, a Switch Driver 160, a Pulse Skip Detection Module 170 and a Pulse Width Adder Module 180.

The switching circuit 110 includes a circuit in which the relationship between the input voltage and the output voltage varies depending on the connection structure between the switches. For example, the switching circuit 110 may be a BOOST converter, a BUCK converter, or a circuit that implements a BUCK-BOOST converter.

The feedback gain module 120 _{feeds back} the output voltage V _OUT of the switching circuit 110 to compare the output V _OUT of the DC-DC converter with the reference voltage V _REF . In one embodiment, the feedback gain module 120 may provide gain (gain) to the output of the switching circuit 110 for output. Here, the gain means a value that can equal the output voltage to the reference voltage when the output of the switching circuit 110 becomes a desired voltage. For example, if the desired output voltage is 4V and the reference voltage is 8V, the gain is 2.

The error amplifier 130 compares the result of feedback of the output of the switching circuit 110 with the reference voltage.

In one embodiment, the error amplifier 130 may compare the output of the feedback gain module 120 with a reference voltage.

In one embodiment, the error amplifier 130 may amplify and output the result of comparing the output of the feedback gain module 120 with the reference voltage.

In one embodiment, the error amplifier 130 may include a compensation circuit to prevent oscillation / divergence.

The PWM module 140 generates a switch signal for controlling the switch of the DC-DC converter circuit 110.

In one embodiment, the PWM module 140 may adjust the duty ratio of the switch signal according to the output of the error amplifier 130.

The switch control logic 150 transfers the switch signal to the switch. Specifically, the switch control logic 150 delivers a switch signal to the switch driver 160 that drives each switch.

The switch driver 160 drives each switch according to the switch signal.

The pulse skip detection module 170 detects whether or not the switch signal is pulse skipped. Specifically, the pulse skip detection module 170 monitors the switch signal and outputs a pulse skip detection signal PS_DET indicating that the pulse of the switch signal is skipped. The pulse skip detection module 170 may compare the switch signal and the clock signal to monitor whether a pulse skip has occurred in the switch signal. In FIG. 1, the pulse skipping module 170 is shown detecting a pulse skip using a switch signal output from the PWM module, but this is only an embodiment of the present invention. Therefore, the switch logic 150, the switch driver The pulse skipping can be detected using a signal at an arbitrary position having an output of the same type as that of the switch signal. Hereinafter, a specific example of the pulse skip detection module 170 will be described with reference to FIGS. 2 to 6. FIG. However, in order to facilitate a clear understanding of the present invention, it is assumed that the pulse width of the switch signal output from the PWM module 140 is constant.

The pulse width addition module 180 increases the pulse width of the switch signal. Specifically, when the pulse skipping of the switch signal is detected, the pulse width adding module 180 increases the pulse width of the switch signal inputted after pulse skipping of the switch signal. Hereinafter, a specific embodiment of the pulse width adding module 180 will be described with reference to FIG.

FIG. 2 is a diagram illustrating an embodiment of a pulse skip detection module 170 according to an embodiment of the present invention. Referring to FIG. 2, the pulse skip detection module 170 includes two flip-flops 210 and 230 and an inverter 220. Specifically, the first flip-flop 210 receives the clock signal at the clock terminal CK and receives the switch signal at the input terminal D. The inverter 220 receives a switch signal at its input terminal. The second flip-flop 230 receives the output of the first flip-flop 210 at the inverting reset terminal R and receives the output of the inverter 220 at the clock terminal CK. . Hereinafter, the operation of the pulse skip detection module 170 shown in FIG. 2 will be described with reference to FIG.

FIG. 3 is a view for explaining the operation of the pulse skip detection module 170 shown in FIG. Referring to FIG. 3, a switch signal, a clock signal, an output (Q) signal of the first flip-flop 210, and a pulse skip detection signal, which is an output of the second flip- Looking at the switch signal, a pulse skip occurs at time t3, indicating that the switch signal changes from a logic high (HIGH) to a logic low (LOW) have. Hereinafter, this will be described in detail.

At time t1, the switch signal is high and the clock signal changes from low to high. At this time, the first flip-flop 210 outputs a high-level switch signal input to the input terminal D as an output terminal Q because a clock signal changing from a low level to a high level is input to the clock terminal CK. Also, since the output of the first flip-flop 230, which is high in the inversion reset stage R, is not reset and the inverted switch signal, which is low in the clock stage CK, is input to the second flip flop 230 , And keeps the previous output high. Therefore, the pulse skip detection signal maintains a high level.

At time t2, the switch signal is low and the clock signal changes from high to low. At this time, the first flip-flop 210 keeps the previous output high because the clock signal changing from high to low is input to the clock terminal CK. The second flip-flop 230 also receives the output of the first flip-flop 210 that is high in the inversion reset stage R and is not reset. The inverted switch 210, which changes from high to low on the clock terminal CK, Signal is input, the high level of the input terminal D is output to the output terminal Q. Therefore, the pulse skip detection signal maintains a high level.

At time t3, the switch signal is low due to a pulse skip and the clock signal changes from low to high. At this time, the first flip-flop 210 outputs a low-level switch signal input to the input terminal D to the output terminal Q because a clock signal changing from a low level to a high level is input to the clock terminal CK. In addition, the second flip-flop 230 outputs a low level because the output of the first flip-flop 210, which is low in the inversion reset stage R, is input and reset. Therefore, the pulse skip detection signal changes from high to low.

At time t4, the switch signal is low and the clock signal changes from high to low. At this time, the first flip-flop 210 maintains the previous output, since the clock signal changing from high to low is input to the clock terminal CK. In addition, the second flip-flop 230 outputs a low level because the output of the first flip-flop 210, which is low in the inversion reset stage R, is input and reset. Therefore, the pulse skip detection signal maintains a low level.

At time t5, the switch signal is high and the clock signal changes from low to high. At this time, since the clock signal changing from low to high to the clock terminal CK is input to the first flip-flop 210, the first flip-flop 210 outputs the high level input to the input terminal D as the output terminal Q. The second flip-flop 230 receives the output of the first flip-flop 210 which is high in the inversion reset stage R and is not reset, and the inverted switch signal that is low in the clock stage CK is input Keeps the previous output low. Therefore, the pulse skip detection signal maintains a low level.

At time t6, the switch signal changes from high to low, and the clock signal changes from high to low. At this time, the first flip-flop 210 maintains the previous output HIGH since the clock signal changing from high to low is input to the clock terminal CK. The second flip-flop 230 receives the output of the first flip-flop 210 which is high in the inversion reset stage R and is not reset. The inverted clock CK, which changes from low to high, Signal is inputted, the high level of the input terminal D is outputted to the output terminal R. Thus, the pulse skip detection signal changes from low to high.

4 is a diagram illustrating another embodiment of the pulse skip detection module 170 according to an embodiment of the present invention.

4, the pulse skipping detection module 170 includes two flip-flops 410 and 430, one inverter 420, and one RS latch 440. The flip- Specifically, in the first flip-flop 410, VDD is input to the input terminal D, a clock signal is input to the clock terminal CK, and a switch signal is input to the reset terminal R. The inverter 420 receives the switch signal and inverts it. The output terminal Q of the first flip flop 410 is connected to the input terminal D of the second flip flop 430 and a clock signal is inputted to the clock terminal CK of the second flip flop 430. The reset terminal R is connected to the inverter 420 . The RS latch 440 has the output terminal Q of the second flip flop connected to the reset terminal R and the output terminal of the inverter 420 connected to the set terminal S thereof. The first flip-flop 410 is reset when the signal input to the reset terminal R changes from low to high (rising edge), and the second flip-flop 430 is reset to the reset terminal R (Falling edge, falling edge) is changed from high to low. The RS latch 440 is composed of two NOR gates and outputs a low when the reset stage R and the set stage S are both high. Hereinafter, the operation of the pulse skip detection module 170 shown in FIG. 4 will be described with reference to FIG.

FIG. 5 is a diagram for explaining the operation of the pulse skip detection module 170 shown in FIG.

Referring to FIG. 5, a clock signal, a switch signal, a pulse skip detection signal as an output of the RS latch 440, an output of the first flip-flop 410, and an output of the second flip-flop 430 are shown. Looking at the switch signal, a pulse skip occurred between times t8 and t9, which causes the switch detection signal to change from high to low at time t9. Hereinafter, the present invention will be described in detail.

At time t1, the clock signal changes from low to high, and the switch signal remains low. At this time, since the first flip-flop 410 receives the switch signal for holding the low level at the reset terminal R and is not reset, and the clock signal changing from low to high to the clock terminal CK is inputted, To the output terminal Q. In addition, the second flip-flop 430 receives the inverted switch signal holding the high level at the reset terminal R and is not reset, and the clock signal changing from low to high to the clock terminal CK is input, And outputs the high input to the output terminal (D) as the output terminal (Q). The RS latch 440 receives the output of the first flip-flop 410, which is high in the reset terminal R, and outputs a low because the inverted switch signal, which is high in the set S, is input. Therefore, the pulse skip detection signal changes from high to low.

At time t2, the clock signal is low and the switch signal changes from low to high. At this time, the first flip-flop 410 outputs a low level because the switch signal changing from low to high to the reset terminal R is input and reset. Further, the second flip-flop 430 outputs a low level because the inverted switch signal changing from high to low to the reset terminal R is input and reset. The RS latch 440 receives the output of the second flip-flop 430 that is low in the reset terminal R and receives the inverted switch signal that is low in the set S, do. Therefore, the pulse skip detection signal maintains a low level.

At time t3, the clock signal is low and the switch signal changes from high to low. At this time, the first flip-flop 410 is not reset due to the input of a low switch signal to the reset terminal R, and a low-in-clock signal is input to the clock terminal CK. In addition, the second flip-flop 430 maintains the previous output low because the inverted switch signal, which is high in the reset terminal R, is not reset and the clock signal is input to the clock terminal CK . In addition, the RS latch 440 receives the output of the second flip-flop 430, which is low in the reset terminal R, and outputs a high because the inverted switch signal, which is high in the input set S, is input. Thus, the pulse skip detection signal changes from low to high.

At time t4, the clock signal changes from low to high, and the switch signal remains low. At this time, since the first flip-flop 410 receives a switch signal that is low in the reset terminal R and is not reset, and a clock signal that changes from low to high to the clock terminal CK is input, And outputs the high level to the output stage (Q). In addition, the second flip-flop 430 receives the inverted switch signal holding the high level at the reset terminal R and is not reset, and the clock signal changing from low to high to the clock terminal CK is input, And outputs the output of the first flip-flop that is the low-level input to the output terminal (D) to the output terminal (Q). In addition, the RS latch 440 outputs a high level because a low level is input to the reset terminal R and an inverted switch signal that is high level to the set terminal S is input. Therefore, the pulse skip detection signal maintains a high level.

At time t5, the clock signal is low and the switch signal changes from low to high. At this time, the first flip-flop 410 outputs a low level because the switch signal changing from low to high to the reset terminal R is inputted and reset. Further, the second flip-flop 430 outputs a low level because the inverted switch signal changing from high to low to the reset terminal R is input and reset. The RS latch 440 receives the output of the second flip-flop 430 which is low in the reset terminal R and receives the inverted switch signal of the low level in the set S, do. Therefore, the pulse skip detection signal maintains a high level.

At time t6, the clock signal is low and the switch signal changes from high to low. At this time, the first flip-flop 410 is not reset due to the input of the inverted switch signal that is high in the reset terminal R, and the clock signal of the low level is input to the clock terminal CK, . In addition, the second flip-flop 420 maintains the previous output, since the inverted switch signal that is low in the reset terminal R is not reset and the clock signal that is low in the clock terminal CK is input . In addition, the RS latch 440 receives the output of the second flip-flop 430, which is low in the reset terminal R, and outputs the high because the inverted switch signal that is high in the set S is input.

At time t7, the clock signal changes from low to high, and the switch signal is low. At this time, since the first flip-flop 410 receives a switch signal that is low in the reset terminal R and is not reset, and a clock signal that changes from low to high to the clock terminal CK is input, And outputs the input high as the output terminal (Q). The second flip-flop 430 receives the inverted switch signal that is high in the reset terminal R and is not reset. The clock signal changing from the low level to the high level is input to the clock terminal CK. And outputs the output of the first flip-flop 410, which is the low-level input signal, to the output terminal Q. The RS latch 440 receives the output of the second flip-flop 430 which is low in the reset terminal R and outputs a high because the inverted switch signal that is high in the set S is input. Thus, the pulse skip signal changes from low to high.

At time t8, the clock signal changes from high to low and the switch signal is low. At this time, since the first flip-flop 410 receives a switch signal that is low in the reset terminal R and is not reset, and a clock signal that changes from high to low in the clock terminal CK is input, . In addition, since the second flip-flop 430 receives the inverted switch signal that is high in the reset terminal R and is not reset, and the clock signal changing from high to low in the clock terminal CK is input, Lt; / RTI > In addition, the RS latch 440 receives the output of the second flip-flop 430, which is low in the reset terminal R, and outputs the high because the inverted switch signal that is high in the set S is input. Therefore, the pulse skip detection signal maintains a high level.

At time t9, the clock signal changes from low to high, and the switch signal is low. At this time, since the first flip-flop 410 receives a switch signal that is low in the reset terminal R and is not reset, and a clock signal that changes from low to high to the clock terminal CK is input, And outputs the input high as the output terminal (Q). The second flip-flop 430 receives the inverted switch signal that is high in the reset terminal R and is not reset. The clock signal changing from the low level to the high level is input to the clock terminal CK. And outputs the output of the first flip-flop 410 to the output terminal Q. In addition, the RS latch 440 receives the output of the second flip-flop 430, which is high in the reset terminal R, and outputs the low because the inverted switch signal, which is high in the set S, is input. Therefore, the pulse skip detection signal changes from high to low.

6 is a diagram showing a configuration of a module for adding a pulse width of a switch signal using a delayed switch signal.

6, the pulse width addition module 180 may include a delay logic 610, an AND gate 620, and an OR gate 630 that add the pulse width of the switch signal using the delayed switch signal . Delay logic 610 may delay the switch signal. Specifically, the delay logic 610 delays the switch signal by the time corresponding to the pulse width to be added. For example, to increase the pulse width of the switch signal to 1.5 times the original pulse width, the delay logic 610 delays the switch signal by 0.5 times the retention time of the pulse.

Hereinafter, the operation of the pulse width adding module 180 shown in FIG. 6 will be described with reference to FIG. The delay logic 610 delays the switch signal by a predetermined time. The AND gate 620 uses the delayed switch signal and the pulse skip detection signal (the output of the delay logic 610) (for convenience of description, the output of the pulse skip detection module 170 shown in FIG. 2 or 4 is inverted And outputs a signal dlay having a high value only at a time when both the delayed switch signal and the pulse skip detection signal are high. The OR gate 630 receives the output of the AND gate 620 and the switch signal and outputs a signal whose delay is delayed by the delay logic 610 in the pulse width of the first switch signal input after pulse skipping.

8 is a diagram illustrating a result of implementing a DC-DC converter according to an embodiment of the present invention with a BOOST converter.

Referring to FIG. 8, an output waveform (Original) of a DC-DC converter according to a conventional pulse skipping method and an output waveform of a DC-DC converter according to a pulse skipping method according to an embodiment of the present invention are shown have. Comparing the conventional pulse skipping method and the pulse skipping method according to the embodiment of the present invention, it can be seen that the number of switching times is remarkably reduced. Therefore, it is expected that the pulse skipping scheme according to the embodiment of the present invention has a reduction effect of the switching operation, as the number of switching times is reduced. Specifically, in the conventional pulse skipping method, 16 switching operations have occurred. However, it can be seen that seven switching operations have occurred in the pulse skipping method proposed in the present invention. However, in the pulse skipping method proposed in the present invention, the ripple phenomenon seems to be increased as compared with the conventional method, but this is merely an example for clearly showing the difference in the switching frequency. Therefore, the added pulse width (the delay time in the above- The ripple phenomenon can be removed to some extent.

The embodiments of the present invention have been described above. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

110: switching circuit
120: feedback gain module
130: Error amplifier
140: PWM module
150: Switch control logic
160: Switch driver
170: Pulse skip detection module
180: Pulse width addition module

Claims

A pulse skip detection module for detecting whether a pulse is skipped in a switch signal and outputting the detection result; And
And a pulse width addition module for increasing a width of a pulse input first after the pulse skip if a skip of a pulse is detected by the pulse skip detector,
To-DC converter.

The method according to claim 1,
Wherein the pulse skip detection module comprises:
A first flip-flop having an input terminal receiving the switch signal, a clock terminal receiving a clock signal,
The input terminal receives VDD, the inverting reset terminal receives the output of the first flip-flop, and the clock terminal receives the inverted signal of the switch signal.
To-DC converter.

The method according to claim 1,
Wherein the pulse skip detection module comprises:
A first flip-flop having an input terminal receiving VDD, a clock terminal receiving a clock signal, and a reset terminal receiving the switch signal;
A second flip-flop having an input terminal receiving the output of the first flip-flop, a clock terminal receiving the clock signal, and a reset terminal receiving the inverted signal of the switch signal; And
The reset terminal receives the output of the second flip-flop, and the reset terminal of the RS latch receives the inverted signal of the switch signal.
To-DC converter.

The method according to claim 1,
Wherein the pulse width adding module comprises:
An AND gate for receiving the delayed signal of the switch signal and the output of the pulse skip detection module; And
An OR gate for receiving the switch signal and the output of the AND gate,
To-DC converter.

A PWM module for generating a switch signal;
A pulse skip detection module for monitoring the switch signal to detect a pulse skip and outputting a pulse skip detection signal as a result of detection; And
A pulse width addition module for outputting a signal obtained by increasing the pulse width of the switch signal by the delay time based on the switch signal and the delay signal obtained by delaying the switch signal by a predetermined time,
To-DC converter.

6. The method of claim 5,
In the pulse skip detection module,
A first flip-flop having an input terminal receiving the switch signal and a clock terminal receiving a clock signal;
An inverter for inverting the switch signal; And
The input terminal receives VDD, the inverting reset terminal receives the output of the first flip-flop, the clock terminal receives the output of the inverter,
To-DC converter.

6. The method of claim 5,
Wherein the pulse skip detection module comprises:
A first flip-flop having an input terminal receiving VDD, a reset terminal receiving the switch signal, and a clock terminal receiving a clock signal;
An inverter for inverting the switch signal;
A second flip-flop having an input terminal receiving the output of the first flip-flop, a reset terminal receiving the output of the inverter, and a clock terminal receiving the clock signal; And
The reset receives the output of the second flip-flop, and the reset terminal receives the output of the inverter,
To-DC converter.

6. The method of claim 5,
Wherein the pulse width adding module comprises:
A delay logic for delaying the switch signal by a predetermined time;
An AND gate receiving the output of the delay logic and the pulse skip detection signal; And
An OR gate for receiving the switch signal and the output of the AND gate,
To-DC converter.

An error amplifier for comparing the reference voltage with the output of the DC-DC converter;
A PWM module for generating a switch signal by adjusting a pulse width based on a comparison result of the error amplifier;
A pulse skip detection module for detecting whether or not the switch signal is skipped based on a clock signal and outputting a pulse skip detection signal; And
A pulse width addition module for increasing a width of a first pulse of the switch signal after the pulse skip;
To-DC converter.

10. The method of claim 9,
Wherein the pulse skip detection module comprises:
A first flip-flop for receiving the switch signal and a clock terminal for receiving the clock signal, the first flip-flop being triggered at a rising edge of a signal input to the clock terminal;
A clock terminal for receiving the inverted signal of the switch signal, and a clock terminal for receiving the inverted signal of the switch signal and for triggering at the rising edge of the signal input to the clock terminal, wherein the input terminal receives VDD, the inverted reset terminal receives the output of the first flip- 2 flip-flop
To-DC converter.

10. The method of claim 9,
Wherein the pulse skip detection module comprises:
A first flip-flop having an input terminal receiving VDD, a clock terminal receiving a clock signal, a reset terminal receiving the switch signal and being reset at a rising edge of a signal input to the reset terminal;
A reset terminal for receiving the inverted signal of the switch signal, and a reset terminal for receiving a reset signal at a falling edge of a signal input to the reset terminal, wherein the input terminal receives the output of the first flip- Flip flop; And
The reset terminal receives the output of the second flip-flop, and the third terminal receives the inverted signal of the switch signal.
To-DC converter.

10. The method of claim 9,
Wherein the pulse width adding module comprises:
A delay logic for delaying the switch signal by a predetermined time;
An AND gate for receiving the delayed signal of the switch signal and the pulse skip detection signal; And
An OR gate for receiving the switch signal and the output of the AND gate,
To-DC converter.