KR20170042451A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a three-dimensional semiconductor memory element and a manufacturing method thereof. The semiconductor element comprises: a first laminated structure having first insulating films and first gate electrodes alternately and repeatedly laminated on a substrate, wherein the first laminated structure has a first area and a second area spaced apart from the first area in one direction; and a channel structure vertically extended in the first area of the first laminated structure. The second area has a stepped structure. In the second area, one end of at least one of the first gate electrodes includes a first sidewall and each one end of the other first gate electrodes includes a second sidewall inclined more steeply than the first sidewall.

Description

TECHNICAL FIELD The present invention relates to a semiconductor device and a manufacturing method thereof,

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device and a manufacturing method thereof.

It is required to increase the degree of integration of semiconductor devices in order to satisfy excellent performance and low price required by consumers. In the case of a semiconductor memory device, the degree of integration is an important factor for determining the price of the product, and thus an increased degree of integration is required. In the case of a conventional two-dimensional or planar semiconductor memory device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor memory device is increasing, but it is still limited, because it requires expensive equipment to miniaturize the pattern.

In order to overcome such limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, a process technology capable of reducing the manufacturing cost per bit of the two-dimensional semiconductor memory device and realizing a reliable product characteristic is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that can reduce process risks.

According to the concept of the present invention, a semiconductor device includes a first laminate structure including first insulating films and first gate electrodes alternately and repeatedly stacked on a substrate, the first laminate structure includes a first region, A second region spaced apart in one direction; And a channel structure extending perpendicularly within the first region of the first laminate structure. Wherein the second region has a stepped structure, and in the second region, at least one end of the first gate electrodes includes a first sidewall, and in the second region, one end of each of the other first gate electrodes May include a second sidewall having a steeper slope than the first sidewall.

In view of one cross section in one direction, a first line and an upper surface of the first insulating film below the at least one first gate electrodes form a first angle, and one cross section in the one direction The second line and the upper surface of the first insulating film below each of the other first gate electrodes form a second angle and the first line is a line connecting the upper portion and the lower portion of the first sidewall And the second line is a line connecting the upper portion and the lower portion of the second sidewall, and the second angle may be larger than the first angle.

The first angle may be between 30 [deg.] And 85 [deg.].

The at least one first gate electrodes may comprise a top first top gate electrode and the other first gate electrodes may comprise first bottom gate electrodes below the first top gate electrode.

Wherein the at least one first gate electrode comprises a first pad portion extending in the one direction and the length in the one direction of the first pad portion is at least equal to a distance from the top of the first pad portion to the bottom It can increase gradually.

In another embodiment of the present invention, in the second region, the first gate electrodes include second pad portions extending in the first direction, and the first gate electrodes extend through the first insulating layers, As shown in FIG.

The semiconductor device may further include a second stacked structure including second insulating films and second gate electrodes alternately and repeatedly stacked on the first stacked structure. Wherein the second laminate structure includes a third region and a fourth region spaced in the first direction and the channel structure further extends vertically into the third region of the second laminate structure, Wherein at least one of the second gate electrodes comprises a third sidewall, and in the fourth region, one end of each of the other second gate electrodes has a stepped structure, And a fourth sidewall having a slope that is more urgent than the third sidewall.

The third sidewall may have substantially the same slope as the first sidewall.

The number of the first gate electrodes and the number of the second gate electrodes may be the same.

The at least one second gate electrodes may comprise a top second top gate electrode and the other second gate electrodes may comprise second bottom gate electrodes below the second top gate electrode.

The semiconductor device may further include a gate insulating film interposed between the first gate electrodes and the channel structure.

The first laminated structure may be provided in a plurality, and the plurality of first laminated structures may extend in parallel with each other in the one direction.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a laminate structure including insulating films and gate electrodes alternately and repeatedly stacked on a substrate, the laminate structure including a cell array region and a contact region / RTI > And a channel structure that is connected to the substrate through the cell array region of the laminated structure. Wherein at least one of the gate electrodes has a first pad portion extending in the one direction and the length of the first pad portion in the one direction is gradually increased from the upper portion of the first pad portion to the lower portion thereof, can do.

The first line and the upper surface of the insulating film below the first pad portion form a first angle, and the first line is a line connecting the first line of the first sidewall of the one end of the first pad portion And the first angle may be between 30 [deg.] And 85 [deg.].

The at least one gate electrode may comprise a top gate electrode.

The gate electrode of each of the first and second pad portions has a first pad portion and a second pad portion. In the contact region, the gate electrodes other than the at least one gate electrode each have second pad portions, It may have a gentler slope than the side wall.

The at least one gate electrode may be two or more, and a plurality of other gate electrodes may be interposed between the at least one gate electrode.

The contact region may have a stepped structure.

The semiconductor device may further include a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially interposed between the channel structure and the gate electrodes.

According to still another aspect of the present invention, a method of manufacturing a semiconductor device includes forming a laminated structure including insulating films and sacrificial films alternately and repeatedly stacked on a substrate; Forming a mask pattern on the laminated structure; And etching the one end of the stacked structure using the mask pattern as an etching mask to form the one end in a stepped structure. Forming the stepped structure with the stepped structure comprises repeating the cycle by performing the following steps in one cycle: using the mask pattern as an etch mask, removing at least one of the insulating films exposed by the mask pattern Performing a first etching process for etching; Performing a second etch process to etch at least one of the sacrificial layers beneath the at least one insulating layer; And trimming the mask pattern to reduce its width and height, the second etch process of at least one cycle may have a lower etch rate for the sacrificial films than the second etch process of another cycle.

Wherein the at least one cycle is a last performed cycle and during the second etching process of the at least one cycle the topmost sacrificial film is formed such that one end of the sacrificial film has a first sidewall, The films may be formed such that one ends thereof each have second sidewalls, and the first sidewalls may have a gentler slope than each of the second sidewalls.

The second etch process of the at least one cycle may have a higher etch selectivity ratio of the sacrificial films to the insulating films than the second etch process of the other cycles.

During the repetition of the cycle, the exposed upper portions of the insulating films can be recessed.

 During the first etching process of the at least one cycle, the tops of the sacrificial films beneath the exposed insulating films may be recessed.

The cycle can be repeated until the insulating film at the lowermost stage and the sacrificial film at the lowermost stage are etched.

The manufacturing method includes: forming channel holes through the cell array region of the laminated structure to expose the substrate; And sequentially forming, in each of the channel holes, a gate insulating film and a channel film covering the inner wall thereof.

The manufacturing method may further include selectively removing the sacrificial layers to form recessed regions between the insulating films; And forming gate electrodes filling the recessed regions.

The semiconductor device and the method of manufacturing the same according to the present invention can lower the etching rate of the etching process of the last cycle in the cycle process for forming one end of the laminated structure in a stepwise structure to reduce the risk of the process and form a normal stepped structure . Thus, the sidewalls of the at least one gate electrode of the semiconductor device according to the present invention may have a gentler slope than the sidewalls of the other gate electrodes.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIG. 3A is a cross-sectional view of a semiconductor memory device according to embodiments of the present invention, taken along line I-I 'of FIG. 2. FIG.
FIG. 3B is an example of an enlarged sectional view of the area M of FIG. 3A, and FIG. 3C is another example of an enlarged sectional view of the area M of FIG.
FIGS. 4 to 26 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method for fabricating a three-dimensional semiconductor memory device according to embodiments of the present invention.
27 is a cross-sectional view taken along line I-I 'of FIG. 2 for explaining a method of manufacturing a three-dimensional semiconductor memory device for comparison with the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention includes a common source line CS, a plurality of bit lines BL, And a plurality of cell strings CSTR disposed between the plurality of cell strings BL.

The common source line CS may be an electrically conductive thin film disposed on the substrate or an impurity region formed in the substrate. In the present embodiments, the common source line CS may be conductive patterns (e.g., metal lines) spaced from the substrate and disposed on the substrate. The bit lines BL may be conductive patterns (e.g., metal lines) spaced from the substrate and disposed on the substrate. In the present embodiments, the bit lines BL may be vertically spaced apart from the common source line CS. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel. The cell strings CSTR may be connected in common to the common source line CS. That is, a plurality of the cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CS. According to one embodiment, the common source lines CS are provided in plural and can be two-dimensionally arranged. Here, electrically the same voltage may be applied to the common source lines CS, or each of the common source lines CS may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CS, a string selection transistor SST connected to the bit line BL, And a plurality of memory cell transistors MCT arranged between the memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CS may be connected in common to the sources of the ground selection transistors GST. In addition, a lower select line LSL, a plurality of word lines WL0-WL5 and an upper select line USL, which are disposed between the common source line CS and the bit lines BL, May be used as the gate electrodes of the selection transistor GST, the memory cell transistors MCT and the string selection transistor SST, respectively. In addition, each of the memory cell transistors MCT may include a data storage element.

2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 3A is a cross-sectional view of a semiconductor memory device according to embodiments of the present invention, taken along line I-I 'of FIG. 2. FIG. FIG. 3B is an example of an enlarged sectional view of the area M of FIG. 3A, and FIG. 3C is another example of an enlarged sectional view of the area M of FIG.

Referring to FIGS. 2 and 3A, a substrate 100 may be provided. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include common source regions (CSL) doped with impurities. The common source regions CSL may have a line shape extending in a second direction D2 parallel to the upper surface of the substrate 100. [ The common source regions CSL may be arranged along a first direction D1 that intersects the second direction D2.

The first stacked structures ST1 and the second stacked structures ST2 in which the insulating films 110 and the gate electrodes WLb1, WLa1, WLb2, and WLa2 are alternately and repeatedly stacked on the substrate 100, Can be arranged. Each of the first lamination structures ST1 may include first gate electrodes WLb1 and WLa1 and each of the second lamination structures ST2 may include second gate electrodes WLb2 and WLa2. . ≪ / RTI > The second lamination structures ST2 may be disposed on the first lamination structures ST1, respectively. Each of the stacked structures ST1 and ST2 may have a line shape extending in the second direction D2 from a plan viewpoint. Each of the stacked structures ST1 and ST2 may be arranged along the first direction D1.

The common source regions CSL may be disposed on the substrate 100 between the stacked structures ST1 and ST2. A lower insulating layer 105 may be disposed between the substrate 100 and the first stacked structures ST1. The lower insulating layer 105 may include, for example, a high dielectric constant layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may have a thickness smaller than that of the insulating layers 110.

The gate electrodes WLb1, WLa1, WLb2 and WLa2 may be stacked along a third direction D3 which is perpendicular to the first direction D1 and the second direction D2. The gate electrodes WLb1, WLa1, WLb2, and WLa2 may be vertically separated from each other by the insulating films 110 disposed therebetween. The first gate electrodes WLb1 and WLa1 may include a first upper gate electrode WLa1 at the uppermost stage and first lower gate electrodes WLb1 under the first upper gate electrode WLa1 . The first lower gate electrode WLb1 at the lowermost stage may be a lower select line LSL. The second gate electrodes WLb2 and WLa2 may include a second upper gate electrode WLa2 at the uppermost stage and second lower gate electrodes WLb2 under the second upper gate electrode WLa2 . The second upper gate electrode WLa2 may be an upper select line USL. In one example, the gate electrodes WLb1, WLa1, WLb2, and WLa2 may comprise doped silicon, metal (e.g., tungsten), metal nitride, metal silicides, or combinations thereof. The insulating films 110 may include a silicon oxide film.

The lower selection line LSL may be used as the gate electrode of the ground selection transistor GST described above with reference to FIG. The upper selection line USL may be used as a gate electrode of the string selection transistor SST described above with reference to FIG. The gate electrodes WLb1, WLa1 and WLb2 except for the lower and upper select lines LSL and USL may be used as the word lines of the memory cell transistors MCT described with reference to Fig. 1 .

Each of the stacked structures ST1 and ST2 may include a cell array region CAR, a first contact region CTR1, and a second contact region CTR2. The first and second contact regions CTR1 and CTR2 may be disposed at at least one end of the stacked structure ST1 and ST2. The first contact region CTR1 may be a region of one end of the first lamination structure ST1 and the second contact region CTR2 may be a region of a first end of the second lamination structure ST2. have. For example, the second contact region CTR2 may be adjacent to the cell array region CAR. The first contact region CTR1 may be spaced apart from the cell array region CAR via the second contact region CTR2. The cell array area CAR, the second contact area CTR2, and the first contact area CTR1 may be arranged in the second direction D2.

Each of the stacked structures ST1 and ST2 is electrically connected to the first and second contact regions CTR1 and CTR2 for electrical connection between the gate electrodes WLb1, WLa1, WLb2 and WLa2 and the peripheral logic structure. CTR2). ≪ / RTI > That is, the vertical height of the first and second contact regions CTR1 and CTR2 may gradually increase as the cell array region CAR is adjacent to the first and second contact regions CTR1 and CTR2. In other words, the stacked structures ST1 and ST2 may have a sloped profile in the first and second contact regions CTR1 and CTR2.

As the first gate electrodes WLb1 and WLa1 of the first contact region CTR1 are away from the upper surface of the substrate 100 in the third direction D3, the planar area of the first gate electrodes WLb1 and WLa1 may be reduced . Therefore, the area of the lower selection line LSL of the lowermost one of the first gate electrodes WLb1 and WLa1 may be the largest. As the second gate electrodes WLb2 and WLa2 of the second contact region CTR2 are away from the upper surface of the substrate 100 in the third direction D3, their planar area can be reduced . Therefore, the area of the upper select line USL at the uppermost one of the second gate electrodes WLb2 and WLa2 may be the smallest.

A first interlayer insulating layer 180 may be disposed on the entire surface of the substrate 100 to cover the stacked structures ST1 and ST2. The first interlayer insulating layer 180 has a planarized upper surface and may cover the first and second contact regions CTR1 and CTR2. A second interlayer insulating film 190 may be disposed on the first interlayer insulating film 180.

A plurality of channel structures passing through the cell array region CAR of the stacked structures ST1 and ST2 may be disposed. The channel structures may include a plurality of channel films 135, respectively. More specifically, a plurality of channel holes CH may pass through the cell array region CAR of the stacked structures ST1 and ST2, and the channel films 135 may pass through the inner walls of the channel holes CH, And may extend toward the substrate 100. The channel layers 135 may be electrically connected to the substrate 100. That is, the channel films 135 may be in direct contact with the upper surface of the substrate 100. From a plan viewpoint, the channel films 135 may be arranged along the second direction D2. For example, the channel films 135 may be arranged in a line along the second direction D2. As another example, the channel films 135 may be arranged in a zigzag manner along the second direction D2.

The channel films 135 may be in the form of open pipes or macroscopic top and bottom. As another example, although not shown, the channel films 135 may be in the form of a closed pipe or macaroni at the bottom.

The channel films 135 may be in an unselected state or may be doped with an impurity having the same conductivity type as the substrate 100. The channel layers 135 may include a semiconductor material having a polycrystalline structure or a single crystal structure. As an example, the channel films 135 may comprise silicon. The inside of the channel films 135 may be filled with a buried insulating pattern 150. For example, the buried insulation pattern 150 may include a silicon oxide layer.

Gate insulating films 145 may be interposed between the gate electrodes WLb1, WLa1, WLb2, and WLa2 and the channel films 135. [ That is, each of the gate insulating films 145 may directly cover the inner wall of the channel hole CH. The gate insulating films 145 may extend along the third direction D3. The gate insulating films 145 may be formed in a pipe shape or a macaroni shape with open upper and lower ends.

Each of the gate insulating films 145 may include one thin film or a plurality of thin films. In one embodiment, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer of a charge trap type flash memory transistor. The tunnel insulating film may be one of materials having a band gap larger than that of the charge storage film. For example, the tunnel insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film. The charge storage film may be one of an insulating film rich in trap sites such as a silicon nitride film, a floating gate electrode, or an insulating film including conductive nano dots. The tunnel insulating layer may contact the channel layer 135 directly. Although not shown, a blocking insulating film may be interposed between each of the gate electrodes WLb1, WLa1, WLb2 and WLa2 and the charge storage film. The blocking insulating layer may extend between each of the gate electrodes WLb1, WLa1, WLb2, and WLa2 and the insulating layer 110. The blocking insulating layer may be one of materials having a smaller band gap than the tunnel insulating layer and a band gap larger than that of the charge storage layer. For example, the blocking insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film.

In another embodiment, each of the gate insulating films 145 may include the tunnel insulating film, the charge storage film, and the blocking insulating film. The tunnel insulating layer may directly contact the channel layer 135, and the blocking insulating layer may directly contact the gate electrodes WLb1, WLa1, WLb2, and WLa2. The charge storage film may be interposed between the tunnel insulating film and the blocking insulating film. At this time, the gate electrodes WLb1, WLa1, WLb2, and WLa2 may be in direct contact with the insulating films 110. [

The buried insulating film 170 can fill the trenches TR between the adjacent stacked structures ST1 and ST2. The buried insulating layer 170 may include a silicon oxide layer.

An upper portion of each of the channel films 135 may include a drain region DR. Conductive pads 160 that are in contact with the drain regions DR of the channel films 135 may be disposed. The second interlayer insulating layer 190 may cover the conductive pads 160. Bit line plugs (BPLG) that are electrically connected to the conductive pads 160 through the second interlayer insulating layer 190 may be disposed. The bit lines BL may be disposed on the bit line plugs BPLG. Each of the bit lines BL may be electrically connected to the plurality of conductive pads 160 through a plurality of the bit line plugs BPLG. The bit lines BL may be in the form of a line extending in the first direction D1.

A wiring structure for electrically connecting the gate electrodes WLb1, WLa1, WLb2, and WLa2 to the peripheral logic structure may be disposed on the first and second contact regions CTR1 and CTR2.

Specifically, the first contact region CTR1 is formed with a first contact hole 171 which is connected to one ends of the first gate electrodes WLb1 and WLa1 through the first and second interlayer insulating films 180 and 190, The plugs PLG1 may be disposed. The second contact region CTR2 is formed with a second contact hole 182 which is connected to one ends of the second gate electrodes WLb2 and WLa2 through the first and second interlayer insulating films 180 and 190, The plugs PLG2 may be disposed. The vertical lengths of the first and second contact plugs PLG1 and PLG2 can be reduced as they are adjacent to the cell array region CAR. The upper surfaces of the first and second contact plugs PLG1 and PLG2 may be coplanar.

In addition, first connection lines CL1 electrically connected to the first contact plugs PLG1 may be disposed on the second interlayer insulating film 190 of the first contact region CTR1. Second connection lines CL2 electrically connected to the second contact plugs PLG2 may be disposed on the second interlayer insulating layer 190 of the second contact region CTR2.

Referring to FIGS. 3A and 3B, one end of the first upper gate electrode WLa1 of the first contact region CTR1 may have a first sidewall SW1. The one end of the first upper gate electrode WLa1 may be adjacent to the first contact plug PLG1 connected to the first upper gate electrode WLa1. One ends of the first lower gate electrodes WLb1 of the first contact region CTR1 may have second sidewalls SW2, respectively. The first sidewall (SW1) may have a gentle slope, and each of the second sidewalls (SW2) may have a vertical slope. Therefore, the first sidewall (SW1) may have a gentler slope than each of the second sidewalls (SW2).

One end of the second upper gate electrode WLa2 of the second contact region CTR2 may have a third sidewall SW3. One ends of the second bottom gate electrodes WLb2 of the first contact region CTR1 may have fourth sidewalls SW4, respectively. The third sidewall SW3 may have a gentle slope, and each of the fourth sidewalls SW4 may have a vertical slope. Therefore, the third side wall SW3 may have a gentler inclination than each of the fourth side walls SW4. Meanwhile, the third sidewall (SW3) may have substantially the same slope as the first sidewall (SW1).

3B, the second upper gate electrode WLa2 in the second contact region CTR2 may have a first pad portion CTP1 extending in the second direction D2. And the second contact plug PLG2 may be directly connected to the first pad portion CTP1. Each of the second lower gate electrodes WLb2 in the second contact region CTR2 may have a second pad portion CTP2 extending in the second direction D2, PLG2 may be directly connected to the second pad portion CTP2.

The inclination of the third sidewall (SW3) of the first pad portion (CTP1) may have a first angle (? 1). Specifically, in view of one cross section in the second direction D2, a first line SWL1 connecting the upper portion and the lower portion of the third sidewall SW3 may be provided. The angle formed by the first line SWL1 with the upper surface of the insulating film 110 under the second upper gate electrode WLa2 may be the first angle? 1. The upper surface of the insulating layer 110 may be substantially parallel to the upper surface of the substrate 100. Here, the first angle? 1 may be smaller than 90 °, and more specifically, the first angle? 1 may be 30 ° to 85 °. On the other hand, the inclination of the fourth sidewall SW4 of the second pad portion CTP2 may be substantially perpendicular (about 90 degrees).

Since the first angle? 1 is smaller than 90 degrees, the width of the first pad portion CTP1 in the second direction D2 may gradually increase from the upper portion to the lower portion thereof. For example, an upper portion of the first pad portion CTP1 may have a first length W1 in the second direction D2, and a lower portion of the first pad portion CTP1 may have a second length D2 ) And a second length W2. At this time, the second length W2 may be greater than the first length W1.

As another example, referring to FIG. 3C, the slope of the fourth sidewall SW4 of the second pad portion CTP2 may have a second angle? 2. Specifically, from the viewpoint of one cross section in the second direction D2, a second line SWL2 connecting the upper portion and the lower portion of the fourth sidewall SW4 may be provided. The angle formed between the second line SWL2 and the upper surface of the insulating film 110 under the second lower gate electrode WLb2 may be the second angle? 2. Here, the second angle? 2 may be larger than the first angle? 1. More specifically, the second angle? 2 may be 80 ° to 90 °.

Although not shown, the first upper gate electrode WLa1 in the first contact region CTR1 may have a third pad portion, and each of the first lower gate electrodes WLb1 may have a fourth pad portion . The structural features of the third pad portion and the fourth pad portion may be similar to those of the first pad portion CTP1 and the second pad portion CTP2 described above with reference to FIGS. 3B and 3C have.

FIGS. 4 to 26 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method for fabricating a three-dimensional semiconductor memory device according to embodiments of the present invention. 27 is a cross-sectional view taken along line I-I 'of FIG. 2 for explaining a method of manufacturing a three-dimensional semiconductor memory device for comparison with the present invention.

2 and 4, the sacrificial layers HLb1, HLa1, HLb2, and HLa2 and the insulating films 110 are alternately and repeatedly deposited on the substrate 100 to form the stacked structures ST1 and ST2 . Specifically, the stacked structures ST1 and ST2 may include a first stacked structure ST1 on the substrate 100 and a second stacked structure ST2 on the first stacked structure ST1. The first laminated structure ST1 may include first sacrificial layers HLb1 and HLa1 and the second laminated structure ST2 may include second sacrificial layers HLb2 and HLa2.

The first sacrificial layers HLb1 and HLa1 may include a first upper sacrificial layer HLa1 at the uppermost stage and first lower sacrificial films HLb1 under the first upper sacrificial film HLa1. The second sacrificial layers HLb2 and HLa2 may include a second upper sacrificial layer HLa2 at the uppermost stage and second lower sacrificial films HLb2 under the second upper sacrificial film HLa2.

For example, the sacrificial layers (HLb1, HLa1, HLb2, HLa2) may be formed to have the same thickness. As another example, the lower first sacrificial layer HLb1 and the second upper sacrificial layer HLa2 of the sacrificial layers HLb1, HLa1, HLb2, and HLa2 may be formed of sacrificial layers HLb1 , HLa1, HLb2). The insulating films 110 may have the same thickness or a part of the insulating films 110 may have different thicknesses.

The sacrificial layers HLb1, HLa1, HLb2 and HLa2 and the insulating films 110 may be formed by thermal CVD, plasma enhanced chemical vapor deposition (CVD), physical chemical vapor deposition May be deposited using an Atomic Layer Deposition (ALD) process. The sacrificial layers (HLb1, HLa1, HLb2, HLa2) may be formed of a silicon nitride film, a silicon oxynitride film, or a silicon film. The sacrificial layers (HLb1, HLa1, HLb2, HLa2) may include a polycrystalline structure or a single crystal structure. The insulating films 110 may be formed of a silicon oxide film.

In addition, a lower insulating layer 105 may be formed between the substrate 100 and the first stacked structure ST1. The lower insulating layer 105 may be formed of a material having a high selectivity to the sacrificial layers HLb1, HLa1, HLb2, HLa2, and the insulating layers 110. [ For example, the lower insulating layer 105 may include a high-k dielectric layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may be formed to have a thickness smaller than that of the sacrificial layers HLb1, HLa1, HLb2, and HLa2 and the insulating layers 110. [

Referring to FIGS. 2 and 5, channel holes CH may be formed to expose the substrate 100 through the stacked structures ST1 and ST2. The channel holes CH may be disposed in the same manner as the channel structures (i.e., the channel films 135) described above with reference to FIGS. 2 and 3.

The formation of the channel holes CH may be performed by forming a mask pattern having openings defining regions in which the channel holes CH are to be formed on the stacked structures ST1 and ST2, And etching the stacked structures ST1 and ST2 with a mask. Thereafter, the mask patterns can be removed. Meanwhile, during the etching process, the upper surface of the substrate 100 may be over-etched. Thus, although not shown, the top surface of the substrate 100 can be recessed.

2 and 6, a gate insulating layer 145 and a channel layer 135 may be formed to sequentially cover the inner wall of each of the channel holes CH. For example, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer. As another example, the gate insulating layer 145 may further include a blocking insulating layer. At this time, the blocking insulating film may be interposed between the sacrificial films (HLb1, HLa1, HLb2, HLa2) and the charge storage film. The gate insulating layer 145 and the channel layer 135 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD), respectively. Then, a buried insulation pattern 150 filling the respective channel holes CH may be formed.

Referring to FIGS. 2 and 7, a first photoresist pattern PR1 may be formed on the second stack structure ST2. The first photoresist pattern PR1 may be formed on the cell array region CAR where the channel films 135 are located and on the second contact region CTR2 adjacent to the cell array region CAR. have. The first photoresist pattern PR1 may expose a first contact region CTR1 spaced apart from the cell array region CAR via the second contact region CTR2.

Specifically, the first photoresist pattern PR1 is formed by preparing a photoresist composition, applying the photoresist composition on the entire surface of the substrate 100 to form a photoresist film, And then exposing and developing the photoresist film to form the first photoresist pattern PR1.

Referring to FIGS. 2 and 8, the insulating film 110 and the second upper sacrificial layer HLa2 at the uppermost portion of the second contact region CTR2 are sequentially formed using the first photoresist pattern PR1 as an etch mask . ≪ / RTI > The process of etching the insulating layer 110 may be a first etching process, and the process of etching the second upper sacrificial layer HLa2 may be a second etching process. A detailed description of the first and second etching processes will be described later. The etched insulating layer 110 and the etched second upper sacrificial layer HLa2 may expose the lower insulating layer 110 and the second lower sacrificial layer HLb2.

Referring to FIGS. 2 and 9, a trimming process may be performed on the first photoresist pattern PR1. That is, an isotropic etching process may be performed on the first photoresist pattern PR1. Thus, the width and height of the first photoresist pattern PR1 can be reduced. Specifically, during the trimming process, the width of the first photoresist pattern PR1 may be reduced by a first length T1 and the height may be reduced by a second length T2.

The trimming process may be performed using an etchant capable of selectively removing the first photoresist pattern PR1. The length of the first photoresist pattern PR1 may be greater than the length of the first photoresist pattern PR1 where the width of the first photoresist pattern PR1 is reduced. This is because the area of the top surface of the first photoresist pattern PR1 is larger than the surface area of the sidewalls of the first photoresist pattern PR1. Thus, the reduced second length T2 during the trimming process may be greater than the first length T1.

The steps described above with reference to FIGS. 8 and 9 may constitute one cycle for forming the sidewalls of the second contact region CTR2 in a stepped structure. That is, the cycle is performed by etching at least one of the insulating films 110 exposed by the first photoresist pattern PR1 (first etching step) using the first photoresist pattern PR1 as a mask, Etching at least one of the second sacrificial layers HLb2 and HLa2 exposed by the etched at least one insulating film 110 (second etching process), and etching the first photoresist pattern PR1 ) To reduce its width and height. The repetition of the cycle is described in detail below.

Referring to FIGS. 2 and 10, the uppermost insulating layer 110 may be etched using the first photoresist pattern PR1 reduced in size by an etching mask. At the same time, the underlying insulating layer 110 exposed by the second upper sacrificial layer HLa2 may be etched together (first etching process). Then, the second upper sacrificial layer HLa2 may be etched using the first photoresist pattern PR1 as an etch mask. At the same time, the second lower sacrificial layer HLb2 exposed by the second upper sacrificial layer HLa2 may be etched together (second etching process). The etched insulating films 110 and the etched second upper sacrificial film HLa2 and the second lower sacrificial film HLb2 are etched by using the other insulating film 110 and the other second lower sacrificial film HLb2, .

Referring to FIGS. 2 and 11, the trimming process may be performed again on the first photoresist pattern PR1. During the trimming process, the width of the first photoresist pattern PR1 may be reduced by the first length T1 and the height may be reduced by the second length T2. This confirms that the cycle is repeated once more.

Referring to FIGS. 2 and 12, as the cycle is repeated, one end of the second stacked structure ST2 (i.e., the second contact region CTR2) may have a stepped structure. In addition, the size of the first photoresist pattern PR1 can be reduced due to the repeated trimming process.

Meanwhile, the first etching process for the insulating films 110 performed for each cycle and the second etching process for the second sacrificial films (HLb2, HLa2) are repeated, and the first photoresist pattern The upper portions of the insulating films 110 exposed by the first conductive film PR1 may be over-deflected. Therefore, the first recesses RC1 may be formed on the upper portions of the exposed insulating layers 110, respectively.

Referring to FIGS. 2 and 13, the trimming process may be performed on the first photoresist pattern PR1. Thereafter, the first etching process ET1 for etching the insulating films 110 exposed by the first photoresist pattern PR1 may be performed. On the other hand, the exposed insulating films 110, which are made thinner by the first recesses RC1, are immediately removed, and the upper portions of the second lower sacrificial layers HLb2 below them are over- . Thus, second recesses RC2 may be formed on upper portions of the second lower sacrificial layers HLb2, respectively.

A description will now be made of a process problem that may occur when the second etching process ET2 is performed as it is after the first etching process ET1 on the result of FIG. Referring to FIGS. 2 and 27, the second etching process ET2 for etching the second sacrificial films HLb2 and HLa2 exposed by the first photoresist pattern PR1 may be performed.

Specifically, the second etching process ET2 may use plasma dry etching using an etching gas capable of etching the second sacrificial films HLb2 and HLa2. In one embodiment, the second case is formed of a sacrificial layer in (HLb2, HLa2) is silicon nitride and / or silicon oxy-nitride film, the etching gas from the group consisting of CH ₃ F, CH ₂ F _2, CF ₄ and SF ₆ And may include at least one etch component selected. The etching component may etch the silicon nitride film and / or the silicon oxynitride film. Further, the etching component can also etch the silicon oxide film (the insulating films 110) having lower physico-chemical resistance than the silicon nitride film. However, it is possible to increase the etch selectivity for the second sacrificial films (HLb2, HLa2) by controlling the ratio of the etching component in the etching gas.

On the other hand, the exposed second lower sacrificial layers HLb2 thinned by the second recesses RC2 can be removed immediately, and all of the insulating films 110 under the exposed second sacrificial layers HLb2 can be removed. This is because the etching gas of the second etching process ET2 described above can etch the insulating films 110 as well. Further, upper portions of the second lower sacrificial layers HLb2 under the removed insulating films 110 are etched at an overgrowth angle to form upper portions of the second lower sacrificial layers HLb2, May be formed. Also, the third recess RC3 may be formed on the first upper sacrificial layer HLa1 of the first contact region CTR1.

That is, as a result of repeating the cycle process as it is, the second lower sacrificial layers HLb2 can be removed without remaining the insulating films 110 to be protected. And the third recesses RC3 may be formed in the second lower sacrificial layers HLb2. As a result, when the second lower sacrificial layers HLb2 are replaced with the second lower gate electrodes WLb2, the second bottom gate electrodes WLb2 are properly formed in the second contact region CTR2 It may not be possible.

As a result of repeating the cycle process as it is, the insulating film 110 on the first upper sacrificial layer HLa1 can be removed without being remained, thereby exposing the first upper sacrificial layer HLa1. In this case, another cycle process, which will be described later, can not be performed properly, and a stepped structure in the first contact region CTR1 may not be normally formed.

To solve the process problem described above with reference to FIG. 27, embodiments of the present invention may replace the second etching process ET2 of the last cycle with the modified second etching process ET2 '. Referring to FIGS. 2 and 14, the modified second etching process ET2 'may be performed on the result of FIG. That is, the second sacrificial layers HLb2 and HLa2 exposed by the first photoresist pattern PR1 may be selectively etched.

The modified second etch process ET2 'may have a lower etch rate for the second sacrificial films HLb2 and HLa2 than the second etch process ET2 described above with reference to FIG. In detail, the modified second etching process ET2 'may use a plasma dry etching process using an etching gas. For example, the etching gas may include CH ₃ F, CH ₂ F ₂ , CF _4, and SF ₆ At least one etch component selected from < RTI ID = 0.0 > However, unlike the second etching process ET2, the etching rate for the second sacrificial films HLb2 and HLa2 can be lowered by further reducing the etching component ratio and increasing the ratio of other components in the etching gas . As a result, the modified second etch process ET2 'has a longer etch time and a lower etch straightness (anisotropic etch) than the second etch process ET2 (reduction in etch efficiency). However, since the modified second etch process ET2 'has a lower etch rate with respect to the silicon oxide film (the insulating films 110) than the second etch process ET2, the second sacrificial films HLb2, HLa2) can be increased.

Through the modified second etching process ET2 ', the exposed second lower sacrificial layers HLb2, which are made thinner by the second recesses RC2, can not be removed immediately and can be removed slowly . In addition, due to the improved etch selectivity, it is possible to prevent the underlying insulating films 110 from being etched together, and the insulating films 110 can remain as they are.

Since the modified second etching process ET2 'is inferior in the etching straightness, the second upper sacrificial layer HLa2 which has been exposed to the full thickness has a gentle slope after the modified second etching process ET2' And a fifth side wall SW5. Since the exposed second sacrificial layers HLb2 have a relatively thin thickness, the sixth sidewalls SW6 having a substantially vertical gradient even after the modified second etching process ET2 ' Lt; / RTI > That is, the fifth sidewall SW5 may have a gentler inclination than each of the sixth sidewalls SW6.

As a result, according to the embodiments of the present invention, the process problems described above with reference to FIG. 27 can be solved by introducing the modified second etching process ET2 'in the last cycle. That is, since the second lower sacrificial layers HLb2 are protected while the insulating films 110 are normally left, the second lower gate electrodes WLb2 are normally formed in the second contact region CTR2 . Furthermore, the problem of exposing the first upper sacrificial layer HLa1 can be solved.

Referring to FIGS. 2 and 15, after removing the first photoresist pattern PR1, a photoresist film PL covering the stacked structures ST1 and ST2 may be formed. The photoresist film PL may be formed by applying the above-described photoresist composition on the entire surface of the substrate 100. The photoresist film PL may be formed to have a uniform thickness, and thus may be inclined on the second contact region CTR2.

Referring to FIGS. 2 and 16, the second photoresist pattern PR2 may be formed by exposing and developing the photoresist film PL. The second photoresist pattern PR2 may be formed on the cell array region CAR, the second contact region CTR2, and the first contact region CTR1. The second photoresist pattern PR2 may expose the insulating films 110 and the first sacrificial films HLb1 and HLa1 outside the first contact region CTR1.

Referring to FIGS. 2 and 17, the insulating film 110 and the first upper sacrificial layer HLa1 at the uppermost portion of the first contact region CTR1 are sequentially formed using the second photoresist pattern PR2 as an etch mask . ≪ / RTI > The etched insulating layer 110 and the etched first upper sacrificial layer HLa1 may expose the other insulating layer 110 and the first lower sacrificial layer HLb1 under the etched insulating layer 110 and the etched first upper sacrificial layer HLa1.

Referring to FIGS. 2 and 18, a trimming process may be performed on the second photoresist pattern PR2. During the trimming process, the width of the second photoresist pattern PR2 may be reduced by the first length T1 and the height may be reduced by the second length T2.

That is, the steps described above with reference to FIGS. 17 and 18 may be the same as the one cycle described above with reference to FIGS. 8 and 9. The cycle may then be repeated.

Referring to FIGS. 2 and 19, the uppermost insulating layer 110 may be etched using the second photoresist pattern PR2 reduced in size by an etching mask. At the same time, the lower insulating layer 110 exposed by the first upper sacrificial layer HLa1 may be etched together (first etching process). Then, the first upper sacrificial layer HLa1 may be etched using the second photoresist pattern PR2 as an etching mask. At the same time, the first lower sacrificial layer HLb1 exposed by the first upper sacrificial layer HLa1 may be etched together (second etching process).

Referring to FIGS. 2 and 20, the trimming process may be performed again on the second photoresist pattern PR2. This confirms that the cycle is repeated once more.

Referring to FIGS. 2 and 21, as the cycle is repeated, one end of the first stacked structure ST1 (i.e., the first contact region CTR1) may have a stepped structure. In addition, the size of the second photoresist pattern PR2 can be reduced due to the repeated trimming process.

12, the first etch process and the second etch process are repeated for each cycle, and the second photoresist pattern PR2 is etched to expose portions of the insulating films 110 exposed by the second photoresist pattern PR2, The upper portion may be over-angled. Accordingly, the first recesses RC1 may be formed on the upper portions of the exposed insulating layers 110, respectively.

Referring to FIGS. 2 and 22, the trimming process may be performed on the second photoresist pattern PR2. Thereafter, the first etching process ET1 for etching the insulating films 110 exposed by the second photoresist pattern PR2 may be performed. As described above with reference to FIG. 13, the upper portions of the first lower sacrificial layers HLb1 are hyperfaded to form the second recesses RC2, respectively.

2 and 23, the modified second etch process ET2 'may be performed to selectively expose the first sacrificial layers HLb1 and HLa1 exposed by the second photoresist pattern PR2, Can be etched. The modified second etching process ET2 'may be the same as that described above with reference to FIG.

The first upper sacrificial layer HLa1 may have a seventh sidewall SW7 having a gentle slope after the modified second etching process ET2 '. Since the exposed first sacrificial layers HLb1 have a relatively thin thickness, the eighth sidewall SW8 having a substantially vertical gradient even after the modified second etching process ET2 ' Lt; / RTI > That is, the seventh sidewall (SW7) may have a gentler inclination than each of the eighth sidewalls (SW8).

2 and 24, after removing the second photoresist pattern PR2, a first interlayer insulating film 180 may be formed on the substrate 100 to cover the stacked structures ST1 and ST2. have. The first interlayer insulating layer 180 may be formed to cover the first and second contact regions CTR1 and CTR2. The first interlayer insulating film 180 may be planarized to expose the upper surface of the second laminated structure ST2.

The stacked structures ST1 and ST2 may be patterned to form trenches TR exposing the substrate 100 between adjacent channel holes CH. Specifically, forming the trenches TR may include forming mask patterns defining a planar position on which the trenches TR are to be formed on the stacked structures ST1 and ST2, And etching the stacked structures ST1 and ST2 with an etch mask.

The trenches TR may be formed to expose the sacrificial layers HLb1, HLa1, HLb2, and HLa2 and the sidewalls of the insulating layers 110. Referring to FIG. In the vertical depth, the trenches TR may be formed to expose the sidewalls of the lower insulating layer 105. Also, although not shown, the trenches TR may have different widths depending on the vertical distance from the substrate 100 by an anisotropic etching process.

As the trenches TR are formed, the stacked structures ST1 and ST2 can be divided into a plurality of stacked structures ST1 and ST2. Each of the stacked structures ST1 and ST2 may have a line shape extending in the second direction D2. One of the stacked structures ST1 and ST2 may be penetrated by a plurality of the channel films 135. [

Referring to FIGS. 2 and 25, the sacrificial layers HLb1, HLa1, HLb2, and HLa2 exposed by the trenches TR may be selectively removed to form the recessed regions 155. Referring to FIG. The recessed regions 155 may correspond to areas where the sacrificial layers HLb1, HLa1, HLb2, and HLa2 are removed. When the sacrificial films HLb1, HLa1, HLb2, and HLa2 include a silicon nitride film or a silicon oxynitride film, the sacrificial films HLb1, HLa1, HLb2, and HLa2 are removed using an etching solution containing phosphoric acid . ≪ / RTI > Portions of the sidewalls of the gate insulating layer 145 may be exposed by the recessed regions 155.

Meanwhile, the first interlayer insulating layer 180 exposed by the recessed regions 155 may have ninth sidewalls SW9 and tenth sidewalls SW10. The ninth sidewall SW9 is formed corresponding to the fifth sidewall SW5 of the second upper sacrificial film HLa2 and the seventh sidewall SW7 of the first upper sacrificial film HLa1 , The ninth sidewalls SW9 may be inclined sidewalls. The tenth sidewalls SW10 are connected to the sixth sidewalls SW6 of the second lower sacrificial layers HLb2 and the eighth sidewalls SW8 of the first lower sacrificial layers HLb1 The tenth sidewalls SW10 may be vertical sidewalls.

Referring to FIGS. 2 and 26, gate electrodes WLb1, WLa1, WLb2, and WLa2 filling the recessed regions 155 may be formed. The formation of the gate electrodes WLb1, WLa1, WLb2 and WLa2 may be performed by forming a conductive film filling the recessed regions 155, And removing the membrane.

The first upper gate electrode WLa1 may have a first sidewall SW1 having a gentle inclination and the second upper gate electrode WLa2 may have a third sidewall SW3 having a gentle inclination. The first bottom gate electrodes WLb1 may each have vertical second sidewalls SW2 and the second bottom gate electrodes WLb2 may have vertical fourth sidewalls SW4. The first and third sidewalls SW1 and SW3 may be formed corresponding to the ninth sidewall SW9 and the second and fourth sidewalls SW2 and SW4 may be formed corresponding to the tenth sidewalls SW9, (SW10), respectively.

After the gate electrodes WLb1, WLa1, WLb2, and WLa2 are formed, common source regions CSL may be formed in the substrate 100. [ The common source regions CSL may be formed through an ion implantation process and may be formed in the substrate 100 exposed by the trenches TR. The common source regions CSL may form a PN junction with the substrate 100. Then, drain regions DR may be respectively formed on the channel films 135 through an ion implantation process.

If the gate insulating layer 145 includes a tunnel insulating layer and a charge storage layer, the blocking layer 155 filling the recessed regions 155 before forming the gate electrodes WLb1, WLa1, WLb2, An insulating film (not shown) may be additionally formed. Then, the gate electrodes WLb1, WLa1, WLb2, and WLa2 that completely fill the recessed regions 155 may be formed on the blocking insulating film.

Referring again to FIGS. 2 and 3A, a buried insulating film 170 filling the trenches TR may be formed. The buried insulating layer 170 may include a silicon oxide layer.

And conductive pads 160 that are in contact with the upper surfaces of the channel films 135 may be formed. A second interlayer insulating layer 190 may be formed to cover the buried insulating layer 170, the conductive pads 160, and the first interlayer insulating layer 180. Bit line plugs (BPLG) that penetrate the second interlayer insulating layer 190 and are in contact with the conductive pads 160 may be formed.

On the other hand, first contact plugs PLG1 that are respectively connected to the first gate electrodes WLb1 and WLa1 of the first contact region CTR1 may be formed through the second interlayer insulating film 190 have. Second contact plugs PLG2 may be formed through the second interlayer insulating film 190 and connected to the second gate electrodes WLb2 and WLa2 of the second contact region CTR2.

On the second interlayer insulating film 190, bit lines BL extending in a first direction D1 may be formed. Each of the bit lines BL may connect a plurality of the bit line plugs BPLG to each other. In addition, first and second connection lines CL1 and CL2 that are in contact with the first and second contact plugs PLG1 and PLG2 may be formed on the second interlayer insulating layer 190, respectively.

Claims (19)

A first lamination structure including first insulating films and first gate electrodes alternately and repeatedly stacked on a substrate, the first lamination structure having a first region and a second region spaced apart in one direction; And
And a channel structure vertically extending within the first region of the first laminate structure,
Wherein the second region has a stepped structure,
In the second region, at least one end of the first gate electrodes includes a first sidewall,
And in the second region, one end of each of the other first gate electrodes includes a second sidewall having a slope that is steeper than the first sidewall.
The method according to claim 1,
A first line and an upper surface of the first insulating film below the at least one first gate electrodes form a first angle,
The second line and the upper surface of the first insulating film below each of the different first gate electrodes form a second angle from the viewpoint of one cross section in one direction,
The first line is a line connecting the upper portion and the lower portion of the first sidewall,
The second line is a line connecting the upper portion and the lower portion of the second sidewall,
Wherein the second angle is larger than the first angle.
3. The method of claim 2,
Wherein the first angle is 30 DEG to 85 DEG.
The method according to claim 1,
Wherein the at least one first gate electrodes comprise a top first top gate electrode,
And the other first gate electrodes comprise first bottom gate electrodes under the first top gate electrode.
The method according to claim 1,
In the second region, the at least one first gate electrodes include a first pad portion extending in the one direction,
Wherein a length of the first pad portion in the one direction is gradually increased from an upper portion to a lower portion of the first pad portion.
6. The method of claim 5,
In the second region, the first gate electrodes each include second pad portions extending in one direction,
And contact plugs penetrating the first insulating films and connected to the first and second pad portions, respectively.
The method according to claim 1,
And a second stacked structure including second insulating films and second gate electrodes alternately and repeatedly stacked on the first stacked structure,
Wherein the second laminated structure includes a third region and a fourth region spaced apart from the first region,
Wherein the channel structure further extends vertically into the third region of the second laminate structure,
The fourth region has a stepped structure,
In the fourth region, at least one end of the second gate electrodes includes a third sidewall,
Wherein one end of each of the other second gate electrodes in the fourth region includes a fourth sidewall having a tilt faster than the third sidewall,
8. The method of claim 7,
And the third sidewall has an inclination substantially equal to the first sidewall.
8. The method of claim 7,
Wherein the number of the first gate electrodes is equal to the number of the second gate electrodes.
The method according to claim 1,
Wherein the at least one second gate electrodes comprise a top second top gate electrode,
And the second different gate electrodes include second lower gate electrodes under the second upper gate electrode.
The method according to claim 1,
And a gate insulating film interposed between the first gate electrodes and the channel structure.
The method according to claim 1,
Wherein the first laminated structure is provided in plurality,
And the plurality of first laminated structures extend parallel to each other in the one direction.
A lamination structure including insulating films and gate electrodes alternately and repeatedly stacked on a substrate, the lamination structure having a cell array region and a contact region spaced apart in one direction; And
And a channel structure that is connected to the substrate through the cell array region of the laminated structure,
In the contact region, at least one of the gate electrodes has a first pad portion extending in the one direction,
Wherein a length of the first pad portion in the one direction is gradually increased from an upper portion to a lower portion of the first pad portion.
14. The method of claim 13,
The first line and the upper surface of the insulating film below the first pad portion form a first angle from the viewpoint of one cross section in one direction,
The first line is a line connecting an upper portion and a lower portion of a first sidewall of one end of the first pad portion,
Wherein the first angle is 30 DEG to 85 DEG.
14. The method of claim 13,
Wherein the at least one gate electrode comprises a top gate electrode.
14. The method of claim 13,
In the contact region, the gate electrodes other than the at least one gate electrode each have second pad portions,
Wherein the first sidewall of the one end of the first pad portion has a gentler slope than the second sidewall of the one end of each of the second pad portions.
14. The method of claim 13,
Wherein the at least one gate electrode comprises two or more,
And a plurality of other gate electrodes are interposed between the at least one gate electrode.
14. The method of claim 13,
Wherein the contact region has a stepped structure.
14. The method of claim 13,
Further comprising a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially interposed between the channel structure and the gate electrodes.

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