KR20170040719A - Memory system with zq global managing scheme - Google Patents

Memory system with zq global managing scheme Download PDF

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Publication number
KR20170040719A
KR20170040719A KR1020150158992A KR20150158992A KR20170040719A KR 20170040719 A KR20170040719 A KR 20170040719A KR 1020150158992 A KR1020150158992 A KR 1020150158992A KR 20150158992 A KR20150158992 A KR 20150158992A KR 20170040719 A KR20170040719 A KR 20170040719A
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KR
South Korea
Prior art keywords
calibration
memory
pull
circuit
signal
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KR1020150158992A
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Korean (ko)
Inventor
이상열
김석일
정회주
신용재
한유근
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삼성전자주식회사
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Priority to US15/282,291 priority Critical patent/US10284198B2/en
Publication of KR20170040719A publication Critical patent/KR20170040719A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The present invention discloses a memory system capable of performing ZQ global management under the control of a memory controller. The memory system includes a memory module including a plurality of semiconductor memory devices having a ZQ calibration circuit and mounted in a memory slot, and a memory controller for controlling the memory module. The memory controller includes a ZQ global management module that receives calibration result data of the ZQ calibration circuit through the memory slot and determines a final calibration value of the ZQ calibration circuit according to the signal loading characteristics of the memory slot in which the memory module is mounted Circuit.

Description

MEMORY SYSTEM WITH ZQ GLOBAL MANAGING FUNCTION {MEMORY SYSTEM WITH ZQ GLOBAL MANAGING SCHEME}

The present invention relates to a memory system, and more particularly, to a memory system capable of performing ZQ global management by a memory controller.

A semiconductor memory device constituting a memory system is connected to a memory controller through a transmission line for transmitting signals such as data, addresses, or commands. Signals transmitted along the transmission line may be reflected at the termination of the transmission line. Reflected signals act as noise, affecting the original signal and eventually degrade signal integrity (SI).

A termination resistor may be connected to the termination node of the transmission line to prevent reflection of the signal. The termination resistance may serve to match the impedance between the inside and the outside of the semiconductor memory device. The termination resistance is mainly used in DRAM (Dynamic Random Access Memory) having a high operating speed. An on-die termination (ODT) technique is used to directly connect a termination resistor on the die of the DRAM to prevent signal interference between the DRAMs. In the case of the DDR3 SDRAM (Double Data Rate 3 Synchronous DRAM), since it has a very high operation speed of 1000 MHz or more, higher signal integrity and stability are required. Since the termination resistance value fluctuates according to changes in the manufacturing process, the power supply voltage, and the operating temperature, if the impedance matching is not accurately performed, rapid transmission of the signal becomes difficult and the signal may be distorted.

DDR3 SDRAM uses ZQ Calibration circuit to ensure high signal quality and stability. The impedance matching in the memory system can be properly performed if the termination resistance value is accurately corrected according to the calibration code generated from the ZQ calibration circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory system capable of performing ZQ global management under the control of a memory controller.

According to an aspect of the inventive concept to achieve the above object,

A memory module including a plurality of semiconductor memory devices having a ZQ calibration circuit and mounted in a memory slot,

And a memory controller for controlling the memory module,

Wherein the memory controller is configured to receive the calibration result data of the ZQ calibration circuit through the memory slot and to determine a final calibration value of the ZQ calibration circuit according to a signal loading characteristic of the memory slot in which the memory module is mounted, And includes a charging circuit.

According to another aspect of the concept of the present invention to achieve the above object,

A memory module including a plurality of semiconductor memory devices having a ZQ calibration circuit and mounted in one of a plurality of memory slots provided in a circuit board,

And a memory controller for controlling the plurality of semiconductor memory devices in the memory module on a rank by rank basis,

Wherein the memory controller receives calibration result data of the ZQ calibration circuit through one of the plurality of memory slots and controls the ZQ fine control of the ZQ calibration circuit in accordance with the signal loading characteristics by position of the rank in the memory module Lt; RTI ID = 0.0 > ZQ < / RTI > global management circuitry.

According to the embodiment of the present invention, the ZQ global management of the memory controller accurately performs calibration according to memory slot or rank-specific signal loading characteristics.

1 is a block diagram of a memory system in accordance with an embodiment of the present invention.
2 is a detailed block diagram of the memory controller of FIG.
Figure 3 is a slot mounting view of memory modules forming the memory groups of Figure 1;
4 is an exemplary diagram of the termination circuit block of Fig.
5 is a block diagram of a calibration and termination circuit implemented in the semiconductor memory device of FIG.
Figure 6 is an implementation detail of the calibration circuit of Figure 5;
7 is an implementation detail view of the on-die termination circuit of FIG.
8 is a detailed block diagram of the data output driver of FIG.
9 is a flowchart of ZQ global management control according to an embodiment of the present invention.
FIG. 10 is a graph showing a difference in signal characteristics according to slot positions at which the memory module is mounted.
11 is a detailed block diagram of a semiconductor memory device according to an embodiment of the present invention.
12 is an operation timing diagram related to calibration result data according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, .

In this specification, when it is mentioned that some element or lines are connected to a target element block, it also includes a direct connection as well as a meaning indirectly connected to the target element block via some other element.

In addition, the same or similar reference numerals shown in the drawings denote the same or similar components as possible. In some drawings, the connection relationship of elements and lines is shown for an effective explanation of the technical contents, and other elements or circuit blocks may be further provided.

Each embodiment described and exemplified herein may also include its complementary embodiment, and details of the basic operation of the ZQ calibration circuit and the on-die termination circuit and of the functional circuit for performing such basic operation are not intended to limit the scope of the present invention Please note that it is not described in detail in order to avoid.

1 is a block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 1, a memory system 1500 includes a memory controller 1000 and memory groups 2000.

Each of the memory groups 2000-1, 2000-2, ..., 2000-n may include a memory module. Where n is a natural number greater than or equal to 2. The memory module includes a plurality of semiconductor memory devices. The memory module includes a plurality of semiconductor memory devices having a ZQ calibration circuit and is mounted in a memory slot.

The memory controller 1000 controls the memory module.

The memory controller 1000 receives the calibration result data of the ZQ calibration circuit through a memory slot and determines the final calibration value of the ZQ calibration circuit according to the signal loading characteristics of the memory slot in which the memory module is mounted. And a charging circuit (1200).

The bus B10 connected between the memory controller 1000 and the memory groups 2000 may be a command and address bus (C / A BUS). The bus B20 connected between the memory controller 1000 and the memory groups 2000 may be a data bus.

Calibration result data may be provided to the ZQ global management circuit 1200 via the bus B20.

The ZQ resistors 1a, 2a, ..., na may be correspondingly connected to the memory groups 2000-1, 2000-2, ..., 2000-n through ZQ pads.

And the second memory group 2000-2 is mounted in a memory slot located farther from the first memory group 2000-1 than the first memory group 2000-1.

Thus, there is a difference in signal loading characteristics between memory slots. Therefore, even if the ZQ calibration is performed once, it is necessary that the ZQ calibration is finally performed accurately, reflecting the difference in the signal loading characteristics. Therefore, in the embodiment of the present invention, the ZQ global management circuit 1200 determines the final calibration value of the ZQ calibration circuit and transmits it to the semiconductor memory device in the corresponding memory group.

2 is a detailed block diagram of the memory controller of FIG.

Referring to FIG. 2, the memory controller 1000 may be an internal memory controller (IMC) included in the host 500 for processing data according to a program. Host 500 may execute various computing functions, such as executing specific calculations or specific software executing tasks. For example, the host 500 may be a microprocessor or a central processing unit. The host 500 may be coupled to the internal memory controller 1000 via a processor bus including an address bus, a control bus, and / or a data bus.

The ZQ global management circuit 1200 included in the memory controller 1000 includes a signal termination register 1210, a ZQ code register 1230, and a ZQ global control unit 1220.

 The signal termination register 1210 stores SI information according to signal loading characteristics of a memory slot.

The ZQ code register 1230 stores the final calibration value.

The ZQ global controller 1220 determines the final calibration value using the SI information and the calibration result data.

The memory controller 1000 can apply the calibration command via the command / address bus B10-1.

The memory controller 1000 may receive the calibration result data via the data bus B20-1.

The memory controller 1000 may provide the final calibration value via the data bus B20-1.

Figure 3 is a slot mounting view of memory modules forming the memory groups of Figure 1;

Referring to FIG. 3, two memory modules 2000-1 and 2000-2 are mounted in the first and second memory slots 350 and 360, respectively. The line 120 connected to the first and second memory slots 350 and 360 is connected to the memory controller 1000. The memory controller 1000 may also be referred to as a chipset.

The line 120 may include a data bus and a control bus. The control bus may be a bus carrying control signals such as a clock signal, a command, or an address signal. The data bus may be a bus carrying data.

Each of the memory modules 2000-1 and 2000-2 includes a plurality of ranks and is mounted to each of the corresponding memory slots 350 and 360 and is connected to the memory controller 1000 through the line 120 . Each of the memory modules 2000-1 and 2000-2 includes a dual in-line memory module DiMM (dual in-line memory module) composed of dual ranks ([R0, R1], [R2, Lt; / RTI > However, the present embodiment is not limited to this, and each of the memory modules 2000-1 and 2000-2 may be a DiMM configured with a quad rank or a single rank. Here, one rank may include at least one semiconductor memory device (e.g., DRAM (DRAM)).

Each of the memory modules 2000-1 and 2000-2 may include On Die Termination (ODT) circuits ([331, 332], [341, 342]). The ODT circuit is a reflection of data input / output when a normal operation such as a write operation or a read operation of the semiconductor memory device included in the memory module is performed And to prevent distortion of data caused by the data. As a result, the ODT circuit is a termination matching circuit included in the semiconductor memory device.

The ODT circuit is connected to the DQ pin or the DQ port of the semiconductor memory device.

It is assumed that the other termination scheme is applied and the ranks RO and R1 of the first memory module 2000-1 perform a write operation or a read operation. In this case, the ODT circuits 341 and 342 of the second memory module 2000-2 are turned on (or activated) in response to the activation of the first termination control signal transmitted through the line 120, And serves as a termination matching circuit coupled to line 120. In this case, the ODT circuits 331 and 332 of the first memory module 2000-1 are turned off (or deactivated) in response to the second termination control signal transmitted through the line 120. The first and second termination control signals are applied from the memory controller 1000.

On the other hand, when the ranks R2 and R3 of the second memory module 2000-2 perform a write operation or a read operation, the operations of the ODT circuits (331, 332, 341, and 342) Lt; RTI ID = 0.0 > ODT < / RTI > That is, the ODT circuits 341 and 342 of the second memory module 2000-2 are turned off and the ODT circuits 331 and 332 of the first memory module 2000-1 are turned on.

3, it is assumed that the second memory slot 360 is a memory slot located farther from the first memory slot 350 than the first memory slot 350 based on the memory controller 1000. Thus, there is a difference in signal loading characteristics between the memory slots 350 and 360. FIG. Therefore, even though the ZQ calibration is performed and hence the on-die termination operation has been performed once, the termination match may have an offset due to the difference in signal loading characteristics. Therefore, it may be necessary for the ZQ global management circuit 1200 to determine the final calibration value of the ZQ calibration circuit and transmit it to the corresponding rank.

4 is an exemplary diagram of the termination circuit block of Fig.

Referring to FIG. 4, the first ODT circuit 331 may use a center tap termination (CTT) type. The first ODT circuit 331 includes switches SW1 and SW2 and termination resistors R1 and R2. The remaining ODT circuits 332, 341, and 342 may include the same components as the first ODT circuit 331.

Each of the switches SW1 and SW2 may be implemented as a MOS transistor. Each of the switches SW1 and SW2 turns on the ODT circuit 331 in response to the activation of the termination control signal ODT_C. That is, each of the switches SW1 and SW2 supplies the power supply voltage VDD and the ground voltage VSS to one end of each of the termination resistors R1 and R2 to turn on the ODT circuit 331 .

The termination resistors R1 and R2 may have the same resistance value. The node A connected between the termination resistors R1 and R2 is connected to the DQ pin of the semiconductor memory device included in the memory module 2000-1 shown in FIG.

5 is a block diagram of a calibration and termination circuit implemented in the semiconductor memory device of FIG.

5, the calibration and termination circuit 2100 may include a calibration circuit 2200 and an ODT circuit 2300.

A ZQ pad 11 is connected to the calibration circuit 2200 and a ZQ resistor RZQ is connected to the ZQ pad 11 as an external resistor. That is, the ZQ resistor RZQ may be a resistor connected to the outside of the chip of the semiconductor memory device, for example, 240 ohms (Ω).

The final pull-up control signal FPUC and the final pull-down control signal FPDC in accordance with the determination of the final calibration value are applied to the calibration circuit 2200.

The final pull-up control signal FPUC or the final pull-down control signal FPDC finely adjusts the resistance value of the ZQ resistor RZQ.

Calibration circuit 2200 performs a calibration operation in response to a calibration enable signal ENC.

The ODT circuit 2300 can perform the ODT operation in response to the ODT enable signal ENO.

The data output driver 2500 can drive the data Din to be output to the output terminal DQ in response to the pull-up calibration code PCODE and the pull-down calibration code NCODE.

The data output driver 2500 may include an equalizing circuit 2550.

In a memory system, a plurality of semiconductor memory devices are commonly connected to one line. An equalizing technique can be applied to overcome bandwidth limitation due to a transmission channel in such a bus structure and to realize high-speed signal transmission. By performing the equalizing, the high frequency component of the input data signal can be amplified or attenuated.

If the driving force of the equalizing deviates from the set value, the transmission impedance value deviates from the normal impedance value. If the driving force is set too small for impedance matching, the size of the input signal becomes small, so that it becomes difficult to judge the signal. The equalizing operation can be implemented by adjusting the capacitance.

In the embodiment of the present invention, when the equalizing circuit 2550 is provided in the semiconductor memory device, the driving force of the equalizing is reflected when determining the final calibration value. Thus, a more precise ZQ calibration is realized.

Figure 6 is an implementation detail of the calibration circuit of Figure 5;

6, the calibration circuit 2200 includes a pull-up calibration code generator 100, a pull-down calibration code generator 200, and a ZQ fine adjuster 300.

The pull-up calibration code generation unit 100 includes a first pull-up unit 130, a first comparison unit 110, and a first code counter 120.

The pull-down calibration code generation unit 200 includes a second pull-up unit 210, a second comparison unit 220, a second code counter 230, and a pull-down unit 240.

The ZQ fine adjustment unit 300 includes a variable pull-up resistor 310 and a variable pull-down resistor 320 connected between the first calibration node ND1 and a distribution voltage input terminal of the first comparator 110. [

The final pull-up control signal FPUC is a signal for adjusting the resistance value of the variable pull-up resistor 310. The final pull-down control signal FPDC is a signal for adjusting the resistance value of the variable pull-down resistor 320.

When the resistance values of the variable pull-up resistor 310 and the variable pull-down resistor 320 are adjusted, a voltage level appearing at the first calibration node ND1 is changed.

As a result, in the embodiment of the present invention, once the ZQ calibration operation is performed, the memory controller 1000 generates a final pull-up control signal FPUC or a final pull-down control signal FPDC). Accordingly, the resistance value of the ZQ resistor RZQ is finely adjusted in accordance with the signal loading characteristics of the memory slot or the memory module or the rank placed in the circuit board.

ZQ calibration refers to the process of generating an impedance code that changes as PVT (Process, Voltage, Temperature) conditions change. The code generated as a result of the ZQ calibration is used to adjust the termination resistance value. In general, a pad to which an external resistor is connected as a reference for calibration is referred to as a ZQ pad (ZQ pad), and for this reason, the term ZQ calibration is often used.

Assuming that the ZQ fine adjustment unit 300 is an initial state without fine adjustment, the first comparison unit 110 generates the ZQ resistance RZQ connected to the ZQ pad 11 and the ZQ resistance RZQ generated by the first pull- Lt; / RTI > to the first calibration node. The first comparator 110 compares the divided voltage of the first calibration node ND1 with a reference voltage VREF (for example, VDD / 2) and outputs an up / down signal UP / DN ).

The first code counter 120 generates a pull-up calibration code PCODE of N + 1 bits (0: N) in response to the up / down signal UP / DN as a comparison result of the first comparator 110 . Where N is a natural number greater than or equal to one. The pull-up calibration code PCODE is generated by turning on / off the parallel resistors in the first pull-up unit 130 (each resistance value can be designed for a binary weight) The pull-up resistance value of the transistor Q1 is adjusted. The adjusted resistance value of the first pull-up unit 130 again affects the divided voltage of the first calibration node ND1, and the first comparator 110 repeats the above-described operation. As a result, the pull-up calibration operation is repeated until the resistance value of the first pull-up section 130 becomes equal to the resistance value of the ZQ resistance RZQ.

The pull-up calibration code PCODE generated by the pull-up calibration operation is input to the second pull-up unit 210 so that the total pull-up resistance value of the second pull-up unit 210 is determined. The pulldown calibration operation is now started. Similar to the pull-up calibration operation, the second comparator 220 receives the distribution voltage generated at the second pull-up unit 210 and the pull-down unit 240 at the second calibration node. The second comparator 220 compares the divided voltage of the second calibration node with a reference voltage and generates an up / down signal (UP / DN) according to the comparison result.

The second code counter 230 generates a pull down calibration code NCODE of N + 1 bits (0: N) in response to the up / down signal UP / DN as a comparison result of the second comparator 220 . The pull-down calibration code NCODE controls the pull-down resistance of the pull-down portion 240 by turning on / off the parallel resistors in the pull-down portion 240. The resistance value of the controlled pull-down unit 240 again affects the distribution voltage of the second calibration node ND2, and the second comparison unit 220 repeats the above-described operation. As a result, the pull-down calibration operation is repeatedly performed until the resistance value of the second pull-up unit 210 and the resistance value of the pull-down unit 240 become equal to each other. When the pull-down calibration operation is completed, the voltage of the second calibration node ND2 becomes equal to the reference voltage VREF.

In the embodiment of the present invention, the ZQ global management circuit 1200 in the memory controller 1000 receives the pull-up calibration code PCODE and the pull-down calibration code NCODE when the pull-up and pull-down operations are completed. The ZQ global management circuit 1200 determines the final calibration value according to the signal loading characteristics of the memory slot or memory module or rank located in the circuit board. As a result, the final pull-up control signal FPUC and the final pull-down control signal FPDC are generated by the ZQ global control unit 1220 and provided to the corresponding memory slot, memory module, or rank. Thus, the ZQ calibration is finally performed accurately, reflecting the difference in signal loading characteristics.

The calibration circuit 2200 of Fig. 6 is merely exemplary and the invention is not so limited.

7 is an implementation detail view of the on-die termination circuit of FIG.

7, the on termination circuit 2300 includes a pull-up control unit 502, a pull-down control unit 504, a pull-up termination unit 506, and a pull-down termination unit 508.

The on termination circuit 2300 terminates the interface pad 510 in response to the pull-up and pull-down calibration codes PCODE, NCODE generated in the calibration circuit 2200. Here, the interface pad 510 may be a data output (DQ) pad.

The pull-up termination section 506 may be configured similar to the first pull-up section 130. As a result, the pull-up termination unit 506 and the first pull-up unit 130 can be designed to be identical or similar, since the resistance value of the pull-up termination unit 506 is determined by the pull-up calibration code PCODE. The operation of the pull-up termination unit 506 will be described below.

Up control unit 502 controls the pull-up termination unit 506 in response to the pull-up calibration code PCODE and the pull-up enable signal PU_EN. The pull-up enable signal PU_EN is a signal for turning on / off the pull-up termination unit 506. When the pull-up enable signal PU_EN is activated, the resistors UR1, UR2, ..., URn in the pull-up termination unit 506 are turned on / off according to the pull-up code PCODE. When the pullup enable signal PU_EN is inactivated, the pullup termination unit 506 does not operate regardless of the pullup code (PCODE). That is, the resistors UR1, UR2, ..., URn in the pull-up termination section 506 are all off.

The pull down termination portion 508 is designed similar to the pull down portion 240. As a result, since the resistance value of the pull-down termination unit 508 is determined by the pull-down calibration code NCODE, the pull-down termination unit 508 and the pull-down unit 240 can be designed to be the same or similar. The operation of the pull-down termination unit 508 will be described below.

The pull-down control unit 504 controls the pull-down termination unit 508 in response to the pull-down calibration code NCODE and the pull-down enable signal PD_EN. The pull-down enable signal PD_EN is a signal for turning on / off the pull-down termination unit 508. When the pull-down enable signal PD_EN is activated, the resistors DR1, DR2, ..., DRn in the pull-down termination unit 508 are turned on / off according to the pull-down code NCODE. When the pull-down enable signal PD_EN is inactivated, the pull-down termination unit 508 does not operate regardless of the pull-down code NCODE.

The on-die termination circuit 2300 can function as a main driver of the data output driver 2500. When the pull-up termination unit 506 is activated by the pull-up enable signal PU_EN, the pull-up termination unit 506 turns the level of the interface pad 510 to a high level. Therefore, 'high' data will be output through the interface pad 510. On the other hand, when the pull-down termination unit 508 is activated by the pull-down enable signal PD_EN, the pull-down termination unit 508 lowers the level of the interface pad 510 to a low level. Accordingly, 'low' data will be output through the interface pad 510.

8 is a detailed block diagram of the data output driver of FIG.

Referring to FIG. 8, the data output driver 2500 includes a pull-up driver 2510 and a pull-down driver 2520.

The pull-up driver 2510 may be configured to be the same as or similar to the pull-up termination unit 506 in FIG. The pull-up driver 2510 can control the data driving force for the data output terminal D out according to the pull-up calibration code PCODE when the data Din is high data. In addition, the pull-down driver 2520 may be implemented in the same or similar manner as the pull-down termination unit 508 in FIG. The pull-down driver 2520 can control the data driving force for the data output terminal Dout according to the pull-down calibration code NCODE when the data Din is 'low' data. Fig. 8 is merely an example and the present invention is not limited thereto.

9 is a flowchart of ZQ global management control according to an embodiment of the present invention.

Referring to FIG. 9, the ZQ global management circuit 1200 performs an initialization operation in S910. The initialization operation initializes the stored value of the ZQ code register 1230 as well as the internal state value of the buffer in the selected memory module. At S920, by issuing the MRS command, the MRS setting is made in the semiconductor memory device. The MRS setting allows the ZQ calibration result data to be output through the I / O paths of the semiconductor memory device by rank or module.

In S930, the ZQ global management circuit 1200 issues a QCL (ZQ Calibration Long) command or a ZQCS (ZQ Calibration Short) command. Thus, the semiconductor memory device executes the ZQ calibration operation. Calibration result data of the ZQ calibration circuit 2200 is thereby generated.

At S940, the ZQ global management circuit 1200 receives the calibration result data via I / O paths by rank or module. Indication data indicative thereof may be received together when the equalizing circuit is applied to the semiconductor memory device.

At S950, the ZQ global management circuit 1200 determines the final ZQ values based on the SI characteristic information by rank, module, or channel. In this case, the equalizing can be reflected in the final ZQ values. That is, when the equalizing circuit 2550 is provided in the semiconductor memory device, the driving force of the equalizing can be reflected when determining the final calibration value. As a result, a more precise ZQ calibration is realized.

SI information according to the signal loading characteristics of the memory slot in which the memory module is mounted and SI information according to the signal loading characteristics of the rank positions in the memory module are stored in the signal termination register 1210 in advance.

In operation S960, the ZQ global management circuit 1200 applies ZQ control data to the semiconductor memory device to finely adjust the variable offset resistance. That is, the final pull-up control signal FPUC and the final pull-down control signal FPDC are output from the ZQ global control unit 1220 and provided to the corresponding semiconductor memory device. Accordingly, the ZQ calibration is finally performed accurately, reflecting the difference in SI characteristics.

FIG. 10 is a graph showing a difference in signal characteristics according to slot positions at which the memory module is mounted.

Referring to FIG. 10, the horizontal axis indicates the distance of the memory slot, and the vertical axis indicates the signal integrity (SI).

Referring to the graph GR1, it is shown that the SI characteristics of the first and second memory slots are different. That is, the SI value of the second memory slot located farther from the memory controller than the first memory slot is represented by level b2, and the SI value of the first memory slot is represented by level b1. As a result, the SI characteristics are different depending on the position of the memory slot installed on the circuit board. In the embodiment of the present invention, this signal loading difference is reflected globally in accordance with the system environment by the control of the memory controller.

11 is a detailed block diagram of a semiconductor memory device according to an embodiment of the present invention.

11, the semiconductor memory device 200-1i includes an address latch 2400, a row decoder 2320, a column decoder 2330, a memory cell array 2300, a sense amplifier 2310, a command decoder 2600 An internal clock signal generator 2700, a calibration circuit 2100, a data input driver 2550, and a data output driver 1500.

The calibration circuit 2100 performs a calibration operation in response to the calibration start signal CAL_ST. A pull-up calibration code (PCODE) and a pull-down calibration code (NCODE) are output via the data output pad (DQ) as calibration result data. The final calibration value determined by the ZQ global control unit 1220 in FIG. 2 is applied to the calibration circuit 2100 as the final pull-up control signal FPUC and the final pull-down control signal FPDC. The final pull-up control signal FPUC and the final pull-down control signal FPDC minutely vary the resistance value of the offset variable resistors in the calibration circuit 2100. Thus, the impedance matching is optimized for the environment of the memory system.

The data output driver 2500 can output the data stored in the memory cell array 2300 via the data output pad DQ.

Data stored in the memory cell array 2300 may be provided to the data output driver 2500 through the sense amplifier 2310. [ At this time, the row decoder 2320 and the column decoder 2330 can provide the address ADDR of the memory cell storing the data to be output to the memory cell array 2300. The address ADDR of the memory cell may be provided to the row decoder 1320 and the column decoder 1330 via an address latch 2400. [

Data applied to the semiconductor memory device may be provided to the data input driver 2500 through the pad DQ. Data provided to the data input driver 2500 may be stored in the memory cell array 2300 through the sense amplifier 2310. [

An address ADDR for selecting a memory cell when data is stored in the memory cell may be provided through an address latch 2400, a row decoder 2320, and a column decoder 2330. [

The command decoder 2600 receives various commands via the command pad CMD. The command decoder 2600 provides commands to circuit blocks such as the row decoder 2320 and the column decoder 2330 and the like. In particular, the command decoder 2600 may provide a calibration start signal (CAL_ST) to the calibration circuit 2100. The calibration start signal CAL_ST may be a ZQCL (ZQ Calibration Long) command or a ZQCS (ZQ Calibration Short) command.

The internal clock signal generator 2700 may generate an internal clock signal based on the external clock signals CK_t and / CK_c. In particular, the calibration circuit 2100 may perform a calibration operation in response to an internal clock signal generated by the internal clock signal generator 2700.

12 is an operation timing diagram related to calibration result data according to an embodiment of the present invention.

Referring to FIG. 12, the first clock CK_t and the second clock CK_c are toggled in phases opposite to each other. That is, the first clock CK_t and the second clock CK_c are provided in the form of a differential signal.

The command CMD shows the issue of the MRS signal and the issue of the ZQ calibration command. The MRS command applied after the interval T10 is a command for instructing the semiconductor memory device to output the calibration result. Accordingly, the semiconductor memory device outputs the ZQ calibration result data once the internal ZQ calibration operation is completed.

The command applied after the interval T40 within the interval T20 may be a ZQCL (ZQ Calibration Long) command. The semiconductor memory device receiving the ZQCL performs the ZQ calibration operation internally and outputs the ZQ calibration result data to the memory controller during the section T30 within the section T50. The interval T30 is sufficiently longer than the time taken to output the calibration result data to the memory controller.

As described above, embodiments are disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention.

1000: Memory controller 1200: ZQ global management circuit
1210: SI register 1230: ZQ code register

Claims (10)

A memory module including a plurality of semiconductor memory devices having a ZQ calibration circuit and mounted in a memory slot; And
And a memory controller for controlling the memory module,
Wherein the memory controller is configured to receive the calibration result data of the ZQ calibration circuit through the memory slot and to determine a final calibration value of the ZQ calibration circuit according to a signal loading characteristic of the memory slot in which the memory module is mounted, Memory circuit. 2. The memory system of claim 1, wherein the calibration result data comprises a pullup calibration code and a pull down calibration code. 2. The memory system of claim 1, wherein the final calibration value is sent to the ZQ calibration circuit to control the ZQ calibration circuit. 2. The memory system of claim 1 wherein the calibration result data modified by the final calibration value is reflected in an on termination operation of an on termination circuit. The apparatus of claim 1, wherein the ZQ global management circuit comprises:
A signal completion register for storing SI information according to signal loading characteristics of the memory slot;
A ZQ code register for storing the final calibration value; And
And a ZQ global control unit for determining the final calibration value using the SI information and the calibration result data. The apparatus of claim 1, wherein the ZQ calibration circuit comprises:
And a variable offset resistor coupled to the first calibration node. 7. The variable offset resistor according to claim 6,
And a variable pull-up resistor and a variable pull-down resistor coupled across the first calibration node. 8. The memory system of claim 7, wherein the voltage of the first calibration node is adjusted when the variable pull-up resistor or the variable pull-down resistor is operated. 8. The memory system of claim 7, wherein the first calibration node is a node where the ZQ pad voltage by the ZQ resistor appears. 2. The memory system of claim 1, wherein the plurality of semiconductor memory devices includes an equalizing circuit for equalizing signal transmission and reception intensities, wherein the determined final calibration value further reflects an equalizing characteristic of the equalizing circuit.
KR1020150158992A 2015-10-02 2015-11-12 Memory system with zq global managing scheme KR20170040719A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200020069A (en) * 2018-08-16 2020-02-26 삼성전자주식회사 Calibration circuit including common node shared by pull-up calibration path and pull-down calibration path, and semiconductor memory device including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200020069A (en) * 2018-08-16 2020-02-26 삼성전자주식회사 Calibration circuit including common node shared by pull-up calibration path and pull-down calibration path, and semiconductor memory device including the same

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