JP2015011730A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the waveform quality of a data bus of a semiconductor device.SOLUTION: The present invention relates to a semiconductor device such as a DRAM provided with a so-called dynamic ODT function. This semiconductor device includes: a data terminal; an output buffer connected to the data terminal; and an adjustment circuit for adjusting an impedance of the output buffer. If a write signal is input after an ODT signal is input from a memory controller, the adjustment circuit sets the impedance of the output buffer to a first termination resistance value once and then, changes it to a second termination resistance value. If the write signal is input immediately after the ODT signal, the adjustment circuit sets the second termination value for the output buffer without setting the first termination resistance value.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an ODT (On Die Termination) function.

  In recent years, a very high data transfer rate is required for data transfer between semiconductor devices (such as between a CPU and a DRAM), and impedance matching between the semiconductor device and the data bus has become increasingly important.

  In DRAM (Dynamic Random Access Memory), an ODT (On Die Termination) function is mounted as standard from the DDR2 (Double-Data-Rate 2) standard. The ODT function is a function of suppressing reflection of voltage waves from the output buffer to the data bus by causing the output buffer included in the DRAM to function as a termination resistor circuit (see Patent Document 1).

  Furthermore, a dynamic ODT function is added from the DDR3 standard. In the dynamic ODT function, the memory controller issues an ODT command to the memory module at the time of writing, so that the output buffers of all DRAMs mounted in the memory module are temporarily set to the first termination resistance value, and further the writing is performed. This is a function for setting the output buffer of the target DRAM to the second termination resistance value.

  For example, it is assumed that writing to the DRAM 1 is executed among the DRAMs 1 to 8 mounted in a certain memory module. At this time, the memory controller sets the resistance value of the output buffer of the DRAM 1 to be written from the first termination resistance value to the second termination resistance value from the state where the resistance value of the output buffer of the DRAM 1 to 8 is set to the first termination resistance value. Switch to. The second termination resistance value is a more appropriate termination resistance value for preventing unnecessary voltage reflection from the write target DRAM itself. The first termination resistance value and the second termination resistance value are usually different. After setting the impedance of the output buffer of each DRAM as described above, the memory controller transmits write data to the input buffer of the DRAM 1. The dynamic ODT function further improves the waveform quality of the data bus.

JP 2010-193030 A

  The output buffer of the write target DRAM is first set to the first termination resistance value by the ODT command, and then set to the second termination resistance value by the write command, but the ODT command and the write command issued by the memory controller. Are not synchronized with each other. For this reason, a write command may be issued immediately after the ODT command. In this case, the resistance value of the output buffer changes from the first termination resistance value to the second termination resistance value in a short period, and such a short-term change in the resistance value may cause a hazard in the data bus. The present inventors have recognized that there is.

  A semiconductor device according to the present invention includes a data terminal, an output buffer connected to the data terminal, and an adjustment circuit for adjusting the impedance of the output buffer. When a write signal is input after an ODT signal is input, the adjustment circuit once sets the first termination resistance value to the impedance of the output buffer and then changes the setting of the second termination resistance value, and the ODT signal and the write signal When the input timing is within a predetermined time difference, the second termination resistance value is set without setting the first termination resistance value in the output buffer.

  According to the present invention, the waveform quality of the data bus of the semiconductor device can be further improved.

It is a block diagram of a semiconductor device. It is a functional block diagram of a portion related to data output in the data input / output circuit. It is a block diagram which shows the structure of a data input / output circuit. It is a circuit diagram of a general ODT control circuit. It is a 1st waveform diagram of each signal in an ODT control circuit. It is a 2nd waveform diagram of each signal in an ODT control circuit. It is a circuit diagram of a pre-stage circuit and a unit buffer. It is a circuit diagram of the 1st control circuit D1P. It is a circuit diagram of the 2nd control circuit E1P. It is a circuit diagram of the 1st control circuit D1N. It is a circuit diagram of the 2nd control circuit E1N. It is a circuit diagram of the ODT control circuit in a 1st embodiment. It is a wave form diagram of each signal in the ODT control circuit of a 1st embodiment. It is a circuit diagram of the ODT control circuit in 2nd Embodiment. It is a wave form diagram of each signal in the ODT control circuit of a 2nd embodiment. It is a circuit diagram of the ODT control circuit in 3rd Embodiment. It is a wave form diagram of each signal in the ODT control circuit of a 3rd embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DDR type SDRAM chip. As external terminals for accessing the semiconductor device 10 from a memory controller or the like, clock terminals 11a and 11b, command terminals 12a to 12e, an address terminal 13, and data A terminal 14, power supply terminals 15a and 15b, data input / output power supply terminals 16a and 16b, and a pair of data strobe terminals 17a and 17b are provided. In addition, although a calibration terminal is also provided, these are not shown.

  The clock terminals 11 a and 11 b are terminals to which external clock signals CK and / CK are respectively supplied. The supplied external clock signals CK and / CK are supplied to the clock input circuit 21. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock input circuit 21 generates a single-phase internal clock signal PreCLK based on the external clock signals CK and / CK, and supplies this to the DLL circuit 80. The DLL circuit 80 generates a phase-controlled internal clock LCLK based on the internal clock signal PreCLK and supplies it to the data input / output circuit 70.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals CMD are supplied to the command input circuit 31. These command signals CMD supplied to the command input circuit 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals. The generated internal command ICMD is supplied to the row control circuit 51, the column control circuit 52, the mode register 53, the data input / output circuit 70, and the like.

  The address terminal 13 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the address input circuit 41. The output of the address input circuit 41 is supplied to the address latch circuit 42. Of the address signal ADD latched by the address latch circuit 42, the row address is supplied to the row control circuit 51, and the column address is supplied to the column control circuit 52. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 53, whereby the contents of the mode register 53 are updated.

  The output of the row control circuit 51 is supplied to the row decoder 61. The row decoder 61 is a circuit that selects any word line WL included in the memory cell array 60. In the memory cell array 60, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 1, one word line WL, one line Only the bit line BL and one memory cell MC are shown). The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 63.

  The output of the column control circuit 52 is supplied to the column decoder 62. The column decoder 62 is a circuit that selects one of the sense amplifiers SA included in the sense circuit 63. The sense amplifier SA selected by the column decoder 62 is connected to the data amplifier 64 via the main I / O line MIO. The data amplifier 64 further amplifies the read data amplified by the sense amplifier SA during the read operation, and supplies it to the data input / output circuit 70 via the read / write bus RWBS. On the other hand, during the write operation, the write data supplied from the data input / output circuit 70 via the read / write bus RWBS is amplified and supplied to the sense amplifier SA.

  The data input / output terminal 14 is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the data input / output circuit 70. The data input / output circuit 70 is supplied with the internal clock LCLK generated by the DLL circuit 80, and outputs read data DQ in synchronization with the internal clock LCLK during a read operation. Although only one data input / output terminal 14 is shown in FIG. 1, the number of data input / output terminals 14 is not necessarily one, and a plurality of data input / output terminals 14 may be provided.

  The power supply terminals 15a and 15b are terminals to which a power supply voltage is supplied. Specifically, the higher power supply voltage VDD is supplied to the power supply terminal 15a, and the lower power supply voltage (ground voltage) VSS is supplied to the power supply terminal 15b. The power supply voltage VDD and the ground voltage VSS are supplied to the internal power supply generation circuit 90, and the internal power supply generation circuit 90 generates the internal voltage VPERI used for the peripheral circuit and the internal voltage VPP used as the word line voltage. The internal voltage VPERI is a voltage obtained by stepping down the power supply voltage VDD. The internal voltage VPP is a voltage obtained by boosting the power supply voltage VDD.

  The data input / output power supply terminals 16a and 16b are terminals to which a data input / output power supply voltage is supplied, respectively. Specifically, the high power supply voltage VDDQ is supplied to the power supply terminal 16a, and the low power supply voltage (ground voltage) VSSQ is supplied to the power supply terminal 16b. The power supply voltage VDDQ and the ground voltage VSSQ are supplied to the data input / output circuit 70.

  The pair of data strobe terminals 17 a and 17 b are terminals to which a data strobe signal is supplied, and are connected to the data input / output circuit 70. Specifically, the data strobe signal DQS is input / output to / from the data strobe terminal 17a, and the inverted signal DQSB of the data strobe signal DQS is input / output to the data strobe terminal 17b.

  The above is the overall configuration of the semiconductor memory 10 according to the present embodiment. Among the elements shown in FIG. 1, the pad group 100 is arranged in the pad region, the array system circuit 200 is arranged in the memory cell array region, and the other peripheral circuits are arranged in the peripheral circuit region.

  FIG. 2 is a functional block diagram of a portion related to data output in the data input / output circuit 70. When reading data from the semiconductor device 10, the data in the memory cell array 60 is output to the outside via the data amplifier 64 via the output control circuit 20, the adjustment circuit 30 and the output buffer 40.

  The output control circuit 20 serializes the data output in parallel from the data amplifier 64. The adjustment circuit 30 adjusts the impedance of the output buffer 40 and the data slew rate. The output buffer 40 outputs the adjusted data from the data terminal 14.

  The adjustment circuit 30 includes an ODT control circuit 18 and an output adjustment circuit 22. The ODT control circuit 18 receives an ODT signal (ODT0) corresponding to the ODT command and a write signal (WRITE0) corresponding to the write command. The ODT control circuit 18 causes the output buffer 40 to function as a termination resistor circuit in response to the ODTC signal. Details will be described later. The output adjustment circuit 22 receives a ZQ signal (ZQP signal and ZQN signal) and an SR signal. The ZQ signal is a signal for setting enable / disable of a MOS transistor (described later) included in the output buffer 40. The SR signal is a signal for adjusting the slew rate of read data.

  FIG. 3 is a block diagram showing a configuration of the data input / output circuit 70. Data input / output circuit 70 includes input buffer 24 in addition to output control circuit 20, adjustment circuit 30 and output buffer 40. Read data from the memory cell array 60 is output to the data terminal 14 via the output buffer 40, and write data is input from the data terminal 14 to the memory cell array 60 via the input buffer 24. Three pre-stage circuits 26-1 to 26-3 included in the adjustment circuit 30 correspond to the output adjustment circuit 22 in FIG. 2. The output buffer 40 includes three buffer groups 28-1 to 28-3. However, the number of the pre-stage circuit 26 and the buffer group 28 of the present invention is not limited to three.

  The buffer group 28-1 includes four unit buffers 48-1 to 48-4, the buffer group 28-2 includes two unit buffers 48-5 and 48-6, and the buffer group 28-3 includes one unit buffer. 48-7 included. The number of unit buffers 48 in the buffer group 28 is not limited to the configuration shown in FIG. 3, but the number of unit buffers 48 in each buffer group 28 is a power of 2, such as 1, 2, 4. Preferably there is. Each unit buffer 48 is connected to the data terminal 14 via the correction resistors RC1 to RC4 and the ESD element 34.

  The unit buffers 48-1 to 48-7 can each adjust the impedance. In the present embodiment, the target value (target impedance) of the impedance of each unit buffer 48 is 120Ω. Each unit buffer 48 is activated when the buffer group 28 including the unit buffer 48 is selected during the read operation, and drives the data terminal 14 to either the high level or the low level.

  A preceding circuit 26 is provided in the preceding stage of the buffer group 28. The pre-stage circuits 26-1 to 26-3 specify whether or not to activate the corresponding buffer group 28, and adjust the impedance of one or more unit buffers 48 included in the corresponding buffer group 28.

  As shown in FIG. 3, activation signals 151P to 153P and activation signals 151N to 153N are supplied from the output control circuit 20 to the pre-stage circuits 26-1 to 26-3, and an ODTC signal is supplied from the ODT control circuit 18. Is done. As described above, the ZQ signal (ZQP, ZQN) and the SR signal are also supplied to the pre-stage circuit 26. When the activation circuits 151P to 153P or the activation signals 151N to 153N are instructed to activate the corresponding buffer group 28, the pre-stage circuits 26-1 to 26-3 respond to the ODTC signal or the like. One of a plurality of output transistors (described later) included in one or more unit buffers 48 in the group 28 is designated to be turned on. These output transistors are turned on / off by activation signals 141P to 143P and activation signals 141N to 143N.

  The output control circuit 20 specifies the buffer group 28 to be activated and the output logic level of the unit buffer 48 to be activated. The designation of the buffer group 28 to be activated is based on the drive capability setting signal DS supplied from the mode register 53.

  As described above, the output control circuit 20 selects the buffer group 28 to be activated based on the drive capability setting signal DS, thereby changing the number of unit buffers 48 to be activated. When the number of unit buffers 48 to be activated changes, the impedance (output impedance) of the data terminal 14 changes.

  As shown in FIG. 3, in this embodiment, the unit buffers 48-1 to 48-7 are connected in parallel to the data terminal 14, so that the output impedance decreases as the number of unit buffers 48 activated increases. Conversely, when the number of unit buffers 48 to be activated decreases, the output impedance increases.

  The output control circuit 20 adjusts the output impedance by selectively activating the buffer groups 28-1 to 28-3. If the resistance value of the unit buffer 48 is Rm, and the resistance values of the correction resistors RC1 to RC4 are Rc1 to Rc3, the output impedance is Rm + Rc4 when only the buffer group 28-3 is activated. It is assumed that the resistance value of the ESD element 34 can be ignored. Similarly, the output impedance when only the buffer group 28-2 is activated is Rm / 2 + Rc3, and the output impedance when only the buffer group 28-1 is activated is (Rm / 2 + Rc1) // (Rm / 2 + Rc2).

  For example, assuming that Rc1 is 60Ω, Rc2 is 60Ω, Rc3 is 60Ω, Rc4 is 120Ω, and Rm is 120Ω (target impedance), when only the buffer group 28-3 is activated, the output impedance is Rm + Rc4 = 240Ω. Similarly, the output impedance when only the buffer group 28-2 is activated is Rm / 2 + Rc3 = 60 + 60 = 120Ω, and the output impedance is halved compared to when the buffer group 28-3 is selected. The output impedance when the buffer group 28-1 is activated is (Rm / 2 + Rc1) // (Rm / 2 + Rc2) = 120 // 120 = 60Ω. In this manner, seven types of output impedances can be set by changing the number of unit buffers 28.

  Next, the configuration, operation, and problems of a general ODT control circuit 18 that realizes the dynamic ODT function will be described.

  FIG. 4 is a circuit diagram of a general ODT control circuit 18. The ODT control circuit 18 receives an ODT0 signal and a WRITE0 signal from the command decoder 32 and outputs an ODTC signal from the decoder 36. Although details will be described later, the pre-stage circuits 26-1 to 26-3 are controlled by the ODTC signal. The ODT0 signal is a signal that is activated when an ODT signal is input to the command terminal 12, and the WRITE0 signal is a signal that is activated when a write signal (WRITE instruction) is input to the command terminal 12.

  The ODT0 signal changes from OD1 to OD2 and OD3 in synchronization with the internal clock LCLK. The WRITE0 signal becomes WR1 and WR2 in synchronization with the internal clock LCLK. When OD3 = H and WR2 = L, OD4 is activated to a high level, but WR3 is not activated. On the other hand, when OD3 = H and WR2 = H, OD4 is deactivated to a low level and WR3 is activated to a high level.

  FIG. 5 is a first waveform diagram of each signal in the ODT control circuit 18. As described above, in the case of a DRAM having a dynamic ODT function, an ODT signal is input from an external memory controller before a write signal. These signals input asynchronously from the memory controller are input to the ODT control circuit 18 in synchronization with the rising edge of the internal clock LCLK. In FIG. 5, first, the ODT0 signal is activated, and OD1, OD2, and OD3 are also activated. Since WRITE0 is at a low level at this stage, OD3 = H and WR3 = L, so OD4 = H and WR4 = L. At this timing (tAON), the decoder 36 issues an ODTC signal that sets the unit buffer 48 to the first termination resistance value RTT_NOM.

  Next, when the WRITE0 signal is activated, WR1 and WR2 become H and WR3 = H in the state of OD3 = H. On the other hand, OD4 returns to L. At this timing (tADC), the decoder 36 issues an ODTC signal for setting the unit buffer 48 to the second termination resistance value RTT_WR. The actual write operation is executed after tADC, and the WRITE0 signal and the ODT0 signal are sequentially inactivated. In response to this, the first termination resistance value RTT_NOM is reset at tADC, and the unit buffer 48 is returned to the high impedance state at tAOF.

  FIG. 6 is a second waveform diagram of each signal in the ODT control circuit 18. In FIG. 6, the write signal is input immediately after the ODT signal. For this reason, the ODT0 signal and the WRITE0 signal are simultaneously activated in synchronization with the same rising edge of the internal clock LCLK. As a result, WR2 = H after OD3 = H and WR2 = L, and half a clock cycle after OD4 = H. When OD3 = H and WR = H, OD4 = L and WR4 = H are changed. Therefore, the second termination resistance value RTT_WR is set shortly after the first termination resistance value RTT_NOM is set. If the termination resistance value of the unit buffer 48 changes in multiple stages in such a short time, it is not preferable because a hazard occurs in the external data bus connected to the data terminal 14.

  In the present embodiment, a solution for such a problem that occurs when the timing at which the ODT signal and the write signal are sent from the external memory controller is too close is proposed. Before that, the adjustment circuit 30 and the output buffer 40 are proposed. Details of the overall configuration and operation will be described with reference to FIGS. Thereafter, as the first to third embodiments, the circuit configuration and operation of the ODT control circuit 18 that solves the above-described problem will be described.

  FIG. 7 is a circuit diagram of the pre-stage circuit 26 and the unit buffer 48. Here, the description will be given with respect to the preceding circuit 26-3 and the unit buffer 48-7, but the same applies to the other preceding circuits 26 and the unit buffer 48. The unit buffer 48-7 includes a pull-up circuit PU and a pull-down circuit PD. The pull-up circuit PU includes a plurality of PMOS transistors 44-1 to 44-n connected in parallel between the power supply line to which the power supply potential VDDQ is supplied and the data terminal 14. The pull-down circuit PD includes a plurality of NMOS transistors 46-1 to 46-n connected in parallel between the power supply line to which the power supply potential VSSQ is supplied and the data terminal 14.

  The pre-stage circuit 26-3 includes a PU control circuit 38 corresponding to the pull-up circuit PU and a PD control circuit 39 corresponding to the pull-down circuit PD. The PU control circuit 38 includes control circuits C1P to CnP corresponding to the PMOS transistors 44-1 to 44-n. A control signal 141P is supplied from each control circuit to the gate electrode of the PMOS transistor 44. Of each bit DP constituting the control signal 141P, a transistor corresponding to a bit at a low level is turned on. The channel widths of the PMOS transistors 44-1 to 44-n are weighted by a power of 2.

  The control circuit C1P includes a first control circuit D1P and a second control circuit E1P. The data signal DP and the ODTC signal are supplied to the first control circuit D1P, and the ZQP signal and the SR signal (not shown) are supplied to the second control circuit E1P.

  The ODTC signal supplied from the ODT control circuit 18 is a signal for causing the output buffer 40 to function as a termination resistor having a predetermined impedance. Specifically, the ODTC signal instructs setting to the first termination resistance value RTT_NOM and the second termination resistance value RTT_WR described above. The ODTC signal is selectively supplied to one or more of the plurality of first control circuits and second control circuits. The decoder 36 of the ODT control circuit 18 can set the unit buffer 48 to the first termination resistance value RTT_NOM or the second termination resistance value RTT_WR by selecting the supply destination of the ODTC signal.

  The ZQP signal is a signal for setting enable / disable of each PMOS transistor 44, and the impedance of the pull-up circuit PU is adjusted by the ZQP signal. The ZQP signal is generated by a calibration circuit (not shown). The PMOS transistor 44n may be always enabled regardless of the ZQP signal. The ZQP signal is an n-bit signal supplied individually for each PMOS transistor 44.

  The PD control circuit 39 includes control circuits C1N to CnN corresponding to the NMOS transistors 46-1 to 46-n. A control signal 141N is supplied from each control circuit to the gate electrode of the NMOS transistor 46. Of the bits DN constituting the control signal 141N, the transistor corresponding to the bit at the high level is turned on. The channel widths of the NMOS transistors 46-1 to 46-n are weighted to a power of 2.

  The control circuit C1N includes a first control circuit D1N and a second control circuit E1N. A data signal DN and an ODTC signal are supplied to the first control circuit D1N, and a ZQN signal and an SR signal (not shown) are supplied to the second control circuit E1N. The ZQN signal is a signal for setting enable / disable of each NMOS transistor 46, and the impedance of the PD control circuit 39 is adjusted by the ZQN signal. The NMOS transistor 46n may always be enabled regardless of the ZQN signal. The ZQN signal is an n-bit signal supplied individually for each NMOS transistor 46.

  In summary, the impedances of the PMOS transistor 44 and the NMOS transistor 46 at the time of reading are adjusted to the target impedance by the ZQP and ZQN signals. By the ODTC signal, the PMOS transistor 44 and the NMOS transistor 46 are set to termination resistance values. There are several types of termination resistance values. For example, the first termination resistance value RTT_NOM is set by supplying the ODTC signal to the control circuits C1P to C4P and C1N to C4N, and the second termination resistance is provided by supplying the ODTC signal to the control circuits C2P to C6P and C2N to C6N. The value RTT_WR may be set.

  FIG. 8 is a circuit diagram of the first control circuit D1P. The first control circuit D1P includes a tristate buffer 72 and a PMOS transistor 74. The tristate buffer 72 is supplied with the data signal DP and the ODTC signal, and the PMOS transistor 74 is supplied with the ODTC signal. The ODTC signal is low active.

  When the ODTC signal is at a low level, the tri-state buffer 72 is invalidated, the PMOS transistor 74 is turned on, and a high-level control signal DXT is output. When the ODTC signal is at a high level, an inverted signal of the data signal DP is output as the control signal DXT.

  FIG. 9 is a circuit diagram of the second control circuit E1P. The second control circuit E1P includes a tristate buffer 76, an NMOS transistor 78, and a slew rate adjustment circuit 82. The tristate buffer 76 is supplied with the control signal DXT and the ZQP signal, and the NMOS transistor 78 is supplied with the ZQP signal.

  When the ZQP signal is high level, the NMOS transistor 78 is turned on, and the input signal of the slew rate adjusting circuit 82 is low level. That is, the output signal DP from the second control circuit E1P is fixed at a high level, and the corresponding PMOS transistor 44 of the pull-up circuit PU is invalidated. When the ZQP signal is at a low level, the control signal DXT is input to the slew rate adjusting circuit 82.

  The slew rate adjusting circuit 82 adjusts the slew rate of the data signal DP by a slew rate setting signal (SR signal). The slew rate setting signal is based on the setting value of the mode register 53. The slew rate adjustment is described in detail in JP 2010-50856 (US 7,952,383).

  In summary, on / off of each PMOS transistor 44 included in the pull-up circuit PU is collectively controlled by the data signal DP. Further, when the ODT function is validated, the pull-up circuit PU is controlled by the ODT signal. Each PMOS transistor 44 is individually enabled / disabled by a ZQP signal.

  FIG. 10 is a circuit diagram of the first control circuit D1N. The first control circuit D1N includes a tristate buffer 73 and an NMOS transistor 75. The tristate buffer 73 is supplied with the data signal DN and the ODTC signal, and the NMOS transistor 75 is supplied with the ODTC signal.

  When the ODTC signal is at a low level, the tristate buffer 73 is invalidated, the NMOS transistor 75 is turned on, and a low level control signal DXC is output. When the ODTC signal is at a high level, an inverted signal of the data signal DN is output as the control signal DXC.

  FIG. 11 is a circuit diagram of the second control circuit E1N. The second control circuit E1N includes a tristate buffer 77, a PMOS transistor 79, and a slew rate adjustment circuit 83. The tri-state buffer 77 is supplied with the control signal DXC and the ZQN signal, and the PMOS transistor 79 is supplied with the ZQN signal.

  When the ZQN signal is at low level, the PMOS transistor 79 is turned on, and the input signal of the slew rate adjusting circuit 83 is at high level. That is, the output signal DN from the second control circuit E1N is fixed at a low level, and the pull-down circuit PD is invalidated. When the ZQN signal is at a high level, the control signal DXC is input to the slew rate adjustment circuit 83. The slew rate adjusting circuit 83 also adjusts the slew rate of the data signal DN by a slew rate setting signal (SR signal).

[First Embodiment]
FIG. 12 is a circuit diagram of the ODT control circuit 18 in the first embodiment. FIG. 13 is a waveform diagram of each signal in the ODT control circuit 18 of the first embodiment. In the first embodiment, a detection circuit 50 is added to the ODT control circuit 18. The detection circuit 50 may be built in the ODT control circuit 18 or may be provided outside the ODT control circuit 18. The detection circuit 50 activates the OW1 and OW2 to the high level and activates the OW3 signal to the high level when the ODT0 signal and the WRITE0 signal as shown in FIG. 6 are detected at the same rise edge of the internal clock LCLK. To stop doing.

  In the first embodiment, in order to prevent the termination resistance value of the output buffer 40 from changing in a short time, the OD4 signal (adjustment signal) is not activated when simultaneous input of the ODT0 signal and the WRITE0 signal occurs. As a result, the second termination resistance value RTT_WR is directly set without going through the first termination resistance value RTT_NOM.

  First, when the ODT0 signal and the WRITE0 signal are input at the same timing, the detection circuit 50 sets the OW3 signal to a low level. For this reason, the OD3 signal is activated to a high level when the OD2 signal becomes a high level, not when the OD1 signal becomes a high level. In other words, the timing at which the OD3 signal goes high is delayed by one clock. As a result, since there is no period in which OD3 (first intermediate signal) = H and WR2 (second intermediate signal) = L, the OD4 signal is fixed at a low level, and the first termination resistance value RTT_NOM is set. Absent. As described above, when the detection circuit 50 detects the simultaneous input of the ODT0 signal and the WRITE0 signal, the activation timing of the OD3 signal (first intermediate signal) can be delayed to prevent the data bus from causing a hazard. .

[Second Embodiment]
FIG. 14 is a circuit diagram of the ODT control circuit 18 in the second embodiment. FIG. 15 is a waveform diagram of each signal in the ODT control circuit 18 of the second embodiment. In the second embodiment, a detection circuit 54 is added to the transmission path of the WRITE0 signal. The detection circuit 54 activates OW1 and OW2 to a high level when the ODT0 signal and the WRITE0 signal are detected at the same rising edge of the internal clock LCLK, and before the WR4 signal is activated to a high level, 2 intermediate signal) is activated to a high level.

  Also in the second embodiment, in order to prevent the termination resistance value of the output buffer 40 from changing in a short time, the OD4 signal (adjustment signal) is not activated when simultaneous input of the ODT0 signal and the WRITE0 signal occurs.

  First, when the ODT0 signal and the WRITE0 signal are input at the same timing, the detection circuit 54 activates the OW2 signal to a high level. For this reason, the WR3 signal is also activated to the high level at the same timing as when the OD3 signal (first intermediate signal) becomes the high level. As a result, since there is no period in which OD3 (first intermediate signal) = H and WR2 (second intermediate signal) = L, the OD4 signal (adjustment signal) is fixed at a low level, and the first termination resistance value RTT_NOM is set. It is never done. As described above, when the detection circuit 54 detects the simultaneous input of the ODT0 signal and the WRITE0 signal, it is possible to prevent the data bus from causing a hazard by advancing the activation timing of the WR2 signal.

[Third Embodiment]
FIG. 16 is a circuit diagram of the ODT control circuit 18 in the third embodiment. FIG. 17 is a waveform diagram of each signal in the ODT control circuit 18 of the third embodiment. In the third embodiment, a first combining unit 56 and a second combining unit 58 are installed at the input portion of the ODT control circuit 18. The first synthesis unit 56 activates the OD0 signal to a high level when ODT0 = H and WRITE0 = L. The second synthesis unit 58 activates the WR0 signal to a high level when ODT0 = H and WRITE0 = H. When the ODT0 signal and the WRITE0 signal are input at the same timing, ODT0 = H and WRITE0 = L are not satisfied, so the OD0 signal is not activated. Therefore, the OD3 signal (first intermediate signal) is activated (generated). ) And the OD4 signal (adjustment signal) is not activated to a high level.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Clock terminal 12 Command terminal 13 Address terminal 14 Data terminal 15, 16 Power supply terminal 17 Data strobe terminal 18 ODT control circuit 20 Output control circuit 21 Clock input circuit 22 Output adjustment circuit 24 Input buffer 26 Pre-stage circuit 28 Buffer group 30 Adjustment circuit 31 Command input circuit 32 Command decoder 34 ESD element 36 Decoder 38 PU control circuit 39 PD control circuit 40 Output buffer 41 Address input circuit 42 Address latch circuit 44 PMOS transistor 46 NMOS transistor 48 Unit buffer 50 Detection circuit 51 Row system control circuit 52 column control circuit 53 mode register 54 detection circuit 56 first synthesis unit 58 second synthesis unit 60 memory cell array 61 row decoder 62 Ram decoder 63 Sense circuit 64 Data amplifier 70 Data input / output circuit 72, 73, 76, 77 Tristate buffer 74, 79 PMOS transistor 75, 78 NMOS transistor 80 DLL circuit 82, 83 Slew rate adjustment circuit 90 Internal voltage generation circuit 100 Pad Group 200 Array system circuit LCLK Internal clock PU Pull-up circuit PD Pull-down circuit

Claims (7)

A data terminal;
An output buffer connected to the data terminal;
An adjustment circuit for adjusting the impedance of the output buffer,
When the write signal is input after the ODT signal is input, the adjustment circuit sets the impedance of the output buffer to the first termination resistance value and then changes the setting to the second termination resistance value. The semiconductor device, wherein when the write signal input timing is within a predetermined time difference, the second termination resistance value is set without setting the first termination resistance value in the output buffer. The ODT signal and the write signal are input in synchronization with the same clock signal,
The adjustment circuit sets the second termination resistance value without setting the first termination resistance value in the output buffer when the ODT signal and the write signal are input at the same clock timing. The semiconductor device according to claim 1. A detection circuit for detecting simultaneous input of the ODT signal and the write signal;
3. The semiconductor device according to claim 2, wherein the detection circuit invalidates an adjustment signal for setting the first termination resistance value in the output buffer when detecting the simultaneous input. 4. The adjustment circuit synthesizes the adjustment signal when one of the first intermediate signal generated from the ODT signal and the second intermediate signal generated from the write signal is active and the other is inactive. And
4. The semiconductor device according to claim 3, wherein the detection circuit prevents synthesis of the adjustment signal by matching activation timings of the first intermediate signal and the second intermediate signal. 5.   The detection circuit matches the activation timings of the first intermediate signal and the second intermediate signal by delaying the activation timing of the first intermediate signal from the activation timing of the second intermediate signal. The semiconductor device according to claim 4.   The detection circuit matches the activation timings of the first intermediate signal and the second intermediate signal by making the activation timing of the second intermediate signal earlier than the activation timing of the first intermediate signal. The semiconductor device according to claim 4. The adjustment circuit includes:
A first combining unit that combines the ODT signal and the write signal to combine the first intermediate signal;
A second combining unit that combines the ODT signal and the write signal to combine the second intermediate signal;
The semiconductor device according to claim 2, wherein the first synthesis unit does not generate the first intermediate signal when the ODT signal and the write signal are input simultaneously.

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