KR20170036583A - Method of operating non-volatile memory device, non-volatile memory device and memory system including the same - Google Patents

Abstract

The present invention relates to an operating method of a non-volatile memory device including a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of vertical strings elongated in a vertical direction on a substrate. The method performs a first memory operation for a first memory block among the memory blocks. When a state signal is in a ready state of the non-volatile memory device for a reference time or more after the first memory operation is completed, a curing operation is performed in a part of the first memory block to move charges in a channel film of at least one vertical string among the vertical strings.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, a nonvolatile memory device, and a memory system including the nonvolatile memory device.

The present invention relates to semiconductor memory devices, and more particularly, to a method of operating a non-volatile memory device, a non-volatile memory device, and a memory system including the same.

The semiconductor memory device may be classified into a volatile semiconductor memory device and a nonvolatile semiconductor memory device. The volatile semiconductor memory device has a drawback that the read and write speed is fast but the stored contents disappear when the power supply is interrupted. On the other hand, the nonvolatile semiconductor memory device preserves its contents even if the power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be stored regardless of whether power is supplied or not.

Non-volatile semiconductor memory devices include, but are not limited to, a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM) Erasable programmable read-only memory (EEPROM), and the like.

A representative example of a non-volatile memory device is a flash memory device. The flash memory device can be used for audio and video of electronic devices such as a computer, a mobile phone, a PDA, a digital camera, a camcorder, a voice recorder, an MP3 player, a personal digital assistant (PDA), a handheld PC, a game machine, a fax machine, a scanner, And is widely used as a data storage medium.

It is an object of the present invention to provide a method of operating a nonvolatile memory device capable of improving performance.

It is an object of the present invention to provide a nonvolatile memory device that implements the above method of operation.

An object of the present invention is to provide a memory system including the non-volatile memory device.

According to an aspect of the present invention, there is provided a method of operating a non-volatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate The method comprising: performing a first memory operation on a first memory block among the memory blocks; and when a status signal indicates a ready state of the nonvolatile memory device for a reference time or longer after completion of the first memory operation , And performs a curing operation on a part of the first memory block so that charge is moved in a channel film of at least one vertical string of the vertical strings.

In one embodiment, each of the plurality of vertical strings includes at least one string select transistor coupled to a bit line coupled to a page buffer, at least one ground select transistor coupled to a common source line, And a plurality of cell transistors connected in series between the at least one string selection transistor and the at least one ground selection transistor.

Turning off at least one string selection transistor of a first one of the plurality of vertical strings to perform the curing operation and applying a voltage to the word lines connected to the cell transistors of the first vertical string, Each of the turn-on voltages corresponding to each of the ground select lines connected to the select transistor and the common source line connected to the at least one ground select transistor can be maintained at the ground voltage.

Each of the turn-on voltages may have a level higher than each of the threshold voltages of the cell transistors and the ground selection transistor.

And a plurality of vertical strings connected to the at least one string selection transistor of the first vertical string to block connection of a page buffer and a bit line connected to a first vertical string of the plurality of vertical strings to perform the curing operation, On voltages corresponding to a select line, word lines connected to the cell transistors of the first vertical string and a ground select line connected to the ground select transistor, respectively, and the at least one ground select transistor The common source line to be connected can be maintained at the ground voltage.

Each of the corresponding turn-on voltages may have a level higher than each of the threshold voltages of the string selection transistor, the cell transistors, and the ground selection transistor.

The curing operation may be performed concurrently on a plurality of vertical strings included in the first memory block.

In an embodiment, the first memory operation is performed sequentially for the memory blocks including the first memory block, and the curing operation is performed when the memory blocks include at least one bad block, And may be performed simultaneously with respect to the remaining memory blocks except for the at least one bad memory block.

The curing operation may be performed excluding the at least one bad memory block based on a comparison of a block address for selecting the memory blocks and a set of bad block addresses including an address of the at least one bad memory block .

Wherein the bad block address set includes a first bad block address pre-stored in a bad block register of an address decoder connected to the memory blocks prior to a power-up sequence of the non-volatile memory device, And a second bad block address stored in the block register.

In an embodiment, the method may further perform a second memory operation on at least a portion of the first memory block after completion of the curing operation.

Wherein the first memory operation is a program operation performed for at least a portion of the first memory block and the second memory operation is a read operation performed for at least a portion of the first memory block.

In order to accomplish one aspect of the present invention, a nonvolatile memory device according to embodiments of the present invention includes a memory cell array, a voltage generator, an address decoder, and a control circuit. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate. The voltage generator generates word line voltages based on the control signal. An address decoder provides the word line voltages to the memory cell array based on an address signal. Wherein the control circuit performs a first memory operation on a first one of the plurality of memory blocks and, after completion of the first memory operation, the status signal indicates a ready state of the nonvolatile memory device A curing operation is performed in a part of the first memory block to cause a charge to move in a channel film of at least one vertical string of the vertical strings in response to a command from an external memory controller, And controls the address decoder.

In one embodiment, each of the plurality of vertical strings includes at least one string select transistor coupled to a bit line coupled to a page buffer, at least one ground select transistor coupled to a common source line, And a plurality of cell transistors connected in series between the at least one string selection transistor and the at least one ground selection transistor.

Wherein the address decoder turns off at least one string selection transistor of a first one of the plurality of vertical strings and, when performing the curing operation, turns off at least one string selection transistor of the first vertical string, On voltages corresponding to each of the ground selection lines connected to the at least one ground selection transistor and a common source line connected to the at least one ground selection transistor at the ground voltage. Each of the turn-on voltages may have a level higher than each of the threshold voltages of the cell transistors and the ground selection transistor.

Wherein the control circuit interrupts the connection of the page buffer with a bit line connected to a first one of the plurality of vertical strings during the curing operation, At least one string select line coupled to the string select transistor, word lines coupled to the cell transistors of the first vertical string, and at least one ground select line coupled to the at least one ground select transistor, On voltages and maintains a common source line connected to the at least one ground selection transistor at a ground voltage. Each of the turn-on voltages may have a level higher than each of the threshold voltages of the string selection transistor, the cell transistors, and the ground selection transistor.

In an embodiment, the address decoder may include a bad block address register, an address comparator, a decoder, and a plurality of select circuits. The bad block address register may store an address of at least one bad block among the memory blocks. The address comparator compares a block address for selecting two or more of the memory blocks with a bad block address set stored in the bad block address register and outputs a match signal indicating whether the block address matches the bad block address set can do. The decoder may decode the match signal and the block address to provide a plurality of block select signals. The plurality of selection circuits may be coupled to each of the memory blocks and may selectively provide turn-on voltages applied from the voltage generator in performing the curing operation to each of the memory blocks based on the block selection signals have.

In order to accomplish one aspect of the present invention, a memory system according to embodiments of the present invention includes at least one nonvolatile memory device and a memory controller. The memory controller controls the at least one non-volatile memory device. The at least one non-volatile memory device includes a memory cell array, a voltage generator, an address decoder, and a control circuit. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate. The voltage generator generates word line voltages based on the control signal. An address decoder provides the word line voltages to the memory cell array based on an address signal. Wherein the control circuit performs a first memory operation on a first one of the plurality of memory blocks and, after completion of the first memory operation, the status signal indicates a ready state of the nonvolatile memory device A cueing operation for causing a charge to move in a channel film of at least one vertical string of the vertical strings is performed in a part of the first memory block in response to a command from the memory controller, And controls the address decoder.

In an embodiment, the control circuit may include a status signal generator that provides the status signal to the memory controller indicating at least the operational status of the non-volatile memory device based on the command. The memory controller may include a counter for comparing the status signal in the ready state with the reference time to provide a determination signal and a processor for generating the command based on the determination signal and a request from the host.

The processor may send a command to the nonvolatile memory device indicating the curing operation if the determination signal indicates that the ready state continues for more than the reference time.

In a method of operating a non-volatile memory device and a non-volatile memory device according to embodiments of the present invention, a first memory operation is performed on a first memory block, and when a ready state of the non-volatile memory device continues for more than a reference time , Performing a curing operation on at least a portion of the first memory block, and then performing a second memory operation on the first memory block to reduce the number of error bits to improve performance.

1 is a block diagram illustrating a memory system in accordance with embodiments of the present invention.
FIG. 2A is a block diagram illustrating a configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention. FIG.
Figure 2B is a block diagram illustrating a non-volatile memory device in the memory system of Figure 1 in accordance with embodiments of the present invention.
3 is a block diagram illustrating the memory cell array of FIG. 2B.
4 is a plan view showing an example of a memory block included in the memory cell array of FIG.
5 is a perspective view taken along line II 'of the memory block shown in FIG.
6 is a cross-sectional view taken along line II 'of the memory block shown in FIG.
FIG. 7 is an enlarged view showing one of the cell transistors included in the memory block shown in FIGS.
Fig. 8 is an equivalent circuit diagram of the memory block shown in Figs. 4 to 6. Fig.
9 is a conceptual diagram for explaining the plane structure of the equivalent circuit diagram shown in Fig.
10 is a block diagram showing a configuration of a control circuit in the nonvolatile memory device of FIG. 2 according to the embodiment of the present invention.
11 is a block diagram showing the configuration of a voltage generator in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.
12A is a flowchart illustrating a method of operating a non-volatile memory device according to embodiments of the present invention.
12B is a timing diagram illustrating the operation of the memory system of FIG. 1 when the method of operation of FIG. 12A is performed.
13 is a flowchart illustrating an example of a curing operation in the method of operation of FIG. 12A according to embodiments of the present invention.
Figure 14 shows one of the vertical strings in the memory block of Figure 8 applied to the operating method of Figure 12a.
15 shows voltages applied to the first vertical string in the curing operation of FIG.
16 is a flowchart illustrating an example of a curing operation in the method of operation of FIG. 12A according to embodiments of the present invention.
FIG. 17 shows one of the vertical strings in the memory block of FIG. 8 to which the operating method of FIG. 12 is applied.
Figure 18 shows the voltages applied to the first vertical string in the curing operation of Figure 16;
19A to 19F are views for explaining the concept of the present invention.
20 shows that the curing operation according to the embodiment of the present invention is performed simultaneously for a plurality of vertical strings included in one memory block.
21 is a block diagram showing the configuration of an address decoder in the nonvolatile memory device of FIG. 2 according to the embodiments of the present invention.
FIG. 22 shows the address decoder shown in FIG. 21 in detail.
23 shows a configuration of the memory system of Fig.
24 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.
25 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.
26 is a block diagram illustrating a universal flash storage (UFS) according to embodiments of the present invention.
27 is a block diagram illustrating a mobile device in accordance with embodiments of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a memory system in accordance with embodiments of the present invention.

Referring to FIG. 1, a memory system (or non-volatile memory system) 10 may include a memory controller 20 and at least one non-volatile memory device 30.

The memory system 10 shown in FIG. 1 may include all data storage media based on a flash memory such as a memory card, a USB memory, an SSD, and the like.

The nonvolatile memory device 30 can perform erase, write, or read operations under the control of the memory controller 20. [ To this end, the nonvolatile memory device 30 receives the command CMD, the address ADDR, and the data DATA via the input / output line. In addition, the nonvolatile memory device 30 may be provided with a power supply PWR via a power supply line. The command CMD may include a command latch enable CLE, an address latch enable ALE, a chip enable CE /, a write enable WE /, a read enable RE / and the like. The nonvolatile memory device 30 may send a status signal RnB to the memory controller 20. [ The state signal RnB is a signal indicating the operation state of the nonvolatile memory device 30. When the state signal RnB is low, it indicates that the nonvolatile memory device 30 is in the busy state. When the nonvolatile memory device 30 is in the high level, , I.e., an idle state.

When the nonvolatile memory device 30 performs the program operation, the status signal RnB may be in the busy state. When the nonvolatile memory device 30 does not perform operations such as program, read, erase, and the like, the status signal RnB may be in a ready state. The memory controller 20 compares the ready state signal RnB with the reference time when the state signal RnB indicates the ready state and if the ready state continues for more than the reference time, The command CMD and the address ADDR for instructing the curing operation can be transmitted. The nonvolatile memory device 30 may perform the curing operation with respect to the memory area designated by the address ADDR in response to the command CMD. The non-volatile memory device 30 may include a memory cell array composed of a plurality of memory blocks.

FIG. 2A is a block diagram illustrating a configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention. FIG.

2A, the memory controller 20 includes at least one processor 21, a buffer memory 22, an error correction circuit 23, a host interface 25, a nonvolatile memory interface 26, and a counter 27 ).

The buffer memory 22 may temporarily store data necessary for driving the memory controller 20. In addition, the buffer memory 22 may buffer data to be used for a program operation upon a write request.

The error correction circuit 23 calculates the error correction code value of the data to be programmed in the write operation, corrects the data read in the read operation based on the error correction code value, The error of the recovered data can be corrected. Although not shown, a code memory for storing code data necessary for driving the memory controller 20 may be further included. The code memory may be implemented as a non-volatile memory device.

The host interface 25 can provide an interface function with an external host. The non-volatile memory interface 26 may provide an interface function with the non-volatile memory device 1100.

The counter 27 receives the status signal RnB from the nonvolatile memory interface 26 and compares the status signal RnB with the reference time when the status signal RnB indicates the ready status, If it continues for more than the reference time, it can provide the processor 21 with a determination signal DS indicative thereof. The processor 21 generates a command and an address for instructing the curing operation in response to the determination signal DS indicating that the ready state continues for the reference time or more and outputs the generated command and address to the nonvolatile memory interface 26 To the nonvolatile memory device (30). For this purpose, the counter 27 may include a register for storing the reference time therein.

Figure 2B is a block diagram illustrating a non-volatile memory device in the memory system of Figure 1 in accordance with embodiments of the present invention.

2B, the non-volatile memory device 30 includes a memory cell array 100, an address decoder 400, a page buffer circuit 460, a data input / output circuit 470, a control circuit 500, 600).

The memory cell array 100 may be connected to the address decoder 400 via at least one string select line SSL, a plurality of word lines WLs and at least one ground select line GSL. In addition, the memory cell array 100 may be connected to the page buffer circuit 460 through a plurality of bit lines BLs.

The memory cell array 100 may include a plurality of non-volatile memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs.

In one embodiment, the memory cell array 100 may be a three dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 100 may include vertical memory cell strings including a plurality of memory cells stacked together. A detailed description of a three dimensional memory cell array is provided in U. S. Patent Nos. 7,679, 133; 8,553,466; 8,654,587; 8,559,235 and U.S. Publication No. 2011/0233648.

3 is a block diagram illustrating the memory cell array of FIG. 2B.

Referring to FIG. 3, the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. In the embodiment, the memory blocks BLK1 to BLKz are selected by the address decoder 400 shown in Fig. For example, the address decoder 400 can select the memory block BLK corresponding to the block address among the memory blocks BLK1 to BLKz. Also, the address decoder 400 may select at least two memory blocks corresponding to the block address among the memory blocks BLK1 to BLKz.

4 is a plan view showing an example of a memory block included in the memory cell array of FIG. 2B. 5 is a perspective view taken along line I-I 'of the memory block shown in FIG. 6 is a cross-sectional view taken along the line I-I 'of the memory block shown in FIG.

4 to 6 show a part of one memory block BLKa of the plurality of memory blocks BLK1, BLK2, ..., BLKz included in the memory cell array 100 of FIG.

4 to 6, the memory block BLKa may be formed on the substrate 111 in a three-dimensional structure along the first to third directions D1, D2, and D3.

The substrate 111 may be a well having a first conductivity type. For example, the substrate 111 may be a P-well implanted with a Group III element such as boron (B, Boron). In one embodiment, the substrate 111 may be a pocket P-well formed in the N-well. Hereinafter, it is assumed that the substrate 111 is a P-well (or a pocket P-well). However, the substrate 111 is not limited to having a P-conductive type.

A plurality of doping regions 121, 122 and 123 extending along the first direction D1 and spaced apart from each other along the second direction D2 may be formed on the substrate 111. [ FIGS. 2 to 4 illustrate a first doped region 121, a second doped region 122, and a third doped region 123.

The plurality of doped regions 121, 122, and 123 may have a second conductivity type different from the first conductivity type, which is the conductivity type of the substrate 111. [ For example, the plurality of doped regions 121, 122, 123 may comprise an N-type conductive material. Hereinafter, it is assumed that a plurality of doped regions 121, 122, and 123 have an N-conductive type. However, the plurality of doped regions 121, 122, and 123 are not limited to having an N-conductive type.

As will be described later, the plurality of doped regions 121, 122, and 123 may be connected in common to the common source line.

A plurality of insulation layers 112 and 112a are arranged in a third direction D3 perpendicular to the substrate 111 between the adjacent doped regions of the plurality of doped regions 121, And may be sequentially formed on the substrate 111. The plurality of insulating films 112 and 112a may be spaced from each other along the third direction D3. The plurality of insulating films 112 and 112a may extend along the first direction D1.

In one embodiment, the plurality of insulating films 112 and 112a may include an insulating material such as silicon oxide.

The thickness of the insulating film 112a contacting the substrate 111 among the plurality of insulating films 112 and 112a may be thinner than the thickness of the other insulating films 112. [

A plurality of insulating films 112 and 112a are sequentially disposed along the first direction D1 and between the adjacent doped regions of the plurality of doped regions 121, 122 and 123 along the third direction D3. A plurality of pillar pillars PL11, PL12, PL21, and PL22 passing through can be formed. The plurality of pillars PL11, PL12, PL21, and PL22 can be in contact with the substrate 111 through the plurality of insulating films 112 and 112a.

In one embodiment, the plurality of pillars PL11, PL12, PL21, and PL22 may be formed by vertically patterning a plurality of insulating films 112 and 112a.

In one embodiment, each of the plurality of pillars PL11, PL12, PL21, PL22 may include a channel layer 114 surrounding the inner material 115 and the inner material 115.

The channel layer 114 may comprise a semiconductor material (e.g., silicon) having the same conductivity type as the conductivity type of the substrate 111. The channel film 114 may be comprised of poly-silicon. For example, the channel film 114 may have a P-conductive type. Hereinafter, it is assumed that the channel film 114 has a P-conductive type. However, the channel film 114 is not limited to having a P-conductive type. For example, the channel layer 114 may comprise an intrinsic semiconductor having no conductivity type.

The inner material 115 may comprise an insulating material. In one embodiment, the inner material 115 may comprise silicon oxide. In another embodiment, the inner material 115 may comprise an air gap.

A charge storage layer 116 (not shown) is formed on the surface of the plurality of insulating films 112 and 112a and the channel film 114 between the plurality of insulating films 112 and 112a, May be formed. The charge storage layer 116 may store data by trapping charge from the channel layer 114.

A plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 are formed in a space surrounded by the charge storage film 116, as shown in FIGS. 5 and 6, GEL10) may be formed. Therefore, each of the gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10 can be formed at different heights from the substrate 111. Illustratively, the memory block BLKa shown in FIGS. 4 to 6 includes the first to tenth gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, and GEL7 , GEL8, GEL9, GEL10).

 In one embodiment, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10 may comprise a metallic conductive material such as tungsten.

In another embodiment, the plurality of gate electrode layers (GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10) may comprise a non-metallic conductive material such as polysilicon have.

The plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 may extend along the first direction D1.

Thus, as shown in FIGS. 5 and 6, a plurality of insulating films 112 and 112a and a plurality of gate electrode films GEL1, GEL2, GEL3, and GEL3 are formed in a third chamber D3 perpendicular to the substrate 111, A plurality of insulating films 112 and 112a and a plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL6, , GEL8, GEL9, and GEL10) may be formed. A plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10, a charge storage film 116 and a channel film 114 are formed in a first direction D1 Can be sequentially formed.

A plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10 are formed on the word line cut (WL CUT) on the plurality of doped regions 121, Lt; / RTI > The word line cut (WL CUT) may expose a plurality of doped regions 121, 122, 123. The word line cut (WL CUT) may extend along the first direction (D1).

In one embodiment, the charge storage layer 116 formed on the top surface of the insulating material at the top of the plurality of insulating materials 112, 112a may be removed.

A plurality of drains 130 may be formed on the plurality of pillars PL11, PL12, PL21, PL22. In one embodiment, the plurality of drains 130 may comprise a semiconductor material having the second conductivity type (e.g., silicon). For example, the plurality of drains 130 may have an N- conductivity type. Hereinafter, it is assumed that the plurality of drains 130 have an N-conduction type. However, the plurality of drains 130 are not limited to having an N-conductive type.

A plurality of bit lines BL1 and BL2 extending in the second direction D2 and spaced apart from each other along the first direction D1 may be formed on the plurality of drains 130. [ In one embodiment, the plurality of bit lines BL1, BL2 and the plurality of drains 130 may be connected to each other through a contact plug.

In one embodiment, the plurality of bit lines BL1, BL2 may comprise a metallic conductive material.

In another embodiment, the plurality of bit lines BL1, BL2 may comprise a non-metallic conductive material such as polysilicon.

Each of the plurality of pillars PL11, PL12, PL21 and PL22 includes a charge storage film 116 and a plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, , GEL10) to construct a single vertical string. 4 to 6, since the plurality of pillars PL11, PL12, PL21 and PL22 are formed on the substrate 111, the memory block BLKa may include a plurality of vertical strings.

Each of the plurality of vertical strings may include a plurality of cell transistors CT stacked in a third direction D 3 perpendicular to the substrate 111. Each of the plurality of gate electrodes GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10 operates as a gate electrode of the cell transistor CT, PL21 and PL22 may operate as a body of the cell transistor CT.

FIG. 7 is an enlarged view showing one of the cell transistors included in the memory block shown in FIGS.

7, the cell transistor CT includes a fifth gate electrode film GEL5, a portion of the pillar PL11 adjacent to the fifth gate electrode film GEL5, and a portion of the fifth gate electrode film GEL5 and the pillar And a charge storage layer 116 formed between the charge storage layer 116 and the charge storage layer 116.

The channel film 114 included in the pillar PL11 may include the same P-type silicon as the substrate 111. [ The channel film 114 may operate as a body of the cell transistor CT. Since the channel film 114 is formed in the third direction D3 perpendicular to the substrate 111, the channel film 114 can operate as a vertical body of the cell transistor CT. Therefore, a vertical channel may be formed in the channel film 114 in the operation of the cell transistor CT.

The charge storage layer 116 may include first to third sub-insulating layers 117, 118, and 119.

The first sub-insulating film 117 may be formed adjacent to the pillar PL11. The first sub-insulating film 117 may function as a tunneling insulating film of the cell transistor CT. In one embodiment, the first sub-insulating layer 117 may include a thermal oxide layer. In another embodiment, the first sub-insulating layer 117 may include a silicon oxide layer.

The second sub-insulating film 118 may store charges tunneled from the channel film 114 through the first sub-insulating film 117. For example, the second sub-insulating film 118 may function as a charge trap layer. In one embodiment, the second sub-insulating layer 118 may include a nitride layer. In another embodiment, the second sub-insulating layer 118 may include a metal oxide layer.

The third sub-insulating film 119 may be formed adjacent to the fifth gate electrode film GEL5. The third sub-insulating film 119 may function as a blocking insulating film of the cell transistor CT. The third sub-insulating film 119 may be formed as a single layer or a multilayer. The third sub-insulating layer 119 may be a high dielectric layer having a higher dielectric constant than the first sub-insulating layer 117 and the second sub-insulating layer 118. In one embodiment, the third sub-insulating layer 119 may include a silicon oxide layer.

In one embodiment, the first to third sub-insulating layers 117, 118, and 119 may have an oxide-nitride-oxide (ONO) structure.

The fifth gate electrode film GEL5 can function as a gate electrode of the cell transistor CT.

Therefore, a plurality of gate electrode films (GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10) that function as gate electrodes, a third sub-insulating film 119 that operates as a blocking insulating film, A first sub-insulating film 117 which operates as a tunneling insulating film and a channel film 114 which operates as a vertical body are stacked in a third direction perpendicular to the substrate 111 Of the cell transistors CT.

Each of the plurality of cell transistors CT may have a cylindrical shape centered on the corresponding pillar PL11, PL12, PL21, PL22.

As will be described later with reference to FIG. 8, the cell transistors CT included in the memory block BLKa can be used for different purposes depending on the height to be formed.

In one embodiment, at least one cell transistor CT formed on top of the cell transistors CT may be used as the string selection transistor SST. For example, the cell transistor CT including the tenth gate electrode film GEL10 may operate as a string selection transistor SST. According to the embodiment, the charge storage film 116 may not be formed in the cell transistor CT operating as the string selection transistor SST.

In one embodiment, at least one cell transistor CT formed below the cell transistors CT may be used as the ground selection transistor GST. For example, the cell transistor CT including the first gate electrode film GEL1 may operate as the ground selection transistor GST. According to the embodiment, the charge storage film 116 may not be formed in the cell transistor CT operating as the ground selection transistor GST.

In one embodiment, the cell transistors CT formed between the at least one string selection transistor SST and the at least one ground selection transistor GST among the cell transistors CT can be used as memory cells have. For example, the cell transistors CT including the second to ninth gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 are respectively connected to the first to eighth memory cells MC1 , MC2, MC3, MC4, MC5, MC6, MC7, MC8).

The plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10 are formed of a string selection line SSL, a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8 and a ground select line GSL.

In one embodiment, a tenth gate electrode film (GEL10) corresponding to the gate electrode of the string selection transistor is connected to a string selection line (SSL), and a first gate electrode film The second to ninth gate electrode layers GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 corresponding to the gate electrodes of the memory cells are connected to the ground selection line GSL, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively.

Fig. 8 is an equivalent circuit diagram of the memory block shown in Figs. 4 to 6. Fig.

8, it is assumed that the memory block shown in FIGS. 4 to 6 further includes one gate electrode film under the first gate electrode film GEL1 and one gate electrode film over the tenth gate electrode film GEL10 .

Referring to FIGS. 4 to 8, a plurality of doped regions 121, 122, and 123 may be connected in common to a common source line CSL.

The vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42 may be formed between the plurality of bit lines BL1, BL2 and the common source line CSL. The vertical strings CS11, CS21, CS31 and CS41 may be connected between the first bit line BL1 and the common source line CSL. The vertical strings CS12, CS22, CS32 and CS42 may be connected between the second bit line BL2 and the common source line CSL.

The vertical strings CS11, CS12, CS21, and CS22 shown in FIG. 8 may correspond to the plurality of pillars PL11, PL12, PL21, and PL22 shown in FIGS. For example, four pillars PL11, PL12, PL21 and PL22, a plurality of gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and GEL10, 116 may form four vertical strings CS11, CS12, CS21, CS22.

In one embodiment, the first gate electrode film GEL1 may form the ground selection transistors GST2 together with the charge storage film 116 and the plurality of pillars PL11, PL12, PL21, and PL22. The first gate electrode film GEL1 corresponding to the gate electrode of the ground selection transistors GST2 may be connected to the ground selection lines GSL12 and GSL22. For example, the ground selection transistors GST formed along the first direction D1 are connected to the same ground selection line, and the ground selection transistors GST spaced along the second direction D2 are different from each other Can be connected to a ground selection line. According to the embodiment, all of the ground selection transistors GST including the first gate electrode film GEL1 may be connected to one ground selection line.

The second to ninth gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 are formed by stacking the charge storage film 116 and the plurality of pillars PL11, PL12, PL21 MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8 can be formed together with the first to eighth memory cells PL1, PL22. The second to ninth gate electrode layers GEL2, GEL3, GEL4, GEL5, GEL6, and GEL6 corresponding to the gate electrodes of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, GEL7, GEL8 and GEL9 may be connected to the first to eighth word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7 and WL8, respectively. That is, the memory cells formed at the same height can be commonly connected to one word line. Therefore, when a voltage is applied to the selected word line among the plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7 and WL8, all the vertical strings CS11, CS12, CS21, The voltage may be applied to all the memory cells connected to the word line.

In one embodiment, the first memory cell MC1 and the eighth memory cell MC8 may be implemented as dummy memory cells DMC1 and DMC2.

The tenth gate electrode film GEL10 may form the string selection transistors SST1, SST together with the charge storage film 116 and the plurality of pillars PL11, PL12, PL21, PL22 . A tenth gate electrode film (GEL10) corresponding to the gate electrode of the string selection transistors (SST) may be connected to the string selection lines (SSL11, SSL21). For example, the string selection transistors SST formed along the first direction D1 are connected to the same string selection line, and the string selection transistors SST spaced along the second direction D2 are different from each other Can be connected to a string selection line.

9 is a conceptual diagram for explaining the plane structure of the equivalent circuit diagram shown in Fig.

Referring to Figures 4-9, the equivalent circuit diagram shown in Figure 8 includes four planes. 8, the vertical strings CS11 and CS12 constitute the first plane PLANEa and the vertical strings CS21 and CS22 constitute the second plane PLANEb and the vertical strings CS31 and CS32 constitute the second plane PLANEb. The vertical strings CS41 and CS42 constitute a third plane PLANEc, and the vertical strings CS41 and CS42 constitute a third plane PLANEc. The first word line WL1 is divided into first sub word lines WLa1 to WLd1 according to a plane and the second word line WL2 is divided into second sub word lines WLa2 to WLd2 according to a plane. The third word line WL3 is divided into third sub word lines WLa3 to WLd3 according to a plane and the fourth word line WL4 is divided into fourth sub word lines WLa4 to WLd4 according to a plane. The fifth word line WL5 is divided into fifth sub word lines WLa5 to Ld5 according to a plane and the sixth word line WL6 is divided into sixth sub word lines WLa6 to WL6 according to a plane, The seventh word line WL7 is divided into seventh sub word lines WLa7 to WLd7 according to a plane and the eighth word line WL8 is divided into eighth sub word lines WLa8 to WLd8).

The vertical strings formed in the same plane are connected to the same string selection line, and the vertical strings formed in different planes can be connected to different string selection lines. For example, the vertical strings CS11 and CS12 included in the first plane PLANEa are connected to the first string selection lines SSL1 and SSL12 and the vertical strings CS1 and CS12 included in the second plane PLANEb CS21, and CS22 may be connected to the second string selection lines SSL21 and SSL22.

By selecting one of the string selection lines SSL11 to SSL42, the vertical strings can be selected on a plane basis. For example, when selecting the first string selection lines SSL11 and SSL12, the vertical strings CS11 and CS12 connected to the first string selection lines SSL11 and SSL12 are connected to a plurality of bit lines BL1 And BL2, and unselected vertical strings CS21 to CS42 may be electrically disconnected from the plurality of bit lines BL1 and BL2.

The vertical strings formed along the second direction D2 are connected to the same bit line, and the vertical strings spaced along the first direction D1 can be connected to different bit lines. For example, the vertical strings CS11, CS21, CS31 and CS41 are connected to the first bit line BL1 and the vertical strings CS12, CS22, CS32 and CS42 are connected to the second bit line BL2 .

Illustratively, FIGS. 4 to 8 show the case where each of the vertical strings has two string selection transistors SST1 and SST2, two ground selection transistors GST1 and GST2, and a string selection transistor SST1 and a ground selection transistor GST2. MC2, MC3, MC4, MC5, MC6, MC7, MC8 between the first to eighth memory cells MC1, MC2, MC3, MC4, MC5. However, the number of the string selection transistors SST, the ground selection transistors GST, and the plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 included in each of the vertical strings is not limited thereto .

As described above, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 corresponds to the corresponding gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, A storage film 116 and a channel film 114. [ Each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8 is connected between the corresponding gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, The charge and discharge can be performed between the charge storage film 116 and the channel film 114 based on the electric field formed in the channel film 114. [ Since the channel film 114 is electrically connected to the substrate 111, a voltage of a different magnitude is applied to the gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 and the substrate 111 The program operation and erase operation can be performed on the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8.

Each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 is connected to the corresponding gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, A program operation can be performed by applying a voltage higher than that of the substrate 111 to tunnel negative charges from the channel film 114 to the charge storage film 116. [

Each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 has a gate electrode layer (GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, The erase operation can be performed by applying a high voltage to the substrate 111 to tunnel negative charges from the charge storage film 116 to the channel film 114. [

In another embodiment, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 is formed of the corresponding gate electrode films GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, A high voltage may be applied to the substrate 111 to perform an erase operation by tunneling positive charges from the channel film 114 to the charge storage film 116. [

Each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 may have a cylindrical shape centered on the corresponding pillars PL11, PL12, PL21, PL22.

Each of the plurality of pillars PL11, PL12, PL21 and PL22 is formed by vertically patterning a plurality of insulating films 112 and 112a. Thus, the plurality of pillars PL11, PL12, PL21, Each of which can be made smaller in width. 6, each of the plurality of pillars PL11, PL12, PL21 and PL22 has a V-shaped cylindrical shape having a lower diameter Wb smaller than the upper diameter Wt and an inclination angle a, Lt; / RTI >

Therefore, the diameters of the pillars in which the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 are formed may differ from each other depending on the height from the substrate 111. [ That is, the diameters of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 may be different from each other depending on the height from the substrate 111. [ For example, a memory cell formed at a lower portion adjacent to the substrate 111 among the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 has a relatively small diameter, MC2, MC3, MC4, MC5, MC6, MC7, and MC8) may have a relatively large diameter.

2B, the control circuit 500 receives a command signal CMD and an address signal ADDR from an external device (for example, a memory controller), and outputs a command signal CMD and an address signal ADDR, The program loop and the read operation of the non-volatile memory device 10 based on the read command. Wherein the program loop may include a program operation and a program verify operation, and the erase loop may include an erase operation and an erase verify.

For example, the control circuit 500 generates control signals CTLs for controlling the voltage generator 600 based on the command signal CMD and generates a row address R_ADDR based on the address signal ADDR. And a column address C_ADDR. The control circuit 500 may provide the row address R_ADDR to the address decoder 400 and provide the column address C_ADDR to the data input / output circuit 470. The row address R_ADDR may include a block address BLK_ADDR. The control circuit 500 may also provide the reset signal RST to the address decoder 400. [ The control circuit 500 may also provide the control signal PBC to the page buffer circuit 460.

The address decoder 400 may be coupled to the memory cell array 100 via at least one string select line SSL, a plurality of word lines WLs, and at least one ground select line GSL. The address decoder 430 determines one of the plurality of word lines WLs as a selected word line based on the row address R_ADDR provided from the control circuit 500, The remaining word lines other than the selected word line among the lines WLs may be determined as unselected word lines.

The voltage generator 600 may generate the word line voltages VWLs required for operation of the non-volatile memory device 30 based on the control signals CTLs provided from the control circuit 500. [ The word line voltages VWLs generated from the voltage generator 600 may be applied to the plurality of word lines WLs through the address decoder 400. [

For example, during an erase operation, the voltage generator 600 may apply an erase voltage to the well of the memory block and a ground voltage to all the word lines of the memory block. In the erase verify operation, the voltage generator 600 may apply an erase verify voltage to all the word lines of one memory block or an erase verify voltage on a word line basis.

For example, in a program operation, the voltage generator 600 may apply a program voltage to a selected word line and apply a program pass voltage to unselected word lines. In addition, during a program verify operation, the voltage generator 600 may apply a program verify voltage to the selected word line and a verify pass voltage to the unselected word lines.

In addition, in a read operation, the voltage generator 600 may apply a read voltage to the selected word line and apply a read pass voltage to the unselected word lines.

The page buffer circuit 460 may be connected to the memory cell array 100 through a plurality of bit lines BLs. The page buffer circuit 460 may include a plurality of page buffers. In one embodiment, one bit line may be coupled to one page buffer. In another embodiment, more than one bit line may be coupled to a page buffer.

The page buffer circuit 460 temporarily stores the data to be programmed in the selected page during the program operation and temporarily stores the read data from the selected page in the read operation.

The data input / output circuit 470 may be connected to the page buffer circuit 460 through the data lines DLs. The data input / output circuit 420 receives the program data DATA from the memory controller 20 and supplies the program data DATA to the page buffer 60 based on the column address C_ADDR provided from the control circuit 500. [ Circuit 460. [0050] The data input / output circuit 470 can supply the memory controller 20 with the read data (DATA) stored in the page buffer circuit 460 based on the column address C_ADDR provided from the control circuit 500 have.

The page buffer circuit 460 and the data input / output circuit 470 read data from the first storage area of the memory cell array 100 and write the read data to the second storage area of the memory cell array 100 can do. That is, the page buffer circuit 460 and the data input / output circuit 470 can perform a copy-back operation.

10 is a block diagram showing a configuration of a control circuit in the nonvolatile memory device of FIG. 2 according to the embodiment of the present invention.

Referring to FIG. 10, the control circuit 500 may include a command decoder 510, an address buffer 520, a control signal generator 530, and a status signal generator 540.

The command decoder 510 may decode the command signal CMD and provide the decoded command D_CMD to the control signal generator 530. [ In an embodiment, the command decoder 510 may provide the decoded command D_CMD to the status signal generator 540. [

The address buffer 520 receives the address signal ADDR and provides the row address R_ADDR of the address signal ADDR to the address decoder 400 and the column address C_ADDR to the data input / output circuit 470 .

The control signal generator 530 receives the decoded command D_CMD and may generate and provide control signals CTLs to the voltage generator 600 based on the operation indicated by the decoded command D_CMD.

The state signal generator 540 generates a state signal RnB indicating the operation state of the nonvolatile memory device 30 based on one of the command CMD and the decoded command D_CMD, To the memory controller (20). For example, the state signal generator 540 may output the state signal RnB to a low level when the non-volatile memory device 30 performs a memory operation such as program, read, erase, Quot;) < / RTI > For example, the status signal generator 540 may output the status signal RnB to a high level when the non-volatile memory device 30 is in an idle state in which it does not perform a memory operation, ) Can be displayed.

11 is a block diagram showing the configuration of a voltage generator in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 11, the voltage generator 600 may include a high voltage generator 610 and a low voltage generator 630. In an embodiment, the voltage generator 600 may further include a negative voltage generator 650.

The high voltage generator 610 generates the program voltage VPGM, the program pass voltage VPPASS, the verify pass voltage VVPASS, and the read pass voltage VSS according to the operation indicated by the decoded command D_CMD in response to the first control signal CTL1. The voltage VRPASS and the erase voltage VRES. Program voltage VPPASS, program verify pass voltage VVPASS and read pass voltage VRPASS are applied to unselected word lines and erase voltage VRES is applied to unselected word lines, May be applied to the substrate of the memory block. The first control signal CTL1 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

The low voltage generator 630 may generate the program verify voltage VPV and the read voltage VRD erase verify voltage VEV in response to the operation indicated by the decoded command D_CMD in response to the second control signal CTL2 have. The program verify voltage VPV, the read voltage VRD and the erase verify voltage VEV may be applied to the selected word line in accordance with the operation. The second control signal CTL2 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

In response to the third control signal CTL3, the negative voltage generator 650 generates a program verify voltage VPV 'having a negative level, a read voltage VRD' and an erase voltage VRD 'according to the operation indicated by the decoded command D_CMD It is possible to generate the verify voltage VEV '. The third control signal CTL3 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

12A is a flowchart illustrating a method of operating a non-volatile memory device according to embodiments of the present invention.

The method of operation of FIG. 12A may be performed through the non-volatile memory device 30 of FIG.

1 to 12A, in a method of operating a nonvolatile memory device according to embodiments of the present invention, a first memory operation is performed on a first memory block BLKa of a plurality of memory blocks BLK1 to BLKz (S100). If the first memory operation is a program operation or an erase operation, the threshold voltages of at least some of the cell transistors of the first memory block BLKa can be changed to the target state by the first memory operation. When the status signal RnB indicates the ready state of the nonvolatile memory device 30 for more than the reference time after the completion of the first memory operation, A curing operation is performed on at least a part of the memory block BLKa (S200). After the curing operation is completed, a second memory operation is performed on at least a part of the first memory block BLKa (S300).

Wherein the first memory operation may be performed on at least a portion of the first memory block BLKa. At least a part of the first memory block BLKa is one page of the first memory block BLKa and the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42 of the first memory block BLKa ), ≪ / RTI > The first memory operation may be a program operation, and the second memory operation may be a read operation. Also, the first memory operation may be a read operation, and the second memory operation may be a read operation. The first memory operation may be an erase operation, and the second memory operation may be a program operation.

12B is a timing diagram illustrating the operation of the memory system of FIG. 1 when the method of operation of FIG. 12A is performed.

Referring to FIGS. 1, 2A, 2B, 10, 12A, and 12B, the memory controller 20 is connected to the nonvolatile memory device (not shown) between the times T0 to T11 at which the status signal RnB is in the ready state 30, the command CMD, the address ADDR, and the data DATA. The nonvolatile memory device 30 receiving the command CMD, the address ADDR and the data DATA can perform the first memory operation between the timings T11 through T12. Here, the first memory operation may be a program operation, and while the nonvolatile memory device 30 is performing the first memory operation, the status signal RnB may indicate a busy state as a low level.

When the first memory operation is completed at the time T12 and the state signal RnB transits to the high level to indicate the ready state, the counter 27 operates to compare the ready state signal RnB with the reference time . The memory controller 20 transmits the command CMD and the address ADDR for the curing operation to the nonvolatile memory device 30 when the ready signal RnB exceeds the reference time at the time T13 do. The nonvolatile memory device 30 receiving the command CMD and the address ADDR instructing the curing operation starts the curing operation at the time T14 and completes the curing operation at the time T15. And transits the state signal RnB to a high level at a time point (T15) when the curing operation is completed.

The memory controller 20 transmits the command CMD and the address ADDR for the second memory operation to the nonvolatile memory device 30 between the times T16 to T17 at which the status signal RnB is at the high level . The nonvolatile memory device 30 receiving the command CMD, the address ADDR and the data DATA can perform the second memory operation between the times T17 and T18. Where the second memory operation may be a read operation. The nonvolatile memory device 30 that has completed the second memory operation transits the state signal RnB back to the high level at the time T18.

As described above, if the ready state of the non-volatile memory device 30 continues for more than the reference time after the completion of the first memory operation, the memory controller 20 instructs the non-volatile memory device 30 to perform the curing operation, The non-volatile memory device 30 may perform a curing operation in response thereto. Thus, the reliability of the second memory operation can be increased.

FIG. 13 is a flowchart showing an example of a curing operation in the operation method of FIG. 12A according to the embodiments of the present invention, FIG. 14 is a flowchart illustrating a curing operation of the method of FIG. And Fig. 15 shows voltages applied to the first vertical string in the curing operation of Fig.

In FIG. 14, the first vertical string CS11 of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41 and CS42 of the memory block of FIG. The case where the first vertical string CS11 includes one ground selection transistor and one string selection transistor will be described as an example.

Referring to FIGS. 13 to 15, in order to perform a curing operation with respect to at least a part of the first memory block BLKa (S200a), a string connected to the string selection transistor SST of the first vertical string CS11 A turn-off voltage VTOFF is applied to the selection line SSL1 to turn off the string selection transistor SST (S210a). The turn-off voltage VTOFF may be the ground voltage GND. The word lines WL1 to WL8 to which the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8 are connected between the first time point T21 and the second time point T22, On voltages VTON1 to VTON8 and VTONG corresponding to the ground selection line GSL1 to which the ground selection transistor GST is connected in operation S220a. At the same time, the common source line CSL connected to the ground selection transistor GST is maintained at the ground voltage GND (S230a). In this case, the turn-on voltages VTON1 to VTON8 and VTONG correspond to the threshold voltages of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8 and the ground selection transistor GST, Lt; RTI ID = 0.0 > a < / RTI >

The turn-on voltages VTON1 to VTON8, VTONG may have the same level, and some or all of them may have different levels.

When the turn-on voltages VTON1 to VTON8 and VTONG corresponding to the word lines WL1 to WL8 and the ground selection line GSL1 are applied, the first to eighth memory cells MC1, MC2, MC3 and MC4 , MC5, MC6, MC7, MC8 and the ground selection transistor GST are turned on. Since an electric field is formed between the gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 and the channel film 114 since the common source line CSL is maintained at the ground voltage . Electrons (drawing charge) trapped in the trap of the channel film 114 after the first memory operation is performed by the thus formed electric field move to the surface of the channel film 114 to form the first to eighth memory cells MC1 and MC2 , MC3, MC4, MC5, MC6, MC7, MC8) can be restored close to the target state.

FIG. 16 is a flowchart showing an example of a curing operation in the operation method of FIG. 12A according to the embodiments of the present invention, FIG. 17 is a flowchart illustrating a curing operation in the memory block of FIG. And Fig. 18 shows voltages applied to the first vertical string in the curing operation of Fig.

In FIG. 17, the first vertical string CS11 of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41 and CS42 of the memory block BLKa shown in FIG. 8 will be described as an example. The case where the first vertical string CS11 includes one ground selection transistor and one string selection transistor will be described as an example.

16 to 18, in order to perform a curing operation with respect to at least a part of the first memory block BLKa (S200b), a bit connected to the string selection transistor SST of the first vertical string CS11 The control signal BLSHF applied to the transistor PT1 connecting the line BL1 and the page buffer PB1 is set to the ground voltage GND so that the bit line from the first time point T21 to the second time point T22 BL1) and the page buffer PB1 (S210b). The string selection line SSL1 connected to the string selection transistor SST from the first time point T21 to the second time point T22 and the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6 On voltages VTSONS, VTON1 to VTON8, and VTONG corresponding to the word lines WL1 to WL8 and the ground selection line GSL1 to which the ground selection transistors GST1, MC7, and MC8 are connected, Respectively (S220b). At the same time, the common source line CSL connected to the ground selection transistor GST is maintained at the ground voltage GND (S230b). The string selection transistor SST, the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8, and the ground selection transistor SST are respectively connected to the turn-on voltages VTONS, VTON1 to VTON8, And may have a level higher than each of the threshold voltages of the transistor GST1. The turn-on voltages (VTONS, VTON1 to VTON8, VTONG) may have the same level, and some or all of them may have different levels.

When the turn-on voltages VTONS, VTON1 to VTON8 and VTONG corresponding to the string selection line SSL, the word lines WL1 to WL8 and the ground selection line GSL1 are applied, The first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8 and the ground selection transistor GST are turned on. Since the common source line CSL is maintained at the ground voltage GND at this time, the gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10, An electric field can be formed. Electrons trapped in the trap of the channel film 114 after the first memory operation is performed by the thus formed electric field move to the surface of the channel film 114 to form the first to eighth memory cells MC1, MC2, MC3, MC4 , MC5, MC6, MC7, MC8) can be restored close to the target state.

19A to 19F are views for explaining the concept of the present invention.

In FIGS. 19A to 19F, the portion 140 indicated by reference numeral 140 in the cell transistor CT of FIG. 7 will be described as an example. Therefore, the portion 140 of Figs. 19A to 19F may include the fifth gate electrode film GEL5, the charge trapping film 118, and the channel film 114. [

19A shows a portion 140 of the cell transistor CT before the first memory operation is performed.

The channel film 114 may be composed of polysilicon as described above, so that a trap 150 may be formed at the grain boundaries of the silicon crystal.

19B shows a portion 140 of the cell transistor CT immediately after the first memory operation is performed.

19B, when the first memory operation is performed on at least a part of the first memory block BLKa including the cell transistor CT, the electrons e are captured in the charge trapping film 118, Electrons can be trapped in the trap 150, which is adjacent to the surface of the substrate 114.

FIG. 19C shows a portion 140 of the cell transistor CT after the first memory operation has been performed and over time.

Referring to FIG. 19C, when a first memory operation is performed on at least a part of the first memory block BLKa including the cell transistor CT and the time passes, The electrons e captured in the cell 150 move in the direction away from the surface of the channel film 114 as indicated by reference numeral 151 and the threshold voltage dispersion of the cell transistor CT may change.

FIG. 19D shows a state in which the cell transistor CT of FIG. 19B is performed immediately after the first memory operation is performed in at least a part of the first memory block BLKa including the cell transistor CT, Of the threshold voltage of the transistor.

As described with reference to FIG. 19C, when the first memory operation is performed on at least a part of the first memory block BLKa including the cell transistor CT, the distribution of the threshold voltage of the cell transistor CT over time Can be moved from the graph GR1 to the graph GR2.

FIG. 19E shows the voltage condition in the case of performing the curing operation according to the embodiments of the present invention in at least a part of the first memory block BLKa including the cell transistor CT, FIG. 19F shows the voltage condition of the curing operation And shows the cell transistor CT after performing.

19E and 19F, a first voltage V1 is applied to the fifth gate electrode film GEL5 to restore the threshold voltage of the cell transistor CT, The second voltage V2 is lower than the first voltage V2. In this case, an electric field EF is formed from the fifth gate electrode film GEL5 toward the channel film 114, and electrons e are emitted from the channel film 114 as indicated by reference numeral 153 by the electric field EF thus formed. To move toward the surface of the membrane 114. Therefore, the threshold voltage of the cell transistor CT can be moved to a state close to the target state immediately after the first memory operation is performed.

A second memory operation may be performed on the first memory block BLKa after the curing operation is performed on at least a portion of the first memory block BLKa.

In an embodiment, the first memory operation may be a program operation (loop) performed on the first memory block BLKa, and the second memory operation may be a read operation performed on the first memory block BLKa Lt; / RTI >

As described with reference to Figs. 19A to 19F, the threshold voltage of the memory cells may change with time after the program operation is performed, and the threshold voltage of the first memory block BLKa may be changed without performing the curing operation If a read operation is performed for a part, the error bit due to the variation of the threshold voltage may increase. If the increased error bit exceeds the correctable range of the error correction code, the performance of the nonvolatile memory device 30 may deteriorate. However, according to the embodiments of the present invention, after performing the curing operation for at least a part of the first memory block BLKa after the first memory operation (program operation), the second memory block BLKa (Read operation). Therefore, since the threshold voltage of the memory cells is moved to a state close to the target state and the read operation is performed, the number of error bits can be reduced to improve the performance.

In an embodiment, the first memory operation may be an erase operation (loop) performed on the first memory block BLKa, and the second memory operation may be a program operation performed after the erase operation.

When the erase operation is performed on the first memory block BLKa, the holes can be trapped in the tunneling insulating film 117 as well as the telephone capturing film 118 in Fig. The holes trapped in the tunneling insulating film 117 can easily move to the trap 150 of the channel film 114 over time and change the threshold voltage of the memory cell.

According to embodiments of the present invention, after the erase operation is performed on the first memory block BLKa, the curing operation described above is performed on the first memory block BLKa to detect the trap 150 of the channel film 114, (Charges) in the first memory block BLKa can be moved to restore the threshold voltage of the memory cells of the first memory block BLKa to the erase state.

The curing operation described above can be performed simultaneously for a plurality of vertical strings included in one memory block.

20 shows that the curing operation according to the embodiment of the present invention is performed simultaneously for a plurality of vertical strings included in one memory block.

In FIG. 20, the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 of the memory block BLKa of FIG. The case where the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 include one ground selection transistor and one string selection transistor will be described as an example.

8 and 20, a first memory operation is sequentially or concurrently performed on the pages of the memory block BLKa, and the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42 The above curing operation can be performed simultaneously. In this case, the string selection transistor SST of each of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 in the section from the first time point T to the second time point T2 The word lines WL1 to WL8 connected to the string selection lines SSL11, SSL21, SSS31 and SSL41 and the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, On voltages VTSONS, VTON1 to VTON8, and VTONG corresponding to the ground selection lines GSL12, GSL22, GSL32, and GSL42 connected to the transistor GST are applied, And maintains the common source line CSL connected to the ground selection transistor GST at the ground voltage GND as described. Thus, the gate electrode films GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 in the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, The first to eighth memory cells MC1, MC2, MC3, MC4, MC5 and MC6 of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, , MC7, MC8) can be moved to a state close to the target state.

In this case, the control signal BLSHF applied to the transistor connecting the bit line connected to each of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41 and CS42 and the corresponding page buffer is set to the ground voltage GND), the connection between the bit line and the page buffer is disconnected from the first time point T21 to the second time point T22, thereby reducing current consumption.

The curing operation according to the embodiments of the present invention can be performed simultaneously on at least two of the plurality of memory blocks BLK1 to BLKz. If the curing operation is performed simultaneously for two or more memory blocks, if the plurality of memory blocks BLK1 to BLKz include at least one bad convex, the at least one bad block may be cached The operation may not be performed.

21 is a block diagram showing the configuration of an address decoder in the nonvolatile memory device of FIG. 2B according to the embodiments of the present invention.

In FIG. 21, the memory cell array 100 and the voltage generator 600 are shown together for convenience of explanation. It is assumed that the memory cell array 100 is composed of a plurality of memory blocks 101 to 108.

Referring to FIG. 21, the address decoder 400 may include a decoder 410, an address comparator 420, a bad block address register 430, and a plurality of selection circuits 441 to 448.

The bad block address register 430 may store a bad block address set which is an address of at least one bad block among the plurality of memory blocks 101 to 108 included in the memory cell array 100. [ Here, the bad block may be a memory block having at least one page including error bits uncorrectable by an error correction code (ECC).

The bad block address set is stored in the first bad block address register IBBA stored in the bad block address register 430 prior to the power-up sequence of the non-volatile memory device 30, And a second bad block address register (RTBBA) stored in the block address register 430. Here, the second bad block address register (RTBBA) may be referred to as a run time bad block address as a block address of a memory block determined as a bad block during operation of the nonvolatile memory device 30. [

The address comparator 420 compares the block address BLK_ADDR provided from the control circuit 500 with the bad block address set and outputs a match signal MS indicating whether or not the block address BLK_ADDR is equal to the bad block address set, (410).

The decoder 410 decodes the block address BLK_ADDR to generate a block select signal for selecting two or more of the plurality of memory blocks 101 to 108 and provides the block select signal to the plurality of select circuits 441 to 448 , It is possible to generate the block selection signal so that the bad block among the memory blocks 101 to 108 is not selected based on the match signal MS.

The selection circuits 441 to 448 may be connected to each of the memory blocks 101 to 108 through a string selection line SSL, a plurality of word lines WLs and a ground selection line GSL. Each of the selection circuits 441 to 448 may selectively provide the word line voltage WLs provided from the voltage generator 600 to each of the corresponding memory blocks 101 to 108 in response to the block selection signal .

FIG. 22 shows the address decoder shown in FIG. 21 in detail.

Although only the configuration of the selection circuit 441 is shown in Fig. 22 in detail, the configuration of each of the selection circuits 442 to 448 may be substantially the same as that of the selection circuit 441. [

22, the decoder 410 decodes the block address BLK_ADDR and the match signal MS to generate block selection signals for simultaneously selecting two or more memory blocks of the plurality of memory blocks 101 to 108 (BS1 to BS8) to each of the selection circuits 441 to 448 while the block selection signals BS1 to BS8 are not selected for the selection circuits 441 to 448, respectively. In response to each of the block selection signals BS1 to BS8, each of the selection circuits 441 to 448 selectively supplies the word line voltage VWLs from the voltage generator 600 to each of the memory blocks 101 to 108 can do.

The decoder 410 can selectively activate each of the block selection signals BS1 to BS8 such that the memory blocks designated by the block address BLK_ADDR are selected and the bad block is not selected based on the match signal MS.

The selection circuit 441 may include a selection signal latch 441a and a plurality of selection transistors ST1 to ST4. The plurality of selection transistors ST1 to ST4 may be connected to the memory block 101 via a string selection line SSL, word lines WLS and a ground selection line GSL. The selection signal latch 441a may latch and store the block selection signal BS1 and provide the block selection signal BS1 latched at the gates of the plurality of selection transistors ST1 to ST4.

When the block selection signal BS1 is activated to the first logic level, the first voltage V1 provided from the voltage generator 600 at the time of performing the curing operation is supplied to the selected transistors ST1 to ST4 The selection signal latch 441a may be initialized in response to the reset signal RST provided from the control circuit 500 after the completion of the curing operation.

The turn-on voltages provided from the voltage generator 600 at the time of the execution of the curing operation, when the memory block 102 corresponds to the bad block and the block select signal BS2 is deactivated to the second logic level, May not be provided to the memory block 102 by the OFF selection transistors ST1 to ST4.

Hereinafter, the curing operation is performed on a plurality of memory blocks at the same time with reference to FIGS. 2B, 21, and 22. FIG.

If the ready state of the non-volatile memory device 30 continues for more than the reference time after the completion of the first memory operation for at least a part of the memory blocks 101 to 108, The control circuit 500 provides the block address BLK_ADDR to the decoder 410 and the address comparator 420 of the address decoder 400 when the block address BLK_ADDR for multi-block curing is input to the address decoder 400. [ The address comparator 420 compares each of the at least two block addresses designated by the block address BLK_ADDR with a set of bad block addresses stored in the bad block address register 430 and outputs a match signal MS indicating the match to the decoder 410). The decoder 410 decodes the block address BLK_ADDR and the match signal MS and selectively outputs each of the block select signals BS1 to BS8 so that the bad block among the memory blocks designated by the block address BLK_ADDR is not selected And provides it to each of the selection circuits 441 to 448.

For example, the block address (BLK_ADDR) designates the memory blocks 101 to 103, and when the memory block 102 is a bad block, the block select signals BS1 and BS3 are activated to the first logic level And the block select signals BS2, BS4 to BS8 may be deactivated to a second logic level. Therefore, the curing operation can be performed simultaneously with respect to the memory blocks 101 and 103. After the curing operation is completed, the control circuit 500 may provide the reset signal RST to the select signal latch 441a of each of the select circuits 441 to 448 to initialize the select signal latch 441a.

As described above, if the curing operation is simultaneously performed on two or more memory blocks, the intervention of the memory controller 20 can be minimized when the curing operation is performed.

Depending on the embodiment, each of the selection circuits 441 to 448 may be configured to include a bad block latch in place of the selection signal latch 441a. In this case, the bad block latch may store the first bad block address and the second bad block address like the bad block address register 430 of FIG. 21, the first bad block address may be stored in the non-volatile memory device 30, And the second bad block address may be updated via the memory controller 20. [

23 shows a configuration of the memory system of Fig.

The memory system of FIG. 23 can be applied when performing a curing operation for a multi-block.

23, the address decoder 400 of the non-volatile memory device 30 includes a first bad block address register 430 and a first bad block address register 430 includes a first bad block address IBBA ). ≪ / RTI > The memory controller 20 may include an address generator 21 and a second bad block address register 23 and a second bad block address register 23 may store a second bad block address (RTBBA). In generating the block address (BLK_ADDR) for performing the curing operation for at least two memory blocks, the address generator 21 generates a second bad block address (RTBBA) stored in the second bad block address register 23, (BLK_ADDR) so as not to include the generated block address (BLK_ADDR) and provide the generated block address (BLK_ADDR) to the nonvolatile memory device (30). The nonvolatile memory device 30 may compare the block address BLK_ADDR with the first bad block address IBBA so that the curing operation is not performed on the memory block corresponding to the first bad block address IBBA .

24 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.

Referring to FIG. 24, the SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200.

Non-volatile memory devices 1100 may optionally be implemented to be provided with an external high voltage (VPP). The non-volatile memory devices 1100 may be implemented as the non-volatile memory device 30 of Fig. 2B described above. Thus, each of the non-volatile memory devices 1100 performs a first memory operation on the first memory block, and if the ready state continues beyond the reference time after completion of the first memory operation, a command from the SSD controller 1200 And perform a curing operation for at least a portion of the first memory block in response. Each of the non-volatile memory devices 1100 may perform a second memory operation on the first memory block after performing the curing operation to reduce the number of error bits to improve performance.

The SSD controller 1200 is coupled to the non-volatile memory devices 1100 through a plurality of channels CH1 through CH4. The SSD controller 1200 includes at least one processor 1210, a buffer memory 1220, an error correction circuit 1230, a host interface 1250, a nonvolatile memory interface 1260, and a counter unit 1270. The counter unit 1270 may include a plurality of counters. The plurality of counters may be assigned to the plurality of channels CH1 to CH4, or may be allocated to each of the non-volatile memory devices 1100. [ 2A, each of the plurality of counters included in the counter unit 1270 receives a status signal from each of the nonvolatile memory devices 1100, and compares the status signal indicating the ready status with a reference time And provides a determination signal to the processor 1210 indicating that the ready state continues for more than the reference time. The processor 1210 can send a command and an address to the corresponding non-volatile memory device 1100 to instruct the curing operation in response to the determination signal, and the corresponding non-volatile memory device 1100 responds to the above- Ring operation can be performed.

The buffer memory 1220 may temporarily store data necessary for driving the memory controller 1200. In addition, the buffer memory 1220 may buffer data to be used for a program operation upon a write request. Buffer memory 1220 in FIG. 24 exists within SSD controller 1200, but is not necessarily limited thereto. The buffer memory may be separately provided outside the SSD controller 1200.

The error correction circuit 1230 calculates the error correction code value of the data to be programmed in the write operation, corrects the data read in the read operation based on the error correction code value, and, in the data recovery operation, The error of the recovered data can be corrected. Although not shown, a code memory for storing code data necessary for driving the memory controller 1200 may further be included. The code memory may be implemented as a non-volatile memory device.

The host interface 1250 may provide an interface function with an external device. The non-volatile memory interface 1260 may provide an interface function with the non-volatile memory device 1100.

25 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.

Referring to FIG. 25, the eMMC 2000 may include at least one NAND flash memory device 2100 and a controller 2200.

The NAND flash memory device 2100 may be implemented as the nonvolatile memory device 30 of FIG. 2B described above. The NAND flash memory device 2100 performs a first memory operation for the first memory block and if the ready state continues for more than the reference time after completion of the first memory operation, After performing a curing operation on at least a portion of the first memory block, a second memory operation may be performed on the first memory block to reduce the number of error bits to improve performance.

The memory controller 2200 is coupled to the NAND flash memory device 2100 through a plurality of channels. The memory controller 2200 includes at least one controller core 2210, a host interface 2250, and a NAND interface 2260. At least one controller core 2210 controls the overall operation of the eMMC 2000. Controller core 2210 may include a counter, as described with reference to Figure 2A. The host interface 2250 performs interfacing with the controller 2210 and the host. The NAND interface 2260 performs the interfacing of the controller 2200 with the NAND flash memory device 2100.

In an embodiment, the host interface 2250 may be a parallel interface (e.g., an MMC interface). In another embodiment, host interface 2250 of eMMC 2000 may be a serial interface (e.g., UHS-II, UFS interface).

The eMMC 2000 receives power supply voltages Vcc and Vccq from the host. Here, the first power voltage Vcc (for example, 3.3V) is provided to the NAND flash memory device 2100 and the NAND interface 2260, and the second power voltage Vccq (for example, 1.8V / 3.3V) And is provided to the controller 2200. In an embodiment, eMMC 2000 may optionally be provided with an external high voltage (Vpp).

26 is a block diagram illustrating a universal flash storage (UFS) according to embodiments of the present invention.

Referring to FIG. 26, the UFS system 3000 may include a UFS host 3100, UFS devices 3200 and 3300, an embedded UFS device 3400, and a removable UFS card 3500. The UFS host 3100 may be an application processor of the mobile device. Each of the UFS host 3100, the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 can communicate with external devices by the UFS protocol. At least one of the UFS devices 3200, 3300, the embedded UFS device 3400, and the removable UFS card 3500 may be implemented as the non-volatile memory device 30 of FIG. 2B. Thus, at least one of the UFS devices 3200, 3300, the embedded UFS device 3400, and the removable UFS card 3500 performs a first memory operation on the first memory block and, after completion of the first memory operation, After performing a curing operation on at least a portion of the first memory block if the ready state continues for more than a reference time, performing a second memory operation on the first memory block to reduce the number of error bits, .

Meanwhile, the embedded UFS device 3400 and the removable UFS card 3400 can communicate by a protocol other than the UFS protocol. The UFS host 3100 and the removable UFS card 3500 can communicate by various card protocols (e.g., UFDs, MMC, secure digital (SD), mini SD, Micro SD, etc.).

27 is a block diagram illustrating a mobile device in accordance with embodiments of the present invention.

27, the mobile device 4000 includes an application processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a mobile RAM 4500.

The application processor 4100 controls the overall operation of the mobile device 4000. The communication module 4200 may be implemented to control wired / wireless communication with the outside. The display / touch module 4300 may be implemented to display data processed by the application processor 4100 or receive data from the touch panel. The storage device 4400 may be implemented to store user data.

Storage device 4400 may be an eMMC, SSD, or UFS device. The storage device 4400 may be implemented as the non-volatile memory device 30 of FIG. 2B. Accordingly, the storage device 4400 performs a first memory operation on the first memory block, and if the ready state continues for more than a reference time after completion of the first memory operation, After performing the operation, a second memory operation may be performed on the first memory block to reduce the number of error bits to improve performance.

The application processor 4100 may determine that the state signal RnB indicating the state of the storage device 4400 including the counter 4110 indicates that the ready state of the storage device 4400 is longer than the reference time, The command and address can be transmitted to the storage device 4400 to be performed.

The mobile RAM 4500 may be implemented to temporarily store data necessary for the processing operation of the mobile device 4000. [

A memory device or storage device according to an embodiment of the present invention may be implemented using various types of packages. In an embodiment, a memory system or storage device according to an embodiment of the present invention may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers -Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, COB, Ceramic Dual In-Line Package, Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline , A Wafer-Level Processed Stack Package (WSP), and the like.

The present invention can be usefully used in any electronic device having a non-volatile memory device. For example, the present invention can be applied to a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital A camera, a digital camera, a music player, a portable game console, a navigation system, and the like.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

10: nonvolatile memory device 100: memory cell array
400: address decoder 460: page buffer circuit
470: Data I / O circuit 500: Control circuit
600: voltage generator

Claims (20)

A method of operating a non-volatile memory device comprising a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate,
The method
Performing a first memory operation on a first one of the memory blocks; And
Wherein when the status signal indicates a ready state of the nonvolatile memory device for more than a reference time after completion of the first memory operation, the charge of the first memory block is transferred to the channel block of the at least one vertical string of the vertical strings, And performing a curing operation on a portion of the non-volatile memory device. The method of claim 1, wherein each of the plurality of vertical strings
At least one string select transistor coupled to a bit line coupled to the page buffer;
At least one ground selection transistor coupled to the common source line; And
And a plurality of cell transistors serially connected between the at least one string selection transistor and the at least one ground selection transistor to form a channel of the vertical string. 3. The method of claim 2, wherein the curing operation
Turning off at least one string selection transistor of the first of the plurality of vertical strings;
Applying each of the turn-on voltages corresponding to each of the word lines connected to the cell transistors of the first vertical string and the ground select line connected to the ground selection transistor; And
And maintaining a common source line coupled to the at least one ground selection transistor at a ground voltage. The method of claim 3,
Each of the turn-on voltages having a level higher than each of the threshold voltages of the cell transistors and the ground selection transistor. 3. The method of claim 2, wherein the curing operation
Blocking connection of a page buffer and a bit line connected to a first vertical string of the plurality of vertical strings;
A string selection line coupled to the at least one string selection transistor of the first vertical string, word lines coupled to the cell transistors of the first vertical string, and a ground selection line coupled to the at least one ground selection transistor, Applying each of the turn-on voltages to the turn-on voltage; And
And maintaining a common source line coupled to the at least one ground selection transistor at a ground voltage. 6. The method of claim 5,
Wherein each of the corresponding turn-on voltages has a level higher than each of the threshold voltages of the string selection transistor, the cell transistors, and the ground selection transistor. 6. The method of claim 5,
Wherein the curing operation is performed simultaneously on a plurality of vertical strings included in the first memory block. The method according to claim 1,
Wherein the first memory operation is sequentially performed on the memory blocks including the first memory block,
Wherein the curing operation is performed concurrently on the remaining memory blocks except for the at least one bad memory block if the memory blocks include at least one bad memory block. 9. The method of claim 8, wherein the curing operation
A method of operating a non-volatile memory device that is performed except for the at least one bad memory block based on a comparison of a block address for selecting the memory blocks and a set of bad block addresses including an address of the at least one bad memory block . 10. The method of claim 9,
Wherein the bad block address set includes a first bad block address pre-stored in a bad block register of an address decoder connected to the memory blocks prior to a power-up sequence of the non-volatile memory device, And a second bad block address stored in a block register. The method according to claim 1,
Further comprising performing a second memory operation on at least a portion of the first memory block after completion of the curing operation,
Wherein the first memory operation is a program operation performed for at least a portion of the first memory block and the second memory operation is a read operation performed for at least a portion of the first memory block . A memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate;
A voltage generator for generating word line voltages based on the control signal;
An address decoder for providing the word line voltages to the memory cell array based on an address signal; And
When a status signal indicates a ready status of the nonvolatile memory device for a reference time or more after completion of the first memory operation, the first memory block performs a first memory operation on the first memory block among the plurality of memory blocks, Controlling the voltage generator and the address decoder such that a curing operation is performed in a part of the first memory block in response to a command from the controller such that charge is moved in a channel film of at least one of the vertical strings A nonvolatile memory device comprising a control circuit. 13. The apparatus of claim 12, wherein each of the plurality of vertical strings
At least one string select transistor coupled to a bit line coupled to the page buffer;
At least one ground selection transistor coupled to the common source line; And
And a plurality of cell transistors serially connected between the at least one string selection transistor and the at least one ground selection transistor to form a channel of the vertical string. 14. The method of claim 13, wherein, in performing the curing operation
The address decoder
Turning off at least one string selection transistor of the first of the plurality of vertical strings,
On voltages corresponding to the word lines connected to the cell transistors of the first vertical string and the ground selection line connected to the at least one ground selection transistor,
Maintaining a common source line connected to said at least one ground selection transistor at a ground voltage,
And each of the turn-on voltages has a level higher than each of the threshold voltages of the cell transistors and the ground selection transistor. 13. The method of claim 13, wherein, in performing the curing operation
The control circuit interrupts the connection of the page buffer and the bit line connected to the first vertical string among the plurality of vertical strings,
The address decoder
A string selection line coupled to the at least one string selection transistor of the first vertical string, word lines coupled to the cell transistors of the first vertical string, and a ground selection line coupled to the at least one ground selection transistor, On voltage is applied,
Maintaining a common source line connected to said at least one ground selection transistor at a ground voltage,
Wherein each of the turn-on voltages has a level higher than each of the threshold voltages of the string selection transistor, the cell transistors, and the ground selection transistor. 13. The apparatus of claim 12, wherein the address decoder
A bad block address register for storing an address of at least one bad block among the memory blocks;
An address comparator for comparing a block address for selecting two or more of the memory blocks with a bad block address set stored in the bad block address register and outputting a match signal indicating whether the block address matches the bad block address set;
A decoder for decoding the match signal and the block address to provide a plurality of block select signals; And
And a plurality of selection circuits coupled to each of the memory blocks and selectively providing turn-on voltages applied from the voltage generator at the time of performing the curing operation to each of the memory blocks based on the block selection signals A non-volatile memory device. 17. The method of claim 16,
Wherein the bad block address set includes a first bad block address pre-stored in the bad block address register prior to a power-up sequence of the non-volatile memory device and a second bad block address stored in the bad block address register during operation of the non- A nonvolatile memory device comprising a bad block address. At least one non-volatile memory device; And
And a memory controller for controlling said at least one non-volatile memory device,
The at least one non-volatile memory device
A memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to the substrate;
A voltage generator for generating word line voltages based on the control signal;
An address decoder for providing the word line voltages to the memory cell array based on an address signal; And
When a status signal indicates a ready state of the nonvolatile memory device for a reference time or more after completion of the first memory operation, the memory controller performs a first memory operation on the first memory block among the plurality of memory blocks, The voltage generator and the address decoder are controlled so that a curing operation is performed in a part of the first memory block so that charge is moved in the channel film of at least one vertical string of the vertical strings A memory system comprising a control circuit. 19. The method of claim 18,
Wherein said control circuit includes a status signal generator for providing said status signal to said memory controller indicating at least an operation status of said nonvolatile memory device based on said command,
The memory controller
A counter for comparing the status signal in the ready state with the reference time and providing a determination signal; And
And a processor for generating the command based on the determination signal and the request from the host. 20. The method of claim 19,
Wherein the processor sends a command to the nonvolatile memory device to indicate the curing operation if the determination signal indicates that the ready state continues for more than the reference time.

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