KR102411026B1 - Method of operating non-volatile memory device, non-volatile memory device and memory system including the same - Google Patents

Abstract

A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to a substrate, wherein the method comprises: A first memory operation is performed on a memory block, and when the state signal indicates the ready state of the non-volatile memory device for a reference time or longer after the completion of the first memory operation, at least one of the vertical strings A curing operation is performed on a portion of the first memory block to move charges in the channel layer.

Description

Method of operating a non-volatile memory device, a non-volatile memory device, and a memory system including the same

The present invention relates to a semiconductor memory device, and more particularly, to a method of operating a nonvolatile memory device, a nonvolatile memory device, and a memory system including the same.

The semiconductor memory device may be largely divided into a volatile semiconductor memory device and a nonvolatile semiconductor memory device. A volatile semiconductor memory device has a high read/write speed, but has a disadvantage in that the stored contents are lost when the power supply is cut off. On the other hand, the nonvolatile semiconductor memory device retains its contents even when power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be preserved regardless of whether power is supplied or not.

Non-volatile semiconductor memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically and electrically erasable programmable read-only memory (EEPROM).

A typical example of a non-volatile memory device is a flash memory device. A flash memory device is a computer, mobile phone, PDA, digital camera, camcorder, voice recorder, MP3 player, personal digital assistant (PDA), portable computer (Handheld PC), game machine, fax, scanner, and the voice and video of electronic devices such as printers, etc. It is widely used as a data storage medium.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of operating a nonvolatile memory device capable of increasing performance.

It is an object of the present invention to provide a nonvolatile memory device implementing the above operation method.

It is an object of the present invention to provide a memory system including the nonvolatile memory device.

In order to achieve the above object of the present invention, there is provided a method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to a substrate. and, in the method, when a first memory operation is performed on a first memory block among the memory blocks, and a status signal indicates a ready state of the non-volatile memory device for a reference time or longer after the first memory operation is completed , a curing operation is performed on a portion of the first memory block so that charges are transferred from a channel layer of at least one of the vertical strings.

In an embodiment, each of the plurality of vertical strings forms at least one string select transistor connected to a bit line connected to a page buffer, at least one ground select transistor connected to a common source line, and a channel of the vertical string. In order to do so, a plurality of cell transistors connected in series between the at least one string select transistor and the at least one ground select transistor may be included.

To perform the curing operation, at least one string selection transistor of a first vertical string among the plurality of vertical strings is turned off, and word lines connected to cell transistors of the first vertical string and ground Each of the turn-on voltages corresponding to each of the ground selection lines connected to the selection transistor may be applied, and the common source line connected to the at least one ground selection transistor may be maintained as a ground voltage.

Each of the turn-on voltages may have a higher level than threshold voltages of the cell transistors and the ground selection transistor, respectively.

In order to perform the curing operation, a connection between a bit line connected to a first vertical string among the plurality of vertical strings and a page buffer is cut off, and a string connected to at least one string select transistor of the first vertical string Applying turn-on voltages corresponding to a selection line, word lines connected to the cell transistors of the first vertical string, and a ground selection line connected to a ground selection transistor, respectively, to the at least one ground selection transistor The connected common source line may be maintained as a ground voltage.

Each of the corresponding turn-on voltages may have a higher level than threshold voltages of the string select transistor, the cell transistors, and the ground select transistor, respectively.

The curing operation may be simultaneously performed on a plurality of vertical strings included in the first memory block.

In an embodiment, the first memory operation is sequentially performed on the memory blocks including the first memory block, and the curing operation is performed when the memory blocks include at least one bad block; It may be simultaneously performed on the remaining memory blocks except for the at least one bad memory block.

The curing operation may be performed except for the at least one bad memory block based on a comparison between a block address for selecting the memory blocks and a bad block address set including the address of the at least one bad memory block. .

The bad block address set includes a first bad block address pre-stored in a bad block register of an address decoder connected to the memory blocks before a power-up sequence of the nonvolatile memory device and the bad block address during operation of the nonvolatile memory device. It may include a second bad block address stored in the block register.

In an embodiment, in the method, a second memory operation may be further performed on at least a portion of the first memory block after the curing operation is completed.

The first memory operation may be a program operation performed on at least a portion of the first memory block, and the second memory operation may be a read operation performed on at least a portion of the first memory block.

In order to achieve the above object of the present invention, a nonvolatile memory device according to embodiments of the present invention includes a memory cell array, a voltage generator, an address decoder, and a control circuit. The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of vertical strings extending in a direction perpendicular to a substrate. The voltage generator generates word line voltages based on a control signal. The address decoder provides the word line voltages to the memory cell array based on an address signal. The control circuit performs a first memory operation with respect to a first memory block among the plurality of memory blocks, and after completion of the first memory operation, a status signal indicating the ready state of the non-volatile memory device for a reference time or longer In this case, the voltage generator and the first memory block perform a curing operation to move charges in a channel layer of at least one of the vertical strings in response to a command from an external memory controller. Controls the address decoder.

In an embodiment, each of the plurality of vertical strings forms at least one string select transistor connected to a bit line connected to a page buffer, at least one ground select transistor connected to a common source line, and a channel of the vertical string. In order to do so, a plurality of cell transistors connected in series between the at least one string select transistor and the at least one ground select transistor may be included.

When the curing operation is performed, the address decoder turns off at least one string selection transistor of a first vertical string among the plurality of vertical strings, and a word line connected to cell transistors of the first vertical string. and turn-on voltages corresponding to each of the ground selection lines connected to the at least one ground selection transistor, respectively, and a common source line connected to the at least one ground selection transistor may be maintained as a ground voltage. Each of the turn-on voltages may have a higher level than each of the threshold voltages of the cell transistors and the ground selection transistor.

When the curing operation is performed, the control circuit cuts off a connection between a bit line connected to a first vertical string among the plurality of vertical strings and a page buffer, and the address decoder includes at least one of the first vertical strings. Turns corresponding to at least one string select line connected to the string select transistor, word lines connected to cell transistors of the first vertical string, and at least one ground select line connected to at least one ground select transistor; Each of the on voltages may be applied and a common source line connected to the at least one ground selection transistor may be maintained as a ground voltage. Each of the turn-on voltages may have a higher level than threshold voltages of the string select transistor, the cell transistors, and the ground select transistor, respectively.

In an embodiment, the address decoder may include a bad block address register, an address comparator, a decoder, and a plurality of selection circuits. The bad block address register may store an address of at least one bad block among the memory blocks. The address comparator compares a block address for selecting two or more of the memory blocks with a bad block address set stored in the bad block address register, and outputs a match signal indicating whether the block address matches the bad block address set can do. The decoder may provide a plurality of block selection signals by decoding the match signal and the block address. The plurality of selection circuits may be connected to each of the memory blocks and selectively provide turn-on voltages applied from the voltage generator to each of the memory blocks when the curing operation is performed based on the block selection signals. have.

In order to achieve the above object of the present invention, a memory system according to embodiments of the present invention includes at least one non-volatile memory device and a memory controller. The memory controller controls the at least one nonvolatile memory device. The at least one non-volatile memory device includes a memory cell array, a voltage generator, an address decoder, and a control circuit. The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of vertical strings extending in a direction perpendicular to a substrate. The voltage generator generates word line voltages based on a control signal. The address decoder provides the word line voltages to the memory cell array based on an address signal. The control circuit performs a first memory operation with respect to a first memory block among the plurality of memory blocks, and after completion of the first memory operation, a status signal indicating the ready state of the non-volatile memory device for a reference time or longer In this case, in response to a command from the memory controller, the voltage generator and the first memory block perform a curing operation to move charges in a channel layer of at least one of the vertical strings on a part of the first memory block. Controls the address decoder.

In an embodiment, the control circuit may include a status signal generator that provides the status signal indicating an operating state of the nonvolatile memory device to the memory controller based on at least the command. The memory controller may include a counter providing a determination signal by comparing the ready state signal with the reference time, and a processor generating the command based on the determination signal and a request from the host.

The processor may transmit a command instructing the curing operation to the non-volatile memory device when the determination signal indicates that the ready state continues for more than the reference time.

In the method of operating a nonvolatile memory device and the nonvolatile memory device according to embodiments of the present invention, when a first memory operation is performed on a first memory block and the ready state of the nonvolatile memory device continues for a reference time or longer , after a curing operation is performed on at least a portion of the first memory block, a second memory operation is performed on the first memory block to reduce the number of error bits, thereby improving performance.

1 is a block diagram illustrating a memory system according to embodiments of the present invention.
2A is a block diagram illustrating a configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention.
2B is a block diagram illustrating a nonvolatile memory device in the memory system of FIG. 1 according to embodiments of the present invention.
3 is a block diagram illustrating the memory cell array of FIG. 2B.
4 is a plan view illustrating an example of a memory block included in the memory cell array of FIG. 1 .
FIG. 5 is a perspective view taken along line II′ of the memory block shown in FIG. 4 .
6 is a cross-sectional view taken along line II′ of the memory block shown in FIG. 4 .
7 is an enlarged view illustrating one of cell transistors included in the memory block illustrated in FIGS. 4 to 6 .
8 is an equivalent circuit diagram of the memory block shown in FIGS. 4 to 6 .
9 is a conceptual diagram for explaining a plane structure of the equivalent circuit diagram shown in FIG. 8 .
10 is a block diagram illustrating a configuration of a control circuit in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.
11 is a block diagram illustrating a configuration of a voltage generator in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.
12A is a flowchart illustrating a method of operating a nonvolatile memory device according to embodiments of the present invention.
12B is a timing diagram illustrating an operation of the memory system of FIG. 1 when the operating method of FIG. 12A is performed.
13 is a flowchart illustrating an example of a curing operation in the operation method of FIG. 12A according to embodiments of the present invention.
FIG. 14 shows one of vertical strings in the memory block of FIG. 8 applied to the operation method of FIG. 12A .
15 illustrates voltages applied to the first vertical string in the curing operation of FIG. 13 .
16 is a flowchart illustrating an example of a curing operation in the operation method of FIG. 12A according to embodiments of the present invention.
FIG. 17 shows one of vertical strings in the memory block of FIG. 8 to which the operation method of FIG. 12 is applied.
18 illustrates voltages applied to the first vertical string in the curing operation of FIG. 16 .
19A to 19F are diagrams for explaining the concept of the present invention.
20 illustrates that a curing operation according to an embodiment of the present invention is simultaneously performed on a plurality of vertical strings included in one memory block.
21 is a block diagram illustrating a configuration of an address decoder in the nonvolatile memory device of FIG. 2 according to embodiments of the present invention.
22 shows the address decoder shown in FIG. 21 in detail.
23 shows the configuration of the memory system of FIG. 1 .
24 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.
25 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.
26 is a block diagram illustrating a universal flash storage (UFS) according to embodiments of the present invention.
27 is a block diagram illustrating a mobile device according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and the text It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or a combination thereof exists, but one or more other features or numbers , it is to be understood that it does not preclude the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with the context of the related art, and are not to be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a block diagram illustrating a memory system according to embodiments of the present invention.

Referring to FIG. 1 , a memory system (or non-volatile memory system) 10 may include a memory controller 20 and at least one non-volatile memory device 30 .

The memory system 10 illustrated in FIG. 1 may include all data storage media based on a flash memory such as a memory card, a USB memory, and an SSD.

The nonvolatile memory device 30 may perform an erase, write, or read operation under the control of the memory controller 20 . To this end, the nonvolatile memory device 30 receives a command CMD, an address ADDR, and data DATA through an input/output line. Also, the nonvolatile memory device 30 may receive power PWR through a power line. The command CMD may include a command latch enable CLE, an address latch enable ALE, a chip enable CE/, a write enable WE/, and a read enable RE/. The nonvolatile memory device 30 may transmit a status signal RnB to the memory controller 20 . The status signal RnB is a signal representing the operating state of the nonvolatile memory device 30 , and when it is at a low level, the nonvolatile memory device 30 is in a busy state, and when it is at a high level, the nonvolatile memory device 30 is in a ready state. , that is, indicating an idle state.

When the nonvolatile memory device 30 performs a program operation, the state signal RnB may be in a busy state. When the nonvolatile memory device 30 does not perform an operation such as program, read, or erase, the state signal RnB may be in a ready state. When the state signal RnB indicates the ready state, the memory controller 20 compares the state signal RnB of the ready state with a reference time, and when the ready state continues for more than the reference time, the nonvolatile memory device 30 It is possible to transmit a command CMD and an address ADDR instructing a curing operation to the . The nonvolatile memory device 30 may perform the curing operation on the memory area designated by the address ADDR in response to the command CMD. The nonvolatile memory device 30 may include a memory cell array including a plurality of memory blocks.

2A is a block diagram illustrating a configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2A , the memory controller 20 includes at least one processor 21 , a buffer memory 22 , an error correction circuit 23 , a host interface 25 , a nonvolatile memory interface 26 , and a counter 27 . ) is included.

The buffer memory 22 may temporarily store data required for driving the memory controller 20 . In addition, the buffer memory 22 may buffer data to be used for a program operation when a write request is made.

The error correction circuit 23 calculates an error correction code value of data to be programmed in a write operation, performs error correction on data read in a read operation based on the error correction code value, and performs an error correction in the nonvolatile memory device 30 in a data recovery operation ), it is possible to correct errors in the recovered data. Although not shown, a code memory for storing code data required to drive the memory controller 20 may be further included. The code memory may be implemented as a non-volatile memory device.

The host interface 25 may provide an interface function with an external host. The nonvolatile memory interface 26 may provide an interface function with the nonvolatile memory device 1100 .

The counter 27 receives the status signal RnB from the non-volatile memory interface 26, and if the status signal RnB indicates a ready state, compares the status signal RnB with a reference time, and the ready state is When the duration is longer than the reference time, a determination signal DS indicating this may be provided to the processor 21 . The processor 21 generates a command and an address instructing a curing operation in response to a determination signal DS indicating that the ready state continues for more than the reference time, and uses the generated command and address to the non-volatile memory interface 26 . It can be provided to the non-volatile memory device 30 through the To this end, the counter 27 may include a register capable of storing the reference time therein.

2B is a block diagram illustrating a nonvolatile memory device in the memory system of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2B , the nonvolatile memory device 30 includes a memory cell array 100 , an address decoder 400 , a page buffer circuit 460 , a data input/output circuit 470 , a control circuit 500 , and a voltage generator ( 600).

The memory cell array 100 may be connected to the address decoder 400 through at least one string selection line SSL, a plurality of word lines WLs, and at least one ground selection line GSL. Also, the memory cell array 100 may be connected to the page buffer circuit 460 through a plurality of bit lines BLs.

The memory cell array 100 may include a plurality of nonvolatile memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs.

In one embodiment, the memory cell array 100 may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 100 may include vertical memory cell strings including a plurality of memory cells stacked on each other. A detailed description of three-dimensional memory cell arrays can be found in US Ser. No. 7,679,133; 8,553,466; 8,654,587; 8,559,235 and US Publication No. 2011/0233648.

3 is a block diagram illustrating the memory cell array of FIG. 2B.

Referring to FIG. 3 , the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. In an embodiment, the memory blocks BLK1 to BLKz are selected by the address decoder 400 illustrated in FIG. 1 . For example, the address decoder 400 may select a memory block BLK corresponding to a block address from among the memory blocks BLK1 to BLKz. Also, the address decoder 400 may select at least two or more memory blocks corresponding to a block address among the memory blocks BLK1 to BLKz.

4 is a plan view illustrating an example of a memory block included in the memory cell array of FIG. 2B . FIG. 5 is a perspective view taken along line I-I' of the memory block shown in FIG. 4 . 6 is a cross-sectional view taken along line II′ of the memory block shown in FIG. 4 .

4 to 6 illustrate a portion of one memory block BLKa among a plurality of memory blocks BLK1 , BLK2 , ..., BLKz included in the memory cell array 100 of FIG. 1 .

4 to 6 , the memory block BLKa may be formed in a three-dimensional structure on the substrate 111 along the first to third directions D1 , D2 , and D3 .

The substrate 111 may be a well having a first conductive type. For example, the substrate 111 may be a P-well into which a group III element such as boron (B) is implanted. In one embodiment, the substrate 111 may be a pocket P-well formed in an N-well. Hereinafter, it is assumed that the substrate 111 is a P-well (or pocket P-well). However, the substrate 111 is not limited to having a P-conductive type.

A plurality of doping regions 121 , 122 , and 123 extending along the first direction D1 and spaced apart from each other along the second direction D2 may be formed on the substrate 111 . 2 to 4 show a first doped region 121 , a second doped region 122 , and a third doped region 123 .

The plurality of doped regions 121 , 122 , and 123 may have a second conductivity type different from the first conductivity type of the substrate 111 . For example, the plurality of doped regions 121 , 122 , and 123 may include an N-type conductive material. Hereinafter, it is assumed that the plurality of doped regions 121 , 122 , and 123 have an N-conductivity type. However, the plurality of doped regions 121 , 122 , and 123 are not limited to having an N-conductivity type.

As will be described later, the plurality of doped regions 121 , 122 , and 123 may be commonly connected to a common source line.

Between adjacent doped regions among the plurality of doped regions 121 , 122 , and 123 , a plurality of insulation layers 112 and 112a move in a third direction D3 that is perpendicular to the substrate 111 . Accordingly, they may be sequentially formed on the substrate 111 . The plurality of insulating layers 112 and 112a may be spaced apart from each other in the third direction D3 . The plurality of insulating layers 112 and 112a may extend along the first direction D1.

In an embodiment, the plurality of insulating layers 112 and 112a may include an insulating material such as silicon oxide.

In an embodiment, the thickness of the insulating layer 112a in contact with the substrate 111 among the plurality of insulating layers 112 and 112a may be thinner than the thickness of the other insulating layers 112 .

Among the plurality of doped regions 121 , 122 , and 123 , the plurality of insulating layers 112 and 112a are sequentially disposed along the first direction D1 and disposed along the third direction D3 between adjacent doped regions. A plurality of pillars PL11 , PL12 , PL21 , and PL22 passing through may be formed. The plurality of pillars PL11 , PL12 , PL21 , and PL22 may penetrate the plurality of insulating layers 112 and 112a to contact the substrate 111 .

In an embodiment, the plurality of pillars PL11 , PL12 , PL21 , and PL22 may be formed by vertically patterning the plurality of insulating layers 112 and 112a.

In an embodiment, each of the plurality of pillars PL11 , PL12 , PL21 , and PL22 may include an inner material 115 and a channel layer 114 surrounding the inner material 115 .

The channel layer 114 may include a semiconductor material (eg, silicon) having the same first conductivity type as that of the substrate 111 . The channel layer 114 may be made of poly-silicon. For example, the channel layer 114 may have a P-conductivity type. Hereinafter, it is assumed that the channel layer 114 has a P-conductivity type. However, the channel layer 114 is not limited to having a P-conductive type. For example, the channel layer 114 may include an intrinsic semiconductor having no conductivity type.

The inner material 115 may include an insulating material. In an embodiment, the inner material 115 may include silicon oxide. In another embodiment, the inner material 115 may include an air gap.

5 and 6 , between the plurality of insulating layers 112 and 112a , a charge storage layer 116 is formed on the surface of the plurality of insulating layers 112 and 112a and the channel layer 114 . ) can be formed. The charge storage layer 116 may store data by trapping charges from the channel layer 114 .

5 and 6, a plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10) can be formed. Accordingly, each of the plurality of gate electrode layers GEL1 , GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , GEL7 , GEL8 , GEL9 , and GEL10 may be formed at different heights from the substrate 111 . For example, in the memory block BLKa illustrated in FIGS. 4 to 6 , the first to tenth gate electrode layers GEL1 , GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , and GEL7 are formed according to the height order from the substrate 111 . , GEL8, GEL9, GEL10).

In an embodiment, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 may include a metallic conductive material such as tungsten.

In another embodiment, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 may include a non-metallic conductive material such as poly silicon. have.

The plurality of gate electrode layers GEL1 , GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , GEL7 , GEL8 , GEL9 , and GEL10 may extend along the first direction D1 .

Accordingly, as shown in FIGS. 5 and 6 , the plurality of insulating layers 112 and 112a and the plurality of gate electrode layers GEL1 , GEL2 , GEL3 GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10 are alternately formed, and a plurality of insulating layers 112 and 112a and a plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7 , GEL8 , GEL9 , and GEL10 may be formed with a charge storage layer 116 . In addition, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10, the charge storage layer 116 and the channel layer 114 are formed in the first direction D1. They may be formed sequentially.

On the plurality of doped regions 121, 122, and 123, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 are in the word line cut WL CUT. can be separated by The word line cut WL CUT may expose the plurality of doped regions 121 , 122 , and 123 . The word line cut WL CUT may extend along the first direction D1 .

In an embodiment, the charge storage layer 116 formed on the uppermost surface of the insulating material located at the top of the plurality of insulating materials 112 and 112a may be removed.

A plurality of drains 130 may be formed on the plurality of pillars PL11 , PL12 , PL21 , and PL22 . In an embodiment, the plurality of drains 130 may include the semiconductor material (eg, silicon) having the second conductivity type. For example, the plurality of drains 130 may have an N-conductivity type. Hereinafter, it is assumed that the plurality of drains 130 have an N-conductivity type. However, the plurality of drains 130 are not limited to having an N-conductivity type.

A plurality of bit lines BL1 and BL2 extending in the second direction D2 and spaced apart from each other in the first direction D1 may be formed on the plurality of drains 130 . In an embodiment, the plurality of bit lines BL1 and BL2 and the plurality of drains 130 may be connected to each other through a contact plug.

In an embodiment, the plurality of bit lines BL1 and BL2 may include a metallic conductive material.

In another embodiment, the plurality of bit lines BL1 and BL2 may include a non-metallic conductive material such as polysilicon.

Each of the plurality of pillars PL11, PL12, PL21, and PL22 includes a charge storage layer 116 and a plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 formed around each other. , GEL10) can form one vertical string. 4 to 6 , since a plurality of pillars PL11 , PL12 , PL21 , and PL22 are formed on the substrate 111 , the memory block BLKa may include a plurality of vertical strings.

Each of the plurality of vertical strings may include a plurality of cell transistors CT stacked in a third direction D3 perpendicular to the substrate 111 . Each of the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 operates as a gate electrode of the cell transistor CT, and the plurality of pillars PL11, PL12, The channel layer 114 included in each of PL21 and PL22 may operate as a body of the cell transistor CT.

7 is an enlarged view illustrating one of cell transistors included in the memory block illustrated in FIGS. 4 to 6 .

Referring to FIG. 7 , the cell transistor CT includes a fifth gate electrode layer GEL5, a portion of the pillar PL11 adjacent to the fifth gate electrode layer GEL5, and the fifth gate electrode layer GEL5 and the pillar. A charge storage layer 116 formed between PL11) may be included.

The channel layer 114 included in the pillar PL11 may include the same P-type silicon as the substrate 111 . The channel layer 114 may operate as a body of the cell transistor CT. Since the channel layer 114 is formed in the third direction D3 perpendicular to the substrate 111 , the channel layer 114 may operate as a vertical body of the cell transistor CT. Accordingly, a vertical channel may be formed in the channel layer 114 during operation of the cell transistor CT.

The charge storage layer 116 may include first to third sub insulating layers 117 , 118 , and 119 .

The first sub insulating layer 117 may be formed adjacent to the pillar PL11 . The first sub insulating layer 117 may operate as a tunneling insulating layer of the cell transistor CT. In an embodiment, the first sub insulating layer 117 may include a thermal oxide layer. In another embodiment, the first sub insulating layer 117 may include a silicon oxide layer.

The second sub insulating layer 118 may store charges tunneling from the channel layer 114 through the first sub insulating layer 117 . For example, the second sub insulating layer 118 may operate as a charge trap layer. In an embodiment, the second sub insulating layer 118 may include a nitride layer. In another embodiment, the second sub insulating layer 118 may include a metal oxide layer.

The third sub insulating layer 119 may be formed adjacent to the fifth gate electrode layer GEL5 . The third sub insulating layer 119 may operate as a blocking insulating layer of the cell transistor CT. The third sub insulating layer 119 may be formed as a single layer or a multilayer. The third sub insulating layer 119 may be a high dielectric layer having a higher dielectric constant than that of the first sub insulating layer 117 and the second sub insulating layer 118 . In an embodiment, the third sub insulating layer 119 may include a silicon oxide layer.

In an embodiment, the first to third sub insulating layers 117 , 118 , and 119 may have an oxide-nitride-oxide (ONO) structure.

The fifth gate electrode layer GEL5 may serve as a gate electrode of the cell transistor CT.

Accordingly, the plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10 serving as the gate electrode, the third sub insulating layer 119 serving as the blocking insulating layer, and the charge trap layer A plurality of second sub insulating layers 118 operating as , the first sub insulating layer 117 operating as a tunneling insulating layer, and a channel layer 114 operating as a vertical body are stacked in the third direction perpendicular to the substrate 111 . of cell transistors CT.

Each of the plurality of cell transistors CT may have a cylindrical shape centered on the corresponding pillars PL11 , PL12 , PL21 , and PL22 .

As will be described later with reference to FIG. 8 , the cell transistors CT included in the memory block BLKa may be used for different purposes depending on the height at which they are formed.

In an embodiment, at least one cell transistor CT formed on an upper portion of the cell transistors CT may be used as the string select transistor SST. For example, the cell transistor CT including the tenth gate electrode layer GEL10 may operate as a string select transistor SST. In some embodiments, the charge storage layer 116 may not be formed in the cell transistor CT operating as the string selection transistor SST.

In an embodiment, at least one cell transistor CT formed below among the cell transistors CT may be used as the ground selection transistor GST. For example, the cell transistor CT including the first gate electrode layer GEL1 may operate as the ground selection transistor GST. In some embodiments, the charge storage layer 116 may not be formed in the cell transistor CT operating as the ground selection transistor GST.

In an embodiment, among the cell transistors CT, the cell transistors CT formed between the at least one string select transistor SST and the at least one ground select transistor GST may be used as memory cells. have. For example, the cell transistors CT including the second to ninth gate electrode layers GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , GEL7 , GEL8 and GEL9 may include the first to eighth memory cells MC1 , respectively. , MC2, MC3, MC4, MC5, MC6, MC7, MC8).

The plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, and GEL10 may include a string selection line SSL, a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8) and the ground selection line (GSL).

In an embodiment, the tenth gate electrode layer GEL10 corresponding to the gate electrode of the string selection transistor is connected to the string selection line SSL, and the first gate electrode layer corresponding to the gate electrode of the ground selection transistor. GEL1 is connected to the ground selection line GSL, and the second to ninth gate electrode layers GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 corresponding to the gate electrodes of the memory cells are Each of the first to eighth word lines WL1 , WL2 , WL3 , WL4 , WL5 , WL6 , WL7 , and WL8 may be connected to each other.

8 is an equivalent circuit diagram of the memory block shown in FIGS. 4 to 6 .

In FIG. 8 , it is assumed that the memory block shown in FIGS. 4 to 6 further includes one gate electrode film under the first gate electrode film GEL1 and one gate electrode film on the tenth gate electrode film GEL10 . .

4 to 8 , the plurality of doped regions 121 , 122 , and 123 may be commonly connected to a common source line CSL.

Vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 may be formed between the plurality of bit lines BL1 and BL2 and the common source line CSL. The vertical strings CS11 , CS21 , CS31 , and CS41 may be connected between the first bit line BL1 and the common source line CSL. The vertical strings CS12 , CS22 , CS32 , and CS42 may be connected between the second bit line BL2 and the common source line CSL.

The vertical strings CS11, CS12, CS21, and CS22 illustrated in FIG. 8 may correspond to the plurality of pillars PL11, PL12, PL21, and PL22 illustrated in FIGS. 4 to 6 , respectively. For example, four pillars PL11, PL12, PL21, PL22, a plurality of gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10, and a charge storage layer ( 116 may form four vertical strings CS11, CS12, CS21, and CS22.

In an embodiment, the first gate electrode layer GEL1 may form the ground selection transistors GST2 together with the charge storage layer 116 and the plurality of pillars PL11 , PL12 , PL21 , and PL22 . The first gate electrode layer GEL1 corresponding to the gate electrode of the ground selection transistors GST2 may be connected to the ground selection lines GSL12 and GSL22. For example, ground selection transistors GST formed along the first direction D1 are connected to the same ground selection line, and ground selection transistors GST spaced apart from each other along the second direction D2 are different from each other. It can be connected to the ground select line. According to an exemplary embodiment, all of the ground select transistors GST including the first gate electrode layer GEL1 may be connected to one ground select line.

In an embodiment, the second to ninth gate electrode layers GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, and GEL9 include the charge storage layer 116 and the plurality of pillars PL11, PL12, and PL21. , PL22 may form first to eighth memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 together. The second to ninth gate electrode layers GEL2, GEL3, GEL4, GEL5, GEL6, corresponding to the gate electrodes of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, GEL7, GEL8, and GEL9 may be connected to the first to eighth word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. That is, memory cells formed at the same height may be commonly connected to one word line. Accordingly, when a voltage is applied to a word line selected from among the plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, the selected The voltage may be applied to all memory cells connected to the word line.

In an embodiment, the first memory cell MC1 and the eighth memory cell MC8 may be implemented as dummy memory cells DMC1 and DMC2 .

In an embodiment, the tenth gate electrode layer GEL10 may form the string selection transistors SST1, together with the charge storage layer 116 and the plurality of pillars PL11, PL12, PL21, and PL22. . The tenth gate electrode layer GEL10 corresponding to the gate electrode of the string select transistors SST may be connected to the string select lines SSL11 and SSL21. For example, string select transistors SST formed along the first direction D1 are connected to the same string select line, and string select transistors SST spaced apart from each other along the second direction D2 are different from each other. It may be connected to a string select line.

9 is a conceptual diagram for explaining a plane structure of the equivalent circuit diagram shown in FIG. 8 .

4 to 9 , the equivalent circuit diagram shown in FIG. 8 includes four planes. In FIG. 8 , vertical strings CS11 and CS12 constitute a first plane PLANEa, vertical strings CS21 and CS22 constitute a second plane PLANEb, and vertical strings CS31 and CS32. may constitute the third plane PLANEc, and the vertical strings CS41 and CS42 may constitute the third plane PLANEd. The first word line WL1 is divided into first sub word lines WLa1 to WLd1 according to a plane, and the second word line WL2 is divided into second sub word lines WLa2 to WLd2 according to a plane. The third word line WL3 is divided into third sub word lines WLa3 to WLd3 according to a plane, and the fourth word line WL4 is divided into fourth sub word lines WLa4 to WLd4 according to a plane. , the fifth word line WL5 is divided into fifth sub word lines WLa5 to Ld5 according to a plane, and the sixth word line WL6 is divided into sixth sub word lines WLa6 to WLa6 according to a plane. WLd6), the seventh word line WL7 is divided into seventh sub word lines WLa7 to WLd7 according to a plane, and the eighth word line WL8 is divided into eighth sub word lines (WL8) according to a plane. WLa8 to WLd8).

Vertical strings formed on the same plane may be connected to the same string selection line, and vertical strings formed on different planes may be connected to different string selection lines. For example, the vertical strings CS11 and CS12 included in the first plane PLANEa are connected to the first string selection lines SSL1 and SSL12, and the vertical strings included in the second plane PLANEb are connected to the vertical strings CS11 and CS12 included in the second plane PLANEb. CS21 and CS22 may be connected to the second string selection lines SSL21 and SSL22.

By selecting a pair of string selection lines SSL11 to SSL42, vertical strings may be selected in units of planes. For example, when the first string selection lines SSL11 and SSL12 are selected, the vertical strings CS11 and CS12 connected to the first string selection lines SSL11 and SSL12 are the plurality of bit lines BL1 . , BL2 , the unselected vertical strings CS21 to CS42 may be electrically cut off from the plurality of bit lines BL1 and BL2 .

Vertical strings formed along the second direction D2 may be connected to the same bit line, and vertical strings spaced apart from each other along the first direction D1 may be connected to different bit lines. For example, the vertical strings CS11 , CS21 , CS31 , and CS41 are connected to the first bit line BL1 , and the vertical strings CS12 , CS22 , CS32 and CS42 are connected to the second bit line BL2 . can

For example, in FIGS. 4 to 8 , each of the vertical strings includes two string select transistors SST1 and SST2 , two ground select transistors GST1 and GST2 , and a string select transistor SST1 and a ground select transistor GST2 . It is illustrated as including first to eighth memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 and MC8 therebetween. However, the number of the string select transistor SST, the ground select transistor GST, and the plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 included in each of the vertical strings is not limited thereto. .

As described above, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8 has a corresponding gate electrode film GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, a charge It may include a storage layer 116 and a channel layer 114 . Each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8 is disposed between the corresponding gate electrode film GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9 and the channel film 114 . A program operation and an erase operation may be performed by tunneling charges between the charge storage layer 116 and the channel layer 114 based on an electric field formed therein. Since the channel layer 114 is electrically connected to the substrate 111 , voltages of different magnitudes are applied to the gate electrode layers GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , GEL7 , GEL8 and GEL9 and the substrate 111 . A program operation and an erase operation may be performed on the memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 .

In one embodiment, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8 has a corresponding gate electrode layer GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9. A program operation may be performed by applying a voltage higher than that of the substrate 111 to tunnel negative charges from the channel layer 114 to the charge storage layer 116 .

In one embodiment, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 is larger than the corresponding gate electrode layer GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9. An erase operation may be performed by applying a high voltage to the substrate 111 to tunnel negative charges from the charge storage layer 116 to the channel layer 114 .

In another embodiment, each of the memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8 has a corresponding gate electrode layer GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9. An erase operation may be performed by applying a high voltage to the substrate 111 to tunnel positive charges from the channel layer 114 to the charge storage layer 116 .

Each of the memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 may have a cylindrical shape centered on a corresponding pillar PL11 , PL12 , PL21 , and PL22 .

Since each of the plurality of pillars PL11, PL12, PL21, and PL22 is formed by vertically patterning the plurality of insulating layers 112 and 112a, the plurality of pillars PL11, PL12, PL21, and PL22 Each of them may become smaller in width toward the bottom. For example, as shown in FIG. 6 , each of the plurality of pillars PL11 , PL12 , PL21 , and PL22 has a V-shaped cylindrical shape having a lower diameter Wb smaller than an upper diameter Wt and an inclination angle a. can have

Accordingly, diameters of pillars on which the memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 are formed may be different from each other according to a height from the substrate 111 . That is, diameters of the memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 may be different according to heights from the substrate 111 . For example, among the memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , and MC8 , a memory cell formed below and adjacent to the substrate 111 has a relatively small diameter, and the memory cells MC1 , MC1 and MC8 have a relatively small diameter. Among MC2, MC3, MC4, MC5, MC6, MC7, and MC8), the upper memory cell may have a relatively large diameter.

Referring back to FIG. 2B , the control circuit 500 receives a command signal CMD and an address signal ADDR from an external device (eg, a memory controller), and receives a command signal CMD and an address signal ADDR. An erase loop, a program loop, and a read operation of the nonvolatile memory device 10 may be controlled based on the . Here, the program loop may include a program operation and a program verify operation, and the erase loop may include an erase operation and an erase verification operation.

For example, the control circuit 500 generates control signals CTLs for controlling the voltage generator 600 based on the command signal CMD, and a row address R_ADDR based on the address signal ADDR. and a column address C_ADDR. The control circuit 500 may provide the row address R_ADDR to the address decoder 400 and provide the column address C_ADDR to the data input/output circuit 470 . The row address R_ADDR may include a block address BLK_ADDR. Also, the control circuit 500 may provide the reset signal RST to the address decoder 400 . Also, the control circuit 500 may provide the control signal PBC to the page buffer circuit 460 .

The address decoder 400 may be connected to the memory cell array 100 through at least one string selection line SSL, a plurality of word lines WLs, and at least one ground selection line GSL. During a program operation or a read operation, the address decoder 430 determines one of the plurality of word lines WLs as the selected word line based on the row address R_ADDR provided from the control circuit 500 , and the plurality of words Among the lines WLs, word lines other than the selected word line may be determined as unselected word lines.

The voltage generator 600 may generate word line voltages VWLs necessary for the operation of the nonvolatile memory device 30 based on the control signals CTLs provided from the control circuit 500 . The word line voltages VWLs generated from the voltage generator 600 may be applied to the plurality of word lines WLs through the address decoder 400 .

For example, during an erase operation, the voltage generator 600 may apply an erase voltage to a well of the memory block and apply a ground voltage to all word lines of the memory block. During the erase verification operation, the voltage generator 600 may apply the erase verification voltage to all word lines of one memory block or may apply the erase verification voltage in units of word lines.

For example, during a program operation, the voltage generator 600 may apply a program voltage to a selected word line and apply a program pass voltage to an unselected word line. Also, during the program verification operation, the voltage generator 600 may apply a program verification voltage to the selected word lines and apply a verification pass voltage to the unselected word lines.

Also, during a read operation, the voltage generator 600 may apply a read voltage to the selected word lines and apply a read pass voltage to the unselected word lines.

The page buffer circuit 460 may be connected to the memory cell array 100 through a plurality of bit lines BLs. The page buffer circuit 460 may include a plurality of page buffers. In one embodiment, one bit line may be connected to one page buffer. In another embodiment, two or more bit lines may be connected to one page buffer.

The page buffer circuit 460 may temporarily store data to be programmed in a selected page during a program operation, and temporarily store data read from the selected page during a read operation.

The data input/output circuit 470 may be connected to the page buffer circuit 460 through data lines DLs. During a program operation, the data input/output circuit 420 receives the program data DATA from the memory controller 20 and stores the program data DATA based on the column address C_ADDR provided from the control circuit 500 into a page buffer. circuit 460 may be provided. During a read operation, the data input/output circuit 470 may provide the read data DATA stored in the page buffer circuit 460 to the memory controller 20 based on the column address C_ADDR provided from the control circuit 500 . have.

Also, the page buffer circuit 460 and the data input/output circuit 470 read data from the first storage area of the memory cell array 100 and write the read data into the second storage area of the memory cell array 100 . can do. That is, the page buffer circuit 460 and the data input/output circuit 470 may perform a copy-back operation.

10 is a block diagram illustrating a configuration of a control circuit in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 10 , the control circuit 500 may include a command decoder 510 , an address buffer 520 , a control signal generator 530 , and a status signal generator 540 .

The command decoder 510 may decode the command signal CMD and provide the decoded command D_CMD to the control signal generator 530 . In an embodiment, the command decoder 510 may provide the decoded command D_CMD to the status signal generator 540 .

The address buffer 520 receives the address signal ADDR, and among the address signals ADDR, the row address R_ADDR is provided to the address decoder 400 , and the column address C_ADDR is provided to the data input/output circuit 470 . can

The control signal generator 530 may receive the decoded command D_CMD, generate control signals CTLs based on an operation indicated by the decoded command D_CMD, and provide the generated control signals CTLs to the voltage generator 600 .

The status signal generator 540 generates a status signal RnB indicating an operating state of the nonvolatile memory device 30 based on one of the command CMD and the decoded command D_CMD, and the status signal RnB. may be provided to the memory controller 20 . For example, when the nonvolatile memory device 30 performs a memory operation such as program, read, or erase, the status signal generator 540 outputs the status signal RnB at a low level to generate the nonvolatile memory device 30 . ) can represent a busy state. For example, when the nonvolatile memory device 30 is in an idle state in which no memory operation is performed, the status signal generator 540 outputs the status signal RnB at a high level to the nonvolatile memory device 30 . ) can represent the ready state.

11 is a block diagram illustrating a configuration of a voltage generator in the nonvolatile memory device of FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 11 , the voltage generator 600 may include a high voltage generator 610 and a low voltage generator 630 . In an embodiment, the voltage generator 600 may further include a negative voltage generator 650 .

The high voltage generator 610 responds to the first control signal CTL1 and according to an operation indicated by the decoded command D_CMD, a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, and a read pass. A voltage VRPASS and an erase voltage VRES may be generated. The program voltage VPGM is applied to the selected word line, the program pass voltage VPPASS, the program verify pass voltage VVPASS, and the read pass voltage VRPASS are applied to the unselected word lines, and the erase voltage VRES is It may be applied to the substrate of the memory block. The first control signal CTL1 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

The low voltage generator 630 may generate a program verification voltage VPV, a read voltage VRD, and an erase verification voltage VEV according to an operation indicated by the decoded command D_CMD in response to the second control signal CTL2. have. The program verification voltage VPV, the read voltage VRD, and the erase verification voltage VEV may be applied to the selected word line according to an operation. The second control signal CTL2 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

The negative voltage generator 650 responds to the third control signal CTL3 according to an operation indicated by the decoded command D_CMD. A verification voltage VEV' may be generated. The third control signal CTL3 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

12A is a flowchart illustrating a method of operating a nonvolatile memory device according to embodiments of the present invention.

The operation method of FIG. 12A may be performed through the nonvolatile memory device 30 of FIG. 2 .

1 to 12A , in the method of operating a nonvolatile memory device according to embodiments of the present invention, a first memory operation is performed with respect to a first memory block BLKa among a plurality of memory blocks BLK1 to BLKz. can be performed (S100). When the first memory operation is a program operation or an erase operation, threshold voltages of at least some cell transistors of the first memory block BLKa may be changed to a target state by the first memory operation. When the state signal RnB indicates the ready state of the nonvolatile memory device 30 for a reference time or more after the completion of the first memory operation, the first A curing operation is performed on at least a portion of the memory block BLKa ( S200 ). After the curing operation is completed, a second memory operation is performed on at least a portion of the first memory block BLKa ( S300 ).

Here, the first memory operation may be performed on at least a portion of the first memory block BLKa. At least a portion of the first memory block BLKa is one page of the first memory block BLKa, and the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42 of the first memory block BLKa. ) may be one, some, or all of them. The first memory operation may be a program operation, and the second memory operation may be a read operation. Also, the first memory operation may be a read operation, and the second memory operation may also be a read operation. The first memory operation may be an erase operation, and the second memory operation may be a program operation.

12B is a timing diagram illustrating an operation of the memory system of FIG. 1 when the operating method of FIG. 12A is performed.

1, 2A, 2B, 10, 12A, and 12B , between the time points T0 to T11 when the status signal RnB is in the ready state, the memory controller 20 operates the nonvolatile memory device ( 30) may transmit a command CMD, an address ADDR, and data DATA. The nonvolatile memory device 30 receiving the command CMD, the address ADDR, and the data DATA may perform a first memory operation between time points T11 to T12. Here, the first memory operation may be a program operation, and while the nonvolatile memory device 30 performs the first memory operation, the status signal RnB may indicate a busy state as a low level.

When the first memory operation is completed at the time T12 and the state signal RnB transitions to a high level to indicate a ready state, the counter 27 operates to compare the ready state state signal RnB with a reference time . When the ready state signal RnB exceeds the reference time at time T13 , the memory controller 20 transmits a command CMD and an address ADDR for a curing operation to the nonvolatile memory device 30 . do. Upon receiving the command CMD and the address ADDR for instructing the curing operation, the nonvolatile memory device 30 starts the curing operation at a time point T14 and completes the curing operation at a time point T15 . At a time point T15 when the curing operation is completed, the state signal RnB transitions to a high level.

The memory controller 20 transmits a command CMD and an address ADDR for a second memory operation to the nonvolatile memory device 30 between time points T16 to T17 when the state signal RnB is at a high level. . The nonvolatile memory device 30 that has received the command CMD, the address ADDR, and the data DATA may perform a second memory operation between time points T17 to T18. Here, the second memory operation may be a read operation. After completing the second memory operation, the nonvolatile memory device 30 transitions the state signal RnB to the high level again at a time point T18.

As described above, when the ready state of the non-volatile memory device 30 continues for a reference time or longer after the completion of the first memory operation, the memory controller 20 instructs the non-volatile memory device 30 to perform a curing operation, The nonvolatile memory device 30 may perform a curing operation in response thereto. Accordingly, the reliability of the second memory operation may be increased.

13 is a flowchart illustrating an example of a curing operation in the operating method of FIG. 12A according to embodiments of the present invention, and FIG. 14 is one of vertical strings in the memory block of FIG. 8 applied to the operating method of FIG. 12A , and FIG. 15 shows voltages applied to the first vertical string in the curing operation of FIG. 13 .

In FIG. 14 , the first vertical string CS11 among the vertical strings CS11 , CS12 , CS21 , CS22 , CS31 , CS32 , CS41 and CS42 of the memory block of FIG. 8 will be described as an example. Also, a case in which the first vertical string CS11 includes one ground selection transistor and one string selection transistor will be described as an example.

13 to 15 , in order to perform a curing operation on at least a portion of the first memory block BLKa ( S200a ), a string connected to the string select transistor SST of the first vertical string CS11 The turn-off voltage VTOFF is applied to the selection line SSL1 to turn off the string selection transistor SST ( S210a ). The turn-off voltage VTOFF may be a ground voltage GND. Word lines WL1 to WL8 to which the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 are connected between the first time point T21 and the second time point T22 Turn-on voltages VTON1 to VTON8 and VTONG corresponding to each of the ground selection lines GSL1 to which the and the ground selection transistor GST are connected are respectively applied (S220a). At the same time, the common source line CSL connected to the ground selection transistor GST is maintained at the ground voltage GND (S230a). Here, the turn-on voltages VTON1 to VTON8 and VTONG are the threshold voltages of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 and the ground selection transistor GST, respectively. may have a higher level than each of them.

The turn-on voltages VTON1 to VTON8 and VTONG may have the same level, or some or all of them may have different levels.

When turn-on voltages VTON1 to VTON8 and VTONG corresponding to the word lines WL1 to WL8 and the ground selection line GSL1 are respectively applied, the first to eighth memory cells MC1, MC2, MC3, and MC4 , MC5, MC6, MC7, MC8) and the ground select transistor GST are turned on. At this time, since the common source line CSL is maintained at the ground voltage GND, an electric field is formed between the gate electrode layers GEL1 , GEL2 , GEL3 , GEL4 , GEL5 , GEL6 , GEL7 , GEL8 , GEL9 and the channel layer 114 . can be After the first memory operation is performed by the electric field formed in this way, electrons (or electric charges) trapped in the trap of the channel film 114 move to the surface of the channel film 114 , and thus the first to eighth memory cells MC1 and MC2 . , MC3, MC4, MC5, MC6, MC7, MC8) of at least a portion of the threshold voltage may be restored close to the target state.

16 is a flowchart illustrating an example of a curing operation in the operating method of FIG. 12A according to embodiments of the present invention, and FIG. 17 is one of vertical strings in the memory block of FIG. 8 to which the operating method of FIG. 12A is applied. , and FIG. 18 shows voltages applied to the first vertical string in the curing operation of FIG. 16 .

In FIG. 17 , the first vertical string CS11 among the vertical strings CS11 , CS12 , CS21 , CS22 , CS31 , CS32 , CS41 and CS42 of the memory block BLKa of FIG. 8 will be described as an example. Also, a case in which the first vertical string CS11 includes one ground selection transistor and one string selection transistor will be described as an example.

16 to 18 , in order to perform a curing operation on at least a portion of the first memory block BLKa ( S200b ), a bit connected to the string select transistor SST of the first vertical string CS11 The bit line (BLSHF) applied to the transistor PT1 connecting the line BL1 and the page buffer PB1 to the ground voltage GND from the first time point T21 to the second time point T22 BL1) and the page buffer PB1 are disconnected (S210b). From the first time point T21 to the second time point T22 , the string select line SSL1 connected to the string select transistor SST and the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6 Turn-on voltages VTONS, VTON1 to VTON8, VTONG corresponding to the word lines WL1 to WL8 to which , MC7, MC8 are connected and the ground select line GSL1 to which the ground select transistor GST1 is connected, respectively are applied respectively (S220b). At the same time, the common source line CSL connected to the ground selection transistor GST is maintained at the ground voltage GND (S230b). Here, the turn-on voltages VTONS, VTON1 to VTON8, and VTONG are the string selection transistor SST, the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, and ground selection, respectively. It may have a level higher than each of the threshold voltages of the transistor GST1. The turn-on voltages VTONS, VTON1 to VTON8, and VTONG may have the same level, or some or all of them may have different levels.

When turn-on voltages VTONS, VTON1 to VTON8, and VTONG corresponding to the string selection line SSL, the word lines WL1 to WL8, and the ground selection line GSL1 are respectively applied, the string selection transistor SST , the first to eighth memory cells MC1 , MC2 , MC3 , MC4 , MC5 , MC6 , MC7 , MC8 , and the ground select transistor GST are turned on. At this time, since the common source line CSL is maintained at the ground voltage GND, it is disposed between the gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10 and the channel layer 114 . An electric field may be formed. After the first memory operation is performed by the electric field formed in this way, electrons captured by the trap of the channel film 114 move to the surface of the channel film 114 and then move to the first to eighth memory cells MC1 , MC2 , MC3 , and MC4 . , MC5, MC6, MC7, MC8) of at least a portion of the threshold voltage may be restored close to the target state.

19A to 19F are diagrams for explaining the concept of the present invention.

In FIGS. 19A to 19F , a portion 140 indicated by reference numeral 140 in the cell transistor CT of FIG. 7 will be described as an example. Accordingly, the portion 140 of FIGS. 19A to 19F may include a fifth gate electrode layer GEL5 , a charge trap layer 118 , and a channel layer 114 .

19A shows the portion 140 of the cell transistor CT before the first memory operation is performed.

Since the channel layer 114 may be made of polysilicon as described above, traps 150 may be formed at grain boundaries of the silicon crystal.

19B shows the portion 140 of the cell transistor CT immediately after the first memory operation is performed.

Referring to FIG. 19B , when the first memory operation is performed on at least a portion of the first memory block BLKa including the cell transistor CT, electrons e are captured in the charge trap layer 118 and the channel layer Electrons may be trapped in the trap 150 that is adjacent to the surface of the 114 .

19C shows the portion 140 of the cell transistor CT after the first memory operation is performed and time has elapsed.

Referring to FIG. 19C , when a first memory operation is performed on at least a portion of the first memory block BLKa including the cell transistor CT and time elapses, traps existing adjacent to the surface of the channel layer 114 . Electrons e captured at 150 move in a direction away from the surface of the channel layer 114 as indicated by reference numeral 151 , so that the threshold voltage distribution of the cell transistor CT may change.

19D illustrates the cell transistor CT immediately after (GR1) and after time elapses (GR2) after the first memory operation is performed on at least a portion of the first memory block BLKa including the cell transistor CT. represents the threshold voltage distribution of

As described with reference to FIG. 19C , when the first memory operation is performed on at least a portion of the first memory block BLKa including the cell transistor CT, the distribution of the threshold voltage of the cell transistor CT over time may move from the graph GR1 to the graph GR2.

FIG. 19E illustrates voltage conditions when a curing operation according to embodiments of the present disclosure is performed on at least a portion of the first memory block BLKa including the cell transistor CT, and FIG. 19F illustrates the curing operation. The cell transistor CT is shown after execution.

19E and 19F , in order to restore the shift of the threshold voltage of the cell transistor CT, the first voltage V1 is applied to the fifth gate electrode layer GEL5 and the channel layer 118 is applied to the substrate ( 111), the second voltage V2 of a lower level than the first voltage V2 is applied. In this case, an electric field EF is formed from the fifth gate electrode film GEL5 toward the channel film 114 , and as indicated by reference numeral 153 , the electrons e are channeled by the electric field EF thus formed. It moves toward the surface of the membrane 114 . Accordingly, the threshold voltage of the cell transistor CT may be moved to a state close to the target state immediately after the first memory operation is performed.

After the curing operation is performed on at least a portion of the first memory block BLKa, a second memory operation may be performed on the first memory block BLKa.

In an embodiment, the first memory operation may be a program operation (loop) performed on the first memory block BLKa, and the second memory operation may be a read operation performed on the first memory block BLKa. can be

As described with reference to FIGS. 19A to 19F , the threshold voltages of the memory cells may change over time after the program operation is performed, and the first memory block BLKa is formed without performing the curing operation. When a read operation is performed on a part, an error bit due to a change in the threshold voltage may increase. When the increased error bits exceed a correctable range of an error correction code, the performance of the nonvolatile memory device 30 may deteriorate. However, according to embodiments of the present invention, after the curing operation is performed on at least a portion of the first memory block BLKa after the first memory operation (program operation), the second memory with respect to the first memory block BLKa Operation (read operation) is performed. Accordingly, since the read operation is performed after the threshold voltage of the memory cells is moved to a state close to the target state, the number of error bits may be reduced to improve performance.

In an embodiment, the first memory operation may be an erase operation (loop) performed on the first memory block BLKa, and the second memory operation may be a program operation performed after the erase operation.

When an erase operation is performed on the first memory block BLKa, holes may be trapped in the tunneling insulating layer 117 as well as the phone trapping layer 118 of FIG. 7 . Holes trapped in the tunneling insulating layer 117 may easily move to the trap 150 of the channel layer 114 over time to change the threshold voltage of the memory cell.

According to embodiments of the present invention, after the erase operation is performed on the first memory block BLKa, the above-described curing operation is performed on the first memory block BLKa to thereby trap the trap 150 of the channel layer 114 . Threshold voltages of memory cells of the first memory block BLKa may be restored to an erased state by moving the holes (charges) captured in the ?

The above-described curing operation may be simultaneously performed on a plurality of vertical strings included in one memory block.

20 illustrates that a curing operation according to an embodiment of the present invention is simultaneously performed on a plurality of vertical strings included in one memory block.

In FIG. 20 , the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 of the memory block BLKa of FIG. 8 will be described as an example. Also, a case in which the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 includes one ground selection transistor and one string selection transistor will be described as an example.

8 and 20 , a first memory operation is sequentially or simultaneously performed on pages of a memory block BLKa, and vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42 ), the above-described curing operation may be performed at the same time. In this case, in the period from the first time point T to the second time point T2, the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 are applied to the string select transistor SST. String selection lines SSL11, SSL21, SSS31, SSL41 are connected, word lines WL1 to WL8 connected to vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42, and ground selection Turn-on voltages VTONS, VTON1 to VTON8, VTONG corresponding to the ground selection lines GSL12, GSL22, GSL32, and GSL42 respectively connected to the transistor GST are applied, and with reference to FIGS. 14 and 17 , As described above, the common source line CSL connected to the ground selection transistor GST is maintained at the ground voltage GND. Accordingly, in each of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, CS42, the gate electrode layers GEL1, GEL2, GEL3, GEL4, GEL5, GEL6, GEL7, GEL8, GEL9, GEL10 and the channel layer An electric field is formed between the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, and MC6 of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42. , MC7, MC8) may be moved to a state close to the target state of at least a portion of the threshold voltage.

In this case, the control signal BLSHF applied to the transistor connecting the bit line connected to each of the vertical strings CS11, CS12, CS21, CS22, CS31, CS32, CS41, and CS42 and the corresponding page buffer is applied to the ground voltage ( GND) to cut off the connection between the bit line and the page buffer from the first time point T21 to the second time point T22, thereby reducing current consumption.

The curing operation according to embodiments of the present invention may be simultaneously performed on at least two or more memory blocks among the plurality of memory blocks BLK1 to BLKz. Also, when the curing operation is simultaneously performed on two or more memory blocks, when the plurality of memory blocks BLK1 to BLKz include at least one bad convexity, the curing operation is performed on the at least one bad block. The action may not be performed.

21 is a block diagram illustrating a configuration of an address decoder in the nonvolatile memory device of FIG. 2B according to embodiments of the present invention.

In FIG. 21 , the memory cell array 100 and the voltage generator 600 are shown together for convenience of description. It is assumed that the memory cell array 100 is composed of a plurality of memory blocks 101 to 108 .

Referring to FIG. 21 , the address decoder 400 may include a decoder 410 , an address comparator 420 , a bad block address register 430 , and a plurality of selection circuits 441 to 448 .

The bad block address register 430 may store a bad block address set that is an address of at least one of the plurality of memory blocks 101 to 108 included in the memory cell array 100 . Here, the bad block may be a memory block including at least one page including error bits in which the plurality of memory blocks 101 to 108 cannot be corrected by an error correction code (ECC).

The bad block address set is a first bad block address register (IBBA) stored in the bad block address register 430 before the power-up sequence of the nonvolatile memory device 30 and a bad block address register (IBBA) during the operation of the nonvolatile memory device 30 . It may include a second bad block address register RTBBA stored in the block address register 430 . Here, the second bad block address register RTBBA is a block address of a memory block determined as a bad block during operation of the nonvolatile memory device 30 , and may be referred to as a run-time bad block address.

The address comparator 420 compares the block address BLK_ADDR provided from the control circuit 500 with the bad block address set, and outputs a match signal MS indicating whether the block address BLK_ADDR and the bad block address set are identical to the decoder (410) may be provided.

The decoder 410 decodes the block address BLK_ADDR to generate a block selection signal for selecting two or more of the plurality of memory blocks 101 to 108 and provides it to the plurality of selection circuits 441 to 448. , a block selection signal may be generated so that a bad block among the memory blocks 101 to 108 is not selected based on the match signal MS.

The selection circuits 441 to 448 may be connected to each of the memory blocks 101 to 108 through a string selection line SSL, a plurality of word lines WLs, and a ground selection line GSL. In addition, each of the selection circuits 441 to 448 may selectively provide the word line voltage WLs provided from the voltage generator 600 to each of the corresponding memory blocks 101 to 108 in response to the block selection signal. .

22 shows the address decoder shown in FIG. 21 in detail.

Although only the configuration of the selection circuit 441 is shown in detail in FIG. 22 , the configuration of each of the selection circuits 442 to 448 may be substantially the same as that of the selection circuit 441 .

Referring to FIG. 22 , the decoder 410 decodes the block address BLK_ADDR and the match signal MS to select two or more memory blocks from among the plurality of memory blocks 101 to 108 at the same time. (BS1 to BS8) may be provided to each of the selection circuits 441 to 448, but the block selection signals BS1 to BS8 may be provided to each of the selection circuits 441 to 448 so that the bad block is not selected. Each of the selection circuits 441 to 448 selectively provides the word line voltage VWLs from the voltage generator 600 to each of the memory blocks 101 to 108 in response to each of the block selection signals BS1 to BS8 can do.

The decoder 410 may selectively activate each of the block selection signals BS1 to BS8 so that memory blocks designated by the block address BLK_ADDR are selected but a bad block is not selected based on the match signal MS.

The selection circuit 441 may include a selection signal latch 441a and a plurality of selection transistors ST1 to ST4 . The plurality of selection transistors ST1 to ST4 may be connected to the memory block 101 through a string selection line SSL, word lines WLS, and a ground selection line GSL. The selection signal latch 441a may latch and store the block selection signal BS1 and provide the latched block selection signal BS1 to the gates of the plurality of selection transistors ST1 to ST4 .

When the block selection signal BS1 is activated to the first logic level, the first voltage V1 provided from the voltage generator 600 when the curing operation is performed is applied to the turned-on selection transistors ST1 to ST4. may be provided to the memory block 101 , and after the curing operation is completed, the selection signal latch 441a may be initialized in response to the reset signal RST provided from the control circuit 500 .

When the memory block 102 corresponds to a bad block and the block selection signal BS2 is deactivated to the second logic level, turn-on voltages provided from the voltage generator 600 when the curing operation is performed. It may not be provided to the memory block 102 by the off selection transistors ST1 to ST4 .

Hereinafter, it will be described that the curing operation is simultaneously performed on a plurality of memory blocks with reference to FIGS. 2B, 21 and 22 .

After the first memory operation for at least a portion of the memory blocks 101 to 108 is completed, when the ready state of the nonvolatile memory device 30 continues for a reference time or longer, the control circuit 500 from the memory controller 20 When the block address BLK_ADDR for multi-block curing is input to , the control circuit 500 provides the block address BLK_ADDR to the decoder 410 and the address comparator 420 of the address decoder 400 . The address comparator 420 compares each of the at least two block addresses specified by the block address BLK_ADDR with the set of bad block addresses stored in the bad block address register 430, and outputs a match signal MS indicating whether or not they match to the decoder ( 410) is provided. The decoder 410 decodes the block address BLK_ADDR and the match signal MS to selectively select each of the block selection signals BS1 to BS8 so that a bad block is not selected among the memory blocks designated by the block address BLK_ADDR. It is activated and provided to each of the selection circuits 441 to 448.

For example, the block address BLK_ADDR designates the memory blocks 101 to 103 , and when the memory block 102 is a bad block, the block selection signals BS1 and BS3 are activated to a first logic level. and the block selection signals BS2 and BS4 to BS8 may be inactivated to the second logic level. Accordingly, a curing operation may be simultaneously performed on the memory blocks 101 and 103 . After the curing operation is completed, the control circuit 500 may initialize the selection signal latch 441a by providing the reset signal RST to the selection signal latch 441a of each of the selection circuits 441 to 448 .

As described above, when the curing operation is simultaneously performed on two or more memory blocks, the intervention of the memory controller 20 can be minimized when the curing operation is performed.

According to an embodiment, each of the selection circuits 441 to 448 may include a bad block latch instead of the selection signal latch 441a. In this case, the bad block latch may store a first bad block address and a second bad block address like the bad block address register 430 of FIG. 21 , and the first bad block address is the nonvolatile memory device 30 . It may be updated internally, and the second bad block address may be updated through the memory controller 20 .

23 shows the configuration of the memory system of FIG. 1 .

The memory system of FIG. 23 may be applied when a curing operation for multi-blocks is performed.

Referring to FIG. 23 , the address decoder 400 of the nonvolatile memory device 30 includes a first bad block address register 430 , and the first bad block address register 430 includes a first bad block address IBBA. ) can be stored. The memory controller 20 may include an address generator 21 and a second bad block address register 23 , and the second bad block address register 23 may store a second bad block address RTBBA. The address generator 21 generates a block address BLK_ADDR for performing a curing operation on at least two memory blocks, a second bad block address RTBBA stored in the second bad block address register 23 . A block address BLK_ADDR may be generated so that , and the generated block address BLK_ADDR may be provided to the nonvolatile memory device 30 . The nonvolatile memory device 30 may compare the block address BLK_ADDR with the first bad block address IBBA to prevent the curing operation from being performed on the memory block corresponding to the first bad block address IBBA. .

24 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.

Referring to FIG. 24 , the SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

The nonvolatile memory devices 1100 may optionally be implemented to receive an external high voltage (VPP). The nonvolatile memory devices 1100 may be implemented as the nonvolatile memory device 30 of FIG. 2B described above. Accordingly, each of the nonvolatile memory devices 1100 performs a first memory operation on the first memory block, and when the ready state continues for a reference time or longer after the completion of the first memory operation, a command from the SSD controller 1200 is applied. In response, a curing operation may be performed on at least a portion of the first memory block. Each of the non-volatile memory devices 1100 may perform a second memory operation on the first memory block after the curing operation is performed to reduce the number of error bits, thereby improving performance.

The SSD controller 1200 is connected to the nonvolatile memory devices 1100 through a plurality of channels CH1 to CH4. The SSD controller 1200 includes at least one processor 1210 , a buffer memory 1220 , an error correction circuit 1230 , a host interface 1250 , a nonvolatile memory interface 1260 , and a counter unit 1270 . The counter unit 1270 may include a plurality of counters. The plurality of counters may be allocated to the plurality of channels CH1 to CH4 or may be allocated to each of the nonvolatile memory devices 1100 . As described with reference to FIG. 2A , each of the plurality of counters included in the counter unit 1270 receives a status signal from each of the nonvolatile memory devices 1100 and compares the status signal indicating the ready state with a reference time. And, when the ready state continues for more than a reference time, a determination signal indicating this may be provided to the processor 1210 . The processor 1210 may transmit a command and an address instructing a curing operation to the corresponding non-volatile memory device 1100 in response to the determination signal, and the corresponding non-volatile memory device 1100 responds to the above-described curing operation. A ring operation can be performed.

The buffer memory 1220 may temporarily store data necessary for driving the memory controller 1200 . Also, the buffer memory 1220 may buffer data to be used for a program operation when a write request is made. Although the buffer memory 1220 is present in the SSD controller 1200 in FIG. 24 , the present invention is not necessarily limited thereto. The buffer memory may exist separately outside the SSD controller 1200 .

The error correction circuit 1230 calculates an error correction code value of data to be programmed in a write operation, performs error correction on data read in a read operation based on the error correction code value, and performs an error correction in the data recovery operation of the nonvolatile memory device 1100 ), it is possible to correct errors in the recovered data. Although not shown, a code memory for storing code data required to drive the memory controller 1200 may be further included. The code memory may be implemented as a non-volatile memory device.

The host interface 1250 may provide an interface function with an external device. The nonvolatile memory interface 1260 may provide an interface function with the nonvolatile memory device 1100 .

25 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.

Referring to FIG. 25 , the eMMC 2000 may include at least one NAND flash memory device 2100 and a controller 2200 .

The NAND flash memory device 2100 may be implemented as the nonvolatile memory device 30 of FIG. 2B described above. The NAND flash memory device 2100 performs a first memory operation on the first memory block, and when the ready state continues for a reference time or longer after the completion of the first memory operation, in response to a command from the memory controller 200 After the curing operation is performed on at least a portion of the first memory block, a second memory operation is performed on the first memory block to reduce the number of error bits, thereby improving performance.

The memory controller 2200 is connected to the NAND flash memory device 2100 through a plurality of channels. The memory controller 2200 includes at least one controller core 2210 , a host interface 2250 , and a NAND interface 2260 . At least one controller core 2210 controls the overall operation of the eMMC (2000). The controller core 2210 may include a counter, as described with reference to FIG. 2A . The host interface 2250 performs interfacing between the controller 2210 and the host. The NAND interface 2260 interfaces the NAND flash memory device 2100 and the controller 2200 .

In an embodiment, the host interface 2250 may be a parallel interface (eg, an MMC interface). In another embodiment, the host interface 2250 of the eMMC 2000 may be a serial interface (eg, UHS-II, UFS interface).

The eMMC 2000 receives power supply voltages Vcc and Vccq from the host. Here, the first power voltage (Vcc, for example, 3.3V) is provided to the NAND flash memory device 2100 and the NAND interface 2260 , and the second power voltage (Vccq, for example, 1.8V/3.3V) is provided to the controller 2200 . In an embodiment, the eMMC 2000 may optionally receive an external high voltage (Vpp).

26 is a block diagram illustrating a universal flash storage (UFS) according to embodiments of the present invention.

Referring to FIG. 26 , the UFS system 3000 may include a UFS host 3100 , UFS devices 3200 and 3300 , an embedded UFS device 3400 , and a removable UFS card 3500 . The UFS host 3100 may be an application processor of a mobile device. Each of the UFS host 3100 , the UFS devices 3200 and 3300 , the embedded UFS device 3400 , and the removable UFS card 3500 may communicate with external devices through the UFS protocol. At least one of the UFS devices 3200 and 3300 , the embedded UFS device 3400 , and the removable UFS card 3500 may be implemented as the nonvolatile memory device 30 of FIG. 2B . Accordingly, at least one of the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 performs a first memory operation on the first memory block, and after completion of the first memory operation, When the ready state continues for more than a reference time, after performing a curing operation on at least a portion of the first memory block, a second memory operation is performed on the first memory block to reduce the number of error bits. can increase

Meanwhile, the embedded UFS device 3400 and the removable UFS card 3400 may communicate using a protocol other than the UFS protocol. The UFS host 3100 and the removable UFS card 3500 may communicate using various card protocols (eg, UFDs, MMC, secure digital (SD), mini SD, Micro SD, etc.).

27 is a block diagram illustrating a mobile device according to embodiments of the present invention.

Referring to FIG. 27 , the mobile device 4000 includes an application processor 4100 , a communication module 4200 , a display/touch module 4300 , a storage device 4400 , and a mobile RAM 4500 .

The application processor 4100 controls the overall operation of the mobile device 4000 . The communication module 4200 may be implemented to control wired/wireless communication with the outside. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data from a touch panel. The storage device 4400 may be implemented to store user data.

The storage device 4400 may be an eMMC, SSD, or UFS device. The storage device 4400 may be implemented as the nonvolatile memory device 30 of FIG. 2B . Accordingly, the storage device 4400 performs a first memory operation on the first memory block, and when the ready state continues for a reference time or longer after completion of the first memory operation, curing at least a portion of the first memory block After performing the operation, a second memory operation may be performed on the first memory block to reduce the number of error bits, thereby improving performance.

When the state signal RnB indicating the state of the storage device 4400 including the counter 4110 indicates that the ready state of the storage device 4400 continues for more than the reference time, the application processor 4100 performs the curing operation To perform this, a command and an address may be transmitted to the storage device 4400 .

The mobile RAM 4500 may be implemented to temporarily store data necessary for a processing operation of the mobile device 4000 .

A memory device or a storage device according to an embodiment of the present invention may be mounted using various types of packages. In an embodiment, the memory system or storage device according to an embodiment of the present invention is a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In -Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP) , Wafer-Level Processed Stack Package (WSP), etc. can be used to be mounted.

The present invention may be usefully applied to any electronic device having a non-volatile memory device. For example, the present invention relates to a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), and a digital device having a non-volatile memory device. It may be applied to a camera (Digital Camera), a music player (Music Player), a portable game console (Portable Game Console), a navigation system, and the like.

As described above, although described with reference to preferred embodiments of the present invention, those of ordinary skill in the art may vary the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. It will be understood that modifications and changes can be made to

10: non-volatile memory device 100: memory cell array
400: address decoder 460: page buffer circuit
470: data input/output circuit 500: control circuit
600: voltage generator

Claims (20)

A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to a substrate;
the method
performing a first memory operation on a first memory block among the memory blocks; and
When the state signal indicates the ready state of the non-volatile memory device for a reference time or longer after the completion of the first memory operation, the first memory block is formed such that charges are moved in the channel layer of at least one of the vertical strings. A method of operating a non-volatile memory device comprising the step of performing a curing operation on a portion. According to claim 1, wherein each of the plurality of vertical strings
at least one string select transistor coupled to a bit line coupled to the page buffer;
at least one ground select transistor coupled to a common source line; and
and a plurality of cell transistors connected in series between the at least one string select transistor and the at least one ground select transistor to form a channel of the vertical string. The method of claim 2, wherein the curing operation
turning off the at least one string select transistor by applying a ground voltage to a string select line connected to at least one string select transistor of a first vertical string among the plurality of vertical strings;
applying turn-on voltages corresponding to each of the word lines connected to the cell transistors of the first vertical string and the ground select line connected to the ground select transistor, respectively; and
and maintaining a common source line connected to the at least one ground select transistor at a ground voltage. 4. The method of claim 3,
Each of the turn-on voltages has a higher level than threshold voltages of the cell transistors and the ground select transistor, respectively. The method of claim 2, wherein the curing operation
blocking a connection between a bit line connected to a first vertical string among the plurality of vertical strings and a page buffer;
Corresponds to a string select line connected to at least one string select transistor of the first vertical string, word lines connected to cell transistors of the first vertical string, and a ground select line connected to at least one ground select transistor, respectively. applying each of the turn-on voltages; and
and maintaining a common source line connected to the at least one ground select transistor at a ground voltage. 6. The method of claim 5,
Each of the corresponding turn-on voltages has a level higher than threshold voltages of the string select transistor, the cell transistor, and the ground select transistor, respectively. 6. The method of claim 5,
The method of operating a nonvolatile memory device, wherein the curing operation is simultaneously performed on a plurality of vertical strings included in the first memory block. According to claim 1,
The first memory operation is sequentially performed on the memory blocks including the first memory block;
When the memory blocks include at least one bad memory block, the curing operation is simultaneously performed on the remaining memory blocks except for the at least one bad memory block. The method of claim 8, wherein the curing operation
The method of operating a nonvolatile memory device is performed except for the at least one bad memory block based on a comparison between a block address for selecting the memory blocks and a bad block address set including the address of the at least one bad memory block . 10. The method of claim 9,
The bad block address set includes a first bad block address pre-stored in a bad block register of an address decoder connected to the memory blocks before a power-up sequence of the nonvolatile memory device and the bad block address during operation of the nonvolatile memory device. A method of operating a nonvolatile memory device including a second bad block address stored in a block register. According to claim 1,
The method further comprising: performing a second memory operation on at least a portion of the first memory block after completion of the curing operation;
The first memory operation is a program operation performed on at least a portion of the first memory block, and the second memory operation is a read operation performed on at least a portion of the first memory block. . A non-volatile memory device comprising:
a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to a substrate;
a voltage generator that generates wordline voltages based on the control signal;
an address decoder providing the word line voltages to the memory cell array based on an address signal; and
When a first memory operation is performed on a first memory block among the plurality of memory blocks, and a status signal indicates a ready state of the nonvolatile memory device for a reference time or longer after the completion of the first memory operation, an external memory Controlling the voltage generator and the address decoder so that a curing operation for moving charges in a channel layer of at least one of the vertical strings in response to a command from a controller is performed on a part of the first memory block A non-volatile memory device comprising a control circuit. 13. The method of claim 12, wherein each of the plurality of vertical strings
at least one string select transistor coupled to a bit line coupled to the page buffer;
at least one ground select transistor coupled to a common source line; and
and a plurality of cell transistors coupled in series between the at least one string select transistor and the at least one ground select transistor to form a channel of the vertical string. The method of claim 13, wherein when the curing operation is performed
The address decoder
turning off at least one string selection transistor of a first vertical string among the plurality of vertical strings;
applying turn-on voltages corresponding to word lines connected to the cell transistors of the first vertical string and a ground selection line connected to at least one ground selection transistor, respectively;
maintaining a common source line connected to the at least one ground select transistor at a ground voltage;
Each of the turn-on voltages has a higher level than threshold voltages of the cell transistors and the ground select transistor, respectively. The method of claim 13, wherein when the curing operation is performed
the control circuit cuts off a connection between a bit line connected to a first vertical string among the plurality of vertical strings and a page buffer;
The address decoder
Corresponds to a string select line connected to at least one string select transistor of the first vertical string, word lines connected to cell transistors of the first vertical string, and a ground select line connected to at least one ground select transistor, respectively. applying a turn-on voltage to
maintaining a common source line connected to the at least one ground select transistor at a ground voltage;
Each of the turn-on voltages has a level higher than threshold voltages of the string select transistor, the cell transistors, and the ground select transistor, respectively. 13. The method of claim 12, wherein the address decoder comprises:
a bad block address register configured to store an address of at least one bad block among the memory blocks;
an address comparator comparing a block address for selecting two or more of the memory blocks with a bad block address set stored in the bad block address register and outputting a match signal indicating whether the block address matches the bad block address set;
a decoder for decoding the match signal and the block address to provide a plurality of block selection signals; and
a plurality of selection circuits connected to each of the memory blocks and selectively providing turn-on voltages applied from the voltage generator to each of the memory blocks when the curing operation is performed based on the block selection signals Non-volatile memory device. 17. The method of claim 16,
The bad block address set includes a first bad block address pre-stored in the bad block address register before the power-up sequence of the non-volatile memory device and a second bad block address stored in the bad block address register during operation of the non-volatile memory device. A non-volatile memory device including a bad block address. at least one non-volatile memory device; and
a memory controller for controlling the at least one nonvolatile memory device;
the at least one non-volatile memory device
a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of vertical strings extending in a direction perpendicular to a substrate;
a voltage generator that generates wordline voltages based on the control signal;
an address decoder providing the word line voltages to the memory cell array based on an address signal; and
When a first memory operation is performed on a first memory block among the plurality of memory blocks, and a status signal indicates a ready state of the nonvolatile memory device for a reference time or longer after the completion of the first memory operation, the memory controller Controlling the voltage generator and the address decoder so that a curing operation for moving charges in a channel layer of at least one of the vertical strings is performed on a part of the first memory block in response to a command from A memory system including control circuitry. 19. The method of claim 18,
the control circuit includes a status signal generator configured to provide the memory controller with the status signal representing the operating status of the nonvolatile memory device based on at least the command;
the memory controller
a counter for providing a determination signal by comparing the state signal of the ready state with the reference time; and
and a processor configured to generate the command based on the determination signal and a request from a host. 20. The method of claim 19,
When the determination signal indicates that the ready state continues for more than the reference time, the processor transmits a command instructing the curing operation to the nonvolatile memory device.

Images