KR20170029287A - Semiconductor device and method for controlling concentration of carrier the same - Google Patents
Semiconductor device and method for controlling concentration of carrier the same Download PDFInfo
- Publication number
- KR20170029287A KR20170029287A KR1020150126439A KR20150126439A KR20170029287A KR 20170029287 A KR20170029287 A KR 20170029287A KR 1020150126439 A KR1020150126439 A KR 1020150126439A KR 20150126439 A KR20150126439 A KR 20150126439A KR 20170029287 A KR20170029287 A KR 20170029287A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- intrinsic region
- type impurity
- impurity region
- intrinsic
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims description 30
- 239000012535 impurity Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 210000000988 bone and bone Anatomy 0.000 claims description 8
- 230000001965 increasing effect Effects 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 238000005215 recombination Methods 0.000 description 12
- 230000006798 recombination Effects 0.000 description 12
- 239000000969 carrier Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000000470 constituent Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for adjusting a carrier concentration thereof, and more particularly, to a technique for improving the performance of a semiconductor plasma antenna device by increasing a carrier concentration in an intrinsic region of a pin diode.
Generally, in order to provide a next generation mobile communication service with a very high capacity and high capacity, an active array antenna is used in which beams are formed by adaptively controlling a plurality of antennas. Since the array antenna system generally uses a metal-based active array antenna having a constant interval, the size of the array antenna system is greatly increased compared with that of a single antenna, and detailed adjustment (phase shift and error correction) Power consumption and cost increase.
In order to overcome the drawbacks of such an array antenna system, a semiconductor plasma antenna technology is attracting attention. Semiconductor plasma antenna technology is to construct an antenna using a semiconductor plasma, which is a collection of charges generated when an electrical or optical stimulus is applied to a semiconductor substrate. That is, a technology in which a plurality of diode cells are formed on a semiconductor substrate, and a cell (a cell having conductivity similar to a conductor) changed to an activated state by applying a voltage to a desired cell is utilized as an antenna element.
Such a semiconductor plasma antenna forms a two-dimensional array of PIN diodes on a semiconductor substrate, and then adjusts the position of the pattern by adjusting an electrical signal, so that a beam, which can freely adjust the direction, width, Forming antenna.
However, in the case of a conventional semiconductor plasma antenna, it is necessary to develop a technology capable of increasing the carrier concentration as the antenna performance is determined by the concentration of the plasma (carrier) formed in the intrinsic region of the pin diode.
An embodiment of the present invention is to provide a semiconductor device capable of enhancing the carrier concentration in an intrinsic region of a semiconductor device and improving the performance of the semiconductor plasma antenna device, and a method for adjusting the carrier concentration thereof.
The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems which are not mentioned can be understood by those skilled in the art from the following description.
A semiconductor device according to an embodiment of the present invention includes: a buried oxide film buried in a semiconductor substrate; An intrinsic region formed on the buried oxide film including a quantum well; And a P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region.
The intrinsic region may include a first intrinsic region formed on the buried oxide film; And a second intrinsic region formed on the first intrinsic region to expose a surface thereof.
In addition, the quantum well may be formed between the first intrinsic region and the second intrinsic region.
In addition, the quantum well may be formed in the intrinsic region between the P-type impurity region and the N-type impurity region.
Also, a channel may be formed in the quantum well.
In addition, the quantum well may be formed on the buried oxide film, and the intrinsic region may be formed on the quantum well.
Further, the semiconductor device may be a pin diode.
A semiconductor device according to another embodiment of the present invention includes: a buried oxide film buried in a semiconductor substrate; An intrinsic region formed on the buried oxide film and having a dog bone structure; And a P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region.
The intrinsic region having the dog bone structure may be formed such that the center portion of the intrinsic region has a narrower width than the p-type impurity region and the intrinsic region on the side of the n-type impurity region.
A semiconductor device according to another embodiment of the present invention includes: a buried oxide film buried in a semiconductor substrate; An intrinsic region formed on the buried oxide film; A P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region, and the intrinsic region may be formed to have a predetermined thickness or less.
The intrinsic region may be formed to a thickness of 100 nm or less.
In addition, a channel may be formed in the entire intrinsic region.
A semiconductor device according to another embodiment of the present invention includes: a buried oxide film buried in a semiconductor substrate; An intrinsic region formed on the buried oxide film; A P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region; The semiconductor substrate, the buried oxide film, and the back gate formed on the rear surface of the intrinsic region.
A first channel formed on the back gate; And a second channel formed on the intrinsic region upper surface.
The semiconductor device may further include an oxide film surrounding the back gate.
A method of adjusting a carrier concentration of a semiconductor device according to an embodiment of the present invention includes: forming a channel on a semiconductor substrate; Type impurity region and a second-type impurity region, the first-type impurity region being connected to the ground voltage terminal, the second-type impurity region being connected to the ground voltage terminal, And the voltage applied to the impurity region is variably controlled to adjust the carrier concentration of the intrinsic region.
The first-type impurity region may be an N + impurity region, and the second-type impurity region may be a P + impurity region.
The present technique can increase the carrier concentration of the intrinsic region of the semiconductor device to improve the performance of the semiconductor antenna device.
1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
2 is a plan view of a semiconductor plasma antenna device in which semiconductor devices according to a first embodiment of the present invention are arranged.
3 is a diagram showing a method of increasing a carrier concentration of a semiconductor device according to the first embodiment of the present invention.
4A is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment of the present invention.
4B is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment of the present invention.
5 is a view for explaining a method of forming a semiconductor device according to a second embodiment of the present invention.
6 is an energy band diagram of a semiconductor device by a semiconductor device according to a second embodiment of the present invention.
7A is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.
7B is a plan view of a semiconductor device according to a fourth embodiment of the present invention.
8A to 8D are process drawings showing a method of forming a semiconductor device according to a fourth embodiment of the present invention.
9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.
10 is a graph showing characteristics of a semiconductor device according to a fifth embodiment of the present invention.
11 is a cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment of the present invention.
Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals whenever possible, even if they are shown in different drawings. In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the difference that the embodiments of the present invention are not conclusive.
In describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. Also, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.
The present invention relates to a pin diode which is a semiconductor device applied to a semiconductor plasma antenna device. Normally, a carrier concentration of an intrinsic semiconductor element is 10 19 / cm 3 or more, and an antenna efficiency of 90% or more can be obtained. The carrier concentration in the intrinsic region of such a semiconductor device is dependent on the lifetime of electrons and holes due to the impurity concentration in the intrinsic region, the carrier confinement performance according to the structure of the unit cell, the surface recombination in the sidewall of the diode, surface recombination characteristics, and the like.
The present invention discloses a structure and a method for increasing a carrier concentration of an intrinsic region applied to a semiconductor plasma antenna apparatus for improving the performance of the semiconductor plasma antenna apparatus.
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 11. FIG.
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a plan view of a semiconductor plasma antenna device in which semiconductor devices according to a first embodiment of the present invention are arranged. Hereinafter, a PIN diode will be described as a semiconductor device in the present invention.
1, a semiconductor device according to a first embodiment of the present invention includes a buried oxide (BOX) buried in a
At this time, the
Referring to FIG. 2, when a plurality of semiconductor elements are arranged to form a semiconductor plasma antenna device, a plurality of
The semiconductor device according to the first embodiment of the present invention can achieve a carrier concentration of the order of 10 < 17 > / cm < 3 >. In order to further increase the carrier concentration, as shown in Fig. 3, the carrier concentration can be adjusted by adjusting the voltage applied across the semiconductor element. That is, the present invention can adjust the carrier concentration in the
Referring to FIG. 3, if the semiconductor device according to the first embodiment of the present invention is composed of a two-dimensional array of an active matrix structure, a voltage applied across the semiconductor device is determined by selecting a Vsel value and a Vdata value Can be determined accordingly. At this time, both values of Vsel and Vdata use the same value.
At this time, in order to appropriately adjust the carrier concentration of the
This variable voltage value can be implemented through a DC-DC converter (not shown) and a regulator circuit (not shown). By controlling the carrier concentration through such variable voltage, the unit semiconductor element cell can operate under the optimum power consumption operating condition.
Although the semiconductor device according to the first embodiment of the present invention discloses an example of using an SOI substrate, it is not only possible to use a general silicon substrate, but also to physically or chemically etch the backside region of the silicon substrate A rear electrode can be formed and used.
As described above, the semiconductor device according to the first embodiment of the present invention can increase the carrier concentration of the
In the present invention, the technique of adjusting the carrier concentration by the variable forward voltage is applied to only the first embodiment of the present invention, but it can be applied to all the embodiments of the present invention to be described later.
4A is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment of the present invention.
The semiconductor device according to the second embodiment of the present invention includes a buried oxide (BOX) buried in a
The
In addition, the carrier plasma generated in the operation of the semiconductor device is not directly radiated into the air like the semiconductor device according to the first embodiment of the present invention shown in FIG. 1, but the
4A, the semiconductor device according to the second embodiment of the present invention discloses the structure of the
5 is a view for explaining a method of forming a semiconductor device according to a second embodiment of the present invention.
Referring to FIG. 5, a heterojunction structure of silicon (Si) and
Referring to FIG. 6, which is an energy band diagram of a semiconductor device according to a second embodiment of the present invention, conduction and a valence band in a silicon (strained-Si) region are bent, carrier confinement can be seen.
Further, when a forward voltage is applied, more carriers are formed in the inversion layer, so that the turn-on voltage of the semiconductor device (PIN diode) can be lowered, thereby forming a PIN unit cell operable at a low voltage.
As described above, the semiconductor device according to the second embodiment of the present invention can further restrain the carrier through the quantum well, thereby increasing the carrier concentration and reducing the surface recombination. Therefore, an improved intrinsic region carrier concentration can be obtained in the PIN diode .
FIG. 7A is a cross-sectional view illustrating a structure of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 7B is a plan view of a semiconductor device according to the fourth embodiment of the present invention.
7A and 7B, a semiconductor device according to a fourth embodiment of the present invention includes a buried
In the semiconductor device according to the first embodiment of the present invention, a trench is formed and isolated for isolation of a unit cell, and then an oxide film is formed in the trench by inserting an isolation material to isolate each unit cell. . However, this device separation technique can accelerate the recombination of carriers by forming tens of thousands of dangling bonds and defects on the intrinsic region side walls.
Thus, the semiconductor device according to the fourth embodiment of the present invention can reduce the surface recombination and improve the reservoir size by forming the
Hereinafter, a method for forming a semiconductor device according to a fourth embodiment of the present invention will be described in detail with reference to FIGS. 8A to 8D.
Referring to FIG. 8A, a fin unit cell 400 is formed in a
Referring to FIG. 8B, a
Referring to FIG. 8C, a thermal oxidation process is performed on the
Next, referring to FIG. 8D, hydrogen annealing may be performed to remove defects formed on the surface, and an oxide film (not shown) may be additionally deposited.
As such, the silicon surface of
9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.
The semiconductor device according to the fifth embodiment of the present invention forms a very thin
9, the semiconductor device according to the fifth embodiment of the present invention includes a buried
In the case of the semiconductor device according to the first embodiment of the present invention described above with reference to FIG. 1, the channel is formed on the surface of the
When the
In addition, the semiconductor device according to the fifth embodiment of the present invention can reduce the number of carriers lost through the channel bottom of the
11 is a cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment of the present invention.
The semiconductor device according to the sixth embodiment of the present invention has a structure capable of adjusting the concentration of the channel carriers by the back gate.
The semiconductor device according to the sixth embodiment of the present invention includes a
The
On the other hand, the formation of the
On the other hand, if the rward bias is increased in the intrinsic region in order to control the concentration of the channel in the semiconductor device (PIN diode), the concentration of the carrier increases, but the point at which the concentration is not increased any more occurs. This phenomenon is caused by the recombination of electrons and holes at a high carrier concentration, which means that by adjusting the voltage across the diode, the carrier concentration in the intrinsic region can not be maximized.
Therefore, in the sixth embodiment of the present invention, the backgate is disposed on the back surface of the PIN diode to adjust the concentration of the carrier, so that the concentration can be appropriately adjusted and the power consumption can be improved.
As described above, the present invention improves the performance of a semiconductor plasma antenna device by changing the structure of a semiconductor device (pin diode) used in a semiconductor plasma antenna device or increasing the carrier concentration of an intrinsic region of a semiconductor device through control by a control voltage . In addition, the semiconductor device of the present invention is not limited to the antenna device and can be applied to various devices.
The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention.
Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.
Claims (17)
An intrinsic region formed on the buried oxide film including a quantum well;
A P-type impurity region and an N-type impurity region which are formed at a predetermined distance from the intrinsic region,
≪ / RTI >
The intrinsic region
A first intrinsic region formed on the buried oxide film;
A second intrinsic region formed on the first intrinsic region,
And a semiconductor layer formed on the semiconductor substrate.
Wherein the quantum well is formed between the first intrinsic region and the second intrinsic region.
And the quantum well is formed between the P-type impurity region and the N-type impurity region in the intrinsic region.
And a channel is formed in the quantum well.
Wherein the quantum well is formed on the buried oxide film,
Wherein the intrinsic region is formed on the quantum well.
Wherein the semiconductor element is a pin diode.
An intrinsic region formed on the buried oxide film and having a dog bone structure;
A P-type impurity region and an N-type impurity region which are formed at a predetermined distance from the intrinsic region,
And a semiconductor layer formed on the semiconductor substrate.
Wherein the intrinsic region having the dog bone structure comprises:
And a central portion of the intrinsic region is formed to have a narrower width than the p-type impurity region and the intrinsic region on the side of the n-type impurity region.
An intrinsic region formed on the buried oxide film;
A P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region,
Wherein the intrinsic region is formed to have a thickness equal to or smaller than a predetermined thickness.
Wherein the intrinsic region is formed to a thickness of 100 nm or less.
And a channel is formed in the entire intrinsic region.
An intrinsic region formed on the buried oxide film;
A P-type impurity region and an N-type impurity region formed at a predetermined distance from the intrinsic region;
The buried oxide film, the back gate formed on the back surface of the intrinsic region,
The semiconductor device comprising: a semiconductor substrate;
A first channel formed on the back gate; And
And a second channel formed on the upper surface of the intrinsic region.
Further comprising an oxide film surrounding the back gate.
Type impurity region is connected to the ground voltage terminal,
Wherein the carrier concentration of the intrinsic region is controlled by variably controlling the voltage applied to the 2-type impurity region.
The first-type impurity region is an N + impurity region,
And the second-type impurity region is a P + impurity region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150126439A KR20170029287A (en) | 2015-09-07 | 2015-09-07 | Semiconductor device and method for controlling concentration of carrier the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150126439A KR20170029287A (en) | 2015-09-07 | 2015-09-07 | Semiconductor device and method for controlling concentration of carrier the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20170029287A true KR20170029287A (en) | 2017-03-15 |
Family
ID=58403300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020150126439A KR20170029287A (en) | 2015-09-07 | 2015-09-07 | Semiconductor device and method for controlling concentration of carrier the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20170029287A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7109124B2 (en) | 2001-12-21 | 2006-09-19 | Plasma Antennas Ltd | Solid state plasma antenna |
-
2015
- 2015-09-07 KR KR1020150126439A patent/KR20170029287A/en unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7109124B2 (en) | 2001-12-21 | 2006-09-19 | Plasma Antennas Ltd | Solid state plasma antenna |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102286671B1 (en) | Thermionically-overdriven tunnel fets and methods of fabricating the same | |
| US10388734B2 (en) | Insulated gate bipolar transistor device having a fin structure | |
| KR101745776B1 (en) | Power Semiconductor Device | |
| US9620499B2 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| US8735227B2 (en) | Semiconductor devices with minimized current flow differences and methods of same | |
| US10587233B2 (en) | High power RF switches using multiple optimized transistors and methods for fabricating same | |
| KR102544772B1 (en) | Amplifiers including tunable tunnel field effect transistor pseudo resistors and related devices | |
| KR20170124639A (en) | Process and structures for fabrication of solar cells | |
| US8541791B2 (en) | Source of photons resulting from a recombination of localized excitons | |
| KR20160119410A (en) | Semiconductor Structure having a Junction Field Effect Transistor and a High Voltage Transistor and Method for Manufacturing the same | |
| CN112234095A (en) | Power MOSFET device with enhanced cell design | |
| CN105405873A (en) | Semiconductor device and manufacturing method thereof | |
| US20110156093A1 (en) | High-voltage power transistor using soi technology | |
| KR20170029287A (en) | Semiconductor device and method for controlling concentration of carrier the same | |
| KR20140080741A (en) | Asymmetric two-terminal biristor and fabrication method | |
| US9252292B2 (en) | Semiconductor device and a method for forming a semiconductor device | |
| EP1820217A2 (en) | Insulated gate field effect transistors | |
| CN110047931B (en) | Silicon carbide planar vertical field effect transistor and manufacturing method thereof | |
| EP0878849A2 (en) | Power diode | |
| CN114335166B (en) | High electron mobility transistor HEMT device, wafer, packaging device and electronic equipment | |
| US20230246027A1 (en) | Vertical fin-based field effect transistor (finfet) with neutralized fin tips | |
| CN106684084B (en) | FET-bipolar transistor combination and switch comprising the same | |
| KR20230104739A (en) | Power Transistors with Soft Recovery Body Diodes | |
| KR101248658B1 (en) | Insulated gate bipolar transistor | |
| US9153675B2 (en) | Power semiconductor and manufacturing method thereof |