KR20170024781A - Controller integrated image processing apparatus for reducing the amount of calculation - Google Patents
Controller integrated image processing apparatus for reducing the amount of calculation Download PDFInfo
- Publication number
- KR20170024781A KR20170024781A KR1020150120243A KR20150120243A KR20170024781A KR 20170024781 A KR20170024781 A KR 20170024781A KR 1020150120243 A KR1020150120243 A KR 1020150120243A KR 20150120243 A KR20150120243 A KR 20150120243A KR 20170024781 A KR20170024781 A KR 20170024781A
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- South Korea
- Prior art keywords
- image processing
- controller
- mcu
- reducing
- processing apparatus
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
- H04N21/462—Content or additional data management, e.g. creating a master electronic program guide from data received from the Internet and a Head-end, controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Databases & Information Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Image Processing (AREA)
Abstract
Description
The present invention relates to an image processing apparatus, and more particularly, to a controller integrated image processing apparatus for reducing the amount of MCU computation that reduces the resources used for display control and improves image processing performance.
2. Description of the Related Art Generally, a display device is an apparatus that receives an image or image information and displays an image or an image. The display device includes a case forming an external shape of the display device, a display module installed to be exposed through an opening formed in the front surface of the case, and image and image information input / And a display unit for displaying an image on the display unit.
The image processing board is provided with various types of input terminals for receiving various kinds of information such as image, video and audio.
Image data processing on the image processing board requires processing after compression because the image data is very large in size compared to other media data. As the compression method, it is required to perform processing such as wavelet transformation, M-JPEG, And the image processing board consists of an FPGA, a DSP chip, a memory, and a TCP / IP chip. The FPGA includes a programmable logic element and a semiconductor including a programmable internal line And programmable logic elements replicate and program the functions of basic logic gates such as AND, OR, XOR, NOT, and more complex decoders or the combination of computational functions.
Most FPGAs contain a memory element with a simple flip-flop or a more complete block of memory for the programmable logic element.
The DSP chip is a chip designed in a structure for professionally processing signal processing.
In the present embedding situation, image processing is performed using MCU.
However, if video input / output is performed through the MCU, the LCD controller should be controlled in the case of LCD, and the camera controller in case of the camera. However, the supporting resolution is very small in the control process, and 89% of the MCU is occupied only in the video input / output .
Accordingly, there is a problem that control or sensor measurement, which is an original function of the MCU, can not be performed in addition to video input / output.
At the same time, mathematical calculations are also necessary for image processing, and MCUs are also consumed to obtain data.
An object of the present invention is to provide a controller integrated image processing apparatus for reducing the amount of MCU computation for reducing the resources used for display control and improving image processing performance, .
An object of the present invention is to provide a controller integrated image processing apparatus for reducing the amount of MCU computation, including a one-chip type image processing board integrated with controllers to reduce the load of the MCU of the image processing apparatus.
It is an object of the present invention to provide a controller integrated image processing apparatus for reducing the amount of MCU computation, including a display unit capable of integrating a controller of a mandatory configuration such as a camera, a display, .
The present invention relates to an apparatus and a method for transmitting / receiving data between devices using an AMBA (Advanced Microcontroller Bus Architecture) so that the MCU can be connected to the MCU, and at the same time, RGB 565 images are transmitted and displayed on a display And an object of the present invention is to provide a controller integrated image processing apparatus for reducing the amount of MCU operation in which an operation control is performed in an FPGA (Field Programmable Gate Array).
The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.
According to another aspect of the present invention, there is provided a controller integrated image processing apparatus for reducing the amount of MCU operation, comprising: an image pickup means, a display means, and a storage means on an image processing board having an MCU; An SRAM controller for controlling the display means, and a camera controller for controlling the image pickup means, which are integrally provided in a one-chip form and include an I2C connector for supporting MCU communication.
Here, it is assumed that a clock is controlled by transmitting / receiving data between devices using an AMBA (Advanced Microcontroller Bus Architecture) so as to be able to connect with an MCU, and an RGB 565 image is transmitted and displayed on a display Control is performed in an FPGA (Field Programmable Gate Array).
The controller integrated image processing apparatus for reducing the MCU operation amount according to the present invention has the following effects.
First, controller integrated image processing reduces the resources used for display control and improves image processing performance.
Second, a load on the MCU of the image processing apparatus can be reduced by providing a one-chip image processing board integrated with controllers.
Third, the MCU calculation amount can be reduced by including a display unit capable of integrating a controller of essential configuration such as a camera, a display, and a storage device on a video processing board and reproducing an image immediately.
1 is a block diagram of a controller integrated image processing apparatus for reducing the amount of MCU operation according to the present invention.
2 is a block diagram of a controller integrated image processing apparatus for reducing the amount of MCU operation according to the present invention.
3 is a block diagram illustrating an example of a controller integrated image processing apparatus for reducing the amount of MCU operation according to the present invention.
Hereinafter, a preferred embodiment of the controller integrated image processing apparatus for reducing the MCU operation amount according to the present invention will be described in detail.
The features and advantages of the controller integrated image processing apparatus for reducing the MCU operation amount according to the present invention will be apparent from the following detailed description of each embodiment.
FIG. 1 is a basic block diagram of a controller integrated image processing apparatus for reducing an MCU operation amount according to the present invention, and FIG. 2 is a block diagram of a controller integrated image processing apparatus for reducing an MCU operation amount according to the present invention.
FIG. 3 is a photograph showing an example of a controller integrated image processing apparatus for reducing an MCU operation amount according to the present invention.
The present invention includes a one-chip type image processing board in which controllers are integrated to reduce the load of the MCU of the image processing apparatus.
In particular, the present invention relates to a method and apparatus for transmitting / receiving data between devices using an AMBA (Advanced Microcontroller Bus Architecture) to enable connection with an MCU, And an operation control for displaying is performed in an FPGA (Field Programmable Gate Array).
1 and 2, the controller integrated image processing apparatus for reducing the MCU operation amount according to the present invention includes an
In order to reduce the resources used for the display control and to improve the image processing performance, the controller integrated image processing apparatus for reducing the MCU calculation amount according to the present invention integrates (1) a controller of essential configuration such as a camera, a display, and a storage device , (2) a display that can instantly reproduce images, (3) clock control by transmitting / receiving data between devices using AMBA to enable connection with MCU, and (4) The RGB 565 video is transferred to the display and displayed on the display.
In the embodiment of the present invention as shown in FIG. 3, a controller for controlling cameras, LCDs, and SRAMs, which are devices necessary for image processing in the Cyclone3 chip environment, which is an FPGA developed by Altera, is integrated, The board is assembled directly.
In addition, the SRAM for storing the image and the LCD for displaying the image are mounted on the board so that various devices can be controlled by only the board.
In addition, in order to connect with MCU, AMBA is used to send / receive data between devices, and clock control is also performed. In addition, MCU can process RGB 565 image and display it on LCD. The load was reduced as much as possible.
According to the present invention, the controller integrated image processing device for decreasing the MCU calculation amount sends image data to the MCU without using the device control, so that only the pure operation necessary for the image processing can be performed by the MCU, Will decrease.
As a result, the video input / output process is one-chip using the FPGA, so that the load and data flow for device control can be reduced and the speed can be improved.
By integrating so many things in one chip, the cost and size to implement the original technology can be greatly reduced, and CCTV can be made smaller and cost-effective even when CCTV is manufactured .
As described above, it will be understood that the present invention is implemented in a modified form without departing from the essential characteristics of the present invention.
It is therefore to be understood that the specified embodiments are to be considered in an illustrative rather than a restrictive sense and that the scope of the invention is indicated by the appended claims rather than by the foregoing description and that all such differences falling within the scope of equivalents thereof are intended to be embraced therein It should be interpreted.
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23.
Claims (2)
An LCD controller for controlling the display means, an SRAM controller for controlling the display means, and a camera controller for controlling the image pickup means, all of which are integrated into one chip, and an I2C connector for supporting MCU communication Controller integrated image processing device for reducing the MCU operation amount.
And an RGB (565) image is transmitted and displayed on a display so that the MCU can process the image. The FPGA (Field Programmable Gate Array) controls the operation of the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150120243A KR20170024781A (en) | 2015-08-26 | 2015-08-26 | Controller integrated image processing apparatus for reducing the amount of calculation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150120243A KR20170024781A (en) | 2015-08-26 | 2015-08-26 | Controller integrated image processing apparatus for reducing the amount of calculation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20170024781A true KR20170024781A (en) | 2017-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020150120243A KR20170024781A (en) | 2015-08-26 | 2015-08-26 | Controller integrated image processing apparatus for reducing the amount of calculation |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20170024781A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120014521A (en) | 2010-08-09 | 2012-02-17 | 삼성전자주식회사 | Image processing board and display apparatus |
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- 2015-08-26 KR KR1020150120243A patent/KR20170024781A/en unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120014521A (en) | 2010-08-09 | 2012-02-17 | 삼성전자주식회사 | Image processing board and display apparatus |
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