KR20170016673A - Method of recuding contact resistance of mos-fet - Google Patents

Method of recuding contact resistance of mos-fet Download PDF

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KR20170016673A
KR20170016673A KR1020150110063A KR20150110063A KR20170016673A KR 20170016673 A KR20170016673 A KR 20170016673A KR 1020150110063 A KR1020150110063 A KR 1020150110063A KR 20150110063 A KR20150110063 A KR 20150110063A KR 20170016673 A KR20170016673 A KR 20170016673A
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contact
gallium arsenide
nickel
indium gallium
tellurium
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KR1020150110063A
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KR101749599B1 (en
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이희덕
이맹
김제영
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충남대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/18—Selenium or tellurium only, apart from doping materials or other impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10337—Indium gallium arsenide [InGaAs]

Abstract

The present invention relates to a technique for reducing the contact resistance of a contact of a MOSFET in the formation of tellurium-nickel-indium indium gallium arsenide.
More specifically, the contact of the present invention is obtained by laminating a tellurium layer and a nickel layer on the source and drain regions of a substrate on which indium gallium arsenide is stacked, and heat-treating the same. The contact resistance of the contact according to embodiments of the present invention is significantly lower than the contact formed with nickel-indium indium gallium arsenide.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a MOS FET,

More particularly, the present invention relates to a method for forming a contact in a process of manufacturing a highly integrated MOSFET (MOS-FET). More specifically, a contact is formed by laminating tellurium and nickel, The method comprising:

With the progress of high integration of MOSFETs, the conventional semiconductor process, that is, the semiconductor process using silicon, is reaching the limit of miniaturization. To overcome these limitations, research is underway to replace conventional silicon substrates with various materials.

Among them, indium gallium arsenide (InGaAs) belonging to the III-V compound is attracting attention as a promising substrate material. Here, a single metal or an alloy is generally laminated on an electrode of a transistor manufactured using indium gallium arsenide as a substrate. The stacked metal layer is called " contact " because it serves to electrically connect the electrodes of the transistor to an external power source.

At this time, if the resistance at the contact (hereinafter referred to as " contact resistance ") is high, the reaction of the transistor is slowed and the performance is deteriorated. Therefore, in order to realize high performance of a transistor manufactured using indium gallium arsenide as a substrate, it is necessary to further reduce the contact resistance.

Korean Patent Publication No. 2004-0059930 (Jul. 2004)

SUMMARY OF THE INVENTION The present invention provides a method for reducing the contact resistance of a contact formed on an indium gallium arsenide substrate.

According to an aspect of the present invention, there is provided a method of reducing a contact resistance of a MOSFET, comprising: forming a source electrode, a drain electrode, and a gate electrode on an indium gallium arsenide (InGaAs) substrate; Laminating a nickel layer on the tellurium layer, heat treating the indium gallium arsenide (InGaAs) substrate on which the tellurium layer and the nickel layer are stacked, and heat treating the source electrode and the indium gallium arsenide substrate through the heat treatment, And forming a contact on each of the drain electrodes.

Here, the tellurium layer and the nickel layer are laminated by a sputtering process.

Here, the tellurium layer is laminated first, and then the nickel layer is laminated.

Here, the rapid thermal annealing is performed at a temperature ranging from 250 ° C to 330 ° C.

The contact resistance of the contact according to the method for reducing the contact resistance of the MOSFET using the tellurium-nickel-indium gallium arsenide according to the embodiment of the present invention is significantly lower than the contact resistance of the conventional contact.

1A to 1D are cross-sectional views illustrating a process of forming source, drain, and gate electrodes in a method of reducing contact resistance of a MOSFET using tellurium-nickel-indium gallium arsenide according to an embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views illustrating a process of manufacturing a contact in a method of reducing contact resistance of a MOSFET using tellurium-nickel-indium gallium arsenide according to an embodiment of the present invention.
3 is a graph showing a change in a current value of a contact according to a thickness of a tellurium layer according to an embodiment of the present invention.
4 is a graph comparing the total resistance of a contact according to an embodiment of the present invention and the total resistance of a contact formed according to a conventional method.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention.

The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, a method for reducing contact resistance of a MOSFET using tellurium-nickel-indium gallium arsenide according to an embodiment of the present invention will be described in detail with reference to the drawings.

Prior to describing the embodiment of the present invention, the term " substrate 110 " used below is used in the same sense as " substrate on which indium gallium arsenide is laminated " Is used.

1A to 1D are cross-sectional views illustrating a process of forming source, drain, and gate electrodes in a method of reducing contact resistance of a MOSFET using tellurium-nickel-indium gallium arsenide according to an embodiment of the present invention.

As shown in FIGS. 1A and 1B, first, a gate insulating layer 121 is stacked on a substrate 110. Here, the substrate 110 is obtained by epitaxially growing an indium gallium arsenide (InGaAs) layer on a silicon substrate. That is, the substrate 110 is made of indium gallium arsenide (InGaAs). Hereinafter, the substrate 110 is used in combination with the indium gallium arsenide substrate 110.

The reason why the indium gallium arsenide substrate 110 is used as a MOSFET substrate in the present invention is as follows.

Conventionally, MOSFETs have been fabricated using Silicon substrate. However, due to the continuous development of high integration of semiconductor devices, they have come to the limit of miniaturization. To overcome these limitations, it is necessary to fabricate a MOSFET with a higher mobility than conventional silicon. Indium gallium arsenide is an example of a III-V compound that has emerged as a promising high mobility semiconductor material. Since indium gallium arsenide is more expensive than silicon, a small amount of indium gallium arsenide is suitable for mass production in the future. In addition, it is preferable to epitaxially grow indium gallium arsenide on a silicon substrate and use it as a substrate of a MOSFET in order to fabricate the silicon-based semiconductor process equipment which has been used previously.

The substrate 110 according to the embodiment of the present invention preferably uses an indium gallium arsenide layer stacked with 150 nanometers.

On the other hand, it is preferable that the gate insulating film 121 is formed by ALD (atomic layer deposition) method, for example, a material having a high dielectric constant, for example, aluminum oxide (Al 2 O 3), which is an oxide of a metal.

The gate electrode layer 122, which is formed on the gate insulating layer 121, is preferably formed of a metal. For example, the gate electrode layer 122 may be formed by depositing aluminum or titanium.

1B, the gate insulator 121 and the gate electrode film 122 are stacked on the entire surface of the indium gallium arsenide substrate 110 to form the gate electrode 120.

1C, a region for forming the source 131 and the drain 132 is formed on the substrate 110 having the gate electrode 120 stacked thereon through a lithography process using a mask. More specifically, the gate electrode 120 is removed in some regions A and B of the substrate 110 on which the source 131 and the drain 132 are to be formed. Here, the method of removing some of the gate electrodes 120 can be realized by dry etching or wet etching.

When the gate electrode 120 is partially removed by an etching process, portions A and B of the substrate 110 are exposed. An ion is injected into the exposed portions A and B to provide an n-type carrier. 1D, silicon is implanted into the regions A and B of the indium gallium arsenide substrate exposed by using the mask to the source 131 and the drain 132, (n-type) carrier.

Hereinafter, a process of forming a contact in the source region 131 and the drain region 132 will be described.

A contact is required on the source 131 and the drain 132 to apply power from the outside to the source 131 and the drain 132 formed on the substrate 110. [ Here, the contact may be formed by laminating a single metal or an alloy, and in the present invention, a contact formed of an alloy will be described intensively.

The above-mentioned alloy contact is largely formed in two ways.

Specifically, a pure single metal is deposited on the source 131 and the drain 132, heat treated to form an alloy contact, or an alloy made by combining metals or metals and other kinds of elements is deposited to form an alloy contact. Examples of the former method include a method of laminating nickel or titanium (Ti) and heat treatment, and the latter method is a method of laminating nitride such as tantalum nitride (TaN) and titanium nitride (TiN).

The nitride contact can selectively form a contact only in the region of the source 131 and the drain 132 requiring a contact. On the other hand, the alloy contact can be formed in a self-aligning manner without a mask.

Metal-indium gallium arsenide alloy contacts formed of nickel and titanium have an advantage that a contact formed of a nitride can not have, but the value of the contact resistance is not sufficiently low. The method of reducing the contact resistance of a MOSFET according to an embodiment of the present invention solves this problem.

Hereinafter, a method of reducing contact resistance of a MOSFET according to an embodiment of the present invention will be described.

FIGS. 2A through 2C are cross-sectional views illustrating a process for fabricating a contact formed of tellurium-nickel-indium gallium arsenide according to an embodiment of the present invention.

 2A, tellurium layers 141 and 142 are deposited on the source and drain regions 131 and 132 formed on the indium gallium arsenide substrate 110, respectively.

Nickel layers 143 and 144 are then deposited on the tellurium layers 141 and 142, respectively, as shown in FIG. 2B.

The lamination of the tellurium layers 141 and 142 and the nickel layers 143 and 144 can be realized by processes such as radio frequency (RF) sputtering, physical vapor deposition (PVD) or electron beam. In this embodiment, the tellurium layers 141 and 142 and the nickel layers 143 and 144 are laminated using a radio frequency (RF) sputtering process. Here, in the sputtering process, a tellurium layer is first deposited to a thickness of 1 to 15 nanometers in an inert gas (argon (Ar)) atmosphere, and then a nickel layer is deposited thereon to a thickness of 15 to 40 nanometers.

Next, as shown in FIG. 2C, the substrate 110 on which the tellurium layers 141 and 142 and the nickel layers 143 and 144 are laminated is heat-treated.

When the heat treatment is carried out, the tellurium layers 141 and 142, the nickel layers 143 and 144, and the indium gallium arsenide layers constituting the substrate 110 react with each other to form tellurium Nickel-indium gallium arsenide alloys 151 and 152 are formed to make the contact of the transistor.

  Here, since the tellurium, nickel and indium gallium arsenide layers are consumed in the process of reacting with each other, the thickness of the nickel layer is determined by the thickness of the indium gallium arsenide layer. At this time, when the nickel layer and the indium gallium arsenide layer have a similar thickness, the indium gallium arsenide layer is consumed in the heat treatment process. Therefore, it is preferable that the nickel layer is laminated thinner than the indium gallium arsenide layer. For example, when the indium gallium arsenide layer has a thickness of 150 nanometers, the nickel layer preferably has a thickness of about 50 nanometers.

The decrease of the resistance of the contact according to the embodiment of the present invention can be judged from the decrease of the current value. Therefore, the decrease of the resistance value of the contact according to the embodiment of the present invention can be determined as the current value of the contact.

3 is a graph showing a change in a current value of a contact according to a thickness of a tellurium layer according to an embodiment of the present invention.

Here, since it is necessary to determine whether the current density of the contact obtained by using the tellurium-nickel-indium gallium arsenide alloy is improved, the current of the contact formed of the nickel-indium gallium arsenide alloy Values are displayed in the same drawing.

As shown in FIG. 3, when the thickness of the tellurium layer and the time of heat treatment are changed, the current value of the contact changes accordingly.

Specifically, the current value of the contact obtained by laminating 30 nanometers of nickel without tellurium and annealing for 30 seconds is a current value of a contact obtained by laminating 30 nanometers of nickel to 5 nanometers of tellurium and annealing for 30 seconds . That is, the contact resistance of the latter using tellurium is low.

The current value of the contact obtained by laminating 30 nm of nickel to 5 nm of tellurium and annealing for 30 seconds was obtained by laminating 30 nm of nickel on 11 nm of tellurium and heat treatment for 30 seconds, . That is, the contact resistance of electrons using a 5 nm-thick tellurium layer is smaller than that of the latter using a 11-nm-thick tellurium layer.

Here, although the current value of the obtained contact is improved by laminating 30 nanometers of nickel to 11 nanometers of tellurium and increasing the time of 30 seconds by 120 seconds, the contact current obtained by heat treatment of 5 nanometers of tellurium for 30 seconds, Value.

Consequently, it can be seen that the thickness of the tellurium layer is preferably 5 nanometers when forming the contact.

Meanwhile, it is preferable that the heat treatment of the transistor is performed for 10 to 150 seconds within a range of 250 ° C to 330 ° C by rapid thermal annealing. The reason for choosing between 250 ° C and 330 ° C is because the temperature range in which nickel and indium gallium arsenide can form an alloy is 250 ° C to 330 ° C.

The resistance value of the tellurium-nickel-indium gallium arsenide alloy contact according to the present invention is lower than that of the conventional contact. Now, the contact formed by the nickel-indium gallium arsenide alloy in the conventional contact will be compared with the resistance of the contact of the present invention to see the difference in the resistance value.

4 is a graph comparing the total resistance of a contact according to an embodiment of the present invention and the total resistance of a contact formed according to a conventional method.

4 is a graph obtained by measuring the total resistance of a contact made of a tellurium-nickel-indium gallium arsenide alloy and a nickel-indium gallium arsenide alloy as a function of voltage. Based on this graph, the contact resistance of the tellurium-nickel-indium gallium arsenide alloy and the nickel-indium gallium arsenide alloy were calculated, respectively, to confirm the decrease in contact resistance using the tellurium-nickel-indium gallium arsenide alloy .

From the graph shown in FIG. 4, the slope value of the total resistance of the contact made of the tellurium-nickel-indium gallium arsenide alloy or the nickel-indium gallium arsenide alloy is calculated. Calculate the specific contact resistivity of a contact obtained by using a tellurium-nickel-indium gallium arsenide alloy or a nickel-indium gallium arsenide alloy by applying the obtained slope value to a circular transmission line model. do. As a result, the contact resistance of the contact using the tellurium-nickel-indium gallium arsenide alloy is 4.94 * 10 -6? Cm 2 and the contact resistance of the contact using the nickel-indium gallium arsenide alloy is 4.58 * 10 -5? Cm 2. That is, it can be seen that the contact resistance of the tellurium-nickel-indium gallium arsenide alloy contact according to the present invention is improved by about 10 times as compared with that of the nickel-indium gallium arsenide alloy contact.

The contact structure of the transistor according to the embodiment of the present invention described above is exemplified by n-mos, but may also be applied to p-mos.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

110: transistor substrate 120: gate electrode
121: gate leading layer 122: gate metal layer
131: source 132: drain
141, 142: tellurium 143, 144: nickel
151, 152: tellurium-nickel-indium gallium arsenide alloy

Claims (4)

Forming a source electrode, a drain electrode and a gate electrode on an indium gallium arsenide (InGaAs) substrate;
Depositing a tellurium layer on the source electrode and the drain electrode;
Depositing a nickel layer on the tellurium layer;
Heat treating the indium gallium arsenide (InGaAs) substrate on which the tellurium layer and the nickel layer are stacked, and
Forming a tellurium-nickel-indium gallium arsenide alloy contact on the source electrode and the drain electrode, respectively, through the heat treatment;
The contact resistance of the MOSFET is reduced. The method of claim 1,
Wherein the laminate of the tellurium layer and the nickel layer is laminated by a sputtering process. The method of claim 1,
Wherein the resistance of the contact varies depending on the thickness of the tellurium layer and the nickel layer or the time of the heat treatment. The method of claim 1,
Wherein the heat treatment is performed at a temperature ranging from 250 ° C to 330 ° C.
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KR20190036775A (en) * 2017-09-28 2019-04-05 충남대학교산학협력단 Method for fabricating mosfet
KR20200081283A (en) * 2018-12-26 2020-07-07 충남대학교산학협력단 Contact of semiconductor device and contact formation method of semiconductor device

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US20150171206A1 (en) * 2013-12-18 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxially Growing III-V Contact Plugs for MOSFETs

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KR20040059930A (en) 2002-12-30 2004-07-06 주식회사 하이닉스반도체 Method for reducing self-aligned bitline contact resistance using Co-Ni silicide

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KR20190036775A (en) * 2017-09-28 2019-04-05 충남대학교산학협력단 Method for fabricating mosfet
KR20200081283A (en) * 2018-12-26 2020-07-07 충남대학교산학협력단 Contact of semiconductor device and contact formation method of semiconductor device

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